Semiconductor Device

Abstract

A semiconductor device comprising: a semiconductor layer that has a main surface and contains SiC as the main component; a gate structure that is formed on the main surface; an insulating layer that is formed over the main surface so as to cover the gate structure; a gate main electrode that is positioned upon the insulating layer and is electrically connected to the gate structure; and a gate pad electrode that includes a connection part, which is positioned upon the gate main electrode so as to be connected to the gate main electrode and is connected to the gate main electrode over a first surface area in plan view, and an electrode surface, which has a second surface area greater than the first surface area in plan view.

Description

[Technical field]

[0001] This application corresponds to Japanese Patent Application No. 2020-082750 filed with the Japan Patent Office on May 8, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a gate pad electrically connected to a gate electrode of an IGBT. Patent Document 2 discloses a technique related to a vertical semiconductor device including a semiconductor layer made of SiC. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-4864 A [Patent Document 2] JP 2012-79945 A Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device according to Patent Document 1 includes a gate pad for supplying power to a gate electrode. The gate pad is wire-bonded, so it needs to be at least a certain size. However, the area directly below the gate pad is an inactive area that cannot function as a transistor. For this reason, if the pad size is ensured, there is a problem that the operating area (active area) in which the device can function as a transistor becomes narrow.

[0005] Therefore, one embodiment of the present invention provides a semiconductor device that can ensure a wide operating region. [Means for solving the problem]

[0006] One embodiment of the present invention provides a semiconductor device including a vertical transistor, the semiconductor layer having a first main surface and a second main surface opposite to the first main surface, the semiconductor layer including SiC as a main component, a control electrode of the vertical transistor provided on the first main surface, a first main electrode of the vertical transistor provided on the first main surface and spaced apart from the control electrode, a second main electrode of the vertical transistor provided on the second main surface, a first electrode covering a portion of the first main surface, a second electrode provided at a distance from the first electrode in a planar view, and a first electrode pad overlapping the first electrode in a planar view and electrically connected to the first electrode, wherein the first electrode is smaller than the first electrode pad in a planar view.

[0007] One embodiment of the present invention provides a semiconductor device including a semiconductor layer having a main surface and containing SiC as a main component, a gate structure formed on the main surface, an insulating layer formed on the main surface so as to cover the gate structure, a gate main electrode disposed on the insulating layer and electrically connected to the gate structure, and a gate pad electrode disposed on the gate main electrode so as to be connected to the gate main electrode, the connection portion having a first area in a plan view and connected to the gate main electrode, and an electrode surface having a second area exceeding the first area in a plan view.

[0008] Provided is a semiconductor device including: a semiconductor layer having a main surface; an active region provided in the semiconductor layer; a non-active region provided in a region of the semiconductor layer outside the active region; a plurality of gate structures formed in the active region; an insulating layer formed on the main surface so as to cover the plurality of gate structures; a gate main electrode disposed on the insulating layer so as to be electrically connected to the plurality of gate structures and overlapping the non-active region in a planar view; and a gate pad electrode disposed on the gate main electrode so as to be electrically connected to the gate main electrode and overlapping the active region and the non-active region in a planar view.

[0009] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing a vertical transistor included in the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a plan view of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a plan view taken along the line IV-IV shown in FIG. [Diagram 5] FIG. 5 is a plan view taken along the line VV shown in FIG. [Figure 6A] FIG. 6A is a cross-sectional view showing a step of a method for manufacturing the semiconductor device shown in FIG. [Figure 6B] FIG. 6B is a cross-sectional view showing a step subsequent to that of FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing a step subsequent to FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing a step subsequent to FIG. 6C. [Figure 6E] FIG. 6E is a cross-sectional view showing a step subsequent to FIG. 6D. [Figure 6F] FIG. 6F is a cross-sectional view showing a step subsequent to FIG. 6E. [Figure 6G] FIG. 6G is a cross-sectional view showing a step subsequent to FIG. 6F. [Figure 6H] FIG. 6H is a cross-sectional view showing a step subsequent to FIG. 6G. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a plan view of the semiconductor device shown in FIG. [Figure 9] FIG. 9 is a plan view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a plan view showing a modification of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a plan view showing the upper surface of an electrode of the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a main part of the semiconductor device according to the third embodiment. [Figure 13] FIG. 13 is a plan view of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a plan view taken along the line XIV-XIV shown in FIG. [Figure 15] FIG. 15 is a plan view showing a modification of the semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a plan view showing the upper surface of an electrode of the semiconductor device shown in FIG. [Figure 17] FIG. 17 is a rear view illustrating an example of the semiconductor package according to the fourth embodiment. [Figure 18] FIG. 18 is a front view showing the internal structure of the semiconductor package shown in FIG. [Figure 19] FIG. 19 is a front view showing another example of the semiconductor package according to the fourth embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing a main part of a semiconductor device according to a first modification of each of the above-mentioned embodiments. [Figure 21] FIG. 21 is a cross-sectional view showing a main part of a semiconductor device according to a second modification of each of the above-mentioned embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangement positions, component connection forms, steps, and step sequences shown in the following embodiments are merely examples and are not intended to limit the present invention. Among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0012] The attached drawings are schematic diagrams and are not necessarily precisely illustrated. Therefore, for example, the scales of the attached drawings are not necessarily the same. In the attached drawings, the same reference numerals are used for substantially the same configurations, and duplicated explanations are omitted or simplified.

[0013] In this specification, terms indicating the relationship between elements, such as perpendicular and orthogonal, terms indicating the shape of elements, such as rectangle and rectangular parallelepiped, and numerical ranges are not expressions that only express a strict meaning, but expressions that mean to include a substantially equivalent range. For example, in the shape of a polygon or polygonal prism, the vertices may be rounded.

[0014] In this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Specifically, the first main surface side of one of the semiconductor layers is the upper side (upper), and the second main surface side of the other is the lower side (lower). When the semiconductor device (vertical transistor) is actually used, the first main surface side may be the lower side (lower) and the second main surface side may be the upper side (upper). Alternatively, the semiconductor device (vertical transistor) may be used with the first main surface and the second main surface inclined or perpendicular to the horizontal plane.

[0015] In addition, the terms "above" and "below" apply not only when two components are arranged with a gap between them so that another component is interposed between them, but also when two components are arranged in close contact with each other.

[0016] In this specification and the drawings, the x-axis, y-axis, and z-axis indicate the three axes of a three-dimensional Cartesian coordinate system. In this specification, the term "stacking direction" refers to a direction perpendicular to the main surface of the semiconductor layer. In addition, the term "planar view" refers to a view from a direction perpendicular to the first main surface of the semiconductor layer.

[0017] Fig. 1 is a cross-sectional view showing a vertical transistor 2 included in a semiconductor device 1 according to a first embodiment. In Fig. 1, in order to make the drawing easier to see, shading representing a cross section of a semiconductor layer 10 is not applied.

[0018] 1 is an example of a switching device and includes a vertical transistor 2. The vertical transistor 2 is, for example, a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in FIG 1, the semiconductor device 1 includes a semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40.

[0019] The semiconductor device 1 includes a semiconductor layer 10 containing, as a main component, SiC (silicon carbide) as an example of a wide band gap semiconductor. Specifically, the semiconductor layer 10 is an n-type SiC semiconductor layer containing a SiC single crystal. The SiC single crystal is, for example, a 4H-SiC single crystal. The 4H-SiC single crystal has an off angle inclined at an angle of 10° or less from the (0001) plane to the [11-20] direction. The off angle may be 0° or more and 4° or less. The off angle may be more than 0° and less than 4°. The off angle is set to, for example, 2° or 4°, or in the range of 2°±0.2° or 4°±0.4°.

[0020] In this embodiment, the semiconductor layer 10 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. In this embodiment, the semiconductor layer 10 has a semiconductor substrate 13 and an epitaxial layer 14. The semiconductor substrate 13 is an n + The epitaxial layer 14 is formed as an n-type drain region. - The drain drift region is formed as a drain-drift region of the MOSFET.

[0021] The semiconductor substrate 13 includes a SiC single crystal. The lower surface of the semiconductor substrate 13 is a second main surface 12. The second main surface 12 is a carbon surface (000-1) where carbon of the SiC crystal is exposed. The epitaxial layer 14 is laminated on the upper surface of the semiconductor substrate 13 and includes a n-type SiC single crystal. - The epitaxial layer 14 is a type SiC semiconductor layer. The upper surface of the epitaxial layer 14 is a first main surface 11. The first main surface 11 is a silicon surface (0001) where silicon of the SiC crystal is exposed.

[0022] The n-type impurity concentration of the semiconductor substrate 13 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 In this specification, the term "impurity concentration" means a peak value of the impurity concentration. The n-type impurity concentration of the epitaxial layer 14 is lower than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 is, for example, 1.0×10 15 cm -3 Above 1.0×10 17 cm -3 The following is the result.

[0023] The thickness of the semiconductor substrate 13 is, for example, not less than 1 μm and less than 1000 μm. The thickness of the semiconductor substrate 13 may be not less than 5 μm. The thickness of the semiconductor substrate 13 may be not less than 25 μm. The thickness of the semiconductor substrate 13 may be not less than 50 μm. The thickness of the semiconductor substrate 13 may be not less than 100 μm.

[0024] The thickness of the semiconductor substrate 13 may be 700 μm or less. The thickness of the semiconductor substrate 13 may be 500 μm or less. The thickness of the semiconductor substrate 13 may be 400 μm or less. The thickness of the semiconductor substrate 13 may be 300 μm or less. The thickness of the semiconductor substrate 13 may be 250 μm or less. The thickness of the semiconductor substrate 13 may be 200 μm or less. The thickness of the semiconductor substrate 13 may be 150 μm or less. The thickness of the semiconductor substrate 13 may be 100 μm or less. In the vertical transistor 2, a current flows in the thickness direction of the semiconductor substrate 13 (i.e., the stacking direction). Therefore, by reducing the thickness of the semiconductor substrate 13, a reduction in the resistance value due to a shortening of the current path can be achieved.

[0025] The thickness of the epitaxial layer 14 is, for example, not less than 1 μm and not more than 100 μm. The thickness of the epitaxial layer 14 may be not less than 5 μm. The thickness of the epitaxial layer 14 may be not less than 10 μm. The thickness of the epitaxial layer 14 may be not more than 50 μm. The thickness of the epitaxial layer 14 may be not more than 40 μm. The thickness of the epitaxial layer 14 may be not more than 30 μm. The thickness of the epitaxial layer 14 may be not more than 20 μm. The thickness of the epitaxial layer 14 may be not more than 15 μm. The thickness of the epitaxial layer 14 may be not more than 10 μm.

[0026] The semiconductor device 1 includes a plurality of trench gate structures 21 and a plurality of trench source structures 31 each formed on a first main surface 11 of a semiconductor layer 10. The trench gate structures 21 and the trench source structures 31 are alternately arranged one by one along the x-axis direction in a plan view, forming a striped structure. In Fig. 1, only the area where one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.

[0027] Both the trench gate structure 21 and the trench source structure 31 are formed in a strip shape extending along the y-axis direction. For example, the x-axis direction is the [11-20] direction, and the y-axis direction is the [1-100] direction. The x-axis direction may be the [-1100] direction (the [1-100] direction). In this case, the y-axis direction may be the [11-20] direction. The distance between the trench gate structure 21 and the trench source structure 31 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0028] 1, the trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20. The gate trench 22 is formed by digging down the first main surface 11 of the semiconductor layer 10 toward the second main surface 12. The gate trench 22 has a rectangular cross-sectional shape in the xz cross section, and is a groove-like recessed portion extending in a strip shape along the y-axis direction.

[0029] The gate trench 22 may have a length in the longitudinal direction (y-axis direction) on the order of millimeters. The gate trench 22 has a length of, for example, 1 mm or more and 10 mm or less. The length of the gate trench 22 may be 2 mm or more and 5 mm or less. The total extension of one or more gate trenches 22 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 It may be the following.

[0030] The gate insulating layer 23 is provided in the form of a film along the sidewall 22a and the bottom wall 22b of the gate trench 22. The gate insulating layer 23 defines a concave space inside the gate trench 22. The gate insulating layer 23 includes, for example, silicon oxide. The gate insulating layer 23 may include at least one of undoped silicon, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0031] The thickness of the gate insulating layer 23 is, for example, not less than 0.01 μm and not more than 0.5 μm. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the portion. For example, the gate insulating layer 23 includes a sidewall portion 23a and a bottom wall portion 23b. The sidewall portion 23a is formed along the sidewall 22a of the gate trench 22. The bottom wall portion 23b is formed along the bottom wall 22b of the gate trench 22.

[0032] The thickness of the bottom wall portion 23b may be greater than the thickness of the sidewall portion 23a. The thickness of the bottom wall portion 23b is, for example, not less than 0.01 μm and not more than 0.2 μm. The thickness of the sidewall portion 23a is, for example, not less than 0.05 μm and not more than 0.5 μm. The gate insulating layer 23 may also include an upper surface portion formed on the upper surface of the first main surface 11 outside the gate trench 22. The thickness of the upper surface portion may be greater than the thickness of the sidewall portion 23a.

[0033] The gate electrode 20 is an example of a control electrode of the vertical transistor 2. The gate electrode 20 is embedded in a gate trench 22. A gate insulating layer 23 is provided between the gate electrode 20 and the sidewall 22a and bottom wall 22b of the gate trench 22. That is, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 is, for example, a conductive layer including conductive polysilicon. The gate electrode 20 may include at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, or conductive metal nitrides such as titanium nitride.

[0034] The width of the trench gate structure 21 is, for example, not less than 0.2 μm and not more than 2.0 μm. As an example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 is, for example, not less than 0.5 μm and not more than 3.0 μm. As an example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0035] The aspect ratio of the trench gate structure 21 is, for example, not less than 0.25 and not more than 15.0. The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. In this embodiment, the aspect ratio of the trench gate structure 21 is the same as the aspect ratio of the gate trench 22.

[0036] As shown in FIG. 1, the trench source structure 31 includes a source trench 32, a deep well region 15, a barrier formation layer 33, and a source electrode 30. The source trench 32 is formed by digging down the first main surface 11 of the semiconductor layer 10 toward the second main surface 12. The source trench 32 has a rectangular cross-sectional shape in the xz cross section and is a groove-like recess extending in a strip shape along the y-axis direction. In this embodiment, the source trench 32 is deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located closer to the second main surface 12 than the bottom wall 22b of the gate trench 22.

[0037] The deep well region 15 is formed in a region along the source trench 32 in the semiconductor layer 10. The deep well region 15 is also called a breakdown voltage holding region. The deep well region 15 is p - The p-type impurity concentration of the deep well region 15 is, for example, 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 The p-type impurity concentration of the deep well region 15 is higher than the n-type impurity concentration of the epitaxial layer 14, for example.

[0038] The deep well region 15 includes a sidewall portion 15a along the sidewall 32a of the source trench 32 and a bottom wall portion 15b along the bottom wall 32b of the source trench 32. The thickness (length in the z-axis direction) of the bottom wall portion 15b is, for example, equal to or greater than the thickness (length in the x-axis direction) of the sidewall portion 15a. At least a portion of the bottom wall portion 15b may be located within the semiconductor substrate 13.

[0039] The source electrode 30 is an example of a first main electrode of the vertical transistor 2. The source electrode 30 is embedded in the source trench 32. The source electrode 30 is, for example, a conductive layer including conductive polysilicon. The source electrode 30 may be n-type polysilicon doped with n-type impurities or p-type polysilicon doped with p-type impurities. The source electrode 30 may include at least one of metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, or conductive metal nitrides such as titanium nitride. The source electrode 30 may be formed of the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 are formed in the same process.

[0040] The barrier-forming layer 33 is interposed between the source electrode 30 and the source trench 32. The barrier-forming layer 33 is formed in a film shape along the side wall 32a and the bottom wall 32b of the source trench 32 between the source electrode 30 and the source trench 32. That is, the source electrode 30 is embedded in a concave space defined by the barrier-forming layer 33. The barrier-forming layer 33 defines a concave space inside the source trench 32. The barrier-forming layer 33 is formed using a material different from that of the source electrode 30. The barrier-forming layer 33 has a higher potential barrier than the potential barrier between the source electrode 30 and the deep well region 15.

[0041] The barrier-forming layer 33 may be an insulating barrier-forming layer. In this case, the barrier-forming layer 33 contains at least one of undoped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride. The barrier-forming layer 33 may be formed using the same material as the gate insulating layer 23. In this case, the barrier-forming layer 33 may have the same film thickness as the gate insulating layer 23. For example, the barrier-forming layer 33 and the gate insulating layer 23 may be formed using silicon oxide. In this case, the barrier-forming layer 33 and the gate insulating layer 23 are simultaneously formed by a thermal oxidation process.

[0042] The barrier-forming layer 33 may be an electrically conductive barrier-forming layer, in which case the barrier-forming layer 33 comprises at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0043] The width of the trench source structure 31 is, for example, not less than 0.6 μm and not more than 2.4 μm. As an example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15. The depth of the trench source structure 31 is, for example, not less than 1.5 μm and not more than 11 μm. As an example, the depth of the trench source structure 31 may be about 2.5 μm.

[0044] The aspect ratio of the trench source structure 31 is greater than that of the trench gate structure 21. The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31. In this embodiment, the width of the trench source structure 31 is the sum of the width of the source trench 32 and the width of the sidewall portions 15a of the deep well region 15 located on both sides of the source trench 32. For example, the aspect ratio of the trench source structure 31 is 1.5 or more and 4.0 or less. By increasing the depth of the trench source structure 31, the effect of maintaining a withstand voltage by the super junction (SJ) structure can be improved.

[0045] 1, the semiconductor device 1 includes a body region 16, a source region 17, and a contact region 18 formed in an epitaxial layer 14 of a semiconductor layer 10. The deep well region 15, the body region 16, the source region 17, and the contact region 18 may be considered as components of the epitaxial layer 14.

[0046] The body region 16 is a p -The body region 16 is a type semiconductor region. In a plan view, the body region 16 is formed in a region between the gate trench 22 and the source trench 32. In a plan view, the body region 16 is formed in a strip shape extending along the y-axis direction. The body region 16 is continuous with the deep well region 15.

[0047] The p-type impurity concentration of the body region 16 is, for example, 1.0×10 16 cm -3 Above 1.0×10 19 cm -3 The p-type impurity concentration of the body region 16 may be equal to that of the deep well region 15. The p-type impurity concentration of the body region 16 may be higher than that of the deep well region 15.

[0048] The source region 17 is an n-type semiconductor layer 10 provided in the surface layer portion of the first main surface 11 of the body region 16. + The source region 17 is a type semiconductor region. The source region 17 is provided in a region along the gate trench 22. The source region 17 is in contact with the gate insulating layer 23 and faces the gate electrode 20 with the gate insulating layer 23 interposed therebetween. Specifically, the source region 17 is in contact with a sidewall portion 23a of the gate insulating layer 23. The source region 17 may be in contact with an upper surface portion of the gate insulating layer 23.

[0049] The source region 17 is formed in a band shape extending along the y-axis direction in a plan view. The width (length in the x-axis direction) of the source region 17 is, for example, 0.2 μm or more and 0.6 μm or less. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration of the source region 17 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The following is the result.

[0050] The contact region 18 is a p +The contact region 18 is a type semiconductor region. The contact region 18 may be considered as a part (high concentration portion) of the body region 16. The contact region 18 is formed in a region along the source trench 32. The contact region 18 is in contact with the barrier-forming layer 33 and faces the source electrode 30 with the barrier-forming layer 33 in between. The contact region 18 is electrically connected to the body region 16. The contact region 18 is electrically connected to the source region 17.

[0051] The contact region 18 is formed in a band shape extending along the y-axis direction in a plan view. The width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 μm or more and 0.4 μm or less. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration of the contact region 18 is, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The following is the result.

[0052] The semiconductor device 1 includes a drain electrode 40 connected to the second main surface 12 of the semiconductor layer 10. The drain electrode 40 is an example of a second main electrode of the semiconductor device 1 (vertical transistor 2). The drain electrode 40 may include at least one of titanium, nickel, copper, aluminum, gold, and silver. For example, the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 12 of the semiconductor layer 10.

[0053] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer stacked in this order from the second main surface 12 of the semiconductor layer 10. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer stacked in this order from the second main surface 12 of the semiconductor layer 10. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may include a single-layer structure having a TiN layer instead of a Ti layer, or a stacked structure having a Ti layer and a TiN layer.

[0054] In the semiconductor device 1 configured as above, an ON state in which a drain current flows and an OFF state in which a drain current does not flow can be switched depending on the gate voltage applied to the gate electrode 20 of the vertical transistor 2. The gate voltage is, for example, a voltage between 10V and 50V. As an example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 is, for example, a reference voltage such as a ground voltage (0V). The drain voltage applied to the drain electrode 40 is equal to or higher than the source voltage. The drain voltage is, for example, equal to or higher than 0V and equal to or lower than 10000V. The drain voltage may be equal to or higher than 1000V.

[0055] When a gate voltage is applied to the gate electrode 20, p - A channel is formed in a portion of the body region 16 that contacts the gate insulating layer 23. As a result, a current path is formed between the source electrode 30 and the drain electrode 40 through the channel of the body region 16. The current path connects the contact region 18, the source region 17, the channel of the body region 16, the epitaxial layer 14, and the semiconductor substrate 13 between the source electrode 30 and the drain electrode 40.

[0056] The drain electrode 40 may be at a higher potential than the source electrode 30. In this case, the drain current flows from the drain electrode 40 to the source electrode 30. That is, the drain region flows through the drain electrode 40, the semiconductor substrate 13, the epitaxial layer 14, the channel of the body region 16, the source region 17, and the contact region 18 in this order to the source electrode 30. In this manner, the drain current flows along the thickness direction of the semiconductor device 1.

[0057] In this embodiment, the pn junction (pn junction) is - Deep well region 15 and n - When the vertical transistor 2 is in an on-state, the source voltage is applied to the p -A drain voltage higher than the source voltage is applied to the n-type deep well region 15 via the drain electrode 40. - The epitaxial layer 14 is then applied with a voltage of 0.1 V.

[0058] That is, a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 14. Therefore, a depletion layer spreads from the interface between the deep well region 15 and the epitaxial layer 14 toward the drain electrode 40. This makes it possible to increase the breakdown voltage of the vertical transistor 2.

[0059] Next, a pad structure for supplying a predetermined voltage to the gate electrode 20 and the source electrode 30 will be described. Fig. 2 is a cross-sectional view of the semiconductor device 1 shown in Fig. 1. Fig. 3 is a plan view of the semiconductor device 1 shown in Fig. 1. Fig. 2 is specifically a cross-sectional view taken along line II-II shown in Fig. 3. In Fig. 2, the specific configuration of the semiconductor layer 10 shown in Fig. 1 is omitted. Also, in Fig. 2, the shading representing the cross section of the semiconductor layer 10 is not applied.

[0060] 2 and 3, the semiconductor device 1 includes a main surface gate electrode 50, a main surface source electrode 55, an insulating layer 60, a gate pad 70, a source pad 75, and a mold layer 80. The pad structure is provided above the first main surface 11 of the semiconductor layer 10.

[0061] 4 is a plan view taken along the line IV-IV shown in FIG. 2. Specifically, FIG. 4 is a plan view of the semiconductor device 1 viewed from the positive side of the z axis, through the gate pad 70, the source pad 75, and the mold layer 80 shown in FIG. 3. For example, the positive side of the z axis is the first main surface 11 side when it is assumed that the second main surface 12 (or the surface of the drain electrode 40) is located on the xy plane where z=0. Specifically, FIG. 5 is a plan view of the semiconductor device 1 viewed from the positive side of the z axis, through the main surface gate electrode 50, the main surface source electrode 55, and the insulating layer 60 shown in FIG. 4, and the gate pad 70, the source pad 75, and the mold layer 80 shown in FIG. 3.

[0062] 3 to 5, the semiconductor layer 10 (semiconductor device 1) has a rectangular shape in a plan view. In the plan view, the length of one side of the semiconductor layer 10 (semiconductor device 1) is, for example, 1 mm or more and 10 mm or less. In the plan view, the length of one side of the semiconductor layer 10 (semiconductor device 1) may be 2 mm or more and 5 mm or less.

[0063] The semiconductor device 1 includes an active region 3 and a non-active region 4 (outer region). The active region 3 is indicated by a two-dot chain line in Fig. 3 and Fig. 5. The active region 3 is a main region through which the drain current of the vertical transistor 2 flows. In other words, the active region 3 is an operating region of the vertical transistor 2. Specifically, the active region 3 substantially coincides with a region covered by the main surface source electrode 55.

[0064] In this embodiment, the active region 3 is separated into a region on one side (left side of the paper) in the x-axis direction of the semiconductor layer 10 in a plan view, and a region on the other side (right side of the paper) in the x-axis direction. In the active region 3, the planar area of ​​the region on one side (left side of the paper) may be different from the planar area of ​​the region on the other side (right side of the paper). In this embodiment, an example is shown in which the planar area of ​​the region on one side (left side of the paper) is less than the planar area of ​​the region on the other side (right side of the paper).

[0065] As shown in Fig. 5, the active region 3 includes a plurality of gate electrodes 20 (trench gate structures 21) and a plurality of source electrodes 30 (trench source structures 31). In Fig. 5, the plurality of gate electrodes 20 and the plurality of source electrodes 30 are illustrated simply so that the number of the gate electrodes 20 and the source electrodes 30 can be counted. However, the number of the gate electrodes 20 and the source electrodes 30 is actually much greater than the number illustrated.

[0066] The inactive region 4 is a region that does not operate as a vertical transistor 2. The inactive region 4 is a frame-shaped (annular) region that surrounds the active region 3. In this embodiment, the inactive region 4 separates the active region 3 into a region on one side (left side of the paper) and a region on the other side (right side of the paper). In other words, the inactive region 4 surrounds the region on one side (left side of the paper) of the active region 3 in a plan view. The inactive region 4 also surrounds the region on one side (left side of the paper) of the active region 3 in a plan view.

[0067] As shown in Fig. 5, gate finger portions 20b, which will be described later, are provided in the non-active region 4. In the example shown in Figs. 3 to 5, the active region 3 is divided into two by the non-active region 4, but the active region 3 may be a single undivided region. The shape and arrangement of the active region 3 can be appropriately adjusted depending on the layout of the gate finger portions 20b.

[0068] 4, the active area 3 is included in the area covered by the main surface source electrode 55. As shown in FIG. 3, the active area 3 includes a part of the area covered by the gate pad 70. The area covered by the main surface gate electrode 50 is included in the non-active area 4, and is not included in the active area 3.

[0069] The main surface gate electrode 50 is an example of a first electrode that covers a part of the first main surface 11. The main surface gate electrode 50 includes at least one of conductive polysilicon, metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, and metal nitrides such as titanium nitride. The main surface gate electrode 50 may be formed using the same material as the gate electrode 20.

[0070] The main surface gate electrode 50 is electrically connected to the gate electrode 20. As shown in Fig. 2, the main surface gate electrode 50 is provided in a line shape on an insulating layer 60 (specifically, a lower insulating layer 61) described later. The main surface gate electrode 50 is connected to the gate electrode 20 (not shown in Fig. 2) through a via conductor penetrating the insulating layer 60 (specifically, the lower insulating layer 61).

[0071] 4, the main surface gate electrode 50 includes a power receiving portion 50a, a power supply portion 50b, and a connection portion 50c. The power receiving portion 50a of the main surface gate electrode 50 is provided on an inner portion of the first main surface 11 in a plan view. Specifically, the power receiving portion 50a is provided on a region of the inactive region 4 located between a region on one side (left side of the paper) of the active region 3 and a region on the other side (right side of the paper) of the active region 3 in a plan view.

[0072] The power receiving portion 50a is located directly below the gate pad 70 described below, and is a portion connected to the gate pad 70 (specifically, the columnar portion 71 described below). In a plan view, a portion of the main surface gate electrode 50 that overlaps with the columnar portion 71 corresponds to the power receiving portion 50a. In a plan view, the power receiving portion 50a of the main surface gate electrode 50 is smaller than the gate pad 70. The shape of the power receiving portion 50a in a plan view (the shape of the columnar portion 71 in a plan view) is, for example, a square or a rectangle. The length of one side of the power receiving portion 50a is 5 μm or more and 50 μm or less. As an example, the shape of the power receiving portion 50a in a plan view may be a square of about 20 μm × 20 μm.

[0073] The power supply unit 50b is a portion that extends along the outer periphery of the semiconductor layer 10 (the periphery of the first principal surface 11) in a plan view. In the example shown in FIG. 4, the power supply unit 50b extends along the x-axis direction of the semiconductor layer 10. In this embodiment, two power supply units 50b are provided so as to sandwich the inner portion of the first principal surface 11 from the positive side and the negative side in the y-axis direction in a plan view. The power supply unit 50b may be provided so as to surround the inner portion of the first principal surface 11 (for example, the principal surface source electrode 55 described later) all around the periphery of the semiconductor layer 10.

[0074] The connection portion 50c is a portion connected to the power receiving portion 50a and the power supply portion 50b. In the example shown in Fig. 4, the connection portion 50c is drawn out from the power receiving portion 50a to the positive side and the negative side in the y-axis direction so as to be connected to the power supply portion 50b, and extends to the power supply portion 50b. The region in which the power receiving portion 50a, the power supply portion 50b, and the connection portion 50c are provided becomes the inactive region 4. For this reason, it is desirable to form the power receiving portion 50a, the power supply portion 50b, and the connection portion 50c as small as possible.

[0075] In this embodiment, the main surface gate electrode 50 is electrically connected to each of the multiple gate electrodes 20 via the power supply portion 50b. Specifically, a through hole is provided in an insulating layer 60 (specifically, a lower insulating layer 61) described below located directly below the power supply portion 50b, and the power supply portion 50b is connected to a gate finger portion 20b (see FIG. 5) described below via the through hole.

[0076] 5, the gate electrodes 20 (trench gate structures 21) are formed in an elongated shape extending in the y-axis direction. The gate electrodes 20 may be divided into a positive side portion and a negative side portion in the y-axis direction at a central portion in the y-axis direction.

[0077] 5, the semiconductor device 1 includes gate finger portions 20b formed on the semiconductor layer 10 (first main surface 11) so as to be electrically connected to a plurality of gate electrodes 20. Specifically, the gate finger portions 20b are interposed between the semiconductor layer 10 (first main surface 11) and an insulating layer 60, which will be described later. The gate finger portions 20b extend in the x-axis direction along the periphery of the first main surface 11 (the outer periphery of the semiconductor device 1) in a plan view.

[0078] In this embodiment, two gate finger portions 20b are provided so as to sandwich the multiple gate electrodes 20 from the positive and negative sides in the y-axis direction in a plan view. The gate finger portions 20b are connected to both ends of the multiple gate electrodes 20 in the y-axis direction. The gate finger portions 20b may be connected to only one end of the multiple gate electrodes 20 in the y-axis direction. The above-mentioned power supply portion 50b is connected to the gate finger portions 20b via a through hole provided in an insulating layer 60 (specifically, a lower insulating layer 61) described later.

[0079] The principal surface source electrode 55 is an example of a second electrode covering a part of the first principal surface 11. The principal surface source electrode 55 is provided at a distance from the principal surface gate electrode 50 in a plan view. For example, the principal surface source electrode 55 is formed in almost the entire region of the first principal surface 11 of the semiconductor layer 10 (semiconductor device 1) in a plan view, excluding the region in which the principal surface gate electrode 50 is provided and the periphery of this region. In a plan view, the principal surface source electrode 55 is larger than the principal surface gate electrode 50.

[0080] Specifically, the main surface source electrode 55 includes a first portion disposed on a region on one side (left side of the drawing) of the active region 3, and a second portion separated from the first portion and disposed on a region on the other side (right side of the drawing) of the active region 3. The planar area of ​​the second portion is larger than the first planar area of ​​the first portion. The sum of the planar areas of the first portion and the second portion is larger than the planar area of ​​the main surface gate electrode 50.

[0081] The principal surface source electrode 55 includes at least one of conductive polysilicon, metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, and metal nitrides such as titanium nitride. The principal surface source electrode 55 may be formed using the same material as the source electrode 30. The principal surface source electrode 55 may be formed using the same material as the principal surface gate electrode 50. In this case, the principal surface gate electrode 50 and the principal surface source electrode 55 can be formed in the same process.

[0082] A plurality of source electrodes 30 are provided directly below the principal surface source electrode 55, and the principal surface source electrode 55 is electrically connected to the source electrode 30. For this reason, as shown in Fig. 1, the principal surface source electrode 55 is directly connected to the upper surfaces of the plurality of source electrodes 30. As shown in Fig. 2, the lower part of the principal surface source electrode 55 forms an active region 3, and the MOSFET structure shown in Fig. 1 is periodically formed in the active region 3.

[0083] The principal surface source electrode 55 has an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first principal surface 11) in a planar view. Preferably, the principal surface source electrode 55 has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first principal surface 11) in a planar view. Meanwhile, the principal surface gate electrode 50 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first principal surface 11) in a planar view. Preferably, the principal surface gate electrode 50 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first principal surface 11) in a planar view.

[0084] The principal surface source electrode 55 is disposed in a region including the center position of the semiconductor layer 10 (first principal surface 11) in a plan view. The principal surface gate electrode 50 is disposed in a region avoiding the principal surface source electrode 55. The principal surface gate electrode 50 may be disposed in a region including the center position of the semiconductor layer 10 (first principal surface 11). In this case, the principal surface source electrode 55 may be disposed so as to surround the periphery of the principal surface gate electrode 50.

[0085] As shown in FIG. 2, the insulating layer 60 includes a lower insulating layer 61, a side insulating layer 62, an upper insulating layer 63, and an end insulating layer 65. In FIG. 4, the non-shaded portion around the main surface gate electrode 50 corresponds to the side insulating layer 62 and the end insulating layer 65. The lower insulating layer 61 is an interlayer insulating film, and is provided on the first main surface 11. Specifically, the lower insulating layer 61 collectively covers the multiple trench gate structures 21. As shown in FIG. 1, the lower insulating layer 61 is provided to prevent contact between the main surface source electrode 55 and the gate electrode 20.

[0086] The lower insulating layer 61 has a plurality of source contact holes 61b. A portion of the main surface source electrode 55 is filled in the plurality of source contact holes 61b. As a result, the main surface source electrode 55 is electrically connected to the plurality of source electrodes 30 in the plurality of source contact holes 61b.

[0087] Although not shown in FIG. 2, as described above, the lower insulating layer 61 has a through hole for connecting the power supply portion 50b (see FIG. 4) of the main surface gate electrode 50 to the gate finger portion 20b (see FIG. 5). A part of the power supply portion 50b is embedded in the through hole of the lower insulating layer 61. The power supply portion 50b is connected to the gate finger portion 20b in the through hole. In this way, the main surface gate electrode 50 is electrically connected to the gate electrode 20.

[0088] The side insulating layer 62 is formed on the lower insulating layer 61, and is provided to prevent contact between the main surface gate electrode 50 and the main surface source electrode 55. As shown in FIG. 4, the side insulating layer 62 is provided to surround the main surface gate electrode 50.

[0089] The upper insulating layer 63 is formed on the upper surface 56 of the main surface source electrode 55. Specifically, the upper insulating layer 63 covers a portion of the main surface gate electrode 50 along the power receiving portion 50a on the main surface source electrode 55. The upper insulating layer 63 covers a portion of the power receiving portion 50a so as to partially expose the upper surface 52 of the power receiving portion 50a. In other words, the upper insulating layer 63 has a through hole 64 that exposes the upper surface 52 of the power receiving portion 50a. As shown in FIG. 2, a portion of the upper insulating layer 63 rides up from above the lower insulating layer 61 onto the power receiving portion 50a.

[0090] More specifically, the upper insulating layer 63 includes a flat portion 63a, a first end portion 63b, and a second end portion 63c. The flat portion 63a is provided on the upper surface 56 of the main surface source electrode 55, and has a substantially uniform thickness. A part of the flat portion 63a is also provided on the upper surface 52 of the power receiving portion 50a.

[0091] The first end 63b is provided on the upper surface 52 of the power receiving portion 50a of the main surface gate electrode 50. The second end 63c is provided on the upper surface 56 of the main surface source electrode 55. The first end 63b and the second end 63c are each a portion having a non-uniform thickness. The first end 63b and the second end 63c are each inclined, for example, so that the thickness gradually decreases. The first end 63b and the second end 63c may have an inclined surface having a constant inclination angle, or may have a curved surface that is curved convexly or concavely.

[0092] In a plan view, the size and shape of the through hole 64 approximately correspond to the size and shape of the power receiving portion 50a of the main surface gate electrode 50. Specifically, in a plan view, the size of the through hole 64 is smaller than the power receiving portion 50a because a part of the upper insulating layer 63 rides on the power receiving portion 50a.

[0093] The end insulating layer 65 is provided on the first main surface 11 along the outer periphery of the main surface source electrode 55. For example, the end insulating layer 65 is formed in an annular shape so as to cover the entire periphery of the main surface source electrode 55 in a plan view. As shown in Fig. 2, the end insulating layer 65 has a portion riding on the lower insulating layer 61 and an electrode covering portion riding on the main surface source electrode 55 (upper surface 56).

[0094] The electrode covering portion of the end insulating layer 65 has a flat portion 65a and an end portion 65b. The flat portion 65a is a portion having a substantially uniform thickness. The end portion 65b is a portion having a non-uniform thickness. The end portion 65b is inclined, for example, so that the thickness gradually decreases. The end portion 65b may have an inclined surface having a constant inclination angle, or may have a curved surface that is curved convexly or concavely. The end insulating layer 65 may cover the power supply portion 50b of the main surface gate electrode 50 shown in FIG. 4.

[0095] The lower insulating layer 61 contains, for example, silicon oxide or silicon nitride as a main component. The lower insulating layer 61, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0096] The side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may each contain a photosensitive resin. The side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may each be made of an organic material such as polyimide or PBO (polybenzoxazole). The upper insulating layer 63 and the end insulating layer 65 may have a thickness of, for example, 3 μm or more and 20 μm or less. The upper insulating layer 63 and the end insulating layer 65 may have a thickness of, preferably, 5 μm or more and 15 μm or less. The upper insulating layer 63 and the end insulating layer 65 may have a thickness of, more preferably, 5 μm or more and 10 μm or less. The lower insulating layer 61, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 may be formed of the same insulating material (for example, an inorganic insulating material such as silicon oxide or silicon nitride).

[0097] The gate pad 70 is an example of a first electrode pad. In a plan view, the gate pad 70 overlaps the main surface gate electrode 50 and is electrically connected to the main surface gate electrode 50. The gate pad 70 completely covers the power receiving portion 50a of the main surface gate electrode 50. That is, in a plan view, the power receiving portion 50a of the main surface gate electrode 50 is located inside the gate pad 70.

[0098] The gate pad 70 overlaps a part of the main surface source electrode 55 in a plan view. That is, a part of the main surface source electrode 55 is located directly below the gate pad 70. In this embodiment, the main surface source electrode 55 is extended to a region where it overlaps with the gate pad 70 in a plan view, so that a part of the region where the gate pad 70 overlaps with the main surface source electrode 55 can be used as the active region 3. This makes it possible to secure a larger area for the active region 3 while securing the area for the gate pad 70.

[0099] 2, the gate pad 70 includes a pillar-shaped portion 71 and a wide portion 72. The pillar-shaped portion 71 is an example of a first conductive layer provided on the main surface gate electrode 50. The pillar-shaped portion 71 extends in a pillar shape in the normal direction (z-axis direction) of the upper surface 52 of the power receiving portion 50a of the main surface gate electrode 50.

[0100] The columnar portion 71 covers the upper surface 52 of the power receiving portion 50a. The columnar portion 71 further covers a part of the flat portion 63a and the first end portion 63b of the upper insulating layer 63. The height (length in the z-axis direction) of the columnar portion 71 is greater (longer) than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 71 is greater (longer) than the maximum thickness of the portion of the upper insulating layer 63 located above the power receiving portion 50a. As a result, the top of the columnar portion 71 is higher than the top of the upper insulating layer 63.

[0101] The columnar portion 71 has a side surface 74 that extends vertically or substantially vertically. The side surface 74 does not necessarily need to extend linearly in a cross-sectional view, and may extend in a curved or uneven shape. The side surface 74 is located on a region where the power receiving unit 50a and the upper insulating layer 63 overlap in a plan view. Specifically, the side surface 74 is located on the flat portion 63a of the upper insulating layer 63. In other words, the columnar portion 71 covers the power receiving unit 50a and the upper insulating layer 63. By positioning the side surface 74 on the flat portion 63a, the columnar portion 71 can be formed more stably than when the side surface 74 is located on the first end portion 63b, which has a relatively large thickness variation.

[0102] The wide portion 72 is an example of a second conductive layer provided on the upper end of the columnar portion 71. The wide portion 72 is a portion obtained by enlarging the size of the upper end of the columnar portion 71 in the xy plane. The size and shape of the wide portion 72 in a planar view correspond to the size and shape of the gate pad 70 in a planar view. In a planar view, the wide portion 72 is larger than the columnar portion 71. In a planar view, the columnar portion 71 is located inside the wide portion 72.

[0103] In a plan view, the outline of the wide portion 72 is formed at a certain interval from the outline of the columnar portion 71 toward the peripheral edge side of the semiconductor layer 10. The wide portion 72 (gate pad 70) overlaps a part of the active region 3 and the inactive region 4 in a plan view. In other words, the wide portion 72 (gate pad 70) overlaps the trench gate structure 21 and the trench source structure 31 in a plan view.

[0104] The wide portion 72 has an upper surface 73 that is used for electrical connection between the semiconductor device 1 (vertical transistor 2) and other circuits. In this embodiment, the upper surface 73 of the wide portion 72 is formed in an island shape in a plan view and is connected to a power supply circuit that supplies a gate voltage. That is, in this embodiment, the gate pad 70 is not formed in a line shape, unlike the main surface gate electrode 50. For example, a metal wire is connected to the upper surface 73 of the wide portion 72 by wire bonding. The metal wire includes at least one of metals such as aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge bonded to the gate pad (upper surface 73 of the wide portion 72).

[0105] In order to perform wire bonding appropriately, the wide portion 72 needs to have a certain size or more. The shape of the wide portion 72 in a plan view is, for example, a square. In this case, the size of the wide portion 72 may be, for example, 800 μm×800 μm or more and 1 mm×1 mm or less. In this case, the direction of connection of the metal wire to the wide portion 72 can be any direction. Of course, the size of the wide portion 72 may be larger than 1 mm×1 mm. Also, the shape of the wide portion 72 in a plan view may be a rectangle. In this case, the size of the wide portion 72 may be 400 mm×800 mm or more.

[0106] In a plan view, the area of ​​the wide portion 72 (i.e., the area of ​​the gate pad 70) is larger than the area of ​​the power receiving portion 50a of the main surface gate electrode 50. In other words, in a plan view, the connection area of ​​the connection portion of the main surface gate electrode 50 and the gate pad 70 is smaller than the area of ​​the upper surface 73 of the gate pad 70. The area of ​​the wide portion 72 is 200 times or more and 40,000 times or less the area of ​​the power receiving portion 50a. The area of ​​the wide portion 72 may be 400 times or more the area of ​​the power receiving portion 50a. As an example, the area of ​​the wide portion 72 may be about 2,500 times the area of ​​the power receiving portion 50a.

[0107] The columnar portion 71 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 72 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 72 is formed, for example, using the same conductive material as the columnar portion 71. The wide portion 72 may be formed of a conductive material different from that of the columnar portion 71.

[0108] The height (length in the z-axis direction) of the gate pad 70 is the sum of the height (length in the z-axis direction) of the columnar portion 71 and the thickness (length in the z-axis direction) of the wide portion 72. The height of the gate pad 70 is, for example, more than 0 mm and not more than 1 mm (for example, not less than several tens of μm and not more than several hundreds of μm). As shown in FIG. 2, the height of the columnar portion 71 is greater (longer) than the thickness of the wide portion 72. The height of the columnar portion 71 may be equal to or less than the thickness of the wide portion 72.

[0109] The source pad 75 overlaps the main surface source electrode 55 in a plan view and is electrically connected to the main surface source electrode 55. The source pad 75 is provided on the main surface source electrode 55. The source pad 75 extends in a thick plate shape in the normal direction (z-axis direction) of the upper surface 56 of the main surface source electrode 55. In a plan view, the area of ​​the source pad 75 is smaller than the area of ​​the main surface source electrode 55.

[0110] The source pad 75 covers the upper surface 56 of the main surface source electrode 55. The source pad 75 also covers a part of the flat portion 63a and the second end portion 63c of the upper insulating layer 63. The source pad 75 also covers a part of the flat portion 65a and the end portion 65b of the end insulating layer 65. The thickness (length in the z-axis direction) of the source pad 75 is larger (longer) than the thicknesses (length in the z-axis direction) of the upper insulating layer 63 and the end insulating layer 65.

[0111] Specifically, the thickness of the source pad 75 is greater (longer) than the maximum thickness of the portion of the upper insulating layer 63 located on the main surface source electrode 55 and the maximum thickness of the portion of the end insulating layer 65 located on the main surface source electrode 55. As a result, the top of the source pad 75 is higher than the top of the upper insulating layer 63 and the top of the end insulating layer 65.

[0112] The source pad 75 has a side surface 77 that extends vertically or substantially vertically. The side surface 77 does not necessarily need to extend linearly in a cross-sectional view, and may extend curvedly or unevenly. The side surface 77 is located in a region where the main surface source electrode 55 and the upper insulating layer 63 overlap in a plan view, or where the main surface source electrode 55 and the end insulating layer 65 overlap in a plan view.

[0113] Specifically, the side surface 77 is located on the flat portion 63a of the upper insulating layer 63 or on the flat portion 65a of the end insulating layer 65. That is, the source pad 75 is in contact with the main surface source electrode 55 and the upper insulating layer 63, or the main surface source electrode 55 and the end insulating layer 65. In this embodiment, the source pad 75 is in contact with the main surface source electrode 55, the upper insulating layer 63, and the end insulating layer 65. This allows the source pad 75 to be stably formed, similar to the case of the columnar portion 71.

[0114] The source pad 75 has a top surface 76 that is used for electrical connection between the semiconductor device 1 (vertical transistor 2) and other circuits. In this embodiment, the top surface 76 of the source pad 75 is connected to a power supply circuit that supplies a source voltage. For example, a metal wire is connected to the top surface 76 of the source pad 75 by wire bonding. The metal wire includes at least one metal such as aluminum, copper, or gold. In this embodiment, an aluminum wire is wedge bonded to the source pad 75.

[0115] The source pad 75 is spaced apart from the gate pad 70 in plan view. This makes it possible to suppress short circuits caused by contact between the source pad 75 and the gate pad 70. The source pad 75 is formed of a conductive material. Specifically, the source pad 75 includes a metal material such as copper or a copper alloy mainly composed of copper. The source pad 75 is formed of, for example, the same material as the gate pad 70. In this case, the source pad 75 can be formed in the same process as the gate pad 70. The source pad 75 may be formed of a material different from that of the gate pad 70.

[0116] The source pad 75 has an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a planar view. Preferably, the source pad 75 has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a planar view. On the other hand, the gate pad 70 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a planar view. Preferably, the gate pad 70 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a planar view.

[0117] The source pad 75 is disposed in a region including the center position of the semiconductor layer 10 (first main surface 11) in a plan view. The gate pad 70 is disposed in a region avoiding the source pad 75. The gate pad 70 may be disposed in a region including the center position of the semiconductor layer 10 (first main surface 11). In this case, the source pad 75 may be disposed so as to surround the periphery of the gate pad 70.

[0118] The semiconductor device 1 includes a mold layer 80 filled between the source pad 75 and the gate pad 70. Specifically, the mold layer 80 fills the space between the gate pad 70 and the source pad 75. The mold layer 80 also covers the upper insulating layer 63 and the end insulating layer 65. The mold layer 80 is also provided in an annular shape along the outer periphery of the semiconductor layer 10 (the periphery of the first main surface 11) in a plan view.

[0119] The mold layer 80 is formed of an insulating material. The mold layer 80 may contain a thermosetting resin. For example, the mold layer 80 contains an epoxy resin. For example, the mold layer 80 may contain an epoxy resin containing carbon, glass fiber, or the like. The thickness (length in the z-axis direction) of the mold layer 80 is, for example, more than 0 mm and 1 mm or less (for example, tens of μm or more and hundreds of μm or less). The thickness of the mold layer 80 may be greater than the thickness of the semiconductor layer 10.

[0120] In this embodiment, the mold layer 80 has an upper surface 81 formed flush with the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75. That is, no step is formed at the boundary between the upper surface 73 of the gate pad 70, the upper surface 76 of the source pad 75, and the upper surface 81 of the mold layer 80. In this case, the upper surface 73 of the gate pad 70 may be a ground surface. Also, the upper surface 76 of the source pad 75 may be a ground surface. Also, the upper surface 81 of the mold layer 80 may be a ground surface. That is, the upper surface 81 of the mold layer 80 may form a ground surface together with the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75.

[0121] A method for manufacturing the semiconductor device 1 according to the first embodiment will be described below. Figures 6A to 6G are cross-sectional views showing a step of the method for manufacturing the semiconductor device shown in Figure 1. In the following, the method for manufacturing the configuration above the semiconductor layer 10 will be mainly described. Known methods can be used to form the trench gate structure 21, the trench source structure 31, and each well region (each semiconductor region) in the semiconductor layer 10.

[0122] First, as shown in FIG. 6A, a lower insulating layer 61 is formed on the first main surface 11 of a semiconductor layer 10 (semiconductor wafer). The lower insulating layer 61 has a plurality of source contact holes 61b. For example, in this process, an insulating film containing silicon oxide or the like is first formed by plasma CVD (Chemical Vapor Deposition). Next, a part of the formed insulating film is removed by photolithography and etching. As a result, the lower insulating layer 61 having a plurality of source contact holes 61b is formed.

[0123] Next, as shown in FIG. 6B, the main surface gate electrode 50 and the main surface source electrode 55 are formed. For example, in this step, a metal film is first formed on the entire surface of the first main surface 11 by vapor deposition or sputtering so as to cover the lower insulating layer 61. Next, a part of the formed metal film is removed by photolithography and etching. This causes the metal film to be patterned, and the main surface gate electrode 50 and the main surface source electrode 55 are formed. The main surface gate electrode 50 and the main surface source electrode 55 may be formed in different steps by repeating a step of forming a metal film using different materials and a step of patterning the metal film.

[0124] Next, as shown in FIG. 6C, a side insulating layer 62, an upper insulating layer 63, and an end insulating layer 65 are formed. The upper insulating layer 63 has a through hole 64. For example, this process includes a coating process and an exposure and development process. In the coating process, a liquid photosensitive resin material that is the source of each insulating layer is applied to the upper surface 52 of the main surface gate electrode 50 and the upper surface 56 of the main surface source electrode 55 by a spin coating method. In the exposure and development process, after the photosensitive resin material is hardened by exposure, unnecessary parts of the photosensitive resin material are removed by an ashing method or a wet etching method. As a result, the side insulating layer 62, the upper insulating layer 63, and the end insulating layer 65 are formed.

[0125] 6D, the columnar portion 71 is formed on the power receiving portion 50a of the main surface gate electrode 50, and the lower source pad 75a is formed on the main surface source electrode 55. For example, in this step, a metal plating layer is selectively formed by electrolytic plating or electroless plating on at least a part of the portion of the main surface gate electrode 50 that is not covered by the upper insulating layer 63, and on at least a part of the portion of the main surface source electrode 55 that is not covered by the upper insulating layer 63.

[0126] A part of the metal plating layer is also formed on the flat portion 63a, the first end 63b, and the second end 63c of the upper insulating layer 63. A part of the metal plating layer is also formed on the flat portion 65a and the end 65b of the end insulating layer 65. A part of the metal plating layer located on the power receiving portion 50a of the main surface gate electrode 50 and a part of the metal plating layer located on the flat portion 63a and the first end 63b of the upper insulating layer 63 are formed as a columnar portion 71 that is a part of the gate pad 70. A part of the metal plating layer located on the main surface source electrode 55 and a part of the metal plating layer located on the second end 63c of the upper insulating layer 63 and the end insulating layer 65 are formed as a lower source pad 75a that is a part of the source pad 75.

[0127] Next, as shown in FIG. 6E, the lower mold layer 80a is formed. For example, this process includes a film-forming process, a curing process, and a thinning process. In the film-forming process, a liquid resin material (e.g., epoxy resin as an example of a thermosetting resin) that is the source of the lower mold layer 80a is applied or printed on the entire surface of the first main surface 11 of the semiconductor layer 10. In this process, the columnar portion 71 and the lower source pad 75a are entirely covered with the resin material. The resin material also enters the space between the columnar portion 71 and the lower source pad 75a.

[0128] In the curing process, the applied or printed resin material is cured by heating. In the thinning process, the resin material is ground until the columnar portion 71 and the lower source pad 75a are exposed. As a result, as shown in FIG. 6E, the upper surface of the columnar portion 71, the upper surface of the lower mold layer 80a, and the upper surface of the lower source pad 75a are all formed flush with each other.

[0129] Next, as shown in FIG. 6F, the gate wiring layer 72b and the source wiring layer 75b are formed. The gate wiring layer 72b and the source wiring layer 75b are formed, for example, using the same material as the columnar portion 71 and the lower source pad 75a, respectively. The gate wiring layer 72b has the same size and shape as the wide portion 72 of the gate pad 70 in a plan view. The source wiring layer 75b has the same size and shape as the lower source pad 75a in a plan view. The gate wiring layer 72b and the source wiring layer 75b function as seed wirings that serve as film formation starting points in the next plating process.

[0130] 6G, the wide portion 72a of the gate pad 70 is formed on the gate wiring layer 72b, and the upper source pad 75c of the source pad 75 is formed on the source wiring layer 75b. For example, in this step, a metal plating layer is selectively formed only on the upper surface of the gate wiring layer 72b and the upper surface of the source wiring layer 75b by electrolytic plating or electroless plating.

[0131] Next, as shown in FIG. 6H, the upper mold layer 80b is formed. For example, this process includes a film-forming process, a curing process, and a thinning process. In the film-forming process, the entire wide portion 72a and the entire upper source pad 75c are covered with a resin material (for example, epoxy resin as an example of a thermosetting resin) by, for example, coating or printing.

[0132] In the curing process, the applied or printed resin material is cured by heating. In the thinning process, the resin material is ground until the wide portion 72a and the upper source pad 75c are exposed. As a result, as shown in FIG. 6H, the upper surface of the wide portion 72a, the upper surface of the upper mold layer 80b, and the upper surface of the upper source pad 75c are formed to be flush with each other.

[0133] 6H, the wide portion 72 of the gate pad 70 is formed by the gate wiring layer 72b and the wide portion 72a. The source pad 75 is formed by the lower source pad 75a, the source wiring layer 75b and the upper source pad 75c. The mold layer 80 is composed of the lower mold layer 80a and the upper mold layer 80b.

[0134] As described above, the gate pad 70 and the source pad 75 are formed by two-stage plating. In the above-mentioned Fig. 2 and the like, illustration and description of the specific layer structures of the gate pad 70, the source pad 75, and the mold layer 80 are omitted. The description of the specific layer structures of the gate pad 70, the source pad 75, and the mold layer 80 also applies to the above-mentioned Fig. 2 and the like.

[0135] Next, the semiconductor layer 10 is thinned by polishing the second main surface 12a of the semiconductor layer 10. Next, a drain electrode 40 is formed on the second main surface 12 by vapor deposition or sputtering. Thereafter, the semiconductor layer 10 and the like are selectively cut together with the mold layer 80 to manufacture the semiconductor device 1 shown in FIG.

[0136] The manufacturing method of the semiconductor device 1 is not limited to the above-mentioned method, but is merely an example. For example, the gate pad 70 and the source pad 75 may be formed by a film formation method other than plating.

[0137] As described above, the semiconductor device 1 according to the first embodiment is a semiconductor device including the vertical transistor 2. The semiconductor device 1 includes the semiconductor layer 10, the vertical transistor 2, the gate electrode 20, the source electrode 30, the drain electrode 40, the main surface gate electrode 50, the main surface source electrode 55, and the gate pad 70.

[0138] The semiconductor layer 10 has a first main surface 11 and a second main surface 12 opposite to the first main surface 11, and contains SiC as a main component. The vertical transistor 2 is provided on the first main surface 11. The gate electrode 20 is provided on the first main surface 11 as a gate electrode of the vertical transistor 2. The source electrode 30 is provided on the first main surface 11 at a distance from the gate electrode 20 as a source electrode of the vertical transistor 2.

[0139] The drain electrode 40 is provided on the second main surface 12 as a drain electrode of the vertical transistor 2. The main surface gate electrode 50 covers a part of the first main surface 11. The main surface source electrode 55 is provided spaced apart from the main surface gate electrode 50 in a plan view. The gate pad 70 overlaps the main surface gate electrode 50 in a plan view and is electrically connected to the main surface gate electrode 50. The main surface gate electrode 50 is smaller than the gate pad 70 in a plan view. For example, the main surface gate electrode 50 is electrically connected to the gate electrode 20. The main surface source electrode 55 is electrically connected to the source electrode 30.

[0140] If the main surface gate electrode 50 is used as an electrode pad for wire bonding instead of the gate pad 70, the main surface gate electrode 50 needs to be formed to have a size equivalent to that of the wide portion 72 of the gate pad 70. In this case, the region of the semiconductor layer 10 covered by the main surface gate electrode 50 is formed as the inactive region 4.

[0141] Therefore, the size of the inactive region 4 becomes the same as the size of the main surface gate electrode 50 formed to be the same size as the wide portion 72, and the active region 3 becomes smaller. In other words, the size of the inactive region 4 becomes much larger than the size of the inactive region 4 of the semiconductor device 1 according to this embodiment. Therefore, since the active region 3 becomes smaller, the semiconductor layer 10 cannot be effectively utilized, and it becomes difficult to reduce the size and cost.

[0142] In contrast, according to the semiconductor device 1 of this embodiment, a gate pad 70 (wide portion 72) is provided which is connected to the main surface gate electrode 50, and wire bonding is performed to the gate pad 70 (wide portion 72). Therefore, it is possible to ensure a gate pad 70 large enough to perform appropriate wire bonding while making the main surface gate electrode 50 small. This allows the main surface gate electrode 50 to be reduced in size, so that the region not covered by the main surface gate electrode 50 can be expanded and used as the active region 3. This realizes a semiconductor device 1 which can ensure a wide operating region.

[0143] For example, the gate pad 70 overlaps a part of the main surface source electrode 55 in a plan view. This allows the region directly below the wide portion 72 to be used as the active region 3. In addition, the main surface source electrode 55 provided directly below the wide portion 72 of the gate pad 70 makes it easy to ensure electrical connection to multiple source electrodes 30.

[0144] The second embodiment will be described below. The second embodiment is different from the first embodiment mainly in that the semiconductor device further includes an electrode for current detection and an electrode pad connected to the electrode for current detection, and the electrode for current detection is smaller than the electrode pad. The following mainly describes the differences from the first embodiment, and the description of the commonalities is omitted or simplified.

[0145] FIG. 7 is a cross-sectional view of the semiconductor device 101 according to the second embodiment. FIG. 8 is a plan view of the semiconductor device 101 shown in FIG. 7. FIG. 9 is a plan view of the upper surface of the electrode of the semiconductor device 101 along the line IX-IX in FIG. 7. Specifically, FIG. 7 shows a cross section along the line VII-VII in FIG. 8. Specifically, FIG. 9 is a plan view of the semiconductor device 101 as seen from the positive side of the z-axis, through the gate pad 70, the source pad 75, the current detection pad 170, and the mold layer 80 shown in FIG. 8. Although not shown in FIG. 7, the semiconductor device 101 includes a vertical transistor 2 that passes a current in the thickness direction of the semiconductor layer 10, as in the first embodiment.

[0146] 7 to 9, the semiconductor device 101 includes a main surface gate electrode 50, a main surface source electrode 55, and a current detection electrode 150. The main surface gate electrode 50 and the main surface source electrode 55 according to the second embodiment are different in arrangement or shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the main surface gate electrode 50 and the main surface source electrode 55 according to the second embodiment will be omitted.

[0147] The current detection electrode 150 is an example of a third electrode. The current detection electrode 150 is disposed at a distance from the main surface gate electrode 50 and the main surface source electrode 55 in a plan view. In this embodiment, the current detection electrode 150 is disposed in a region defined by the main surface gate electrode 50 and the main surface source electrode 55 in a plan view. The current detection electrode 150 corresponds to a part obtained by separating a part of the main surface source electrode 55 according to the first embodiment.

[0148] The current detection electrode 150 includes at least one of conductive polysilicon, metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, and metal nitrides such as titanium nitride. The current detection electrode 150 is formed of the same material as the main surface gate electrode 50 and the main surface source electrode 55, for example.

[0149] The current detection electrode 150 is electrically connected to N (N-munber) source electrodes 30 among the multiple source electrodes 30 provided on the first main surface 11 of the semiconductor layer 10. N is a natural number. N is, for example, 10 or less. The vertical transistor 2 included in the semiconductor device 101 can flow a drain current from the drain electrode 40 provided on the second main surface 12 of the semiconductor layer 10 toward the multiple source electrodes 30 provided on the first main surface 11 of the semiconductor layer 10. The current detection electrode 150 is an electrode for extracting a current (one component of a drain current) flowing through the N source electrodes 30 among the multiple source electrodes 30. The N source electrodes 30 are used for detecting a current (drain current) flowing through the vertical transistor 2.

[0150] 7, the current detection electrode 150 is provided on the lower insulating layer 61. The current detection electrode 150 is electrically connected to one or more source electrodes 30 via one or more source contact holes 61b provided in the lower insulating layer 61. For example, the number of source contact holes 61b corresponds to N. In other words, by adjusting the number of source contact holes 61b, the number N of source electrodes 30 to which the current detection electrode 150 is connected can be adjusted.

[0151] The main surface source electrode 55 is electrically connected to M source electrodes 30 out of the multiple source electrodes 30. M is a natural number greater than N. M is, for example, 100 to 10,000 times N. Therefore, a current that is 1 / 10,000 to 1 / 100 of the current flowing through the main surface source electrode 55 flows through the current detection electrode 150 connected to the N source electrodes 30.

[0152] As a result, even if a large drain current flows between the drain electrode 40 and the multiple source electrodes 30 of the semiconductor device 101 due to some factor, the current flowing through the current detection electrode 150 can be reduced. For example, the maximum amount of current flowing through the current detection electrode 150 can be suppressed to about 1 A. As a result, the current detection electrode 150 can be used to detect an increase in current within the current detection range. In other words, an increase or decrease in the drain current can be indirectly detected within the detection range of the current detection electrode 150.

[0153] The current detection electrode 150 is smaller than the current detection pad 170 in a plan view. The shape of the current detection electrode 150 in a plan view is, for example, a square or a rectangle. The length of one side of the current detection electrode 150 is 5 μm or more and 50 μm or less. As an example, the current detection electrode 150 may have a square shape in a plan view and a size of about 20 μm×20 μm. As shown in FIG. 9, the size of the current detection electrode 150 is the same as the size of the power receiving portion 50a of the main surface gate electrode 50. The size of the current detection electrode 150 may be smaller than the size of the power receiving portion 50a. The size of the current detection electrode 150 may be larger than the size of the power receiving portion 50a.

[0154] The current detection electrode 150 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the current detection electrode 150 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11). The current detection electrode 150 is disposed in a region avoiding the main surface source electrode 55 and the main surface gate electrode 50 in a plan view. The current detection electrode 150 may be disposed in a region including the center position of the semiconductor layer 10. In this case, the main surface source electrode 55 may be disposed so as to surround the periphery of the current detection electrode 150.

[0155] 7 and 8, the semiconductor device 101 includes a gate pad 70, a source pad 75, and a current detection pad 170. The gate pad 70 and the source pad 75 according to the second embodiment are different in arrangement or shape from those of the first embodiment, but their configurations are substantially the same as those of the first embodiment. Therefore, a description of the gate pad 70 and the source pad 75 according to the second embodiment will be omitted.

[0156] The current detection pad 170 is an example of a second electrode pad. The current detection pad 170 overlaps the current detection electrode 150 in a plan view and is electrically connected to the current detection electrode 150. In the semiconductor device 101 according to this embodiment, the current detection pad 170 connected to the current detection electrode 150 has a similar configuration to the gate pad 70.

[0157] 7, the current detection pad 170 includes a columnar portion 171 and a wide portion 172. The columnar portion 171 is an example of a first conductive layer provided on the current detection electrode 150. The columnar portion 171 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 152 of the current detection electrode 150. The columnar portion 171 is connected to the current detection electrode 150 via a through-hole 164 provided in the upper insulating layer 63.

[0158] The columnar portion 171 covers the upper surface 152 of the current detection electrode 150. The columnar portion 171 further covers a part of the flat portion 63a and the first end portion 63b of the upper insulating layer 63. The height (length in the z-axis direction) of the columnar portion 171 is greater (longer) than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 171 is greater (longer) than the maximum thickness of the portion of the upper insulating layer 63 located on the current detection electrode 150. As a result, the top of the columnar portion 171 is higher than the top of the upper insulating layer 63.

[0159] The columnar portion 171 has a side surface 174 that extends vertically or substantially vertically. The side surface 174 does not necessarily need to extend linearly in a cross-sectional view, and may extend curvedly or unevenly. The side surface 174 is located on a region where the current detection electrode 150 and the upper insulating layer 63 overlap in a plan view. Specifically, the side surface 174 is located on the flat portion 63a of the upper insulating layer 63. That is, the columnar portion 171 covers the current detection electrode 150 and the upper insulating layer 63. This allows the columnar portion 171 to be stably formed, similar to the columnar portion 71 according to the first embodiment.

[0160] The wide portion 172 is an example of a second conductive layer provided on the upper end of the columnar portion 171. The wide portion 172 is a portion obtained by enlarging the size of the upper end of the columnar portion 171 in the xy plane. The size and shape of the wide portion 172 in a planar view correspond to the size and shape of the current detection pad 170 in a planar view. The wide portion 172 has an upper surface 173 that is used for electrical connection between the semiconductor device 101 (vertical transistor 2) and other circuits.

[0161] In this embodiment, the upper surface 173 of the wide portion 172 is connected to a control circuit that controls the semiconductor device 101 (vertical transistor 2) based on the detected current. For example, a metal wire is connected to the upper surface 173 of the wide portion 172 by wire bonding. The metal wire includes at least one of metals such as aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge bonded to the current detection pad 170 (upper surface 173 of the wide portion 172).

[0162] In order to perform wire bonding appropriately, the wide portion 172 needs to have a certain size or more. The shape of the wide portion 172 in a plan view is, for example, a square. In this case, the size of the wide portion 172 may be 800 μm×800 μm or more and 1 mm×1 mm or less. In this case, the direction of connection of the metal wire to the wide portion 172 can be any direction. The size of the wide portion 172 may be larger than 1 mm×1 mm.

[0163] The shape of the wide portion 172 in a plan view may be rectangular. In this case, the size of the wide portion 172 may be 400 mm × 800 mm or more. The size of the wide portion 172 is the same as the size of the wide portion 72 of the gate pad 70. The size of the wide portion 172 may be smaller than the size of the wide portion 72. The size of the wide portion 172 may be larger than the size of the wide portion 72.

[0164] In a plan view, the area of ​​the wide portion 172 (i.e., the area of ​​the current detection pad 170) is larger than the area of ​​the current detection electrode 150. The area of ​​the wide portion 172 is 200 times or more and 40,000 times or less than the area of ​​the current detection electrode 150. The area of ​​the wide portion 172 may be 400 times or more than the area of ​​the current detection electrode 150. As an example, the area of ​​the wide portion 172 may be about 2,500 times the area of ​​the current detection electrode 150.

[0165] The columnar portion 171 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 172 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 172 is formed, for example, using the same conductive material as the columnar portion 171. The wide portion 172 may be formed using a conductive material different from that of the columnar portion 171. The current detection pad 170 is formed, for example, using the same material as the gate pad 70 and the source pad 75. This allows the current detection pad 170, the gate pad 70, and the source pad 75 to be formed in the same process.

[0166] The height (length in the z-axis direction) of the current detection pad 170 is the sum of the height (length in the z-axis direction) of the columnar portion 171 and the thickness (length in the z-axis direction) of the wide portion 172. The height of the current detection pad 170 is, for example, more than 0 mm and not more than 1 mm (for example, not less than several tens of μm and not more than several hundreds of μm). As shown in FIG. 7, the height of the columnar portion 171 is greater (longer) than the thickness of the wide portion 172. The height of the columnar portion 171 may be equal to or less than the thickness of the wide portion 172.

[0167] The current detection pad 170 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the current detection pad 170 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. The current detection pad 170 is disposed in a region avoiding the gate pad 70 and the source pad 75. The current detection pad 170 may be disposed in a region including the center position of the semiconductor layer 10 (first main surface 11). In this case, the source pad 75 may be disposed so as to surround the periphery of the current detection pad 170.

[0168] In this embodiment, as shown in Fig. 7, the semiconductor device 101 includes an active region 103 and a non-active region 104. The active region 103 is a main region through which the drain current of the vertical transistor 2 flows. The active region 103 is a region overlapping with the main surface source electrode 55 in a plan view. The active region 103 does not include a region overlapping with either the main surface gate electrode 50 or the current detection electrode 150. On the other hand, a part of the region overlapping with the gate pad 70 and the current detection pad 170 in a plan view is included in the active region 103.

[0169] The inactive region 104 is a region that does not operate as the vertical transistor 2. The inactive region 104 is a region other than the active region 103 in a plan view. As shown in FIG. 7 , the inactive region 104 includes the current detection region 102. The current detection region 102 is a region that overlaps with the current detection electrode 150 in a plan view. In this embodiment, the region that overlaps with the main surface gate electrode 50 or the current detection electrode 150 in a plan view is included in the inactive region 104.

[0170] Specifically, the current detection pad 170 overlaps a part of the main surface source electrode 55 in a plan view. In other words, a part of the main surface source electrode 55 is located directly below the current detection pad 170. In this embodiment, the main surface source electrode 55 is extended to a region where it overlaps with the current detection pad 170 in a plan view, so that a part of the region where the current detection pad 170 overlaps with the main surface source electrode 55 can be used as the active region 103. This makes it possible to secure a larger area for the active region 103 while securing the area for the current detection pad 170.

[0171] As described above, the semiconductor device 101 according to the second embodiment further includes a plurality of source electrodes 30, a current detection electrode 150, and a current detection pad 170. The plurality of source electrodes 30 are arranged at intervals from each other in a plan view. The current detection electrode 150 is provided at intervals from the main surface gate electrode 50 and the main surface source electrode 55 in a plan view, and is electrically connected to N (N is a natural number) source electrodes 30. The current detection pad 170 overlaps the current detection electrode 150 in a plan view, and is electrically connected to the current detection electrode 150. The main surface source electrode 55 is electrically connected to M (M is a natural number larger than N) source electrodes 30. The current detection electrode 150 is smaller than the current detection pad 170 in a plan view.

[0172] As described above, the number N of source electrodes 30 to which the current detection electrode 150 is connected (i.e., the source electrodes 30 included in the current detection region 102) may be, for example, less than or equal to 10. In contrast, as shown in FIG. 7, the number of source electrodes 30 included in the area 105 directly below the wide portion 172 of the current detection pad 170 is much more than 10.

[0173] For this reason, if the current detection electrode 150 is used as an electrode pad for wire bonding instead of the current detection pad 170, the current detection electrode 150 needs to be formed to have a size equivalent to that of the wide portion 172 of the current detection pad 170. In this case, the area 105 directly below the wide portion 172 of the current detection pad 170 is formed as the inactive area 104.

[0174] Therefore, the size of the inactive region 104 becomes the size of the current detection electrode 150 formed to be the same size as the wide portion 172, and the active region 103 becomes small. In other words, the size of the inactive region 104 becomes much larger than the size of the inactive region 104 of the semiconductor device 101 according to this embodiment. Therefore, since the active region 103 becomes small, the semiconductor layer 10 cannot be effectively utilized, and it becomes difficult to reduce the size and cost.

[0175] In contrast, according to the semiconductor device 101 of this embodiment, a current detection pad 170 (wide portion 172) is provided which is connected to the current detection electrode 150, and wire bonding is performed on the current detection pad 170 (wide portion 172). Therefore, it is possible to ensure a current detection pad 170 that is large enough to perform appropriate wire bonding while making the current detection electrode 150 small. In addition, since the current detection electrode 150 can be reduced in size, the area not covered by the current detection electrode 150 can be expanded and used as the active area 103. Thus, a semiconductor device 101 that can ensure a wide operating area is realized.

[0176] The manufacturing method of the semiconductor device 101 according to this embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment. Specifically, the semiconductor device 101 can be manufactured by adjusting the shapes in each of the patterning steps of the main surface gate electrode 50, the main surface source electrode 55, and the current detection electrode 150, the patterning step of the insulating layer 60, and the patterning step of the gate pad 70, the source pad 75, and the current detection pad 170.

[0177] In the semiconductor device 101 according to this embodiment, an example has been described in which the gate pad 70 has a similar configuration to the current detection pad 170 , but the gate pad 70 may have a similar configuration to the source pad 75 .

[0178] Fig. 10 is a plan view of a modified example of the semiconductor device 101 according to the second embodiment (hereinafter referred to as semiconductor device 101a). Fig. 11 is a plan view of the upper surface of the electrode of the semiconductor device 101a shown in Fig. 10. Figs. 10 and 11 correspond to Figs. 8 and 9 of the second embodiment, respectively.

[0179] In the semiconductor device 101a according to the modification, the main surface gate electrode 50A and the gate pad 70a have the same size and shape in a plan view. That is, in a plan view, the main surface gate electrode 50A is larger than the power receiving portion 50a of the main surface gate electrode 50 according to the second embodiment. The current detection electrode 150 and the current detection pad 170 are the same as those in the second embodiment. That is, the semiconductor device 101a according to the modification includes the current detection electrode 150 as an example of a first electrode, and the current detection pad 170 as an example of a first electrode pad.

[0180] In this way, in the semiconductor device 101a according to the modified example, a configuration (specifically, the current detection pad 170) that increases the area in a plan view is applied only to the current detection electrode 150. This allows the current detection electrode 150 to be made smaller than the current detection pad 170 while ensuring the area of ​​the pad for electrical connection to the current detection electrode 150. Therefore, a part of the area that overlaps with the current detection pad 170 in a plan view can be effectively used as an active area. This allows a wide operating area to be ensured.

[0181] The third embodiment will be described below. The third embodiment differs from the first embodiment mainly in that the semiconductor device further includes a diode having an electrode and an electrode pad connected to the electrode of the diode, and the electrode of the diode is smaller than the electrode pad. The following mainly describes the differences from the first embodiment, and the description of the commonalities is omitted or simplified.

[0182] FIG. 12 is a cross-sectional view showing a main part of the semiconductor device 201 according to the third embodiment. FIG. 13 is a plan view of the semiconductor device 201 shown in FIG. 12. FIG. 14 is a plan view taken along the line XIV-XIV shown in FIG. 12. Specifically, FIG. 12 shows a cross section taken along the line XII-XII in FIG. 13. Specifically, FIG. 14 is a plan view showing the semiconductor device 201 as seen from the positive side of the z-axis, through the gate pad 70, the source pad 75, the anode electrode pad 270, the cathode electrode pad 275, and the mold layer 80 shown in FIG. 13.

[0183] 12, the semiconductor device 201 includes a diode 290 provided on the first main surface 11 of the semiconductor layer 10. In this embodiment, the diode 290 is a pn diode and includes a p-type semiconductor layer 291 and an n-type semiconductor layer 292. For example, the p-type semiconductor layer 291 includes polysilicon doped with a p-type impurity, and the n-type semiconductor layer 292 includes polysilicon doped with an n-type impurity. The p-type semiconductor layer 291 and the n-type semiconductor layer 292 are in contact with each other and form a pn diode having a pn junction.

[0184] The diode 290 is provided in a recess 293 provided in the first main surface 11 of the semiconductor layer 10. The recess 293 is formed by digging down the first main surface 11 of the semiconductor layer 10 toward the second main surface 12. For example, the recess 293 has the same depth as the depth of the gate trench 22. The recess 293 can be formed in the same process as the gate trench 22.

[0185] The recess 293 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the recess 293 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. The recess 293 is provided in a region avoiding the main surface source electrode 55 and the main surface gate electrode 50 in a plan view. The recess 293 may be provided in a region including the center position of the semiconductor layer 10 (first main surface 11). In this case, the main surface source electrode 55 may be disposed so as to surround the periphery of the recess 293.

[0186] The semiconductor device 201 includes an insulating layer 223 formed to cover the bottom wall and side walls of the recess 293. The insulating layer 223 is interposed between the semiconductor layer 10 and the diode 290. That is, the diode 290 is provided on the insulating layer 223. The insulating layer 223 includes, for example, silicon oxide. The insulating layer 223 may include at least one of undoped silicon, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride. The insulating layer 223 includes, for example, the same material as the gate insulating layer 23 and has the same thickness as the gate insulating layer 23. As a result, the insulating layer 223 can be formed in the same process as the gate insulating layer 23.

[0187] Note that the semiconductor layer 10 may not be provided with either or both of the recess 293 and the insulating layer 223. The diode 290 may be provided on the first main surface 11 of the semiconductor layer 10. In this case, the diode 290 may be disposed on the insulating layer 223 that covers the first main surface 11.

[0188] The diode 290 includes an anode electrode 250 and a cathode electrode 255. The temperature of the semiconductor device 201 can be detected based on the magnitude of the voltage between the anode electrode 250 and the cathode electrode 255. In other words, the diode 290 is used as a temperature sensor (temperature-sensitive diode).

[0189] The anode electrode 250 is electrically connected to the p-type semiconductor layer 291. The anode electrode 250 includes, for example, at least one of conductive polysilicon, a metal such as titanium, nickel, copper, aluminum, silver, gold, or tungsten, or a metal nitride such as titanium nitride.

[0190] The cathode electrode 255 is electrically connected to the n-type semiconductor layer 292. As shown in Fig. 14, the cathode electrode 255 is provided at a distance from the anode electrode 250 in a plan view. In this embodiment, a lower insulating layer 61 is provided between the cathode electrode 255 and the anode electrode 250. Furthermore, the anode electrode 250 and the cathode electrode 255 are provided at a distance from each of the main surface gate electrode 50 and the main surface source electrode 55 in a plan view.

[0191] 14, the main surface gate electrode 50 and the main surface source electrode 55 according to the third embodiment are different in arrangement or shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the main surface gate electrode 50 and the main surface source electrode 55 according to the third embodiment will be omitted.

[0192] The cathode electrode 255 includes at least one of conductive polysilicon, metals such as titanium, nickel, copper, aluminum, silver, gold, and tungsten, and metal nitrides such as titanium nitride. The cathode electrode 255 may be formed using the same material as the anode electrode 250.

[0193] 12 and 13, the semiconductor device 201 includes a gate pad 70, a source pad 75, an anode electrode pad 270, and a cathode electrode pad 275. The gate pad 70 and the source pad 75 according to the third embodiment are different in arrangement or shape from those in the first embodiment, but their configurations are substantially the same as those in the first embodiment. Therefore, a description of the gate pad 70 and the source pad 75 according to the third embodiment will be omitted.

[0194] The anode electrode pad 270 overlaps the anode electrode 250 in a plan view, and is electrically connected to the anode electrode 250. In the semiconductor device 201 according to this embodiment, the anode electrode pad 270 connected to the anode electrode 250 has a similar configuration to the gate pad 70.

[0195] 12, the anode electrode pad 270 includes a columnar portion 271 and a wide portion 272. The columnar portion 271 is an example of a first conductive layer provided on the anode electrode 250. The columnar portion 271 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 251 of the anode electrode 250.

[0196] The wide portion 272 is an example of a second conductive layer provided on the upper end of the columnar portion 271. The wide portion 272 is a portion obtained by enlarging the size of the upper end of the columnar portion 271 in the xy plane. The size and shape of the wide portion 272 in a planar view correspond to the size and shape of the anode electrode pad 270 in a planar view. The wide portion 272 has an upper surface 273 that is used for electrical connection between the semiconductor device 201 (diode 290) and other circuits.

[0197] In this embodiment, the upper surface 273 of the wide portion 272 is connected to a voltmeter or the like that detects the voltages of the anode electrode 250 and the cathode electrode 255. For example, a metal wire is connected to the upper surface 273 of the wide portion 272 by wire bonding. The metal wire includes at least one of metals such as aluminum, copper, and gold. In this embodiment, the aluminum wire is wedge bonded to the anode electrode pad 270 (the upper surface 273 of the wide portion 272).

[0198] In order to perform wire bonding appropriately, the wide portion 272 needs to have a certain size or more. The shape and size of the wide portion 272 in a plan view are, for example, the same as the shape and size of the wide portion 72 of the gate pad 70 in a plan view. At least one of the shape and size of the wide portion 272 in a plan view may be different from the shape and size of the wide portion 72 in a plan view.

[0199] In a plan view, the area of ​​the wide portion 272 (i.e., the area of ​​the anode electrode pad 270) is larger than the area of ​​the anode electrode 250. The area of ​​the wide portion 272 may be 200 times or more and 40,000 times or less than the area of ​​the anode electrode 250. The area of ​​the wide portion 272 may be 400 times or more than the area of ​​the anode electrode 250. As an example, the area of ​​the wide portion 272 may be about 2,500 times the area of ​​the anode electrode 250.

[0200] The columnar portion 271 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 272 includes a metal material such as copper or a copper alloy mainly composed of copper. The wide portion 272 is formed, for example, using the same conductive material as the columnar portion 271. The wide portion 272 may be formed using a conductive material different from that of the columnar portion 271.

[0201] The height (length in the z-axis direction) of the anode electrode pad 270 is the sum of the height (length in the z-axis direction) of the columnar portion 271 and the thickness (length in the z-axis direction) of the wide portion 272. The height of the anode electrode pad 270 is, for example, more than 0 mm and not more than 1 mm (for example, not less than several tens of μm and not more than several hundreds of μm). As shown in FIG. 12, the height of the columnar portion 271 is greater (longer) than the thickness of the wide portion 272. The height of the columnar portion 271 may be equal to or less than the thickness of the wide portion 272.

[0202] The cathode electrode pad 275 overlaps the cathode electrode 255 in a plan view and is electrically connected to the cathode electrode 255. In the semiconductor device 201 according to this embodiment, the cathode electrode pad 275 connected to the cathode electrode 255 has a similar configuration to the gate pad 70 and the anode electrode pad 270.

[0203] 12, the cathode electrode pad 275 includes a columnar portion 276 and a wide portion 277. The columnar portion 276 is an example of a first conductive layer provided on the cathode electrode 255. The columnar portion 276 extends in a columnar shape in the normal direction (z-axis direction) of the upper surface 256 of the cathode electrode 255.

[0204] The wide portion 277 is an example of a second conductive layer provided on the upper end of the columnar portion 276. The wide portion 277 is a portion obtained by enlarging the size of the upper end of the columnar portion 276 in the xy plane. The size and shape of the wide portion 277 in a planar view correspond to the size and shape of the cathode electrode pad 275 in a planar view.

[0205] The wide portion 277 has an upper surface 278 that is used for electrically connecting the semiconductor device 201 (diode 290) to other circuits. In this embodiment, the upper surface 278 of the wide portion 277 is connected to a voltmeter or the like that detects the voltages of the anode electrode 250 and the cathode electrode 255. For example, a metal wire is connected to the upper surface 278 of the wide portion 277 by wire bonding.

[0206] In terms of shape, material, etc., the columnar portion 276 and wide portion 277 of the cathode electrode pad 275 are similar to the columnar portion 276 and wide portion 277 of the anode electrode pad 270. Therefore, a description of the shape, material, etc. of the cathode electrode pad 275 will be omitted.

[0207] The anode electrode pad 270 and the cathode electrode pad 275 are formed, for example, using the same material as the gate pad 70 and the source pad 75. This allows the anode electrode pad 270, the cathode electrode pad 275, the gate pad 70 and the source pad 75 to be formed in the same process.

[0208] The semiconductor device 201 may include an insulating layer (not shown) covering a part of the upper surface 251 of the anode electrode 250 and a part of the upper surface 256 of the cathode electrode 255. The insulating layer is made of an organic material such as polyimide or PBO. In this case, the side surface of the columnar portion 271 of the anode electrode pad 270 and the side surface of the columnar portion 276 of the cathode electrode pad 275 may each be provided on a flat portion of the insulating layer, similar to the side surface 74 of the columnar portion 71 according to the first embodiment.

[0209] Each of the anode electrode pad 270 and the cathode electrode pad 275 has an area, in plan view, of 20% or less of the area of ​​the semiconductor layer 10 (first main surface 11). Preferably, each of the anode electrode pad 270 and the cathode electrode pad 275 has an area, in plan view, of 10% or less of the area of ​​the semiconductor layer 10 (first main surface 11).

[0210] Moreover, the anode electrode pad 270 and the cathode electrode pad 275 are disposed in a region avoiding the gate pad 70 and the source pad 75. One of the anode electrode pad 270 and the cathode electrode pad 275 may be disposed in a region including the center position of the semiconductor layer 10 (first main surface 11), or the source pad 75 may be disposed so as to surround the periphery of the anode electrode pad 270 and the cathode electrode pad 275.

[0211] In this embodiment, as shown in Fig. 12, the semiconductor device 201 includes an active region 203 and a non-active region 204. The active region 203 is a main region through which the drain current of the vertical transistor 2 flows. The active region 203 is a region overlapping with the main surface source electrode 55 in a plan view. The active region 203 does not include a region overlapping with either the main surface gate electrode 50 or the recess 293. Parts of the regions overlapping with the gate pad 70, the anode electrode pad 270, and the cathode electrode pad 275 in a plan view are included in the active region 103.

[0212] The inactive region 204 is a region that does not operate as the vertical transistor 2. The inactive region 204 is a region other than the active region 203 in a plan view. As shown in Fig. 12, a diode 290 is formed in the inactive region 204. In this embodiment, a region that overlaps with the main surface gate electrode 50 or the recess 293 in a plan view is included in the inactive region 204.

[0213] Specifically, the anode electrode pad 270 and the cathode electrode pad 275 each overlap a part of the main surface source electrode 55 in a plan view. That is, a part of the main surface source electrode 55 is located directly below the anode electrode pad 270 and directly below the cathode electrode pad 275. In this embodiment, the main surface source electrode 55 is extended to a region overlapping the anode electrode pad 270 or the cathode electrode pad 275 in a plan view.

[0214] Therefore, a part of the area where the main surface source electrode 55 and the anode electrode pad 270 overlap, or a part of the area where the main surface source electrode 55 and the cathode electrode pad 275 overlap can be used as the active area 203. This makes it possible to secure a larger area for the active area 203 while securing the areas for the anode electrode pad 270 and the cathode electrode pad 275.

[0215] As described above, the semiconductor device 201 according to this embodiment includes the diode 290, the anode electrode pad 270, and the cathode electrode pad 275. The diode 290 includes the anode electrode 250 and the cathode electrode 255, and is provided on the first main surface 11. The anode electrode pad 270 overlaps the anode electrode 250 in a plan view and is electrically connected to the anode electrode 250. The cathode electrode pad 275 overlaps the cathode electrode 255 in a plan view and is electrically connected to the cathode electrode 255. The anode electrode 250 is smaller than the anode electrode pad 270 in a plan view. The cathode electrode 255 is smaller than the cathode electrode pad 275 in a plan view.

[0216] If the anode electrode 250 is used as an electrode pad for wire bonding instead of the anode electrode pad 270, the anode electrode 250 needs to have a size equivalent to that of the wide portion 272. On the other hand, if the cathode electrode 255 is used as an electrode pad for wire bonding instead of the cathode electrode pad 275, the cathode electrode 255 needs to have a size equivalent to that of the wide portion 277.

[0217] In these cases, the area covered by the anode electrode 250 and the cathode electrode 255 is formed as the inactive area 204. Therefore, the size of the inactive area is the same as the size of the anode electrode 250 and the cathode electrode 255 formed to be the same size as the wide portion 272 and the wide portion 277, and the active area 203 is small. In other words, the size of the inactive area is much larger than the size of the inactive area 204 of the semiconductor device 201 according to this embodiment. Therefore, the semiconductor layer 10 cannot be effectively utilized, making it difficult to reduce the size and cost.

[0218] In contrast, in the semiconductor device 201 according to this embodiment, an anode electrode pad 270 (wide portion 272) is provided which is connected to the anode electrode 250, and a cathode electrode pad 275 (wide portion 277) is provided which is connected to the cathode electrode 255. Wire bonding is performed on each of the anode electrode pad 270 (wide portion 272) and the cathode electrode pad 275 (wide portion 277).

[0219] Therefore, while making the anode electrode 250 and the cathode electrode 255 small, it is possible to ensure the anode electrode pad 270 and the cathode electrode pad 275, each of which has a size sufficient for appropriate wire bonding. In addition, since the anode electrode 250 and the cathode electrode 255 can be reduced in size, the area not covered by the anode electrode 250 or the cathode electrode 255 can be expanded and used as the active area 203. In this way, a semiconductor device 201 that can ensure a wide operating area is realized.

[0220] The manufacturing method of the semiconductor device 201 according to this embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment. Specifically, the semiconductor device 201 can be manufactured by adjusting the shapes in each of the patterning steps of the main surface gate electrode 50, the main surface source electrode 55, the anode electrode 250, and the cathode electrode 255, the patterning step of the insulating layer 60, and the patterning steps of the gate pad 70, the source pad 75, the anode electrode pad 270, and the cathode electrode pad 275.

[0221] In the semiconductor device 201 according to this embodiment, an example has been described in which the gate pad 70 has a configuration similar to that of the anode electrode pad 270 and the cathode electrode pad 275. However, the gate pad 70 may have a configuration similar to that of the source pad 75.

[0222] Fig. 15 is a plan view of a modified example of the semiconductor device 201 according to the third embodiment (hereinafter referred to as semiconductor device 201a). Fig. 16 is a plan view showing the upper surface of the electrode of the semiconductor device 201a shown in Fig. 15. Figs. 15 and 16 correspond to Figs. 13 and 14 of the third embodiment, respectively.

[0223] In the semiconductor device 201a according to the modification, the main surface gate electrode 50A and the gate pad 70a have the same size and shape in plan view. That is, in plan view, the main surface gate electrode 50A is larger than the power receiving portion 50a of the main surface gate electrode 50 according to the third embodiment.

[0224] The anode electrode 250, the cathode electrode 255, the anode electrode pad 270, and the cathode electrode pad 275 are the same as those in the third embodiment. That is, the semiconductor device 201a according to the modification includes the anode electrode 250 as an example of a first electrode, and the anode electrode pad 270 as an example of a first electrode pad. The semiconductor device 201a according to the modification includes the cathode electrode 255 as an example of a second electrode, and the cathode electrode pad 275 as an example of a second electrode pad.

[0225] In this way, in the semiconductor device 201a according to the modification, a configuration (specifically, the anode electrode pad 270 and the cathode electrode pad 275) for increasing the area in a plan view is applied only to the anode electrode 250 and the cathode electrode 255. In other words, the anode electrode 250 can be made smaller than the anode electrode pad 270, and the cathode electrode 255 can be made smaller than the cathode electrode pad 275, while ensuring the area of ​​the pads for electrical connection to the anode electrode 250 and the cathode electrode 255, respectively.

[0226] As a result, a part of the area overlapping with the anode electrode pad 270 or the cathode electrode pad 275 in a plan view can be expanded and effectively used as an active area, thereby ensuring a wide operating area.

[0227] Either the anode electrode pad 270 or the cathode electrode pad 275 may have the same configuration as the source pad 75. For example, the anode electrode 250 and the anode electrode pad 270 may have the same shape and size in a plan view. The cathode electrode 255 and the cathode electrode pad 275 may have the same shape and size in a plan view.

[0228] A semiconductor package having a semiconductor device will be described below as the fourth embodiment. Fig. 17 is a rear view showing an example of a semiconductor package 300 according to the fourth embodiment. Fig. 18 is a front view showing the internal structure of the semiconductor package 300 shown in Fig. 17.

[0229] 17 and 18, the semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, a terminal 302d, a terminal 302g, a terminal 302s, a bonding wire 303g, a bonding wire 303s, and a semiconductor device 1.

[0230] The package body 301 has a rectangular parallelepiped shape. The package body 301 houses the semiconductor device 1. In other words, the package body 301 is a sealing body that seals the semiconductor device 1. The package body 301 may contain an epoxy resin. The package body 301 is formed, for example, from an epoxy resin containing carbon, glass fiber, or the like.

[0231] Terminals 302d, 302g, and 302s protrude from the bottom of package body 301 and are arranged in a row along the bottom of package body 301. Terminals 302d, 302g, and 302s are formed of, for example, aluminum, but may be formed of other metal materials such as copper.

[0232] Inside the package body 301, the gate pad 70 of the semiconductor device 1 is electrically connected to a terminal 302g by a bonding wire 303g or the like. The source pad 75 of the semiconductor device 1 is electrically connected to a terminal 302s by a bonding wire 303s or the like. The drain electrode 40 of the semiconductor device 1 is joined to a wide portion of the terminal 302d located inside the package body 301 by solder or a sintered layer made of silver or copper or the like.

[0233] The semiconductor package 300 may include the semiconductor device 101, 101a, 201, or 201a instead of the semiconductor device 1. In this case, the package body 301 may further include a terminal to which the current detection pad 170 of the semiconductor device 101 is connected. The package body 301 may further include a plurality of terminals to which the anode electrode pad 270 and the cathode electrode pad 275 of the semiconductor device 201 are respectively connected.

[0234] As described above, the semiconductor package 300 includes the semiconductor device 1, 101, 101a, 201 or 201a, and therefore can ensure a wider operating area than when a general semiconductor device is included.

[0235] Another example of the semiconductor package shown in Fig. 17 will be described below. Fig. 19 is a front view showing another example of the semiconductor package 300 according to the fourth embodiment (hereinafter referred to as a semiconductor package 400). The semiconductor package 400 shown in Fig. 19 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 1.

[0236] The package body 401 has a rectangular parallelepiped shape. The package body 401 houses the semiconductor device 1. In other words, the package body 401 is a sealing body that seals the semiconductor device 1. The package body 401 may contain an epoxy resin. The package body 401 is formed, for example, from an epoxy resin containing carbon, glass fiber, and the like.

[0237] The multiple terminals 402 protrude from the long side of the package body 401 and are arranged side by side along the long side of the package body 401. The multiple terminals 402 are made of, for example, aluminum, but may be made of other metal materials such as copper.

[0238] Inside the package body 401, the gate pad 70, the source pad 75 and the drain electrode 40 of the semiconductor device 1 are electrically connected to corresponding terminals 402 by bonding wires or the like. The semiconductor package 400 may include a plurality of semiconductor devices 1. In other words, the package body 401 may have a plurality of semiconductor devices 1 built therein.

[0239] The semiconductor package 400 may include the semiconductor device 101, 101a, 201, or 201a instead of or in addition to the semiconductor device 1. In this case, inside the package body 401, the current detection pad 170 of the semiconductor device 101, or the anode electrode pad 270 and the cathode electrode pad 275 of the semiconductor device 201 are each electrically connected to a corresponding terminal 402 by a bonding wire or the like.

[0240] As described above, the semiconductor package 400 includes the semiconductor device 1, 101, 101a, 201 or 201a, and therefore can ensure a wider operating area than when a general semiconductor device is included.

[0241] 20 is a cross-sectional view showing a main part of a semiconductor device 501 according to a first modification of each of the above-mentioned embodiments. As described above, a bonding wire is used for electrically connecting the terminal of the semiconductor package 300 or 400 and the semiconductor device 1, 101, 101a, 201 or 201a. When the bonding wire is an aluminum wire, a nickel layer may be formed on the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75, which are metal plating layers, as shown in FIG.

[0242] In Fig. 20, bonding wires 303g and 303s are also shown as an example of a bonding wire. As shown in Fig. 20, the nickel layer 90 is an example of a metal layer formed of a metal material different from the metal material forming the gate pad 70 and the source pad 75. The nickel layer 90 is a layer containing nickel as a main component. Specifically, the nickel layer 90 is a metal layer made of simple nickel.

[0243] Similarly, in the case of the semiconductor device 101, 101a, 201 or 201a, the nickel layer 90 may be provided on the upper surface of each of the current detection pad 170, the anode electrode pad 270 and the cathode electrode pad 275.

[0244] Fig. 21 is a cross-sectional view showing a main part of a semiconductor device 601 according to a second modification of each of the above-mentioned embodiments. As in the semiconductor device 601 shown in Fig. 21, the gate pad 70 may include a columnar portion 71 made of copper and a wide portion 672 made of nickel. The source pad 75 may include a lower source pad 75a made of copper and an upper source pad 675c made of nickel.

[0245] For example, the semiconductor device 601 shown in Fig. 21 can be manufactured by performing a plating method using nickel instead of copper in the plating step shown in Fig. 6G. In the example shown in Fig. 21, the upper surface 73 of the wide portion 672, the upper surface 76 of the upper source pad 675c, and the upper surface 81 of the mold layer 80 are formed to be flush with each other.

[0246] In the example shown in FIG. 20 or FIG. 21, another layer may be formed instead of the nickel layer on the outermost surface of the metal plating layer (specifically, the gate pad 70 and the source pad 75) which is the bonding portion of the aluminum bonding wire. For example, a two-layer structure including a nickel layer and a palladium layer provided on the nickel layer (i.e., a NiPd layer) may be provided on the metal plating layer. Also, a three-layer structure (e.g., a NiPdAu layer) in which another metal layer such as a gold (Au) layer is formed on the upper surface of the two-layer structure may be formed. The NiPd layer and the NiPdAu layer are suitable not only for bonding with a bonding wire, but also for bonding with an external terminal by silver sintering.

[0247] The form of the semiconductor package including the semiconductor device 1, 101, 101a, 201, 201a, 501, or 601 is not limited to the form of the semiconductor package 300 and the semiconductor package 400. As the semiconductor package, a small outline package (SOP), a quad flat non-lead package (QFN), a dual flat package (DFP), a quad flat package (QFP), a single inline package (SIP), or a small outline J-leaded package (SOJ) may be adopted. In addition, various semiconductor packages similar to these may be adopted as the semiconductor package.

[0248] Although the semiconductor device according to one or more aspects has been described based on a number of embodiments, the present invention is not limited to these embodiments. As long as the modifications do not deviate from the gist of the present invention, modifications that a person skilled in the art may make to the present embodiments and modifications constructed by combining components in different embodiments are also included within the scope of the present invention.

[0249] For example, in a plan view, the gate pad 70 may cover only a portion of the main surface gate electrode 50. In other words, the gate pad 70 does not have to completely cover the main surface gate electrode 50. A similar structure may be applied to the current detection pad 170, the anode electrode pad 270, and the cathode electrode pad 275.

[0250] For example, in each embodiment, the conductivity type of each semiconductor region or layer may be reversed, i.e., an n-type semiconductor may be provided instead of a p-type semiconductor, and a p-type semiconductor may be provided instead of an n-type semiconductor.

[0251] For example, in each embodiment, n + Instead of the p-type semiconductor substrate 13, + A SiC semiconductor substrate of the type may be used. Thereby, the vertical transistor 2 is formed as an IGBT (Insulated Gate Bipolar Transistor). That is, a semiconductor device including an IGBT as a vertical transistor can be provided. In this case, the "source" of the MISFET is replaced with the "emitter" of the IGBT. Also, the "drain" of the MISFET is replaced with the "collector" of the IGBT. The emitter of the IGBT is an example of a first main electrode, and the collector of the IGBT is an example of a second main electrode. The semiconductor device according to each embodiment can achieve the same effects as those described above even when it includes an IGBT instead of a MISFET.

[0252] Examples of features extracted from this specification and the drawings are given below. In the following, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiment, but are not intended to limit the scope of each item to the embodiment.

[0253] [A1] A method for manufacturing a semiconductor device (1, 101, 101a, 201, 201a) including a vertical transistor (2), comprising the steps of: a first step of forming a control electrode (20) and a first main electrode (30) of the vertical transistor (2) at a distance from each other on a first main surface (11) of a semiconductor layer (10) having a first main surface (11) and a second main surface (12) opposite to the first main surface (11), the semiconductor layer (10) including SiC as a main component; A method for manufacturing a semiconductor device (1, 101, 101a, 201, 201a), comprising: a second step of forming a first electrode (50, 250) and a first electrode (55, 255) spaced apart from each other; and a third step of forming a first electrode pad (70) electrically connected to the first electrode (50, 250) so as to overlap the first electrode (50, 250) in a planar view, wherein the first electrode (50, 250) is smaller than the first electrode pad (70) in a planar view.

[0254] [A2] The method for manufacturing the semiconductor device (1, 101, 101a, 201, 201a) according to A1, wherein the third step includes a fourth step of forming a first conductive layer (71) on the first electrode (50, 250), a fifth step of forming an insulating layer (80) along the outer periphery of the first conductive layer (71) in a planar view, and a sixth step of forming a second conductive layer (72) larger than the first conductive layer (71) on the first conductive layer (71) and the insulating layer (80).

[0255] [A3] The method for manufacturing the semiconductor device (1, 101, 101a, 201, 201a) according to A2, wherein the sixth step includes a seventh step of forming a wiring layer (72b) larger than the first conductive layer (71) on the first conductive layer (71) and the insulating layer (80), and an eighth step of selectively forming a metal plating layer (72a) on the wiring layer (72b).

[0256] [A4] The method for manufacturing the semiconductor device (1, 101, 101a, 201, 201a) according to A2 or A3, wherein the fifth step forms the insulating layer (80) by molding a resin material (80b) so as to cover the first conductive layer (71), and grinding the molded resin material (80b) until the first conductive layer (71) is exposed.

[0257] [B1] A semiconductor device (1, 101, 101a, 201, 201a) including a vertical transistor (2), the semiconductor layer (10) having a first main surface (11) and a second main surface (12) opposite to the first main surface (11), the semiconductor layer (10) including SiC as a main component, a control electrode (20) of the vertical transistor (2) provided on the first main surface (11), a first main electrode (30) of the vertical transistor (2) provided on the first main surface (11) at a distance from the control electrode (20), and a second main electrode (30) of the vertical transistor (2) provided on the second main surface (12). a first electrode (55, 255) spaced apart from the first electrode (50, 250) in a planar view; and a first electrode pad (70) overlapping the first electrode (50, 250) in a planar view and electrically connected to the first electrode (50, 250), wherein the first electrode (50, 250) is smaller than the first electrode pad (70) in a planar view.

[0258] [B2] The semiconductor device (1, 101, 101a, 201, 201a) according to B1, wherein the first electrode pad (70) overlaps a portion of the first electrode (55, 255) in a plan view.

[0259] [B3] The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2, wherein the first electrode (50, 250) is electrically connected to the control electrode (20), and the first electrode (55, 255) is electrically connected to the first main electrode (30).

[0260] [B4] The semiconductor device (1, 101, 101a, 201, 201a) according to B3 further comprises a plurality of the first main electrodes (30) arranged at intervals from each other in a planar view, a third electrode (150) arranged at intervals from the first electrodes (50, 250) and the first electrodes (55, 255) in a planar view and electrically connected to N (N is a natural number) of the first main electrodes (30), and a second electrode pad (170) overlapping the third electrode (150) in a planar view and electrically connected to the third electrode (150), wherein the first electrodes (55, 255) are electrically connected to M (M is a natural number greater than N) of the first main electrodes (30), and the third electrode (150) is smaller than the second electrode pad (170) in a planar view.

[0261] [B5] The semiconductor device (1, 101, 101a, 201, 201a) according to B3 or B4, further comprising: a diode (290) including an anode electrode (250) and a cathode electrode (255) and provided on the first main surface (11); an anode electrode pad (270) overlapping the anode electrode (250) in a planar view and electrically connected to the anode electrode (250); and a cathode electrode pad (275) overlapping the cathode electrode (255) in a planar view and electrically connected to the cathode electrode (255), wherein the anode electrode (250) is smaller than the anode electrode pad (270) in a planar view, and the cathode electrode (255) is smaller than the cathode electrode pad (275) in a planar view.

[0262] [B6] The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2, further comprising a plurality of the first main electrodes (30), and the first electrode (50, 250) is electrically connected to one of the plurality of first main electrodes (30).

[0263] [B7] The semiconductor device (1, 101, 101a, 201, 201a) according to B1 or B2, further comprising a diode (290) provided on the first main surface (11) and a second electrode pad overlapping the first electrode (55, 255) in a planar view and electrically connected to the first electrode (55, 255), wherein the first electrode (50, 250) is an anode electrode (250) of the diode (290), the first electrode (55, 255) is a cathode electrode (255) of the diode (290), and is smaller than the second electrode pad (170) in a planar view.

[0264] [C1] A semiconductor device (1, 101, 101a, 201, 201a) including: a semiconductor layer (10) having a main surface (11) and containing SiC as a main component; a gate structure (21) formed on the main surface (11); an insulating layer (61) formed on the main surface (11) so as to cover the gate structure (21); a gate main electrode (50) arranged on the insulating layer (61) and electrically connected to the gate structure (21); and a gate pad electrode (70) arranged on the gate main electrode (50) so as to be connected to the gate main electrode (50), the gate pad electrode (70) including a connection portion connected to the gate main electrode (50) with a first area in a plan view, and an electrode surface (73) having a second area exceeding the first area in a plan view.

[0265] [C2] The semiconductor device (1, 101, 101a, 201, 201a) according to C1, wherein the electrode surface (73) of the gate pad electrode (70) is exposed to the outside.

[0266] [C3] The semiconductor device (1, 101, 101a, 201, 201a) according to C1 or C2, wherein the gate main electrode (50) is formed in a line shape on the insulating layer (61).

[0267] [C4] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C3, wherein the second area of ​​the electrode surface (73) exceeds an area of ​​the gate main electrode (50).

[0268] [C5] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C4, further comprising an active region (3, 103, 203) provided in the semiconductor layer (10) and a non-active region (4, 104, 204) provided in a region of the semiconductor layer (10) outside the active region (3, 103, 203), wherein the gate structure (21) is formed in the active region (3, 103, 203), the gate main electrode (50) is formed in the non-active region (4, 104, 204) in a planar view, and the gate pad electrode (70) overlaps the active region (3, 103, 203) and the non-active region (4, 104, 204) in a planar view.

[0269] [C6] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C5, further comprising a current conducting electrode (55) arranged on the insulating layer (61) at a distance from the gate main electrode (50).

[0270] [C7] The semiconductor device (1, 101, 101a, 201, 201a) according to C6, wherein the gate pad electrode (70) overlaps a portion of the current conducting electrode (55) in a plan view.

[0271] [C8] The semiconductor device (1, 101, 101a, 201, 201a) according to C6 or C7, further comprising a current conducting pad electrode (75) arranged on the current conducting electrode (55).

[0272] [C9] The semiconductor device (1, 101, 101a, 201, 201a) according to C8, wherein the current conducting pad electrode (75) overlaps a portion of the gate main electrode (50) in a plan view.

[0273] [C10] The semiconductor device (1, 101, 101a, 201, 201a) according to C8 or C9, wherein the current conducting pad electrode (75) includes an electrode surface (76) having a third area that exceeds the second area of ​​the gate pad electrode (70) in a planar view.

[0274] [C11] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C10, further comprising a first resin layer (63, 65) partially covering the gate main electrode (50) so as to expose a portion of the gate main electrode (50) on the insulating layer (61), and the gate pad electrode (70) is disposed on a portion of the gate main electrode (50) exposed from the first resin layer (63, 65).

[0275] [C12] The semiconductor device (1, 101, 101a, 201, 201a) according to C11, further comprising a second resin layer (80) partially covering the first resin layer (63, 65) so as to expose a portion of the gate main electrode (50) on the insulating layer (61), and the gate pad electrode (70) is arranged on a portion of the gate main electrode (50) exposed from the first resin layer (63, 65) and the second resin layer (80).

[0276] [C13] The semiconductor device (1, 101, 101a, 201, 201a) according to C12, wherein the first resin layer (63, 65) is made of a photosensitive resin layer, and the second resin layer (80) is made of a thermosetting resin layer.

[0277] [C14] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C1 to C13, wherein the gate structure (21) is a trench gate structure (21).

[0278] [C15] A semiconductor layer (10) having a main surface (11), an active region (3, 103, 203) provided in the semiconductor layer (10), a non-active region (4, 104, 204) provided in a region outside the active region (3, 103, 203) in the semiconductor layer (10), a plurality of gate structures (21) formed in the active region (3, 103, 203), an insulating layer (61) formed on the main surface (11) so as to cover the plurality of gate structures (21), and a gate main electrode (50) arranged on the insulating layer (61) so as to be electrically connected to a gate insulating layer (21) and overlapping the inactive region (4, 104, 204) in a planar view, and a gate pad electrode (70) arranged on the gate main electrode (50) so as to be electrically connected to the gate main electrode (50), and overlapping the active region (3, 103, 203) and the inactive region (4, 104, 204) in a planar view.

[0279] [C16] The semiconductor device (1, 101, 101a, 201, 201a) according to C15, wherein the gate main electrode (50) does not overlap the active region (3, 103, 203) in a plan view.

[0280] [C17] The semiconductor device (1, 101, 101a, 201, 201a) according to C15 or C16, wherein the gate pad electrode (70) includes a connection portion having a first area in a plan view and connected to the gate main electrode (50), and an electrode surface (73) having a second area in a plan view that exceeds the first area.

[0281] [C18] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of C15 to C17, wherein the active region (3, 103, 203) includes a plurality of divided regions provided in the semiconductor layer (10) at intervals in a planar view, and the inactive region (4, 104, 204) includes a portion of the semiconductor layer (10) located between the plurality of divided regions in a planar view.

[0282] [C19] The semiconductor device (1, 101, 101a, 201, 201a) described in C18, wherein the gate main electrode (50) includes a portion that overlaps with a portion located between the plurality of divided regions in the inactive region (4, 104, 204) in a planar view, and the gate pad electrode (70) includes a portion that overlaps with a portion located between the plurality of divided regions in the inactive region (4, 104, 204) in a planar view.

[0283] [C20] The semiconductor device (1, 101, 101a, 201, 201a) according to C19, wherein the gate pad electrode (70) overlaps a plurality of the divided regions in a plan view.

[0284] [D1] A semiconductor layer (10) having a main surface (11) and mainly composed of SiC, a diode structure (290, 291, 292) formed on the main surface (11), an insulating layer (61) formed on the main surface (11) so as to cover the diode structure (290, 291, 292), and a first polarity electrode (250 / 255) on one side and a second polarity electrode (255 / 255) on the other side disposed on the insulating layer (61) and electrically connected to the diode structure (290, 291, 292). a first connection portion arranged on the first polarity electrode (250 / 255) so as to be connected to the first polarity electrode (250 / 255), the first connection portion being connected to the first polarity electrode (250 / 255) with a first area in a planar view, and a first polarity pad electrode (270 / 275) including a first electrode surface (272 / 278) having a second area greater than the first area in a planar view.

[0285] [D2] The semiconductor device (1, 101, 101a, 201, 201a) according to D1, wherein the second area of ​​the first polarity pad electrode (270 / 275) exceeds an area of ​​the first polarity electrode (250 / 255) in a plan view.

[0286] [D3] The semiconductor device (1, 101, 101a, 201, 201a) according to D1 or D2, further comprising a second polarity pad electrode (275 / 270) including a second connection portion arranged on the second polarity electrode (255 / 250) so as to be connected to the second polarity electrode (255 / 250) and connected to the second polarity electrode (255 / 250) with a third area in a planar view, and a second electrode surface (278 / 272) having a fourth area greater than the third area.

[0287] [D4] The semiconductor device (1, 101, 101a, 201, 201a) according to D3, wherein the fourth area of ​​the second polarity pad electrode (275 / 270) exceeds an area of ​​the second polarity electrode (255 / 250) in a plan view.

[0288] [D5] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D4, wherein the diode structure (290, 291, 292) includes a polysilicon layer, a first region (291 / 292) of a first conductivity type formed in the polysilicon layer, and a second region (292 / 291) of a second conductivity type formed in the polysilicon layer so as to form a p-n junction with the first region (291 / 292), and the first polarity electrode (250 / 255) is electrically connected to the first region (291 / 292) of the diode structure (290, 291, 292), and the second polarity electrode (255 / 250) is electrically connected to the second region (292 / 291) of the diode structure (290, 291, 292).

[0289] [D6] The semiconductor device (1, 101, 101a, 201, 201a) according to D5, further comprising a recess (293) formed in the main surface (11), the diode structure (290, 291, 292) being disposed within the recess (293).

[0290] [D7] The semiconductor device (1, 101, 101a, 201, 201a) according to D6, wherein the diode structure (290, 291, 292) has an upper end located on the bottom wall side of the recess (293) with respect to the main surface (11).

[0291] [D8] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D7, further comprising: an active region (3, 103, 203) provided in the semiconductor layer (10); a non-active region (4, 104, 204) provided in a region of the semiconductor layer (10) outside the active region (3, 103, 203); and a gate structure (21) formed in the active region (3, 103, 203).

[0292] [D9] The semiconductor device (1, 101, 101a, 201, 201a) according to D8, wherein the diode structure (290, 291, 292) is formed in the inactive region (4, 104, 204).

[0293] [D10] The semiconductor device (1, 101, 101a, 201, 201a) according to any one of D1 to D9, wherein the diode structure (290, 291, 292) functions as a temperature sensitive diode.

[0294] Furthermore, the above-described embodiments can be modified, replaced, added, omitted, etc., within the scope of the claims or their equivalents. The present invention can be used in semiconductor devices, semiconductor packages, etc., as an industrial applicability. [Explanation of symbols]

[0295] 1 Semiconductor device 3. Active Area 4. Inactive Area 10 Semiconductor layer 11 First main surface (main surface) 21 Trench gate structure (gate structure) 50 Main surface gate electrode (main gate electrode) 55 Main surface source electrode (current conducting electrode) 61 Lower insulating layer (insulating layer) 62 Side insulating layer (first resin layer) 63 Upper insulating layer (first resin layer) 65 End insulation layer (first resin layer) 70 Gate pad (gate pad electrode) 73 Top surface of gate pad (electrode surface) 75 Source pad (source pad electrode) 76 Top surface of source pad (electrode surface) 80 Mold layer (second resin layer) 101 Semiconductor device 101a Semiconductor device 201 Semiconductor device 201a Semiconductor device 250 Anode electrode (first polarity electrode) 255 Cathode electrode (second polarity electrode) 290 Diode (Diode Structure) 293 Recess

Claims

1. A semiconductor layer having a main surface and containing SiC as a main component; a gate structure formed on the major surface; an insulating layer formed on the main surface so as to cover the gate structure; a main gate electrode disposed on the insulating layer and electrically connected to the gate structure; a gate pad electrode disposed on the gate main electrode so as to be connected to the gate main electrode, the gate pad electrode including a connection portion connected to the gate main electrode with a first area in a plan view, and an electrode surface having a second area larger than the first area in a plan view; a current conducting electrode disposed on the insulating layer and spaced from the main gate electrode; a current conducting pad electrode disposed on the current conducting electrode; the current conducting pad electrode overlaps a portion of the main gate electrode in a plan view.

2. The semiconductor device according to claim 1 , wherein said electrode surface of said gate pad electrode is exposed to the outside.

3. 3. The semiconductor device according to claim 1, wherein said main gate electrode is formed in a line shape on said insulating layer.

4. 4. The semiconductor device according to claim 1, wherein the second area of ​​the electrode surface exceeds an area of ​​the main gate electrode.

5. an active region provided in the semiconductor layer; a non-active region provided in the semiconductor layer outside the active region, the gate structure is formed in the active area; the main gate electrode is formed in the inactive region in a plan view; 5. The semiconductor device according to claim 1, wherein the gate pad electrode overlaps the active region and the non-active region in a plan view.

6. 6. The semiconductor device according to claim 1, wherein the gate pad electrode overlaps a portion of the current conducting electrode in a plan view.

7. 7. The semiconductor device according to claim 1, wherein the current conducting pad electrode includes an electrode surface having a third area that exceeds the second area of ​​the gate pad electrode in a plan view.

8. 8. The semiconductor device according to claim 1, wherein the gate structure is a trench gate structure.

9. The semiconductor device according to claim 1, wherein the main gate electrode is formed in a line shape in a plan view.

10. The active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, The semiconductor device according to claim 5 , wherein the inactive region includes a portion of the semiconductor layer located between a plurality of the divided regions in a plan view.

11. The gate main electrode includes a portion overlapping a portion located between the plurality of divided regions in the inactive region in a plan view, The semiconductor device according to claim 10 , wherein the gate pad electrode includes a portion that overlaps with a portion located between the plurality of divided regions in the inactive region in a plan view.

12. A semiconductor device as described in claim 10 or 11, wherein the gate pad electrode overlaps multiple of the divided regions in a planar view.

13. A semiconductor device according to claim 1, wherein at least one of the gate pad electrode and the current conducting pad electrode is made of copper or a copper alloy.

14. An active region provided in the semiconductor layer; a non-active region provided in the semiconductor layer outside the active region, the gate structure includes a plurality of gate structures; A plurality of the gate structures are formed in the active area; the main gate electrode overlaps the non-active region in a plan view; 14. The semiconductor device according to claim 1, wherein the gate pad electrode overlaps the active region and the non-active region in a plan view.

15. A semiconductor device according to claim 1, wherein, in a plan view, the current conducting pad electrode is arranged so as to surround the gate pad electrode.

16. A semiconductor device as described in any one of claims 5, 10 to 12 and 14, wherein, in a planar view, the area of ​​a first portion of the active area arranged in a region between a first side of the semiconductor layer and the gate pad electrode is larger than the area of ​​a second portion of the active area arranged in a region between a second side opposite the first side of the semiconductor layer and the gate pad electrode.

17. a semiconductor layer having a primary surface; an active region provided in the semiconductor layer; a non-active region provided in the semiconductor layer outside the active region; a plurality of gate structures formed in the active area; an insulating layer formed on the main surface so as to cover the plurality of gate structures; a gate main electrode disposed on the insulating layer so as to be electrically connected to the gate structures and overlapping the non-active region in a plan view; a gate pad electrode disposed on the gate main electrode so as to be electrically connected to the gate main electrode, the gate pad electrode overlapping the active area and the non-active area in a plan view; the active region includes a plurality of divided regions provided in the semiconductor layer at intervals in a plan view, the inactive region includes a portion of the semiconductor layer located between the plurality of divided regions in a plan view, the main gate electrode includes a portion overlapping a portion located between the plurality of divided regions in the inactive region in a plan view, The gate pad electrode includes a portion that overlaps with a portion located between the divided regions in the inactive region in a plan view.

18. The semiconductor device according to claim 17 , wherein the main gate electrode is formed in a line shape in a plan view.

19. 19. The semiconductor device according to claim 17, wherein the gate pad electrode includes a connection portion having a first area in a plan view and connected to the gate main electrode, and an electrode surface having a second area in a plan view that is greater than the first area.

20. 20. The semiconductor device according to claim 17, wherein the gate pad electrode overlaps a plurality of the divided regions in a plan view.

21. A semiconductor device as described in Claim 19, wherein the electrode surface of the gate pad electrode is exposed to the outside.

22. The semiconductor device according to claim 17, wherein the main gate electrode is formed in a line shape on the insulating layer.

23. A semiconductor device as described in claim 19 or 21, wherein the second area of ​​the electrode surface exceeds the area of ​​the gate main electrode.

24. A semiconductor device as claimed in any one of claims 19, 21 and 23, further comprising a current conducting electrode disposed on the insulating layer and spaced from the main gate electrode.

25. The semiconductor device as described in claim 24, wherein the gate pad electrode overlaps a portion of the current conducting electrode in a plan view.

26. A semiconductor device as described in claim 24 or 25, further comprising a current conducting pad electrode arranged on the current conducting electrode.

27. The semiconductor device as described in claim 26, wherein the current conducting pad electrode overlaps a portion of the main gate electrode in a plan view.

28. A semiconductor device as described in claim 26 or 27, wherein the current conducting pad electrode includes an electrode surface having a third area that exceeds the second area of ​​the gate pad electrode in a planar view.

29. A semiconductor device described in any one of claims 17 to 28, wherein the gate structure is a trench gate structure.

30. A semiconductor device according to claim 17, wherein at least one of the gate pad electrode and the current conducting pad electrode is made of copper or a copper alloy.

31. A semiconductor device as described in any one of claims 26 to 28 and 30, wherein, in a plan view, the current conducting pad electrode is arranged so as to surround the periphery of the gate pad electrode.

32. A semiconductor device as described in any one of claims 17 to 31, wherein, in a planar view, the area of ​​a first portion of the active area arranged in a region between a first side of the semiconductor layer and the gate pad electrode is larger than the area of ​​a second portion of the active area arranged in a region between a second side opposite the first side of the semiconductor layer and the gate pad electrode.

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