Imaging device

Abstract

This imaging device 100 comprises a photoelectric conversion layer 2, a counter electrode 1, a first electrode 10, a second electrode 20, a first transmission gate 11, a second transmission gate 21, a first amplifying transistor 14, and a second amplifying transistor 24. In a first readout period when the first transmission gate 11 suppresses signal charge transmission and including a first period when the second transmission gate 21 transmits a signal charge, the first transistor 14 outputs a signal corresponding to a potential of the first gate, and in a second readout period when the second transmission gate 21 suppresses signal charge transmission and including a second period when the first transmission gate 11 transmits a signal charge, the second transistor 24 outputs a signal corresponding to a potential of the second gate.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Conventionally, image sensors that utilize photoelectric conversion are known. For example, CMOS (Complementary Metal Oxide Semiconductor) type image sensors with photodiodes are widely used. CMOS type image sensors have the advantages of low power consumption and the ability to access each pixel. CMOS type image sensors generally use a so-called rolling shutter as a signal readout method, which sequentially exposes each row of the pixel array and reads out the signal charge.

[0003] In rolling shutter operation, the start and end of exposure are different for each row of the pixel array. Therefore, when capturing an image of a fast moving object, a distorted image of the object may be obtained, and when a flash is used, a difference in brightness may occur within the image. For these reasons, there is a demand for a so-called global shutter function in which the start and end of exposure is common to all pixels in the pixel array.

[0004] For example, Patent Document 1 discloses a CMOS image sensor capable of global shutter operation. In the technology described in Patent Document 1, a transfer transistor and a charge storage unit (capacitor or diode) are provided in each of a plurality of pixels. In each pixel, the charge storage unit is connected to a photodiode via a transfer transistor.

[0005] Patent Document 2 discloses an imaging element having a storage electrode facing a photoelectric conversion layer and a semiconductor layer via an insulating layer. The technology of Patent Document 2 makes it possible to store signal charges in the photoelectric conversion layer and the semiconductor layer by changing the voltage of the storage electrode and to transfer the signal charges to pixel electrodes at a predetermined timing. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2007 / 0013798 [Patent Document 2] JP 2016-63165 A Summary of the Invention [Problem to be solved by the invention]

[0007] The present disclosure provides an imaging device that has a global shutter function and suppresses exposure dead time. [Means for solving the problem]

[0008] An imaging device according to one embodiment of the present disclosure includes a photoelectric conversion layer that converts light into signal charges, a counter electrode that applies a bias voltage to the photoelectric conversion layer, a first electrode and a second electrode that are arranged apart from each other and collect the signal charges from the photoelectric conversion layer, a first transfer gate that controls the transfer of the signal charges from the photoelectric conversion layer to the first electrode, a second transfer gate that controls the transfer of the signal charges from the photoelectric conversion layer to the second electrode, a first amplifying transistor having a first gate electrically connected to the first electrode, and a second amplifying transistor having a second gate electrically connected to the second electrode, wherein the first transistor outputs a signal corresponding to the potential of the first gate during a first readout period that includes a first period during which the second transfer gate transfers the signal charges and during which the first transfer gate suppresses the transfer of the signal charges, and the second transistor outputs a signal corresponding to the potential of the second gate during a second readout period that includes a second period during which the first transfer gate transfers the signal charges and during which the second transfer gate suppresses the transfer of the signal charges.

[0009] It should be noted that the general or specific aspects may be realized by an element, a device, a module, a system, or a method. Furthermore, the general or specific aspects may be realized by any combination of an element, a device, an apparatus, a module, a system, and a method.

[0010] Additionally, additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings, and the benefits and / or advantages may be provided by the various embodiments or features disclosed in the specification and drawings individually, and not all are required to obtain one or more of them. Effect of the Invention

[0011] The imaging device according to the present disclosure has a global shutter function and can suppress exposure dead time. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of an imaging device according to the first embodiment. [Figure 2A] FIG. 2A is a diagram showing an example of a circuit configuration of a pixel of the imaging device according to the first embodiment. [Figure 2B] FIG. 2B is a plan view showing the layout of electrodes of a photoelectric conversion unit of the imaging device according to the first embodiment. [Diagram 3] FIG. 3 is a diagram showing an example of a cross-sectional structure of a main part of a pixel of the imaging device according to the first embodiment. [Figure 4] FIG. 4 is a timing chart showing an example of the operation of the pixel of the imaging device according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing a potential profile of a pixel in each period of FIG. 4 according to the first embodiment. [Figure 6] FIG. 6 is a timing chart showing an example of the operation of the pixel of the imaging device according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of a pixel of the imaging device according to the second embodiment. [Figure 8]FIG. 8 is a diagram illustrating an example of a circuit configuration of a pixel of an imaging device according to the third embodiment. [Figure 9] FIG. 9 is a timing chart showing an example of the operation of the pixel of the imaging device according to the fourth embodiment. [Figure 10] FIG. 10 is a diagram showing a potential profile of a pixel in each period of FIG. 9 according to the fourth embodiment. [Figure 11] FIG. 11 is a timing chart showing an example of the operation of the pixel of the imaging device according to the fifth embodiment. [Figure 12] FIG. 12 is a diagram showing a potential profile of a pixel in each period of FIG. 11 according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a circuit configuration of a pixel of an imaging device according to the sixth embodiment. [Figure 14] FIG. 14 is a timing chart showing an example of the operation of the pixel of the imaging device according to the sixth embodiment. [Figure 15] FIG. 15 is a diagram showing a potential profile of a pixel in each period of FIG. 14 according to the sixth embodiment. [Figure 16] FIG. 16 is a timing chart showing an example of the operation of the pixel of the imaging device according to the seventh embodiment. [Figure 17] FIG. 17 is a diagram showing a potential profile of a pixel of the imaging device according to the seventh embodiment. [Figure 18] FIG. 18 is a diagram showing an example of a cross-sectional structure of a main part of a pixel of an imaging device according to the eighth embodiment. [Figure 19] FIG. 19 is a timing chart showing an example of the operation of the pixel of the imaging device according to the eighth embodiment. [Figure 20A] FIG. 20A is a diagram showing an example of a circuit configuration of a pixel of an imaging device according to the ninth embodiment. [Figure 20B] FIG. 20B is a diagram showing another example of the circuit configuration of a pixel of the imaging device according to the ninth embodiment. [Figure 21] FIG. 21 is a diagram showing a modified example of the circuit configuration of a pixel in the imaging device according to the ninth embodiment. [Figure 22]FIG. 22 is a diagram showing another modified example of the circuit configuration of a pixel in the imaging device according to the ninth embodiment. In FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (Knowledge that forms the basis of this disclosure) The technology of Patent Document 1 or Patent Document 2 can also realize a global shutter. However, it is not possible to utilize the signal charge generated in the photoelectric conversion layer during the readout period due to the rolling operation. This results in wasted time. In other words, there is a problem that wasted time, that is, exposure dead time, occurs during the readout period of the signal charge.

[0014] In order to eliminate such wasted time, the inventors of the present application have intensively studied a configuration that can effectively utilize the signal charge generated during the readout period, and as a result have arrived at the novel technology of the present disclosure that has an efficient global shutter function and can suppress the exposure dead time.

[0015] In order to solve such problems, an imaging device according to one embodiment of the present disclosure includes a plurality of pixels, each of which includes a photoelectric conversion layer that converts light into a signal charge, a counter electrode that applies a bias voltage to the photoelectric conversion layer, a first electrode and a second electrode that are arranged apart from each other and collect the signal charge generated in the photoelectric conversion layer, a first transfer gate that controls transfer of the signal charge to the first electrode, a second transfer gate that controls transfer of the signal charge to the second electrode, a first amplification transistor having a first gate electrically connected to the first electrode, and a second gate electrically connected to the second electrode. and a second amplifying transistor, wherein in a first readout period during which the first amplifying transistor outputs a signal corresponding to the potential of the first gate, the first transfer gate suppresses the transfer of the signal charge to the first electrode, and in a second readout period during which the second amplifying transistor outputs a signal corresponding to the potential of the second gate, the second transfer gate suppresses the transfer of the signal charge to the second electrode, the first readout period includes a first period during which the second transfer gate transfers the signal charge to the second electrode, and the second readout period includes a second period during which the first transfer gate transfers the signal charge to the first electrode.

[0016] According to this, the operation of reading out the signal charge collected by the first electrode and the operation of the second electrode collecting the signal charge by exposure and transfer are performed in parallel. Also, the operation of reading out the signal charge collected by the second electrode and the operation of the first electrode collecting the signal charge by exposure and transfer are performed in parallel. As a result, a global shutter function can be realized and the dead time of exposure can be suppressed.

[0017] Here, the length of the first period may be equal to the length of the first read period, and the length of the second period may be equal to the length of the second read period.

[0018] According to this, the second transfer gate transfers the signal charge to the second electrode during the entire first readout period. Also, the first transfer gate transfers the signal charge to the first electrode during the entire second readout period. As a result, even if a large amount of signal charge is generated due to strong light, the generated signal charge can be prevented from overflowing from the first transfer gate and the second transfer gate.

[0019] Here, the first read period and the second read period may be continuously and alternately repeated.

[0020] This makes it possible to capture images continuously while suppressing dead time in exposure.

[0021] Here, the first readout period may include a third period immediately before the first period, and the second transfer gate may suppress the transfer of the signal charge during the third period, and the second readout period may include a fourth period immediately before the second period, and the second transfer gate may suppress the transfer of the signal charge during the fourth period.

[0022] According to this, the signal charge is temporarily stored between the first transfer gate and the second transfer gate in the third period, and then the signal charge is transferred to the second electrode in the first period. Also, the signal charge is temporarily stored between the first transfer gate and the second transfer gate in the fourth period, and then the signal charge is transferred to the first electrode in the second period. Even in this form, it is possible to realize the global shutter function and suppress the dead time of exposure.

[0023] Here, each of the plurality of pixels may further include a first charge accumulation section electrically connected to the first electrode and accumulating the signal charges collected by the first electrode, and a second charge accumulation section electrically connected to the second electrode and accumulating the signal charges collected by the second electrode.

[0024] Here, the first charge storage section may have a smaller capacitance than the second charge storage section.

[0025] According to this, the sensitivity of the detection signal output from the first amplifying transistor can be made different from the sensitivity of the detection signal output from the second amplifying transistor by the capacitance difference between the first charge storage section and the second charge storage section, and as a result, for example, by combining these detection signals, the dynamic range can be expanded.

[0026] Here, each of the plurality of pixels may further include a capacitor connected to the second pixel electrode.

[0027] This makes it possible to differentiate the detection sensitivity of the signal charge by the first amplifying transistor from the detection sensitivity of the signal charge by the second amplifying transistor, and as a result, for example, by combining these detection signals, it is possible to expand the dynamic range.

[0028] Here, each of the plurality of pixels may further include a charge storage electrode located between the first transfer gate and the second transfer gate and facing the counter electrode via the photoelectric conversion layer.

[0029] This makes it possible to form an electric field between the counter electrode and the charge storage electrode, and as a result, the signal charges generated in the photoelectric conversion layer can be moved toward the charge storage electrode.

[0030] Here, each of the plurality of pixels may further include a semiconductor layer located between the photoelectric conversion layer, and the first electrode and the second electrode.

[0031] Here, the charge mobility of the semiconductor layer may be greater than the charge mobility of the photoelectric conversion layer.

[0032] This can increase the speed of transfer by the first transfer gate and also the speed of transfer by the second transfer gate.

[0033] Here, the length of the first read period may be equal to the length of the second read period.

[0034] This makes it possible to suppress or eliminate dead time in exposure.

[0035] Here, the length of the first readout period may be equal to the length of one vertical synchronization period.

[0036] According to this, by switching between the first readout period and the second readout period for each vertical synchronization period, that is, for each frame period, it is possible to suppress the dead time of exposure.

[0037] Here, the length of the second read period may be longer than the length of the first read period.

[0038] According to this, the length of the second readout period, i.e., the exposure time for generating the signal charge collected in the first electrode, is longer than the length of the first readout period, i.e., the exposure time for generating the signal charge collected in the second electrode. As a result, the sensitivity of the detection signal output from the first amplification transistor is higher than the sensitivity of the detection signal output from the second amplification transistor. Therefore, for example, by combining these detection signals, the dynamic range can be expanded.

[0039] Here, the pixel may further include a voltage supply circuit connected to the opposing electrode, the voltage supply circuit supplying a first voltage to the opposing electrode during the first readout period, and supplying a second voltage different from the first voltage to the opposing electrode during the second readout period.

[0040] According to this, the quantum efficiency of the photoelectric conversion layer can be changed by the voltage supplied to the counter electrode.

[0041] Here, the photoelectric conversion layer may include a first photoelectric conversion layer sensitive to light in a first wavelength range, and a second photoelectric conversion layer sensitive to light in a second wavelength range different from the first wavelength range.

[0042] This makes it possible to change the spectral sensitivity characteristics of the photoelectric conversion layer by varying the voltage supplied to the counter electrode, thereby making it possible to switch between imaging sensitive to infrared light and imaging sensitive to visible light, for example.

[0043] Here, each of the plurality of pixels may further include a first feedback circuit that negatively feeds back the potential of the first electrode to the first electrode.

[0044] According to this, by operating the first feedback circuit during the reset operation of the potential of the first electrode, it is possible to reduce the influence of reset noise.

[0045] Here, each of the plurality of pixels may further include a second feedback circuit that negatively feeds back the potential of the second electrode to the second electrode.

[0046] According to this, by operating the second feedback circuit during the reset operation of the potential of the second electrode, it is possible to reduce the influence of reset noise.

[0047] Moreover, an imaging device according to one embodiment of the present disclosure includes a plurality of pixels, each of which includes a photoelectric conversion layer that converts light into a signal charge, a counter electrode that applies a bias voltage to the photoelectric conversion layer, a first electrode and a second electrode that are arranged apart from each other and collect the signal charge generated in the photoelectric conversion layer, a first transfer gate that controls the transfer of the signal charge to the first electrode, a second transfer gate that controls the transfer of the signal charge to the second electrode, a first charge storage unit electrically connected to the first electrode, and a second charge storage unit electrically connected to the second electrode, wherein the capacity of the second charge storage unit is greater than the capacity of the first charge storage unit.

[0048] According to this, the sensitivity of the detection signal output from the first amplifying transistor can be made different from the sensitivity of the detection signal output from the second amplifying transistor by the capacitance difference between the first charge storage section and the second charge storage section, and as a result, for example, by combining these detection signals, the dynamic range can be expanded.

[0049] Here, the second charge storage unit may include a capacitor.

[0050] This makes it possible to differentiate the sensitivity of the detection signal output from the first amplifying transistor from the sensitivity of the detection signal output from the second amplifying transistor, and as a result, for example, by combining these detection signals, it is possible to expand the dynamic range.

[0051] Here, the semiconductor memory device may include a first amplification transistor having a first gate electrically connected to the first electrode, and a second amplification transistor having a second gate electrically connected to the second electrode.

[0052] This provides a global shutter function and can reduce the dead time of exposure.

[0053] Here, the device may include a first amplifying transistor having a first gate electrically connected to the second electrode, the first gate being electrically connected to the second electrode via a first switch.

[0054] This makes it possible to obtain two detection signals with different sensitivities depending on whether the first switch is connected or not, and as a result, by combining these detection signals, it is possible to expand the dynamic range.

[0055] Here, the semiconductor device may further include a feedback circuit that negatively feeds back the potential of the first charge accumulation section to the first charge accumulation section.

[0056] According to this, by operating the feedback circuit during the reset operation of the potential of the first charge accumulation unit, it is possible to reduce the influence of reset noise.

[0057] Moreover, an imaging device according to one aspect of the present disclosure includes a plurality of pixels, each of which includes a photoelectric conversion layer that converts light into a signal charge, a counter electrode that applies a bias voltage to the photoelectric conversion layer, a first electrode that is spaced apart from each other and collects the signal charge generated in the photoelectric conversion layer, a first transfer gate that controls the transfer of the signal charge to the first electrode, and a feedback circuit that negatively feeds back the potential of the first electrode to the first electrode.

[0058] According to this, by operating the feedback circuit during the reset operation of the potential of the first electrode, it is possible to reduce the influence of reset noise.

[0059] In addition, all or part of these comprehensive or specific aspects may be realized by a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized by any combination of the system, the method, the integrated circuit, the computer program, and the recording medium.

[0060] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0061] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims are described as optional components.

[0062] In addition, more detailed explanations than necessary may be omitted. For example, detailed explanations of already well-known matters and duplicate explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily redundant and to facilitate understanding by those skilled in the art. Note that the accompanying drawings and the following explanation are intended to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter described in the claims.

[0063] In addition, all numerical values ​​described below are exemplified to specifically explain the present disclosure, and the present disclosure is not limited to the exemplified numerical values. Furthermore, the connection relationships between the components are exemplified to specifically explain the present disclosure, and the connection relationships that realize the functions of the present disclosure are not limited to these.

[0064] In addition, each drawing is a schematic diagram and is not necessarily a precise illustration, and therefore, for example, the scale of each drawing does not necessarily match.

[0065] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent.

[0066] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. In addition, the terms "above" and "below" are applied not only to the case where two components are arranged with a gap between them and another component exists between the two components, but also to the case where two components are arranged closely together and are in contact with each other.

[0067] (Embodiment 1) [Overall configuration of imaging device] 1 is a diagram showing an example of the configuration of an imaging device according to embodiment 1. An imaging device 100 shown in FIG.

[0068] Each pixel 102 has a photoelectric conversion unit that converts incident light into an electric charge, and two readout circuits. That is, two readout circuits are provided for one photoelectric conversion unit in each pixel 102. A plurality of pixels 102 are arranged two-dimensionally on, for example, a semiconductor substrate, so that the pixel array 101 forms an imaging area. In this example, the pixels 102 are arranged in a matrix of m rows and n columns, and the center of each pixel 102 is located on a lattice point of a square lattice. Of course, the arrangement of the pixels 102 is not limited to the example shown in the figure, and for example, a plurality of pixels 102 may be arranged so that each center is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like.

[0069] 1, the peripheral circuits include a row scanning circuit 103, a signal processing circuit 104, an output circuit 105, a control circuit 106, and a voltage supply circuit 107. The peripheral circuits may be disposed on a semiconductor substrate on which the pixel array 101 is formed, or a part of the peripheral circuits may be disposed on another substrate.

[0070] The row scanning circuit 103 is also called a vertical scanning circuit. The row scanning circuit 103 selects a plurality of pixels 102 arranged in m rows and n columns on a row-by-row basis, and performs operations such as reading out signal voltages and resetting charge storage nodes in the pixels. To this end, the row scanning circuit 103 supplies selection control signals SEL1, SEL2 and reset control signals RS1, RS2 to each row of the pixels 102.

[0071] 1 only diagrammatically illustrates the connection between each pixel 102 and the row scanning circuit 103, and the number of control lines arranged for each row of the pixels 102 is not limited to four. In an embodiment described later, for example, the row scanning circuit 103 may also have a connection to control lines for supplying a transfer gate signal TG1 and a transfer gate signal TG2 provided corresponding to each row of the pixels 102.

[0072] The signal processing circuit 104 is connected to vertical signal lines VSIG1(1), VSIG2(1) to VSIG1(n), VSIG2(n) provided corresponding to each column of the pixels 102. The output of the pixels 102 is selected row by row by the row scanning circuit 103, and is read out to the signal processing circuit 104 via the vertical signal lines VSIG1(1), VSIG2(1) to VSIG1(n), VSIG2(n). The signal processing circuit 104 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion, on the output signals read out from the pixels 102. The output of the signal processing circuit 104 is read out to the outside of the imaging device 100 via an output circuit 105.

[0073] The control circuit 106 receives command data, a clock, and the like provided from, for example, an external source of the imaging device 100, and controls the entire imaging device 100. The control circuit 106 typically has a timing generator, and supplies drive signals to the row scanning circuit 103, the signal processing circuit 104, the voltage supply circuit 107, and the like.

[0074] The voltage supply circuit 107 supplies a bias voltage V1, a voltage AE, a transfer gate signal TG1, and a transfer gate signal TG2 to all the pixels 102 under the control of the control circuit 106.

[0075] [Pixel configuration] Fig. 2A is a diagram showing an example of a circuit configuration of a pixel 102 according to embodiment 1. As shown in Fig. 2A, the pixel 102 can be roughly divided into three parts: a photoelectric conversion unit OE, and readout circuits R1 and R2. The photoelectric conversion unit OE in the figure shows a schematic cross-sectional configuration.

[0076] The photoelectric conversion unit OE in FIG. 2A includes a counter electrode 1, a photoelectric conversion layer 2, a semiconductor layer 3, an insulating layer 4, a charge storage electrode 5, a first electrode 10, a first transfer gate 11, a second electrode 20, and a second transfer gate 21.

[0077] The counter electrode 1 applies a bias voltage V1 to the photoelectric conversion layer 2. The counter electrode 1 is a transparent electrode made of, for example, ITO, and is also called an upper electrode. Although not shown in FIG. 2A, a sealing film, a color filter, and a microlens may be disposed on the counter electrode 1. Instead of or in addition to the color filter, an infrared transmission filter may be disposed.

[0078] The photoelectric conversion layer 2 converts incident light from the counter electrode 1 side into signal charges.

[0079] The semiconductor layer 3, which is also called a channel layer, has a higher charge mobility than the photoelectric conversion layer 2 and facilitates the movement of charges.

[0080] The insulating layer 4 insulates the semiconductor layer 3 from the charge storage electrode 5, the first transfer gate 11, and the second transfer gate .

[0081] The charge storage electrode 5 transfers the signal charges generated in the photoelectric conversion layer 2 to the semiconductor layer 5 due to the potential difference between the counter electrode 1 and the charge storage electrode 5, and accumulates them near the interface with the insulating layer 4. The quantum efficiency of the photoelectric conversion layer 2 can be adjusted according to the potential difference between the counter electrode 1 and the charge storage electrode 5.

[0082] The first electrode 10 is also called a first pixel electrode. The first electrode 10 penetrates the insulating layer 4 and contacts the semiconductor layer 3. Signal charges move in the semiconductor layer 3 toward the first electrode 10 due to an electric field generated by a potential difference between the charge storage electrode 5 and the first electrode. The first electrode 10 collects the signal charges that have moved in the semiconductor layer 3. The first electrode 10 is connected to a first charge storage unit FD1, and the signal charges collected by the first electrode are stored in the first charge storage unit FD1.

[0083] A transfer gate signal TG1 is input to the first transfer gate 11. The first transfer gate 11 controls the transfer of signal charges in the semiconductor layer 3 according to the voltage value of the transfer gate signal TG1. For example, when the transfer gate signal TG1 is at a high level, the transfer path above the first transfer gate 11 is in a conductive state, and the signal charges are transferred to the first electrode 10. When the transfer gate signal TG1 is at a low level, the transfer path above the first transfer gate 11 is in a non-conductive state, and the signal charges are not transferred to the first electrode 10. When the transfer gate signal TG1 is at an intermediate level, the transfer path above the first transfer gate 11 is in a semi-conductive state, and the overflowing signal charges are transferred to the first electrode 10 only when the signal charges exceed a predetermined amount.

[0084] When the transfer gate signal TG1 is at a high level, a voltage that forms an electric field that allows the signal charges above the charge storage electrode 5 to move to the first electrode 10 is supplied to the first transfer gate 11. For example, if the signal charges are holes, the voltage applied to the first transfer gate 11 when the transfer gate signal TG1 is at a high level may be a voltage lower than the voltage of the charge storage electrode 5 and higher than the voltage of the first electrode 10. Also, for example, if the signal charges are electrons, the voltage applied to the first transfer gate 11 when the transfer gate signal TG1 is at a high level may be a voltage higher than the voltage of the charge storage electrode 5 and lower than the voltage of the first electrode 10.

[0085] When the transfer gate signal TG1 is at a low level, a voltage that forms an electric field that acts as a barrier against the movement of the signal charges above the charge storage electrode 5 to the first electrode 10 is supplied to the first transfer gate 11. For example, if the signal charges are holes, the voltage applied to the first transfer gate 11 when the transfer gate signal TG1 is at a low level may be a voltage higher than the voltage of the charge storage electrode 5. Also, for example, if the signal charges are electrons, the voltage applied to the first transfer gate 11 when the transfer gate signal TG1 is at a low level may be a voltage lower than the voltage of the charge storage electrode 5.

[0086] When the transfer gate signal TG1 is at the middle level, a voltage is supplied to the first transfer gate 11 to form an electric field that allows the signal charges above the charge storage electrode 5, which exceed a predetermined amount, to move to the second electrode. For example, if the signal charges are holes, the voltage applied to the first transfer gate 11 when the transfer gate signal TG1 is at the middle level may be higher than the voltage of the charge storage electrode 5 and lower than the voltage applied when the transfer gate signal TG1 is at the low level. Also, for example, if the signal charges are electrons, the voltage applied to the first transfer gate 11 when the transfer gate signal TG1 is at the middle level may be lower than the voltage of the charge storage electrode 5 and higher than the voltage applied when the transfer gate signal TG1 is at the low level.

[0087] The second electrode 20 is also called a second pixel electrode. The second electrode 20 penetrates the insulating layer 4 and contacts the semiconductor layer 3. The signal charge moves in the semiconductor layer 3 toward the second electrode 20 due to an electric field generated by a potential difference between the charge storage electrode 5 and the second electrode. The second electrode 20 collects the signal charge that has moved in the semiconductor layer 3. The second electrode 20 is connected to the second charge storage section FD2, and the charge collected by the second electrode 20 is stored in the second charge storage section FD2.

[0088] A transfer gate signal TG2 is input to the second transfer gate 21. The second transfer gate 21 controls the transfer of signal charges in the semiconductor layer 3 according to the voltage value of the transfer gate signal TG2. For example, when the transfer gate signal TG2 is at a high level, the transfer path above the second transfer gate 21 is in a conductive state, and the signal charges are transferred to the second electrode 20. When the transfer gate signal TG2 is at a low level, the transfer path above the second transfer gate 21 is in a non-conductive state, and the signal charges are not transferred to the second electrode 20. When the transfer gate signal TG2 is at an intermediate level, the transfer path above the second transfer gate 21 is in a semi-conductive state, and the overflowing signal charges are transferred to the second electrode 20 only when the signal charges exceed a predetermined amount.

[0089] When the transfer gate signal TG2 is at a high level, a voltage that forms an electric field that allows the signal charges above the charge storage electrode 5 to move to the second electrode 20 is supplied to the second transfer gate 21. For example, if the signal charges are holes, the voltage applied to the second transfer gate 21 when the transfer gate signal TG2 is at a high level may be a voltage lower than the voltage of the charge storage electrode 5 and higher than the voltage of the second electrode 20. Also, for example, if the signal charges are electrons, the voltage applied to the second transfer gate 21 when the transfer gate signal TG2 is at a high level may be a voltage higher than the voltage of the charge storage electrode 5 and lower than the voltage of the second electrode 20.

[0090] When the transfer gate signal TG2 is at a low level, a voltage that forms an electric field that acts as a barrier against the movement of the signal charges above the charge storage electrode 5 to the second electrode 20 is supplied to the second transfer gate 21. For example, if the signal charges are holes, the voltage applied to the second transfer gate 21 when the transfer gate signal TG2 is at a low level may be a voltage higher than the voltage of the charge storage electrode 5. Also, for example, if the signal charges are electrons, the voltage applied to the second transfer gate 21 when the transfer gate signal TG2 is at a low level may be a voltage lower than the voltage of the charge storage electrode 5.

[0091] When the transfer gate signal TG2 is at the middle level, a voltage is supplied to the second transfer gate 21 to form an electric field that allows the signal charges above the charge storage electrode 5, which exceed a predetermined amount, to move to the second electrode 20. For example, when the signal charges are holes, the voltage applied to the second transfer gate 21 when the transfer gate signal TG2 is at the middle level may be higher than the voltage of the charge storage electrode 5 and lower than the voltage applied when the transfer gate signal TG2 is at the high level. Also, when the signal charges are electrons, the voltage applied to the second transfer gate 21 when the transfer gate signal TG2 is at the middle level may be lower than the voltage of the charge storage electrode 5 and higher than the voltage applied when the transfer gate signal TG2 is at the high level.

[0092] A light shielding portion may be provided so as to prevent light from entering the portion of the photoelectric conversion layer 2 located above the first electrode 10 and the second electrode 20. This makes it possible to suppress the generation of signal charges not controlled by the first transfer gate 11 and the second transfer gate 21, thereby reducing noise.

[0093] 2A outputs a signal corresponding to the amount of signal charge accumulated in the first charge accumulation unit FD1 to the vertical signal line SIG1. The readout circuit R1 also resets the signal charge accumulated in the first charge accumulation unit FD1. The readout circuit R1 includes the first charge accumulation unit FD1, a first reset transistor 13, a first amplification transistor 14, and a first selection transistor 15.

[0094] The first charge storage unit FD1 is electrically connected to the first electrode 10 and stores signal charges transferred from the first electrode 10. The first charge storage unit FD1 may include a diffusion layer. The first charge storage unit FD1 may include a capacitor. Hereinafter, the first charge storage unit FD1 may be simply referred to as FD1.

[0095] The first reset transistor 13 resets the first charge storage unit FD1 to a reference potential in accordance with a reset control signal RS1.

[0096] The first amplifying transistor 14 amplifies a voltage corresponding to the amount of signal charge accumulated in the first charge accumulation unit FD1 and outputs the amplified voltage to the vertical signal line SIG1 via the first selection transistor 15. The first amplifying transistor 14 configures a source follower circuit together with a current source provided on the vertical signal line SIG1. The first selection transistor 15 is a switch that connects the first amplifying transistor 14 and the vertical signal line SIG1 in accordance with a selection control signal SEL1.

[0097] 2A is a circuit for reading out the signal charge stored in the second charge storage unit FD2 to the vertical signal line SIG2 as a voltage according to the amount of the signal charge. The readout circuit R2 includes the second charge storage unit FD2, a second reset transistor 23, a second amplification transistor 24, and a second selection transistor 25.

[0098] The second charge storage unit FD2 is electrically connected to the second electrode 20 and stores the signal charge transferred from the second electrode 20. The second charge storage unit FD2 may include a diffusion layer. The second charge storage unit FD2 may include a capacitor. Hereinafter, the second charge storage unit FD2 may be simply referred to as FD2.

[0099] The second reset transistor 23 resets the second charge storage unit FD2 to the reference potential in accordance with the reset control signal RS2.

[0100] The second amplifying transistor 24 amplifies a voltage corresponding to the amount of signal charge accumulated in the second charge accumulation unit FD2 and outputs the amplified voltage to the vertical signal line SIG2 via the second selection transistor 25. The second amplifying transistor 24 configures a source follower circuit together with a current source provided on the vertical signal line SIG2. The second selection transistor 25 is a switch that connects the second amplifying transistor 24 and the vertical signal line SIG2 in accordance with a selection control signal SEL2.

[0101] Next, a layout example of electrodes under the photoelectric conversion unit OE will be described.

[0102] Fig. 2B is a plan view showing the layout of electrodes under the photoelectric conversion unit OE of the imaging device according to embodiment 1. The dashed line in Fig. 2B indicates the outline of the pixel 102. The charge storage electrode 5 is disposed in the center of the pixel 102 in a plan view. As shown in Fig. 2B, the charge storage electrode 5 is rectangular.

[0103] The first transfer gate 11 and the second transfer gate 21 are disposed on either side of the charge storage electrode 5 in a plan view. The first transfer gate 11 and the second transfer gate are in the shape of a long and narrow rectangle.

[0104] The first electrode 10 and the second electrode 20 are arranged, in a plan view, with the charge storage electrode 5, the first transfer gate 11, and the second transfer gate 21 sandwiched therebetween. The first electrode 10 and the second electrode 20 are each in the form of a long and narrow rectangle.

[0105] Next, a more detailed configuration example of the pixel 102 will be described.

[0106] Fig. 3 is a diagram showing an example of a cross-sectional structure of a main part of a pixel 102 of the image pickup device according to embodiment 1. As shown in Fig. 3, the pixel 102 has a configuration in which an insulating layer 7, an insulating layer 4, a semiconductor layer 3, a photoelectric conversion layer 2, and a counter electrode 1 are laminated in this order on a semiconductor substrate 6. The pixel 102 includes a charge storage electrode 5, a first electrode 10, a first transfer gate 11, a second electrode 20, and a second transfer gate 21 in the insulating layer 7.

[0107] The semiconductor substrate 6 is, for example, a silicon substrate. The semiconductor substrate 6 includes a first diffusion layer 12 that functions as a part of the first charge storage portion FD1 and a second diffusion layer 22 that functions as a part of the second charge storage portion FD2. The first diffusion layer 12 is electrically connected to the first electrode 10 via a contact 10c. The second diffusion layer 22 is electrically connected to the second electrode 20 via a contact 20c.

[0108] Elements such as transistors constituting the readout circuits R1 and R2 are formed on the semiconductor substrate 6. A wiring layer is formed in the insulating layer 7. Signals are input to the first transfer gate 11, the charge storage electrode 5, and the second transfer gate 21c via the wiring layer.

[0109] [Timing chart of an example of operation] FIG. 4 is a timing chart showing an example of the operation of the pixel 102. In FIG.

[0110] FIG. 5 is a diagram showing a potential profile of the pixel 102 in each period of FIG.

[0111] 4 shows, from the top, timing charts of a vertical synchronization signal VD, a transfer gate signal TG1, a selection control signal SEL1, a reset control signal RS1, a transfer gate signal TG21, a selection control signal SEL2, a reset control signal RS2, and a voltage AE of the charge storage electrode 5. For ease of understanding, FIG. 4 shows the operation of only one row out of m rows of the pixels 102. Each of the periods V(m-1), Vm, V(m+1), and V(m+2) is a vertical synchronization period, that is, one frame period.

[0112] The transfer gate signals TG1 and TG2 alternate between high and low levels every frame period.

[0113] During the period from time t0 to time t5, i.e., the period V(m-1), the transfer gate signal TG1 is set to a low level, and the transfer gate signal TG2 is set to a high level. As a result, during this period, the signal charge generated in the photoelectric conversion film 2 is transferred to the FD2. Also, during this period, a pixel signal corresponding to the amount of signal charge accumulated in the FD1 is output to the vertical signal line VSIG2 from the first amplification transistor 14 via the first selection transistor 15. Specifically, first, at time t1, the selection control signal SEL1 becomes a high level, and a pixel signal corresponding to the amount of signal charge accumulated in the FD1 is output to the vertical signal line VSIG1. Next, at time t2, the reset control signal RS1 becomes a high level, and the FD1 is reset to the reference potential. Next, at time t3, the reset control signal RS1 becomes a low level, and then a reference signal corresponding to the reference potential is output to the vertical signal line VSIG1. Thereafter, at time t5, the selection control signal SEL1 becomes a low level, and the readout operation is completed. By taking the difference between the pixel signal output to the vertical signal line VSIG1 and the reference signal, a signal corresponding to the amount of light incident on the photoelectric conversion unit OE in one frame period immediately preceding the period V(m-1) is obtained.

[0114] Next, during the period from time t5 to time t10, that is, the period Vm, the transfer gate signal TG1 is set to a high level, and the transfer gate signal TG2 is set to a low level. As a result, during this period, the signal charge generated in the photoelectric conversion film 2 is transferred to FD1. Also, during this period, a pixel signal corresponding to the amount of signal charge accumulated in FD2 is output to the vertical signal line VSIG2 from the second amplification transistor 24 via the second selection transistor 25. Specifically, first, at time t6, the selection control signal SEL2 becomes a high level, and a pixel signal corresponding to the amount of signal charge accumulated in FD2 is output to the vertical signal line VSIG2. Next, at time t7, the reset control signal RS2 becomes a high level, and FD2 is reset to the reference potential. Next, at time t8, the reset control signal RS2 becomes a low level, and then a reference signal corresponding to the reference potential is output to the vertical signal line VSIG2. Thereafter, the selection control signal SEL2 becomes a low level, and the readout operation is completed. By taking the difference between the pixel signal output to the vertical signal line VSIG2 and the reference signal, a signal corresponding to the amount of light incident on the photoelectric conversion unit OE during the period V(m-1) is obtained. After that, during the period V(m+1), the same operation as during the period V(m-1) is performed. Moreover, during the period V(m+2), the same operation as during the period Vm is performed.

[0115] In this embodiment, the period V(m-1) is an example of a “first read period”, and the period Vm is an example of a “second read period”. In addition, in this embodiment, the period V(m-1) is an example of a “first period”, and the period Vm is an example of a “second period”.

[0116] In this embodiment, the first period is the entire first read period, and the second period is the entire second read period. However, as described in a later embodiment, the first period and the second period may be a part of the first read period and a part of the second read period, respectively.

[0117] The signal charges may be holes or electrons. The same applies to the following embodiments.

[0118] [Timing chart of detailed operation example] For ease of explanation, the operation of one row of pixels 102 has been described in Fig. 4. Below, the operation of each of the pixels 102 in multiple rows will be described.

[0119] FIG. 6 is a timing chart showing an example of the operation of the pixel of the imaging device according to the first embodiment.

[0120] In the figure, a signal given an (i) indicates that it is a signal to a pixel in the i-th row of multiple rows, and similarly, a signal given an (i+1) indicates that it is a signal to a pixel in the (i+1)-th row of multiple rows.

[0121] In a period V(m-1), the transfer gate signals TG1 and TG2 of all the rows of the pixels 102 are at low and high levels, respectively, so that the signal charges generated in the photoelectric conversion layers 2 of the pixels 102 of all the rows are transferred to the FD2.

[0122] Also, in the period V(m-1), pixel signals corresponding to the amount of signal charge accumulated in FD1 are read out one row or multiple rows at a time. Specifically, first, the selection control signal SEL1(i) goes to high level, and the i-th row is selected. Then, a pixel signal corresponding to the amount of signal charge accumulated in FD1 is output. Then, the reset control signal RS(i) goes to high level, and FD1 is reset to the reference potential. Next, after the reset control signal RS(i) goes to low level, a reference signal corresponding to the reference potential is output. Then, the selection control signal SEL1(i) goes to low level. Thereafter, in the same manner, the (i+1)th row is selected by the selection control signal SEL1(i+1), and a pixel signal and a reference signal are output. In this way, in the period V(m-1), pixel signals corresponding to the amount of signal charge accumulated in FD1 are read out for the pixels 102 in all rows.

[0123] Next, in a period Vm, the transfer gate signals TG1 and TG2 of the pixels 102 in all rows are at high and low levels, respectively, so that the signal charges generated in the photoelectric conversion layers 2 of the pixels 102 in all rows are transferred to the FD1.

[0124] Also, in the period V(m), pixel signals corresponding to the amount of signal charge accumulated in FD2 are read out one row or multiple rows at a time. Specifically, first, the selection control signal SEL2(i) goes to high level, and the i-th row is selected. Then, a pixel signal corresponding to the amount of signal charge accumulated in FD2 is output. Then, the reset control signal RS(i) goes to high level, and FD2 is reset to the reference potential. Next, after the reset control signal RS(i) goes to low level, a reference signal corresponding to the reference potential is output. Then, the selection control signal SEL1(i) goes to low level. Similarly, the (i+1)th row is selected by the selection control signal SEL1(i+1), and a pixel signal and a reference signal are output. In this way, in the period V(m), pixel signals corresponding to the amount of signal charge accumulated in FD2 are read out for the pixels 102 in all rows.

[0125] As described above, in this embodiment, in a certain frame period, the signal charge generated during that period is transferred to FD1, and the signal charge accumulated in FD2 during the previous frame period is read out. Then, in the next frame period, the signal charge generated during that period is transferred to FD2, and the signal charge accumulated in FD1 during the previous frame period is read out. In this way, by alternately switching between FD1 and FD2 and storing and reading out the signal charge, a global shutter function can be realized, and the dead time of exposure can be suppressed or eliminated.

[0126] (Embodiment 2) In the first embodiment, the first transfer gate signal TG1 and the second transfer gate signal TG2 change complementary to each other. This embodiment differs from the first embodiment in that there is a period during which both the first transfer gate TG1 and the second transfer gate TG2 are at a low level.

[0127] Fig. 7 is a timing chart showing an example of the operation of a pixel of the imaging device according to this embodiment. In the example of operation in Fig. 7, the same points as in Fig. 6 will not be described repeatedly, and different points will be mainly described below.

[0128] In period V(m-1), the first transfer gate signal TG1 is at a low level. On the other hand, the second transfer gate signal TG2 is at a low level in period T3 and at a high level in period T1. In period T3, the signal charge is held in the semiconductor layer 3 between the first transfer gate 11 and the second transfer gate 21. Thereafter, in period T1, the signal charge is transferred to the first electrode 10.

[0129] In period V(m), the second transfer gate signal TG2 is at a low level. On the other hand, the first transfer gate signal TG1 is at a low level in period T4 and becomes at a high level in the following period T2. In period T4, the signal charge is held in the semiconductor layer 3 between the first transfer gate 11 and the second transfer gate 21. Thereafter, in period T2, the signal charge is transferred to the second electrode 20.

[0130] In this embodiment, each frame period includes a period during which both TG1 and TG2 are at a low level. This period is not a dead time for exposure, and the signal charges generated in the photoelectric conversion unit OE are accumulated in the semiconductor layer 3 even during this period.

[0131] In this embodiment, the period V(m-1) is an example of a “first read period”, and the period Vm is an example of a “second read period”. In this embodiment, the period T1 is an example of a “first period”, and the period T2 is an example of a “second period”.

[0132] The potential diagram corresponding to the operation example of Fig. 7 is similar to Fig. 5. However, Fig. 5(a) differs in that it corresponds to period T1 instead of the entire period V(m-1).

[0133] According to this embodiment, in a certain frame period, as in the first embodiment, the signal charge generated during that period is transferred to FD1, and the signal charge accumulated in FD2 during the previous frame period is read out. Then, in the next frame period, the signal charge generated during that period is transferred to FD2, and the signal charge accumulated in FD1 during the previous frame period is read out. In this way, by alternately switching between FD1 and FD2 for accumulation and reading of signal charge, a global shutter function can be realized, and the dead time of exposure can be suppressed or eliminated.

[0134] (Embodiment 3) In the first and second embodiments, it is assumed that the capacitance of FD1 is the same as that of FD2. In the third embodiment, the capacitance of FD1 is different from that of FD2. As a result, the imaging device of this embodiment can generate a sensitivity difference between the detection signal obtained from FD1 and the detection signal obtained from FD2. Therefore, for example, the dynamic range can be expanded by combining the detection signal obtained from FD1 and the detection signal obtained from FD2.

[0135] Fig. 8 is a diagram showing an example of a circuit configuration of a pixel of an imaging device according to this embodiment. The pixel in Fig. 8 differs from the pixel in Fig. 2A of embodiment 1 in that a capacitor 22C is added. Since the other configurations and operations are the same as those of embodiment 1 or embodiment 2, their explanations will be omitted, and the following explanation will focus on the differences.

[0136] In this embodiment, the FD2 includes a capacitor 22C. One end of the capacitor 22C is connected to the second electrode 20, the source of the second reset transistor 23, and the gate of the second amplification transistor 24. A predetermined voltage VCP is applied to the other end of the capacitor 22C. The predetermined voltage VCP is for adjusting the amount of charge that can be stored in the capacitor 22C.

[0137] In this embodiment, the capacitance of FD2 is larger than the capacitance of FD1 due to the addition of the capacitor 22C. This makes the sensitivity of the detection signal output from the first amplifying transistor 14 higher than the sensitivity of the detection signal output from the second amplifying transistor 24. As a result, for example, by combining these detection signals, the dynamic range can be expanded.

[0138] In the present embodiment, the capacitor 22C is added, but the present invention is not limited to this. For example, in FIG. 3, the diffusion layers 12 and 22 may have different configurations so that the capacitance of the diffusion layer 22 is larger than the capacitance of the diffusion layer 12.

[0139] Also, the length of the exposure period corresponding to the detection signal obtained from FD1 may be made different from the length of the exposure period corresponding to the detection signal obtained from FD2. Specifically, the length of the exposure period in which the signal charge transferred to FD1 is generated may be made different from the length of the exposure period in which the signal charge transferred to FD2 is generated. For example, in FIG. 7, the length of the period V(m), period V(m+2), etc. may be made longer than the length of the period V(m-1), period V(m+1), etc. Alternatively, for example, in FIG. 7, the timing of the period T1 in the period V(m), period V(m+2), etc. may be shifted forward, so that the length of the period from the end of the period T1 to the end of the next period T2 may be made longer than the length of the period from the end of the period T2 to the end of the next period T1. Even in such a form, the dynamic range can be expanded by combining the detection signal obtained from FD1 and the detection signal obtained from FD2.

[0140] (Embodiment 4) In the first to third embodiments, an operation example in which the transfer gate signals TG1 and TG2 are alternately switched every frame is described. In the present embodiment, an operation example in which the transfer gate signals TG1 and TG2 are switched within one frame is described. In the present embodiment, the signal charge that cannot be transferred to FD1 and remains above the charge storage electrode 5 is transferred to FD2.

[0141] The circuit configuration of the pixel of the imaging device of this embodiment is the same as that of the third embodiment shown in FIG.

[0142] Fig. 9 is a timing chart showing an example of the operation of the pixel of the imaging device of this embodiment, and Fig. 10 is a diagram showing a potential profile of the pixel 102 in each period of Fig. 9.

[0143] In the period from time t0 to time t7, the selection control signals SEL1 and SEL2 are at a high level, and during this period, signals are output from the pixels 102 to the vertical signal line VSIG1.

[0144] In the period from time t1 to time t2, the reset control signals RS1 and RS2 are at a high level, which resets the potentials of FD1 and FD2 to the reference potentials VRST1 and VRST2, respectively.

[0145] In the period from time t2 to time t3, a signal VR1 corresponding to the reference potential VRST1 is output to the vertical signal line VSIG1, and a signal VR2 corresponding to the reference potential VRST2 is output to the vertical signal line VSIG2.

[0146] In the period from time t3 to time t4, the transfer gate signal TG1 goes high, and the signal charge stored above the charge storage electrode 5 is transferred to FD1. At this time, if the amount of signal charge is greater than a predetermined amount, FD1 is saturated, and some of the signal charge that has not been transferred to FD1 remains above the charge storage electrode 5.

[0147] In the period from time t4 to time t5, a signal VS1 corresponding to the amount of signal charge transferred to FD1 is output to a vertical signal line VSIG1. A downstream signal processing circuit 104 obtains a signal corresponding to the amount of signal charge transferred to FD1 by correlated double sampling of the signals VS1 and VR1.

[0148] In the period from time t5 to time t6, the transfer gate signal TG2 goes high. As a result, the signal charge remaining above the charge storage electrode 5 without being transferred to FD1 is transferred to FD2. Since FD2 includes the capacitor 22C, the capacitance of FD2 is larger than the capacitance of FD1. Therefore, FD2 can store more signal charge than FD1.

[0149] In the period from time t6 to time t7, a signal VS2 corresponding to the amount of signal charge transferred to FD2 is output to the vertical signal line VSIG2. The signal processing circuit 104 at the subsequent stage can obtain a signal corresponding to the amount of signal charge remaining above the charge storage electrode 5 without being transferred to FD1, i.e., the amount of signal charge transferred to FD2, by correlated double sampling of the signals VS2 and VR2.

[0150] In this embodiment, the capacity of FD1 is set smaller than the capacity of FD2. As a result, a high-sensitivity detection signal can be obtained from the signal charge transferred to FD1. A low-sensitivity detection signal can be obtained from the signal charge that is not transferred to FD1 and remains and is transferred to FD2. Therefore, for example, by combining these detection signals, the dynamic range can be expanded. In addition, since these signal charges are signal charges obtained during almost the same exposure period, there is almost no deviation in the exposure period between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In addition, since these signal charges are photoelectrically converted by the same photoelectric conversion unit OE, the optical centers are also the same between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In this way, in this embodiment, the dynamic range can be expanded without causing almost any deviation in the exposure time or optical center.

[0151] (Embodiment 5) In the first to third embodiments, the transfer gate signals TG1 and TG2 are alternately switched. In the present embodiment, an operation example will be described in which the transfer gate signal TG1 is always at a high level and the transfer gate signal TG2 is always at a low level or a middle level.

[0152] The circuit configuration of the pixel of the imaging device of this embodiment is the same as that of the third embodiment shown in FIG.

[0153] 11 is a timing chart showing an example of the operation of a pixel of the imaging device of this embodiment. In the figure, "H" indicates a high level, "M" indicates a middle level, and "L" indicates a low level. In the figure, the transfer gate signal TG1 is always at a high level. The transfer gate signal TG2 is always at a middle level or a low level. FIG. 12 is a diagram showing a potential profile of the pixel 102 in each period of FIG. 11.

[0154] In this embodiment, the charge generated on the charge storage electrode 5 is first stored in FD1. When the light is strong and the charge stored in FD1 exceeds the potential barrier on the second transfer gate 21, the charge overflowing from FD1 is stored in FD2.

[0155] 11, at time t0, the selection control signal SEL1 and the selection control signal SEL2 change from low level to high level. This starts a period for outputting a signal from the pixel 102 to the vertical signal line VSIG1. Since the transfer gate signal TG1 is always at high level, at this point in time, signal charges generated by photoelectric conversion are accumulated in the FD1.

[0156] In the period from time t0 to time t1, a signal VS1 corresponding to the amount of signal charge stored in FD1 is output to a vertical signal line VSIG1.

[0157] In the period from time t1 to time t2, the reset control signal RS1 is at a high level, which resets the potential of FD1 to the reference potential VRST1.

[0158] In the period from time t2 to time t3, a signal VR1 corresponding to the reference potential VRST1 is output to the vertical signal line VSIG1. The signal processing circuit 104 at the subsequent stage obtains a signal corresponding to the amount of signal charge accumulated in FD1 by correlated double sampling of the signals VS1 and VR1.

[0159] When signal charges are generated during the exposure period in an amount greater than the amount that FD1 can accumulate, the charges are transferred to FD2 over the potential barrier created by the second transfer gate 21. Since a capacitor 22C is added to FD2, the capacitance of FD2 is greater than the capacitance of FD1. Therefore, FD2 can accumulate more signal charges than FD1.

[0160] In the period from time t2 to time t3, a signal VS2 corresponding to the amount of signal charge accumulated in FD2 is output to the vertical signal line VSIG2.

[0161] In the period from time t3 to time t4, the reset control signal RS2 is at a high level, which resets the potential of FD2 to the reference potential VRST2.

[0162] In the period from time t4 to time t5, a signal VR2 corresponding to the reference potential VRST2 is output to the vertical signal line VSIG2. The signal processing circuit 104 at the subsequent stage obtains a signal corresponding to the amount of signal charge transferred to FD2 by correlated double sampling of the signals VS2 and VR2.

[0163] In the imaging device of this embodiment, a high-sensitivity detection signal can be obtained from the signal charges accumulated in the FD1. A low-sensitivity detection signal can be obtained from the signal charges transferred to the FD2 over the potential barrier of the second transfer gate 21. Therefore, for example, by combining these detection signals, the dynamic range can be expanded. In addition, since these signal charges are signal charges obtained in almost the same exposure period, there is almost no difference in the exposure period between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In addition, since these signal charges are photoelectrically converted by the same photoelectric conversion unit OE, the optical centers are also the same between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In this way, in this embodiment, the dynamic range can be expanded without causing almost any difference in exposure time or optical center.

[0164] The level of the transfer gate signal TG2 may be set between low and high levels according to the required sensitivity, and may be fixed or may be changed according to the imaging environment.

[0165] (Embodiment 6) In the first to fifth embodiments, configuration examples including the readout circuit R1 and the readout circuit R2 have been described. In the present embodiment, a configuration example including one readout circuit will be described.

[0166] Fig. 13 is a diagram showing an example of a circuit configuration of a pixel of the imaging device of this embodiment. Fig. 14 is a timing chart showing an example of the operation of the pixel of the imaging device of this embodiment. Fig. 15 is a diagram showing a potential profile of the pixel 102 in each period of Fig. 14.

[0167] The circuit configuration of the pixel in Fig. 13 differs from that in Fig. 8 in that it does not have a readout circuit R2 and that it has an additional connection switch 31. The differences will be mainly described below. The connection switch 31 switches whether or not FD2 is connected to FD1. In other words, the connection switch 31 changes the capacitance of FD1. For example, the connection switch 31 is in an off state when the switch control signal WDR is at a low level, and is in an on state when it is at a high level.

[0168] 14, at time t0, the selection control signal SEL1 changes from low level to high level, starting a period during which the pixel 102 outputs a signal to the vertical signal line VSIG1.

[0169] In the period from time t1 to time t2, the reset control signal RS1 is at a high level, which resets the potential of FD1 to the reference potential VRST1.

[0170] In the period from time t2 to time t3, a signal VR1 corresponding to the reference potential VRST1 is output to the vertical signal line VSIG1.

[0171] In the period from time t3 to time t4, the transfer gate signal TG1 goes high, causing the signal charges stored above the charge storage electrode 5 to be transferred to FD1.

[0172] In the period from time t4 to time t5, a signal VS1 corresponding to the amount of signal charge transferred to FD1 is output to a vertical signal line VSIG1. A downstream signal processing circuit 104 obtains a signal corresponding to the amount of signal charge transferred to FD1 by correlated double sampling of the signals VS1 and VR1.

[0173] In the period from time t5 to time t6, the transfer gate signal TG2 goes high. As a result, if the amount of signal charge stored above the charge storage electrode 5 is greater than the amount that can be transferred to FD1, the excess amount of signal charge is transferred to FD2. Since the capacitor 22C is added to FD2, the capacitance of FD2 is greater than the capacitance of FD1. Therefore, it is possible to transfer and store more signal charge in FD2 than in FD1.

[0174] During the period from time t5 to time t9, the switch control signal WDR goes high, causing FD1 and FD2 to be shorted, and the signal charges transferred to FD1 and FD2 are added together.

[0175] In the period from time t6 to time t7, a signal VS2 corresponding to the amount of signal charge stored in FD1 and FD2 is output to the vertical signal line VSIG1.

[0176] In the period from time t7 to time t8, the reset control signal RS1 goes high again, which resets the potentials of FD1 and FD2 to the reference potential VRST1.

[0177] In the period from time t8 to time t9, a signal VR2 corresponding to the reference potential VRST1 is output to the vertical signal line VSIG1. The signal processing circuit 104 at the subsequent stage obtains a signal corresponding to the sum of the signal charges transferred to FD1 and the signal charges transferred to FD2 by correlated double sampling of the signals VS2 and VR2.

[0178] In this embodiment, a high-sensitivity detection signal can be obtained from the signal charge transferred to FD1. A low-sensitivity detection signal can be obtained from the signal charge obtained by adding up the signal charge transferred to FD1 and the signal charge transferred to FD2. Therefore, for example, by combining these detection signals, the dynamic range can be expanded. In addition, since these signal charges are signal charges obtained during almost the same exposure period, there is almost no difference in the exposure period between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In addition, since these signal charges are photoelectrically converted by the same photoelectric conversion unit OE, the optical center is also the same between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In this way, in this embodiment, the dynamic range can be expanded without causing almost any difference in exposure time or optical center.

[0179] In general, noise called optical shot noise occurs in signal charges, the number of which is √N, which is equivalent to the square root of the number of charges. In this embodiment, the signal charges transferred to FD2 are added to the signal charges transferred to FD1 and then read out, so that the S / N ratio (=N / √N) due to optical shot noise can be made large.

[0180] (Embodiment 7) This embodiment differs from the sixth embodiment in that the second transfer gate 21 is always at a middle level or a low level. An example of the circuit configuration of a pixel of the imaging device of this embodiment is the same as that of the sixth embodiment shown in FIG.

[0181] Fig. 16 is a timing chart showing an example of the operation of the pixel of the imaging device of this embodiment, and Fig. 17 is a diagram showing a potential profile of the pixel 102 in each period of Fig. 16.

[0182] In this embodiment, the signal charge generated in the photoelectric conversion layer 2 is accumulated above the charge storage electrode 5 by a potential barrier formed by the first transfer gate 11 and the second transfer gate 21. The voltage values ​​of the transfer gate signals TG1 and TG2 are set so that the potential barrier by the first transfer gate 11 is higher than the potential barrier by the second transfer gate 21. The potential barrier above the first transfer gate 11 and the potential barrier above the second transfer gate 21 can also be set by the impurity concentration implanted into the semiconductor layer 3 above the first transfer gate 11 and above the second transfer gate 21. In this embodiment, when the signal charge accumulated above the charge storage electrode 5 becomes equal to or greater than a predetermined amount, the signal charge equal to or greater than the predetermined amount is transferred to the FD2 over the potential barrier by the second transfer gate 21.

[0183] 16, at time t0, the selection control signal SEL1 changes from low level to high level, starting a period for outputting signals from pixels to the vertical signal line VSIG1.

[0184] In the period from time t1 to time t2, the reset control signal RS1 is at a high level, which resets the potential of FD1 to the reference potential VRST1.

[0185] In the period from time t2 to time t3, a signal VR1 corresponding to the reference potential VRST1 is output to the vertical signal line VSIG1.

[0186] In the period from time t3 to time t4, the transfer gate signal TG1 goes high, and the signal charges stored above the charge storage electrode 5 are transferred to FD1. In this embodiment, the potential barrier created by the second transfer gate 21 is smaller than the potential barrier created by the first transfer gate 11. Therefore, of the signal charges generated during the exposure period, the signal charges that can overcome the potential barrier created by the second transfer gate 21 have already been transferred to FD2.

[0187] In the period from time t4 to time t5, a signal VS1 corresponding to the amount of signal charge transferred to FD1 is output to a vertical signal line VSIG1. A downstream signal processing circuit 104 obtains a signal corresponding to the amount of signal charge transferred to FD1 by correlated double sampling of the signals VS1 and VR1.

[0188] In the period from time t5 to time t8, the switch control signal WDR is at high level, which causes FD1 and FD2 to be shorted, and the signal charges transferred to FD1 and FD2 are added together.

[0189] In the period from time t5 to time t6, a signal VS2 corresponding to the amount of the combined signal charges is output to the vertical signal line VSIG1.

[0190] In the period from time t6 to time t7, the reset control signal RS1 goes high again, which resets the potentials of FD1 and FD2 to the reference potential VRST1.

[0191] In the period from time t7 to time t8, a signal VR2 corresponding to the reference potential VRST1 is output to the vertical signal line VSIG1. The signal processing circuit 104 at the subsequent stage can obtain a signal corresponding to the sum of the signal charges transferred to FD1 and the signal charges transferred to FD2 by correlated double sampling of the signals VS2 and VR2.

[0192] In this embodiment, a high-sensitivity detection signal can be obtained from the signal charge transferred to FD1. A low-sensitivity detection signal can be obtained from the signal charge obtained by adding up the signal charge transferred to FD1 and the signal charge transferred to FD2. Therefore, for example, by combining these detection signals, the dynamic range can be expanded. Furthermore, since these signal charges are signal charges obtained during almost the same exposure period, there is almost no deviation in the exposure period between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. Furthermore, since these signal charges are photoelectrically converted by the same photoelectric conversion unit OE, the optical centers are also the same between the image obtained from the high-sensitivity detection signal and the image obtained from the low-sensitivity detection signal. In this way, in this embodiment, the dynamic range can be expanded with almost no deviation in the exposure time or the optical center. Furthermore, since the signal VS2 of the highly saturated pixel also includes the signal VS1 of the high-sensitivity pixel, there is no degradation in the S / N ratio of the optical shot noise. In this embodiment, it is possible to realize a wide dynamic range by transferring and reading out the signal charge that could not be read in the conventional example to FD2.

[0193] (Embodiment 8) In this embodiment, an example of an operation for changing the spectral sensitivity characteristics of the photoelectric conversion layer 2 will be described.

[0194] Fig. 18 is a diagram showing a cross-sectional structure of a pixel 102. The cross-sectional structure of Fig. 18 differs from the cross-sectional structure of Fig. 3 in that the photoelectric conversion layer 2 has a laminated structure made up of a first photoelectric conversion layer 2a and a second photoelectric conversion layer 2b. The following mainly describes the differences.

[0195] The first photoelectric conversion layer 2a and the second photoelectric conversion layer 2b have different spectral sensitivity characteristics. For example, the first photoelectric conversion layer 2a has sensitivity in the wavelength range of visible light. The second photoelectric conversion layer 2b has sensitivity in the wavelength range of infrared light.

[0196] FIG. 19 is a timing chart showing the driving of pixels of the imaging device according to this embodiment. FIG. 19 differs from FIG. 7 in that the voltage applied to the counter electrode 1 is changed. In FIG. 19, the second V1 from the top shows the change in voltage applied to the counter electrode 1. In frame period V(m-1), voltage Vb is applied to the counter electrode 1. In frame period V(m), voltage Va, which is different from voltage Vb, is applied to the counter electrode 1. Here, voltage Va is higher than voltage Vb. After frame V(m), voltages Va and Vb are alternately applied to the counter electrode 1 for each frame.

[0197] In the frame period V(m-1), the bias voltage applied to the photoelectric conversion layer 2 is relatively large, so that both the first photoelectric conversion layer 2a and the second photoelectric conversion layer 2b perform photoelectric conversion. Thus, the pixel 102 has sensitivity to both the wavelength ranges of visible light and infrared light. In the frame period V(m), the bias voltage applied to the photoelectric conversion layer 2 is relatively small, so that the first photoelectric conversion layer 2a performs photoelectric conversion, but the second photoelectric conversion layer 2b does not perform photoelectric conversion. Thus, the pixel 102 has sensitivity to the wavelength range of visible light, but not to the wavelength range of infrared light.

[0198] In this way, the voltage V1 applied to the counter electrode 1 is changed between frames. This makes it possible to obtain an image signal based on visible light and infrared light during one frame period, and to obtain an image signal based on visible light during another frame period. The above-mentioned technology for changing the spectral sensitivity characteristics is disclosed in detail in International Publication WO2018 / 025544. This International Publication is incorporated herein by reference.

[0199] In the example shown in FIG. 19, the voltage V1 applied to the counter electrode 1 is changed. However, the voltage V1 of the counter electrode 1 may be kept constant and the voltage of the charge storage electrode 5 may be changed. When changing the voltage of the charge storage electrode 5, the voltages of the first transfer gate 11, the second transfer gate 21, the first electrode 10, and the second electrode 20 may be changed in accordance with the change in the voltage of the charge storage electrode 5 so as not to affect the transfer of the signal charge. Note that the technology for changing the potentials of the first electrode 10 and the second electrode 20 is described in detail in Japanese Patent Publication No. 2019-0544499. This publication is incorporated herein by reference. Even in this form, it is possible to obtain an image signal based on visible light and infrared light in one frame period and an image signal based on visible light in another frame period.

[0200] The photoelectric conversion layer 2 may be a single layer. In this case, the spectral sensitivity characteristics do not change, but the quantum efficiency of the photoelectric conversion layer 2 can be changed by changing the bias voltage. This makes it possible to obtain a high-sensitivity detection signal in one frame period and a low-sensitivity detection signal in another frame period. By combining these detection signals, the dynamic range can be expanded.

[0201] (Embodiment 9) In this embodiment, a configuration example for negatively feeding back the potential of the first electrode 10, that is, the potential of the first charge accumulation unit FD1 during the reset operation will be described.

[0202] Fig. 20A is a diagram showing an example of a circuit configuration of a pixel of the imaging device of this embodiment. The circuit configuration of Fig. 20A differs from the circuit configuration of Fig. 8 in that the readout circuit R1 includes a feedback circuit 201. The following mainly describes the differences.

[0203] The feedback circuit 201 includes a differential amplifier 17 provided for each column. During a reset operation, the feedback circuit 201 negatively feeds back the potential of FD1 to FD1 via the first amplifying transistor 14, the first selection transistor 15, the differential amplifier 17, and the first reset transistor 13. This makes it possible to reduce the kTC noise that occurs when the first reset transistor 13 is turned off.

[0204] The above-mentioned technology for reducing kTC noise is disclosed, for example, in JP 2017-046333 A. This publication is incorporated herein by reference.

[0205] As shown in FIG. 20B, the read circuit R2 may also include a feedback circuit 202 similar to the feedback circuit 201.

[0206] 20A, the second transfer gate 21, the second electrode 20, and the readout circuit R2 may be omitted. In this case, the signal charge accumulated above the charge storage electrode 5 is transferred only to the first electrode 10. In this case, the signal charge accumulated above the charge storage electrode 5 in a certain frame period may be transferred to FD1 simultaneously for all pixels, and a signal corresponding to the amount of signal charge transferred to FD1 may be output sequentially to the vertical signal line SIG1. Then, in parallel with the signal output, the signal charge of the next frame may be accumulated above the charge storage electrode 5. With such an operation, the global shutter function can be realized and the dead time of exposure can be suppressed.

[0207] Fig. 21 is a diagram showing a modified example of the circuit configuration of a pixel of the imaging device of this embodiment. The circuit configuration of Fig. 21 differs from the circuit configuration of Fig. 20A in that the readout circuit R1 includes a feedback circuit 300 instead of the feedback circuit 201. The following description will focus on the differences.

[0208] The feedback circuit 300 includes a transistor 301, a capacitor C9, and a capacitor C10. One of the source and drain of the first amplifying transistor 14 is configured to be selectively supplied with either a voltage VA1 or a voltage VA2. The other of the source and drain of the first amplifying transistor 14 is connected to a vertical signal line SIG1 via a selection transistor 15. During a reset operation, the feedback circuit 300 negatively feeds back the potential of FD1 to FD1 via the first amplifying transistor 14, the first selection transistor 15, and the transistor 301.

[0209] During a reset operation, the switch 18 is turned on and the switch 19 is turned off. During a readout operation in which a signal is read out from the pixel 102, the switch 18 is turned off and the switch 19 is turned on. As a result, during a reset operation, the first amplifying transistor 14 operates as a source-grounded amplifier. During a readout operation, the first amplifying transistor 14 operates as a source-follower amplifier and outputs a signal to the vertical signal line SIG1.

[0210] The above-mentioned technology for reducing kTC noise is disclosed in JP 2016-127593 A. This publication is incorporated herein by reference.

[0211] Fig. 22 is a diagram showing another modified example of the circuit configuration of the pixel of the imaging device of this embodiment. The circuit configuration of Fig. 22 differs from the circuit configuration of Fig. 21 in that the readout circuit R1 includes a feedback circuit 400 instead of the feedback circuit 300. The following mainly describes the differences.

[0212] The feedback circuit 400 includes a transistor 401, a capacitor C9, and a capacitor C10. The feedback circuit 400 feeds back the potential of FD1 to FD1 via a transistor and the first reset transistor 13 during a reset operation.

[0213] The above-mentioned technology for reducing kTC noise is disclosed in JP 2016-127593 A. This publication is incorporated herein by reference.

[0214] According to the imaging device of this embodiment, it is possible to reduce the kTC noise that occurs when the first reset transistor 13 is turned off during the reset operation.

[0215] The processing units included in each of the imaging devices according to the above embodiments are typically realized as an LSI, which is an integrated circuit. These units may be individually implemented as single chips, or some or all of them may be included in a single chip.

[0216] The integrated circuit is not limited to an LSI, but may be realized by a dedicated circuit or a general-purpose processor. A field programmable gate array (FPGA) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure the connections and settings of the circuit cells inside the LSI may also be used.

[0217] In each of the above embodiments, a part of each component may be realized by executing a software program suitable for the component. The component may be realized by a program execution unit such as a CPU or a processor reading and executing a software program recorded on a recording medium such as a hard disk or a semiconductor memory.

[0218] Furthermore, each of the above embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents. [Industrial Applicability]

[0219] The imaging device and imaging system according to the present disclosure can be used in various camera systems and sensor systems, such as digital still cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras. [Explanation of symbols]

[0220] 1 Counter electrode 2 Photoelectric conversion layer 2a First photoelectric conversion layer 2b Second photoelectric conversion layer 3 Semiconductor layer 4. Insulation Layer 5 Charge storage electrode 6. Semiconductor Substrates 7 Insulating layer 10 1st electrode 10c, 20c Contank 11 First Transfer Gate 12 First diffusion layer 13 First reset transistor 14 First amplifying transistor 15 First selection transistor 16 Current source 17 Differential Amplifier 20 2nd electrode 21 Second Transfer Gate 22 Second diffusion layer 22C Capacitor 23 Second reset transistor 24 Second Amplification Transistor 25 Second selection transistor 26 Current source 27 Differential Amplifier 31 Connection switch 100 Imaging device 101 pixel array 102 pixels 103 Row Scanning Circuit 104 Signal Processing Circuit 105 Output circuit 106 Control circuit 107 Voltage supply circuit 201, 202, 300, 400 Feedback circuit FD1 First charge storage section FD2 2nd charge storage section F1, F11, FB1, FB2 feedback lines OE Photoelectric conversion section R1, R2 Readout circuit RS1, RS2 Reset control signals SEL1, SEL2 Selection control signal SIG1, SIG2 vertical signal line TG1, TG2 Transfer gate signals WDR switch control signal

Claims

1. A plurality of pixels are provided, Each of the plurality of pixels is a photoelectric conversion layer that converts light into a signal charge; A counter electrode that applies a bias voltage to the photoelectric conversion layer; a first electrode and a second electrode that are spaced apart from each other and collect the signal charges generated in the photoelectric conversion layer; a first transfer gate for controlling the transfer of the signal charges to the first electrode; a second transfer gate for controlling the transfer of the signal charges to the second electrode; a first amplifying transistor having a first gate electrically connected to the first electrode; a second amplifying transistor having a second gate electrically connected to the second electrode; Including, during a first readout period during which the first amplification transistor outputs a signal corresponding to a potential of the first gate, the first transfer gate suppresses transfer of the signal charge to the first electrode; during a second readout period during which the second amplification transistor outputs a signal corresponding to a potential of the second gate, the second transfer gate suppresses the transfer of the signal charge to the second electrode; the first readout period includes a first period during which the second transfer gate transfers the signal charge to the second electrode; the second readout period includes a second period during which the first transfer gate transfers the signal charge to the first electrode; the first read period includes a third period immediately preceding the first period, In the third period, the second transfer gate suppresses the transfer of the signal charges to the second electrode; the second read period includes a fourth period immediately preceding the second period, In the fourth period, the first transfer gate suppresses the transfer of the signal charges to the first electrode. Imaging device.

2. An imaging device, A plurality of pixels are provided, Each of the plurality of pixels is a photoelectric conversion layer that converts light into a signal charge; A counter electrode that applies a bias voltage to the photoelectric conversion layer; a first electrode and a second electrode that are spaced apart from each other and collect the signal charges generated in the photoelectric conversion layer; a first transfer gate for controlling the transfer of the signal charges to the first electrode; a second transfer gate for controlling the transfer of the signal charges to the second electrode; a first amplifying transistor having a first gate electrically connected to the first electrode; a second amplifying transistor having a second gate electrically connected to the second electrode; Including, during a first readout period during which the first amplification transistor outputs a signal corresponding to a potential of the first gate, the first transfer gate suppresses transfer of the signal charge to the first electrode; during a second readout period during which the second amplification transistor outputs a signal corresponding to a potential of the second gate, the second transfer gate suppresses the transfer of the signal charge to the second electrode; the first readout period includes a first period during which the second transfer gate transfers the signal charge to the second electrode; the second readout period includes a second period during which the first transfer gate transfers the signal charge to the first electrode; The imaging device further includes a voltage supply circuit connected to the counter electrode, The voltage supply circuit includes: supplying a first voltage to the counter electrode during the first readout period; supplying a second voltage different from the first voltage to the counter electrode during the second readout period; Imaging device.

3. The photoelectric conversion layer is A first photoelectric conversion layer having sensitivity to light in a first wavelength range; a second photoelectric conversion layer having sensitivity to light in a second wavelength range different from the first wavelength range; Including, The imaging device according to claim 2 .

4. The length of the first period is equal to the length of the first read period; The length of the second period is equal to the length of the second read period. The imaging device according to claim 2 or 3.

5. The first read period and the second read period are alternately repeated in succession. The imaging device according to claim 1 .

6. Each of the plurality of pixels is a first charge accumulation section electrically connected to the first electrode and accumulating the signal charges collected by the first electrode; a second charge accumulation section electrically connected to the second electrode and configured to accumulate the signal charges collected by the second electrode; Further comprising: The imaging device according to claim 1 .

7. The capacitance of the first charge storage unit is smaller than the capacitance of the second charge storage unit. The imaging device according to claim 6.

8. Each of the plurality of pixels further includes a capacitor connected to the second electrode. The imaging device according to claim 1 .

9. Each of the plurality of pixels further includes a charge storage electrode located between the first transfer gate and the second transfer gate and facing the counter electrode via the photoelectric conversion layer. The imaging device according to claim 1 .

10. Each of the plurality of pixels further includes a semiconductor layer located between the photoelectric conversion layer, the first electrode, and the second electrode. The imaging device according to claim 1 .

11. The charge mobility of the semiconductor layer is higher than the charge mobility of the photoelectric conversion layer. The imaging device according to claim 10.

12. The length of the first read period is equal to the length of the second read period. The imaging device according to claim 1 .

13. The length of the first readout period is equal to the length of one vertical synchronization period. The imaging device according to claim 12.

14. The length of the second read period is longer than the length of the first read period. The imaging device according to claim 1 .

15. Each of the plurality of pixels further includes a first feedback circuit that negatively feeds back the potential of the first electrode to the first electrode. The imaging device according to claim 1 .

16. Each of the plurality of pixels further includes a second feedback circuit that negatively feeds back the potential of the second electrode to the second electrode. The imaging device according to claim 15.

17. A voltage supply circuit is provided, The voltage supply circuit includes: supplying, to the first transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charges to the first electrode during the first readout period; supplying, to the second transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charges to the second electrode during the second readout period; supplying a voltage to the second transfer gate in the first period to form an electric field that allows the signal charges to move to the second electrode; supplying, to the first transfer gate, a voltage that forms an electric field that allows the signal charges to move to the first electrode during the second period; The imaging device according to claim 1 .

18. A voltage supply circuit is further provided, The voltage supply circuit includes: supplying, to the first transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charges to the first electrode during the first readout period and the fourth period; supplying, to the second transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charges to the second electrode during the second readout period and the third period; supplying a voltage to the second transfer gate in the first period to form an electric field that allows the signal charges to move to the second electrode; supplying, to the first transfer gate, a voltage that forms an electric field that allows the signal charges to move to the first electrode during the second period; The imaging device according to claim 1 .

19. A pixel array display device comprising: a plurality of pixels; and a voltage supply circuit; Each of the plurality of pixels is a photoelectric conversion layer that converts light into a signal charge; A counter electrode that applies a bias voltage to the photoelectric conversion layer; a first electrode and a second electrode that are spaced apart from each other and collect the signal charges generated in the photoelectric conversion layer; a first transfer gate for controlling the transfer of the signal charges to the first electrode; a second transfer gate for controlling the transfer of the signal charges to the second electrode; a first amplifying transistor having a first gate electrically connected to the first electrode; a second amplifying transistor having a second gate electrically connected to the second electrode; Including, The voltage supply circuit includes: supplying, to the first transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charge to the first electrode during a first readout period in which the first amplification transistor outputs a signal corresponding to the potential of the first gate; supplying, to the second transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charge to the second electrode during a second readout period in which the second amplification transistor outputs a signal corresponding to the potential of the second gate; supplying a voltage to the second transfer gate to form an electric field that allows the signal charge to move to the second electrode during a first period included in the first readout period; supplying a voltage to the first transfer gate to form an electric field that allows the signal charge to move to the first electrode during a second period included in the second readout period; the first read period includes a third period immediately preceding the first period, In the third period, the second transfer gate suppresses the transfer of the signal charges to the second electrode; the second read period includes a fourth period immediately preceding the second period, In the fourth period, the first transfer gate suppresses the transfer of the signal charges to the first electrode. Imaging device.

20. A pixel pixel array comprising: a plurality of pixels; and a voltage supply circuit; Each of the plurality of pixels is a photoelectric conversion layer that converts light into a signal charge; A counter electrode that applies a bias voltage to the photoelectric conversion layer; a first electrode and a second electrode that are spaced apart from each other and collect the signal charges generated in the photoelectric conversion layer; a first transfer gate for controlling the transfer of the signal charges to the first electrode; a second transfer gate for controlling the transfer of the signal charges to the second electrode; a first amplifying transistor having a first gate electrically connected to the first electrode; a second amplifying transistor having a second gate electrically connected to the second electrode; Including, The voltage supply circuit includes: supplying, to the first transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charge to the first electrode during a first readout period in which the first amplification transistor outputs a signal corresponding to the potential of the first gate; supplying, to the second transfer gate, a voltage that forms an electric field that acts as a barrier against the movement of the signal charge to the second electrode during a second readout period in which the second amplification transistor outputs a signal corresponding to the potential of the second gate; supplying a voltage to the second transfer gate to form an electric field that allows the signal charge to move to the second electrode during a first period included in the first readout period; supplying a voltage to the first transfer gate to form an electric field that allows the signal charge to move to the first electrode during a second period included in the second readout period; connected to the counter electrode, supplying a first voltage to the counter electrode during the first readout period; supplying a second voltage different from the first voltage to the counter electrode during the second readout period; Imaging device.

Images