Semiconductor chips

Abstract

To provide a semiconductor chip capable of reducing its manufacturing cost.SOLUTION: A semiconductor chip 10 includes a substrate 23 and an epitaxial layer 24, and has a rectangular shape when viewed in a thickness direction. The semiconductor chip 10 includes an operation layer region 25 and a chip outer periphery region 26. When a length of the semiconductor chip 10 in a crystal plane orientation <11-20> is set to a length A1 and the maximum length of the operation layer region 25 in the direction of the crystal plane orientation <11-20> is set to a length A2, and also when a length of the semiconductor chip 10 in a direction orthogonal to the direction of the crystal plane orientation <11-20> is set to a length B1 and the maximum length of the operation layer region 25 in the direction orthogonal to the direction of the crystal plane orientation <11-20> is set to a length B2, a difference value obtained by subtracting the length A2 from the length A1 and a difference value obtained by subtracting the length B2 from the length B1 are different.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to semiconductor chips. [Background technology]

[0002] A method for manufacturing a semiconductor device is known in which a device portion is formed on a substrate made of silicon carbide and the device portion is separated into individual pieces (see, for example, Patent Document 1). According to Patent Document 1, trench grooves are formed in the substrate along the shape of an electrode film, and the device portion is separated into individual pieces along the trench grooves. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-206221 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacture of semiconductor chips, it is necessary to improve the so-called yield and reduce the manufacturing cost. Therefore, one of the objects of the present invention is to provide a semiconductor chip that can reduce the manufacturing cost. [Means for solving the problem]

[0005] A semiconductor chip according to the present disclosure includes a substrate made of SiC and including a first main surface with an off-angle of 4° or less, and an epitaxial layer formed on the first main surface, and is rectangular when viewed in the thickness direction. When viewed in the thickness direction of the semiconductor chip, the semiconductor chip includes an operating layer region including an active region arranged in a central region of the semiconductor chip and a field stop region arranged on the outer periphery of the active region, and a chip outer periphery region surrounding the operating layer region and arranged along the outer edge of the semiconductor chip. The outer edges of the field stop region are each arranged along the outer edge of the semiconductor chip and include four sides that constitute the outer edge of the operating layer region. If the length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is length A1, the maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is length A2, the length of the semiconductor chip in a direction perpendicular to the direction of the crystal plane orientation <11-20> is length B1, and the maximum length of the operating layer region in the direction perpendicular to the direction of the crystal plane orientation <11-20> is length B2, the difference between length A1 and length A2 is different from the difference between length B1 and length B2. Effect of the Invention

[0006] According to the above semiconductor chip, the manufacturing cost can be reduced. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view of a part of a semiconductor chip according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing a part of the semiconductor chip shown in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view showing a part of the semiconductor chip shown in FIG. [Figure 4] FIG. 4 is a diagram showing a state in which an active layer region is formed on a disk-shaped substrate in the first embodiment, as viewed in the thickness direction. [Diagram 5] FIG. 5 is a schematic plan view of a semiconductor chip in the second embodiment. [Figure 6]FIG. 6 is a diagram showing a state in which an active layer region is formed on a disk-shaped substrate in the second embodiment, as viewed in the thickness direction. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. The semiconductor chip according to the present disclosure includes a substrate made of SiC and including a first main surface with an off angle of 4° or less, and an epitaxial layer formed on the first main surface, and is rectangular when viewed in the thickness direction. The semiconductor chip includes an operating layer region including an active region arranged in a central region of the semiconductor chip and a field stop region arranged on the outer periphery of the active region when viewed in the thickness direction of the semiconductor chip, and a chip outer periphery region surrounding the operating layer region and arranged along the outer edge of the semiconductor chip. The outer edge of the field stop region is arranged along the outer edge of the semiconductor chip and includes four sides that constitute the outer edge of the operating layer region. If the length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is length A1, the maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is length A2, the length of the semiconductor chip in a direction perpendicular to the direction of the crystal plane orientation <11-20> is length B1, and the maximum length of the operating layer region in the direction perpendicular to the direction of the crystal plane orientation <11-20> is length B2, the difference between length A1 and length A2 is different from the difference between length B1 and length B2.

[0009] The semiconductor chip is rectangular, and includes an operating layer region including an active region arranged in the center of the semiconductor chip and a field stop region arranged on the outer periphery of the active region, as viewed in the thickness direction of the semiconductor chip, and a chip peripheral region surrounding the operating layer region and arranged along the outer edge of the semiconductor chip. Such a semiconductor chip is manufactured, for example, by using a disk-shaped substrate (wafer), forming a device section using an epitaxial layer grown on the substrate as an active region, and then dicing the substrate to separate it into individual pieces. A plurality of semiconductor chips can be obtained from one substrate. In consideration of separating each semiconductor chip into individual pieces, a dicing region including a cutting margin arranged between each semiconductor chip is provided on the substrate. That is, the substrate on which the epitaxial layer is formed includes a plurality of operating layer regions arranged at intervals from each other as viewed in the thickness direction of the substrate, chip peripheral regions arranged on the outer periphery of each operating layer region, and a dicing region arranged on the outer periphery of each chip peripheral region.

[0010] Here, defects may occur during the crystal growth of the epitaxial layer formed on the substrate. If crystal defects are present in the region that operates as a device section, the crystal defects may become a current path. This may cause a breakdown voltage failure of the semiconductor chip. From the viewpoint of ensuring the reliability of the semiconductor chip to ensure reliable operation, such a semiconductor chip will be a defective product.

[0011] The number of semiconductor chips that can be obtained from one substrate is limited. Therefore, unless the number of defective semiconductor chips obtained from one substrate can be reduced and a large number of high-reliability good semiconductor chips can be obtained, the yield will decrease. As a result, it will be impossible to reduce manufacturing costs.

[0012] In some cases, a semiconductor chip is required to include a semiconductor layer made of SiC (silicon carbide) as an operating layer in terms of improving breakdown voltage. Here, the present inventors have focused on the fact that when epitaxial crystal growth is performed using a substrate made of SiC in a semiconductor chip, crystal defects are more likely to occur during crystal growth than when epitaxial crystal growth is performed using a substrate made of Si (silicon). Then, when manufacturing a semiconductor chip using a substrate made of SiC, the following points have been found. That is, when epitaxial crystal growth is performed on a substrate made of SiC, the direction in which crystal defects grow from the main surface of the substrate is longer in the direction of the crystal plane orientation <11-20>. Then, the inventors have focused on the fact that crystal defects starting from the main surface of the substrate extend longer in the direction of the crystal plane orientation <11-20> than in the direction perpendicular to the direction of the crystal plane orientation <11-20>. The inventors have conducted extensive research into ways to prevent as many defective products as possible that are caused by crystal defects in the active layer region, and have come up with the present invention.

[0013] According to the semiconductor chip of the present disclosure, the length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is length A1, the maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is length A2, the length of the semiconductor chip in the direction perpendicular to the direction of the crystal plane orientation <11-20> is length B1, and the maximum length of the operating layer region in the direction perpendicular to the direction of the crystal plane orientation <11-20> is length B2. Since the growth direction of the crystal defect is the direction of the crystal plane orientation <11-20>, by configuring in this way, the probability that the crystal defect is included in the operating layer region during epitaxial crystal growth can be reduced compared to the case where the difference value of ... That is, the idea of ​​the inventors is to arrange many crystal defects that occur during epitaxial crystal growth in the chip outer peripheral region and dicing region that do not affect the operation of the semiconductor chip. Therefore, among the multiple semiconductor chips obtained from one substrate, the number of semiconductor chips that cause voltage failure and become defective products can be reduced. As a result, the manufacturing cost can be reduced.

[0014] In the above semiconductor chip, in a cross section of the semiconductor chip cut in the thickness direction, if the thickness of the epitaxial layer is T1, the difference obtained by subtracting the length A2 from the length A1 may be greater than the value obtained by dividing the thickness T1 by the tangent of the off-angle of the substrate. The thickness T1 of the epitaxial layer is specified according to the breakdown voltage required for the semiconductor chip. In this way, the difference obtained by subtracting the length A2 from the length A1 can be appropriately set according to the thickness T1 of the epitaxial layer, thereby further reducing the probability that crystal defects are included in the operating layer region. Therefore, the manufacturing cost can be more appropriately reduced.

[0015] In the above semiconductor chip, the off angle may be 4 degrees. Such a semiconductor chip has good productivity, and therefore the manufacturing cost can be further reduced.

[0016] In the semiconductor chip, the thickness T1 may be 4 μm or more and 30 μm or less. In this way, the withstand voltage required for a semiconductor chip can be sufficiently ensured, and when the semiconductor chip according to the present disclosure is used, the area of ​​the active layer region in the chip area can be prevented from becoming excessively small, thereby providing a semiconductor chip with low resistance when conductive.

[0017] In the above semiconductor chip, the difference between length A1 and length A2 may be greater than the difference between length B1 and length B2. In this way, many crystal defects can be arranged between the operating layer regions of the semiconductor chips arranged at intervals in the crystal plane orientation <11-20>, and the probability of manufacturing a semiconductor chip in which crystal defects are included in the operating layer region and thus the breakdown voltage is poor can be reduced. This improves the yield of the semiconductor chips and further reduces the manufacturing cost.

[0018] In the above semiconductor chip, the difference between length A1 and length A2 may be 0.2 mm or more. The difference between length B1 and length B2 may be 0.1 mm or more. By specifying each length in this way, it is possible to reliably reduce manufacturing costs.

[0019] In the above semiconductor chip, the difference between length A1 and length A2 may be 0.5 mm or more. The difference between length B1 and length B2 may be 0.1 mm or more. By specifying each length in this manner, it is possible to more reliably reduce manufacturing costs.

[0020] In addition, in the above semiconductor chip, the difference between length A1 and length A2 may be smaller than the difference between length B1 and length B2. In this way, many crystal defects can be arranged between the operating layer regions of the semiconductor chips spaced apart in a direction perpendicular to the crystal plane orientation <11-20>, and the probability of manufacturing a semiconductor chip in which crystal defects are included in the operating layer region and thus the breakdown voltage is poor can be reduced. This improves the yield of the semiconductor chips and further reduces the manufacturing cost.

[0021] In the above semiconductor chip, the difference between length A1 and length A2 may be 0.1 mm or more. The difference between length B1 and length B2 may be 0.2 mm or more. By specifying each length in this way, it is possible to reliably reduce manufacturing costs.

[0022] In the above semiconductor chip, the difference between length A1 and length A2 may be 0.2 mm or more. The difference between length B1 and length B2 may be 0.3 mm or more. By specifying each length in this way, it is possible to reliably reduce manufacturing costs.

[0023] In the above semiconductor chip, the difference between length A1 and length A2 may be 0.1 mm or more. The difference between length B1 and length B2 may be 0.5 mm or more. By specifying each length in this manner, it is possible to more reliably reduce manufacturing costs.

[0024] [Details of the embodiment of the present disclosure] Next, an embodiment of a semiconductor chip according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0025] (Embodiment 1) The configuration of the semiconductor chip in the first embodiment of the present disclosure will be described. FIG. 1 is a schematic cross-sectional view of a semiconductor chip according to the first embodiment when a part of the semiconductor chip is cut. In FIG. 1, a part of the semiconductor chip is illustrated in a schematic manner. FIG. 2 is a schematic plan view showing a part of the semiconductor chip shown in FIG. 1. FIG. 3 is a schematic cross-sectional view showing a part of the semiconductor chip shown in FIG. 1. In FIG. 1, FIG. 2, and FIG. 3, the direction indicated by the arrow X and the opposite direction indicate the direction of the crystal plane orientation <11-20> described later. In addition, the direction indicated by the arrow Y and the opposite direction indicate the direction perpendicular to the direction of the crystal plane orientation <11-20>. In addition, the direction indicated by the arrow Z and the opposite direction indicate the thickness direction of the semiconductor chip. In FIG. 3, crystal defects are illustrated in a schematic manner from the viewpoint of facilitating understanding.

[0026] 1, 2 and 3, the semiconductor chip 20 according to the first embodiment is included in a semiconductor device such as a power module. The semiconductor chip 20 includes a first electrode 11 and a second electrode 12 also called a back electrode. The first electrode 11 and the second electrode 12 are both made of, for example, Al (aluminum). The semiconductor chip 20 is used as, for example, a transistor chip or a diode chip. When the semiconductor chip 20 is a transistor chip, the first electrode 11 becomes a source electrode or a gate electrode, and the second electrode 12 becomes a drain electrode. When the semiconductor chip 20 is a diode chip, the first electrode 11 becomes an anode electrode, and the second electrode 12 becomes a cathode electrode.

[0027] The semiconductor chip 20 includes a semiconductor layer made of SiC as an operating layer. The semiconductor chip 20 is a wide band gap semiconductor chip. A wide band gap semiconductor chip is a semiconductor chip having a semiconductor layer made of a material with a band gap larger than that of silicon as an operating layer. Such a wide band gap semiconductor chip has a high dielectric breakdown voltage, i.e., a high withstand voltage. In addition, since the resistance of the drift layer can be reduced, the on-resistance can be reduced.

[0028] The semiconductor chip 20 is rectangular when viewed in the thickness direction. When viewed in the thickness direction of the semiconductor chip 20, the outer edge 21 of the semiconductor chip 20 includes four sides 22a, 22b, 22c, and 22d. The sides 22a, 22b, 22c, and 22d are each composed of a line segment. The sides 22a and 22b are arranged parallel to each other with a gap in the X direction, forming an opposing pair. The sides 22c and 22d are arranged parallel to each other with a gap in the Y direction, i.e., in a direction perpendicular to the X direction, forming an opposing pair. The sides 22a, 22b, 22c, and 22d are directly connected to each other.

[0029] The semiconductor chip 20 includes a substrate 23 including a first main surface 23a having an off angle of 4° or less, and an epitaxial layer 24 formed on the first main surface 23a. The epitaxial layer 24 is formed by epitaxial crystal growth on the first main surface 23a of the substrate 23. In this embodiment, the off angle indicated by the angle θ in FIG. 3 is 4°. It is preferable that the off angle of the first main surface 23a is greater than 0° and equal to or less than 4°. The thickness of the epitaxial layer 24 is indicated by a thickness T1. The thickness of the substrate 23 is indicated by a thickness T2. The thickness of the semiconductor chip 20 excluding the first electrode 11 and the second electrode 12 is indicated by a thickness T3. Here, the thickness T2 of the epitaxial layer 24 is determined according to the magnitude of the withstand voltage required for the semiconductor chip 20. Specifically, when the withstand voltage required for the semiconductor chip 20 is 1200V, the thickness T2 is set to 10 μm or more. Furthermore, when the withstand voltage required for the semiconductor chip 20 is 3300V, the thickness T2 is set to 30 μm or more. In this embodiment, the thickness T1 is set to 4 μm or more and 30 μm or less. The thickness T1 may be set to 5 μm or more and 30 μm or less.

[0030] The semiconductor chip 20 includes an operating layer region 25 and a chip peripheral region 26. The operating layer region 25 includes an active region 27 arranged in a central region of the semiconductor chip 20, a termination region arranged on the peripheral side of the active region 27 and including guard ring regions 28a, 28b, and 28c, and a field stop region 29 arranged on the peripheral side of the active region 27 and on the peripheral side of the termination region.

[0031] Guard ring region 28a is disposed close to active region 27 and is provided to surround active region 27. Guard ring region 28b is provided to surround guard ring region 28a. Guard ring region 28c is disposed close to field stop region 29 and is provided to surround guard ring region 28b. Guard ring regions 28a, 28b, and 28c are disposed at intervals toward outer edge 21 of semiconductor chip 20. Guard ring regions 28a, 28b, and 28c are, for example, p-type semiconductor regions.

[0032] The field stop region 29 is provided to surround the guard ring region 28c. The field stop region 29 is a region of an n-type semiconductor. An outer edge 31 of the field stop region 29 constitutes the outer edge 31 of the active layer region 25. The field stop region 29 is, for example, a region of an n-type semiconductor.

[0033] When viewed in the thickness direction of the semiconductor chip 20, the outer edge 31 of the field stop region 29 includes four sides 32a, 32b, 32c, and 32d. The sides 32a, 32b, 32c, and 32d are each composed of a line segment. The sides 32a and 32b are arranged in parallel with a gap in the X direction and form an opposing pair. The sides 32c and 32d are arranged in parallel with a gap in the Y direction and form an opposing pair. Each of the sides 22a, 22b, 22c, and 22d is connected via a circular arc portion.

[0034] The above-mentioned semiconductor chip 20 is manufactured by using a disk-shaped substrate, forming a device section by using a part of an epitaxial layer grown on the substrate as an active region, and then dicing the substrate into individual pieces. Fig. 4 is a view of the disk-shaped substrate in the thickness direction showing the state in which the operating layer region is formed in the first embodiment. In Fig. 4, a part including the operating layer region 25 in the region surrounded by a dashed line is enlarged and illustrated.

[0035] Referring to FIG. 4, the disk-shaped substrate 23 is provided with a notch 34 in part to clarify its directionality. The substrate 23 on which the epitaxial layer is formed includes a plurality of operating layer regions 25 spaced apart from each other when viewed in the thickness direction of the substrate 23, a chip peripheral region 26 arranged on the outer periphery of each operating layer region 25, and a dicing region 35 arranged on the outer periphery of each chip peripheral region 26. The operating layer regions 25 are formed to be spaced apart from each other in the X direction and the Y direction. From the viewpoint of facilitating the individualization of each semiconductor chip 20, for example, the dicing region 35 is arranged in a lattice pattern. That is, in the substrate 23, operating layer regions 25 having the same structure are formed periodically in the X direction and the Y direction.

[0036] During epitaxial crystal growth, crystal defects may occur. Referring to FIG. 3, the direction in which the crystal defect 37 grows from the first main surface 23a of the substrate 23 as a starting point 36 is longer in the direction of the crystal plane orientation <11-20>. The crystal defect 37 extends longer in the direction of the crystal plane orientation <11-20> than in the direction perpendicular to the direction of the crystal plane orientation <11-20> for the crystal defect 37 starting from the first main surface 23a of the substrate 23. That is, the crystal defect 37 grows with the epitaxial crystal growth and reaches the surface 24a of the epitaxial layer 24. That is, the end 38 of the crystal defect 37 appears on the surface 24a of the epitaxial layer 24. When viewed in the thickness direction of the semiconductor chip 20, the length of the crystal defect 37 in the X direction is indicated by a length D1. The length D1 is due to the thickness T1 of the epitaxial layer 24. In this embodiment, since the off-angle θ is 4°, the thickness T1 divided by the tangent (tan) of the off-angle 4° of the substrate is the length D1 of the crystal defect 37. When the thickness T1 is 10 μm, the length D1 of the crystal defect 37 is 143 μm. When the thickness T1 is 30 μm, the length D1 of the crystal defect 37 is 429 μm. When viewed in the thickness direction of the semiconductor chip 20, the crystal defect 37 often has an isosceles triangle shape with the starting point 36 as the apex. In this case, for example, if the length D1 in the X direction is 0.15 μm, the length in the Y direction perpendicular to the X direction is 0.05 μm.

[0037] Here, the length of the semiconductor chip 20 in the X direction, which is the direction of the crystal plane orientation <11-20>, is defined as length A1. Length A1 is the length between side 22a and side 22b. The maximum length of the operating layer region 25 in the X direction, which is the direction of the crystal plane orientation <11-20>, is defined as length A2. Length A2 is the length between side 32a and side 32b. The length of the semiconductor chip 20 in the Y direction, which is the direction perpendicular to the direction of the crystal plane orientation <11-20>, is defined as length B1. Length B1 is the length between side 22c and side 22d. The maximum length of the operating layer region 25 in the Y direction, which is the direction perpendicular to the direction of the crystal plane orientation <11-20>, is defined as length B2. Length B2 is the length between side 32c and side 32d. The difference value obtained by subtracting length A2 from length A1 is the sum of length m1 between sides 22a and 32a and length m2 between sides 22b and 32b (length m1+length m2). The difference value obtained by subtracting length B2 from length B1 is the sum of length n1 between sides 22c and 32c and length n2 between sides 22d and 32d (length n1+length n2).

[0038] In the semiconductor chip 20 of the present disclosure, the value of the difference (length A1-length A2) obtained by subtracting the length A2 from the length A1 is different from the value of the difference (length B1-length B2) obtained by subtracting the length B2 from the length B1. In this embodiment, the value of the difference obtained by subtracting the length A2 from the length A1 is greater than the value of the difference obtained by subtracting the length B2 from the length B1. In the semiconductor chip 20 of the present disclosure, the length B2 in the Y direction of the operating layer region 25 is longer than the length A2 in the X direction. In this embodiment, the value of the difference obtained by subtracting the length A2 from the length A1 is 0.5 mm or more. The value of the difference obtained by subtracting the length B2 from the length B1 is 0.1 mm or more. Specifically, the value of the difference obtained by subtracting the length A2 from the length A1 is 0.5 mm. Moreover, the value of the difference obtained by subtracting the length B2 from the length B1 is 0.1 mm.

[0039] The direction in which the crystal defect 37 grows is longer in the direction of the crystal plane orientation <11-20>, which is the step flow growth direction. That is, it is longer in the X direction. Then, for the crystal defect 37 starting from the first main surface 23a of the substrate 23 as the starting point 36, the crystal defect extends longer in the direction of the crystal plane orientation <11-20> than in the direction perpendicular to the direction of the crystal plane orientation <11-20>. Therefore, by configuring in this way, when the crystal defect 37 exists between the respective operating layer regions 25 of the semiconductor chip 20 arranged at intervals in the direction of the crystal plane orientation <11-20>, the probability that the crystal defect 37 is included in the operating layer region 25 can be reduced, compared to the case where the difference value obtained by subtracting the length A2 from the length A1 is the same as the difference value obtained by subtracting the length B2 from the length B1. That is, the crystal defect 37 generated during the epitaxial crystal growth can be arranged more in the chip outer peripheral region 26 and the dicing region 35, which do not affect the operation of the semiconductor chip 20. This makes it possible to reduce the number of semiconductor chips 20 that become defective due to breakdown voltage defects among the multiple semiconductor chips 20 obtained from one substrate 23. As a result, it is possible to reduce manufacturing costs.

[0040] In this embodiment, the difference value obtained by subtracting the length A2 from the length A1 is greater than the difference value obtained by subtracting the length B2 from the length B1. Therefore, many crystal defects 37 can be arranged between the respective operating layer regions 25 of the semiconductor chips 20 arranged at intervals in the crystal plane orientation <11-20>, and the probability that the crystal defects 37 are included in the operating layer region 25 can be reduced. Therefore, the probability that a semiconductor chip with a breakdown voltage defect is manufactured can be reduced, the yield of the semiconductor chips can be improved, and the manufacturing cost can be further reduced.

[0041] In this embodiment, the difference between length A1 and length A2 is 0.5 mm or more. Also, the difference between length B1 and length B2 is 0.1 mm or more. By specifying each length in this manner, it is possible to more reliably reduce the manufacturing cost.

[0042] Furthermore, in a cross section of the semiconductor chip 20 cut in the thickness direction, the difference obtained by subtracting the length A2 from the length A1 is configured to be larger than the value obtained by dividing the thickness T1 by the tangent of the off-angle of the substrate 23. Therefore, the difference obtained by subtracting the length A2 from the length A1 can be appropriately set according to the thickness T1 of the epitaxial layer 24, thereby further reducing the probability that the crystal defects 37 will be included in the operating layer region 25. Therefore, the manufacturing cost can be more appropriately reduced.

[0043] In this embodiment, the off angle is 4 degrees. Therefore, such a semiconductor chip 20 has good productivity, and therefore the manufacturing cost can be further reduced.

[0044] In this embodiment, the thickness T1 is 4 μm or more and 30 μm or less. Therefore, the withstand voltage required for the semiconductor chip 20 can be sufficiently ensured, and when the semiconductor chip 20 according to the present disclosure is used, the area of ​​the operating layer region 25 in the chip area is prevented from becoming excessively small, and the semiconductor chip 20 having low resistance during conduction can be provided.

[0045] In the above embodiment, the difference between length A1 and length A2 may be 0.2 mm or more. The difference between length B1 and length B2 may be 0.1 mm or more. By specifying each length in this way, it is possible to reliably reduce manufacturing costs.

[0046] (Embodiment 2) Next, another embodiment, embodiment 2, will be described. Fig. 5 is a schematic plan view of a semiconductor chip in embodiment 2. Fig. 6 is a view of a disk-shaped substrate in the thickness direction, showing a state in which an operating layer region is formed in embodiment 2. The semiconductor chip in embodiment 2 differs from embodiment 1 in that the difference value obtained by subtracting length A2 from length A1 is smaller than the difference value obtained by subtracting length B2 from length B1.

[0047] 5 and 6, in the semiconductor chip of the second embodiment, the difference value obtained by subtracting the length A2 from the length A1 is smaller than the difference value obtained by subtracting the length B2 from the length B1. In this way, many crystal defects 37 can be arranged between the operating layer regions 25 of the semiconductor chips 20 arranged at intervals in a direction perpendicular to the crystal plane orientation <11-20>, and the probability of manufacturing a semiconductor chip 20 in which the operating layer regions 25 contain crystal defects 37 and have a breakdown voltage failure can be reduced. Therefore, the yield of the semiconductor chips 20 can be improved, and the manufacturing cost can be further reduced.

[0048] In this embodiment, the difference obtained by subtracting length A2 from length A1 is 0.1 mm or more. The difference obtained by subtracting length B2 from length B1 is 0.5 mm or more. Specifically, the difference obtained by subtracting length A2 from length A1 is 0.1 mm. The difference obtained by subtracting length B2 from length B1 is 0.5 mm. By specifying each length in this manner, it is possible to more reliably reduce manufacturing costs.

[0049] In the above embodiment, the difference obtained by subtracting the length A2 from the length A1 may be 0.1 mm or more. The difference obtained by subtracting the length B2 from the length B1 may be 0.2 mm or more. By specifying each length in this manner, it is possible to reliably reduce the manufacturing cost. In the above embodiment, the difference obtained by subtracting the length A2 from the length A1 may be 0.2 mm or more. The difference obtained by subtracting the length B2 from the length B1 may be 0.3 mm or more. By specifying each length in this manner, it is possible to reliably reduce the manufacturing cost.

[0050] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Industrial Applicability]

[0051] The semiconductor chip of the present disclosure can be particularly advantageously applied in cases where reduction in manufacturing costs is required. [Explanation of symbols]

[0052] 11 First electrode 12 Second electrode 20. Semiconductor Chips 21,31 Outer edge 22a, 22b, 22c, 22d, 32a, 32b, 32c, 32d 23 Substrate 23a First main surface 24 Epitaxial layer 24a surface 25 Operating layer area 26 Chip Outer Area 27 Active area 28a, 28b, 28c Guard ring area 29 Field Stop Region 34 Cutout 35 Dicing Area 36 Starting point 37 Crystal Defects 38 Termination A1, A2, B1, B2, D1, m1, m2, n1, n2 length T1, T2, T3 thickness θ angle

Claims

1. A semiconductor chip including a substrate made of SiC and including a first main surface having an off-angle of 4° or less, and an epitaxial layer formed on the first main surface, the semiconductor chip being rectangular when viewed in a thickness direction, When viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region disposed in a central region of the semiconductor chip and a field stop region disposed on an outer periphery of the active region; a chip periphery region surrounding the operating layer region and disposed along an outer edge of the semiconductor chip; The outer edge of the field stop region is disposed along the outer edge of the semiconductor chip and includes four sides constituting the outer edge of the operating layer region, The length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is defined as length A. １ year, The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length A ２ year, The length of the semiconductor chip in a direction perpendicular to the crystal plane orientation <11-20> is defined as length B １ year, The maximum length of the operating layer region in the direction perpendicular to the crystal plane orientation <11-20> is defined as length B ２ Then, The length A １ from the length A ２ The difference between the length B and the length １ from the length B ２ Unlike the difference value obtained by subtracting In a cross section of the semiconductor chip cut in a thickness direction, a difference value obtained by subtracting the length A2 from the length A1, where the thickness of the epitaxial layer is T1, is greater than a value obtained by dividing the thickness T1 by the tangent of the off-angle of the substrate.

2. The semiconductor chip according to claim 1 , wherein the off-angle is 4°.

3. The thickness T １ The semiconductor chip according to claim 1 or 2, wherein the thickness of the first insulating layer is 4 μm or more and 30 μm or less.

4. The length A １ from the length A ２ The difference obtained by subtracting １ from the length B ２ The semiconductor chip according to claim 1 , wherein the difference between the first and second resistances is greater than a difference obtained by subtracting

5. A semiconductor chip comprising: a substrate made of SiC and including a first main surface having an off-angle of 4° or less; and an epitaxial layer formed on the first main surface, the semiconductor chip being rectangular in thickness direction, When viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region disposed in a central region of the semiconductor chip and a field stop region disposed on an outer periphery of the active region; a chip periphery region surrounding the operating layer region and disposed along an outer edge of the semiconductor chip; The outer edge of the field stop region is disposed along the outer edge of the semiconductor chip and includes four sides constituting the outer edge of the operating layer region, The length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is defined as length A 1 , The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length A 2 , The length of the semiconductor chip in a direction perpendicular to the crystal plane orientation <11-20> is defined as length B 1 , If the maximum length of the operating layer region in a direction perpendicular to the crystal plane orientation <11-20> is length B 2 , then: a difference value obtained by subtracting the length A 2 from the length A 1 is different from a difference value obtained by subtracting the length B 2 from the length B 1 , a difference value obtained by subtracting the length A 2 from the length A 1 is greater than a difference value obtained by subtracting the length B 2 from the length B 1 ; a difference value obtained by subtracting the length A2 from the length A1 is 0.2 mm or more; A semiconductor chip, wherein a difference obtained by subtracting the length B 2 from the length B 1 is 0.1 mm or more.

6. A semiconductor chip comprising: a substrate made of SiC and including a first main surface having an off-angle of 4° or less; and an epitaxial layer formed on the first main surface, the semiconductor chip being rectangular in thickness direction, When viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region disposed in a central region of the semiconductor chip and a field stop region disposed on an outer periphery of the active region; a chip periphery region surrounding the operating layer region and disposed along an outer edge of the semiconductor chip; The outer edge of the field stop region is disposed along the outer edge of the semiconductor chip and includes four sides constituting the outer edge of the operating layer region, The length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is defined as length A 1 , The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length A 2 , The length of the semiconductor chip in a direction perpendicular to the crystal plane orientation <11-20> is defined as length B 1 , If the maximum length of the operating layer region in a direction perpendicular to the crystal plane orientation <11-20> is length B 2 , then: a difference value obtained by subtracting the length A 2 from the length A 1 is different from a difference value obtained by subtracting the length B 2 from the length B 1 , a difference value obtained by subtracting the length A 2 from the length A 1 is greater than a difference value obtained by subtracting the length B 2 from the length B 1 ; The length A １ from the length A ２ The difference obtained by subtracting is 0.5 mm or more, The length B １ From the length B ２ A semiconductor chip, wherein the difference obtained by subtracting

7. The length A １ from the length A ２ The difference obtained by subtracting １ From the length B ２ The semiconductor chip according to claim 1 , wherein the difference between the first and second resistances is smaller than the difference between the first and second resistances.

8. A semiconductor chip comprising: a substrate made of SiC and including a first main surface having an off-angle of 4° or less; and an epitaxial layer formed on the first main surface, the semiconductor chip being rectangular in thickness direction, When viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region disposed in a central region of the semiconductor chip and a field stop region disposed on an outer periphery of the active region; a chip periphery region surrounding the operating layer region and disposed along an outer edge of the semiconductor chip; The outer edge of the field stop region is disposed along the outer edge of the semiconductor chip and includes four sides constituting the outer edge of the operating layer region, The length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is defined as length A 1 , The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length A 2 , The length of the semiconductor chip in a direction perpendicular to the crystal plane orientation <11-20> is defined as length B 1 , If the maximum length of the operating layer region in a direction perpendicular to the crystal plane orientation <11-20> is length B 2 , then: a difference value obtained by subtracting the length A 2 from the length A 1 is different from a difference value obtained by subtracting the length B 2 from the length B 1 , a difference value obtained by subtracting the length A 2 from the length A 1 is smaller than a difference value obtained by subtracting the length B 2 from the length B 1 ; a difference value obtained by subtracting the length A2 from the length A1 is 0.1 mm or more; A semiconductor chip, wherein a difference obtained by subtracting the length B 2 from the length B 1 is 0.2 mm or more.

9. A semiconductor chip comprising: a substrate made of SiC and including a first main surface having an off-angle of 4° or less; and an epitaxial layer formed on the first main surface, the semiconductor chip being rectangular in thickness direction, When viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region disposed in a central region of the semiconductor chip and a field stop region disposed on an outer periphery of the active region; a chip periphery region surrounding the operating layer region and disposed along an outer edge of the semiconductor chip; The outer edge of the field stop region is disposed along the outer edge of the semiconductor chip and includes four sides constituting the outer edge of the operating layer region, The length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is defined as length A 1 , The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length A 2 , The length of the semiconductor chip in a direction perpendicular to the crystal plane orientation <11-20> is defined as length B 1 , If the maximum length of the operating layer region in a direction perpendicular to the crystal plane orientation <11-20> is length B 2 , then: a difference value obtained by subtracting the length A 2 from the length A 1 is different from a difference value obtained by subtracting the length B 2 from the length B 1 , a difference value obtained by subtracting the length A 2 from the length A 1 is smaller than a difference value obtained by subtracting the length B 2 from the length B 1 ; The length A １ from the length A ２ The difference obtained by subtracting is 0.2 mm or more, The length B １ From the length B ２ A semiconductor chip, wherein the difference obtained by subtracting

10. A semiconductor chip comprising: a substrate made of SiC and including a first main surface having an off-angle of 4° or less; and an epitaxial layer formed on the first main surface, the semiconductor chip being rectangular in thickness direction, When viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region disposed in a central region of the semiconductor chip and a field stop region disposed on an outer periphery of the active region; a chip periphery region surrounding the operating layer region and disposed along an outer edge of the semiconductor chip; The outer edge of the field stop region is disposed along the outer edge of the semiconductor chip and includes four sides constituting the outer edge of the operating layer region, The length of the semiconductor chip in the direction of the crystal plane orientation <11-20> is defined as length A 1 , The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length A 2 , The length of the semiconductor chip in a direction perpendicular to the crystal plane orientation <11-20> is defined as length B 1 , If the maximum length of the operating layer region in a direction perpendicular to the crystal plane orientation <11-20> is length B 2 , then: a difference value obtained by subtracting the length A 2 from the length A 1 is different from a difference value obtained by subtracting the length B 2 from the length B 1 , a difference value obtained by subtracting the length A 2 from the length A 1 is smaller than a difference value obtained by subtracting the length B 2 from the length B 1 ; The length A １ from the length A ２ The difference obtained by subtracting is 0.1 mm or more, The length B １ from the length B ２ A semiconductor chip, wherein the difference obtained by subtracting

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