Method for manufacturing heterojunction bipolar transistor

Abstract

This heterojunction bipolar transistor is provided with a heat dissipation structure (114) which is formed of a metal and penetrates a protective layer (110), while having one end thereof in contact with a heat dissipation substrate (101) that is arranged around an element part. This heterojunction bipolar transistor is also provided with: a collector wiring line (115) which is formed on the protective layer (110) so as to be in contact with the heat dissipation structure (114) and a collector electrode (108); a base contact electrode (116) which penetrates the protective layer (110), while being connected to a base electrode (109); and a base wiring line (117) which is formed on the protective layer (110), while being connected to the base contact electrode (116).

Description

[Technical field]

[0001] The present invention relates to a heterojunction bipolar transistor. Ta's It relates to a manufacturing method. [Background technology]

[0002] Indium phosphide (InP)-based heterojunction bipolar transistors (HBTs) are transistors with excellent high speed and high output, suitable for integrated circuits for optical / wireless communication. To further increase the speed of InP-based HBTs, it is necessary to reduce capacitance and electron transit time by miniaturizing the elements while maintaining the operating current. In addition, to increase output, it is required to increase the number of emitters in a so-called multi-finger structure, in which multiple emitters are integrated to share the base or collector, and to reduce the emitter spacing.

[0003] On the other hand, miniaturization increases the thermal resistance of the element, so the junction temperature (temperature inside the element) of the element increases with miniaturization. In addition, in a multi-finger structure, heat generated by the emitter region located on the periphery hinders the heat dissipation of the emitter region located in the center compared to a single-finger HBT, so the junction temperature increases further.

[0004] The junction temperature is a factor that has a significant impact not only on direct electrical characteristics such as current gain and high-frequency characteristics, but also on long-term reliability, so heat dissipation measures are essential for increasing the speed of HBTs.

[0005] In order to improve the heat dissipation of the HBT, for example, a technique has been proposed in which the HBT structure is formed on a support substrate having high thermal conductivity (Non-Patent Document 1).

[0006] 3, the HBT structure in Non-Patent Document 1 has a collector electrode 302 made of metal formed on a heat dissipation substrate 301, and a collector contact layer 303, a collector layer 304, a base layer 305, and an emitter layer 306, all made of compound semiconductor crystals, formed on collector electrode layer 302. In addition, a base electrode 307 is formed on base layer 305, and an emitter electrode 308 is formed on emitter layer 306.

[0007] This HBT structure is obtained by epitaxially growing each layer constituting the HBT on an InP growth substrate, bonding it to a heat dissipation substrate 301 via a collector electrode layer 302, removing the InP growth substrate that is no longer needed, and processing each layer to form the HBT structure.

[0008] Generally, heat generated inside an HBT is dissipated toward the substrate side by thermal conduction in a solid. According to the above structure, the layers below collector contact layer 303 are made of a material with a higher thermal conductivity than the compound semiconductors that make up emitter layer 306, base layer 305, collector layer 304, and collector contact layer 303, so that the heat dissipation of the HBT can be improved.

[0009] On the other hand, unlike when an HBT structure is formed on a typical InP substrate, a process of bonding to a heat dissipation substrate is required, and as described below, there is a concern that various problems may occur in various manufacturing methods.

[0010] First, as shown in Non-Patent Document 1, in order to realize the above-mentioned HBT structure on a heat dissipation substrate in a single substrate bonding process, unlike the case of fabricating an HBT structure on a normal InP substrate, it is necessary to epitaxially grow the HBT crystal layers in the reverse order (emitter layer, base layer, collector layer from the side in contact with the InP substrate).

[0011] Normally, in epitaxial growth, an optimal temperature profile is set to maximize the crystal quality of various materials and to prevent deterioration of the crystal quality of the underlying semiconductor and unintended thermal diffusion of the constituent elements. However, when the HBT crystal layer is epitaxially grown from the emitter layer side, the semiconductor materials of the lower and upper layers are swapped, which can make it difficult to set an optimal temperature profile.

[0012] Furthermore, the outermost layer of the emitter layer (the layer in direct contact with the emitter electrode) often uses InGaAs with a high In composition to reduce the emitter contact resistance. Since InGaAs with a high In composition does not lattice match InP, it is generally difficult to form high-quality crystals with it. However, because it is the outermost layer, there is no need to consider the crystal quality of the semiconductor material above it, and in addition, by controlling the thickness below the critical film thickness and suppressing lattice relaxation, it is possible to achieve a crystal quality that provides sufficient electrical characteristics.

[0013] However, when growing from the emitter layer side, the emitter layer, base layer, and collector layer are formed on InGaAs with a high In composition, which is lattice mismatched, and this raises concerns that the crystal quality of the HBT crystal layer may deteriorate, or that it may become difficult to introduce InGaAs with a high In composition into the emitter layer in the first place.

[0014] For these reasons, when the structure of Non-Patent Document 1 is realized in a single substrate bonding process, there is a concern that the crystal quality of the HBT crystal layer may be degraded or restrictions may be placed on the composition.

[0015] The simplest method to solve the above problem is to perform the substrate bonding process twice. First, after epitaxial growth of the HBT crystal growth layer, it is bonded to the support substrate using some kind of temporary adhesive layer, and the InP substrate is removed. At this time, the order of the HBT crystal layer is reversed and formed on the support substrate. Next, the HBT crystal layer on the support substrate and the heat dissipation substrate are bonded via a metal layer in the same manner as in Non-Patent Document 1, and the unnecessary temporary adhesive layer and support substrate are removed. At this stage, the HBT crystal layer is transferred twice, so that the HBT crystal layer is formed on the heat dissipation substrate in the order in which it was grown on the InP substrate. Finally, the HBT structure is fabricated by a known method to obtain the structure of Non-Patent Document 1.

[0016] In this case, the HBT crystal layers can be grown on the InP growth substrate in the usual order (from the collector layer to the emitter layer), so there is no degradation of crystal quality during the epitaxial growth process. However, the substrate bonding process is simply doubled, which not only complicates the process but also raises concerns that the quality of the HBT crystal layers may deteriorate in some cases.

[0017] Generally, if any particles or localized unevenness occurs on the bonded surfaces, it is possible that an unbonded area 100 to 1000 times larger in size than the bonded surfaces will occur, depending on the physical properties of the bonded materials. Therefore, the more times the bonding process is performed, the greater the risk of unintended unbonded areas occurring, which can potentially cause a decrease in yield.

[0018] In the second bonding step, bonding pressure is applied to the HBT crystal layer, which is thin (up to 1 μm thick) and extremely mechanically fragile, to bond it to the heat dissipation substrate. The HBT crystal layer is held onto the support substrate by a temporary adhesive layer, but there is a concern that the bonding pressure may cause minute deformations in the temporary adhesive layer, which could result in a deterioration in crystal quality or, in the worst case, cracks. Therefore, an ideal temporary adhesive layer would be one that is easy to peel off and difficult to deform (high Young's modulus), but a high Young's modulus is a trade-off with ease of bonding, and it is not easy to select a temporary adhesive layer that satisfies all of the requirements in a balanced manner.

[0019] In order to avoid the above problems, a technique has been proposed for forming an HBT structure with the collector up by one substrate bonding without changing the epitaxial growth sequence (Non-Patent Document 2).

[0020] For example, as shown in FIG. 4, a bonding layer 402 made of benzocyclobutene (BCB) is formed on a heat dissipation substrate 401, and an HBT element portion is formed thereon in the following order: a first emitter electrode 403, a second emitter electrode 404, an emitter layer 405, a base layer 406, a collector layer 407, a sub-collector layer 408, and a collector electrode 409.

[0021] Furthermore, on the extension of the short side of the emitter layer 405, a thermal via 410 made of Au is formed in contact with the heat dissipation substrate 401 and is connected to the first emitter electrode 403. Furthermore, the element portion and the thermal via 410 are covered with a protective layer 411 made of BCB.

[0022] In this structure, the HBT element portion including the first emitter electrode 403, the second emitter electrode 404, the emitter layer 405, the base layer 406, the collector layer 407, and the sub-collector layer 408 is fabricated on an InP substrate, and then bonded to a heat dissipation substrate via a bonding layer 402.

[0023] After this bonding, the InP growth substrate, which is no longer necessary, is removed, and a collector electrode 409 is formed on the sub-collector layer 408. Finally, an opening is formed in the bonding layer 402 on the periphery of the element portion, and a thermal via 410 is formed so as to contact the heat dissipation substrate 401 and the first emitter electrode 403, and then the entire element portion is covered with a protective layer 411, thereby obtaining the device.

[0024] By constructing the adhesive layer (bonding layer) from BCB, which has a low Young's modulus, it is possible to bond to the heat dissipation substrate under relatively low bonding pressure conditions compared to when a metal is used as the bonded material, which makes it possible to avoid damage to the HBT element part, which has weak mechanical strength. Also, in this structure, heat generated in the element part is dissipated from the emitter electrode to the heat dissipation substrate through the Au thermal vias, resulting in higher heat dissipation compared to an HBT structure on an InP substrate. [Prior art documents] [Non-patent literature]

[0025] [Non-Patent Document 1] Y. Shiratori et al., "High-Speed ​​InP / InGaAsSb DHBT on High-Thermal-Conductivity SiC Substrate", IEEE Electron Device Letters, vol. 39, no. 6, pp. 807-810, 2018. [Non-Patent Document 2] T. Kraemer et al., "InP DHBT Process in Transferred-Substrate Technology With ft and fmax Over 400 GHz", IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1897-1903, 2009. Summary of the Invention [Problem to be solved by the invention]

[0026] However, in the structure of Non-Patent Document 2, because the BCB with extremely low thermal conductivity exists directly below the element part, the path for heat conduction from the emitter layer to the heat dissipation substrate becomes longer by the length of the emitter electrode and the thickness of the Au thermal via. Therefore, compared to Non-Patent Document 1, where the entire area directly below the element part is made of a material with high thermal conductivity, the effect of improving heat dissipation is limited.

[0027] In addition, because Au thermal vias of a certain size are required between HBT element sections for heat dissipation, when forming a multi-finger structure in which multiple emitters are densely arranged in parallel, restrictions are imposed on the emitter spacing, which can be a major problem, especially when increasing the output of HBTs.

[0028] As described above, with existing technology, it is not easy to improve the heat dissipation performance of InP-based HBTs while suppressing degradation in crystal quality and integration density.

[0029] The present invention has been made to solve the above problems, and has an object to improve heat dissipation by suppressing deterioration in crystal quality and integration density of InP-based HBTs. [Means for solving the problem]

[0030] FThe heterojunction bipolar transistor includes a heat dissipation substrate made of an insulating material having a higher thermal conductivity than InP, a first emitter electrode formed on the heat dissipation substrate, a second emitter electrode formed on the first emitter electrode with an area smaller than that of the first emitter electrode, an emitter layer made of a compound semiconductor and formed on the second emitter electrode, a base layer made of a compound semiconductor and formed on the emitter layer, a collector layer made of a compound semiconductor and formed on the base layer, a collector contact layer made of a compound semiconductor and formed on the collector layer, a collector electrode formed on the collector contact layer, a base electrode formed connected to the base layer, the second emitter electrode, an emitter layer made of a compound semiconductor and formed on the second emitter electrode, a base layer formed on the base layer, a collector contact layer made of a compound semiconductor and formed on the collector layer, a collector electrode formed on the collector contact layer, a base electrode formed connected to the base layer, and a collector electrode formed on the collector contact layer. the heat dissipation structure is made of metal and one end is in contact with the heat dissipation substrate around the element portion and formed to penetrate the protective layer; a collector wiring formed on the protective layer and in contact with the heat dissipation structure and the collector electrode; a base contact electrode connected to the base electrode and formed to penetrate the protective layer; and a base wiring formed on the protective layer and in contact with the heat dissipation structure and the collector electrode.

[0031] A method for producing a heterojunction bipolar transistor according to the present invention is a method for producing the above-mentioned heterojunction bipolar transistor, comprising a first step of crystal-growing an etch stop layer, a collector contact-forming layer, a collector-forming layer, a base-forming layer, and an emitter-forming layer, each of which is made of a compound semiconductor, in that order on a growth substrate made of InP; forming a second emitter electrode on the emitter-forming layer; processing the emitter-forming layer, the base-forming layer, and the collector-forming layer to form an emitter layer, a base layer, and a collector layer; a second step of forming an element section by forming a base electrode on the growth substrate; a third step of forming a first structure made of metal on the growth substrate around the element section; a fourth step of forming a first protective layer that fills the area around the element section and has a flattened surface with one end side of the first structure and the second emitter electrode exposed; a fifth step of forming a first adhesive metal layer on the flattened first protective layer; a sixth step of preparing a heat dissipation substrate made of an insulating material having a higher thermal conductivity than InP and having a second adhesive metal layer formed on its surface; A seventh step of forming an adhesive metal layer by integrating the first adhesive metal layer and the second adhesive metal layer to bond the growth substrate and the heat dissipation substrate together; an eighth step of removing the growth substrate and the etch stop layer to form a state in which the element portion is formed on the heat dissipation substrate with the second emitter electrode disposed on the heat dissipation substrate side, and exposing the collector contact formation layer; a ninth step of forming a collector electrode on the collector contact formation layer; and a ninth step of processing the collector contact formation layer to form a collector contact layer, and in addition, removing a part of the collector layer and a part of the base layer to form a collector contact layer that reaches a part of the base electrode. a tenth step of forming a contact hole; an eleventh step of forming, on the first structure, a first emitter contact electrode constituting a part of the emitter contact electrode, a first heat dissipation structure made of metal and constituting a part of the heat dissipation structure, and forming a base contact electrode; an eleventh step of processing the first structure to form a second emitter contact electrode connected to the first emitter contact electrode to form an emitter contact electrode, a second heat dissipation structure constituting a part of the heat dissipation structure and connected to the first heat dissipation structure, and processing an adhesive metal layer to form a first emitter electrode;The method includes a 12th step of forming a heat dissipation structure consisting of the first heat dissipation structure, the second heat dissipation structure, and the third heat dissipation structure by forming a third heat dissipation structure connected to the second heat dissipation structure, a 13th step of forming a protection layer consisting of the first protection layer and the second protection layer by forming a second protection layer on the first protection layer, and a 14th step of forming an emitter wiring, a base wiring, and a collector wiring. Effect of the Invention

[0032] As described above, according to the present invention, a protective layer that covers an element portion and the like is formed on a heat dissipation substrate, and a heat dissipation structure made of metal is provided, one end of which is in contact with the surface of the heat dissipation substrate surrounding the element portion and penetrates the protective layer. This makes it possible to suppress deterioration in the crystal quality and integration density of the InP-based HBT and improve heat dissipation performance. [Brief description of the drawings]

[0033] [Figure 1A] FIG. 1A is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2A] FIG. 2A is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2B] FIG. 2B is a cross-sectional view showing a state of the heterojunction bipolar transistor in the middle of a process for explaining the method for manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention. [Figure 2C] FIG. 2C is a cross-sectional view showing a state of the heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of the heterojunction bipolar transistor according to the embodiment of the present invention. [Figure 2D] FIG. 2D is a cross-sectional view showing a state of the heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of the heterojunction bipolar transistor according to the embodiment of the present invention. [Figure 2E] FIG. 2E is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for illustrating a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2F] FIG. 2F is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2G] FIG. 2G is a cross-sectional view showing a state of the heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of the heterojunction bipolar transistor according to the embodiment of the present invention. [Figure 2H] FIG. 2H is a cross-sectional view showing a state of the heterojunction bipolar transistor in the middle of a process for illustrating the method for manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention. [Figure 2I] FIG. 2I is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for illustrating a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2J] FIG. 2J is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2K] FIG. 2K is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2L] FIG. 2L is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2M] FIG. 2M is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2N]FIG. 2N is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2O] FIG. 2O is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2P] FIG. 2P is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for illustrating a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2Q] FIG. 2Q is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2R] FIG. 2R is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2S] FIG. 2S is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. [Figure 2T] FIG. 2T is a cross-sectional view showing a state of a heterojunction bipolar transistor in the middle of a process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention. [Diagram 3] FIG. 3 is a cross-sectional view showing the configuration of the HBT structure disclosed in Non-Patent Document 1. As shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the configuration of the HBT structure disclosed in Non-Patent Document 2. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, a heterojunction bipolar transistor according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B.

[0035] This heterojunction bipolar transistor first comprises a heat dissipation substrate 101 made of an insulating material having a higher thermal conductivity than InP, a first emitter electrode 102 formed on the heat dissipation substrate 101, and a second emitter electrode 103 formed on the first emitter electrode 102 with an area smaller than that of the first emitter electrode 102.

[0036] This heterojunction bipolar transistor also includes an emitter layer 104 formed on the second emitter electrode 103, a base layer 105 formed on the emitter layer 104, a collector layer 106 formed on the base layer 105, and a collector contact layer 107 formed on the collector layer 106. Each of these layers (crystal layers) is made of a compound semiconductor (e.g., a III-V compound semiconductor).

[0037] This heterojunction bipolar transistor also includes a collector electrode 108 formed on collector contact layer 107, and a base electrode 109 formed in connection with base layer 105. This heterojunction bipolar transistor also includes a protective layer 110 formed on heat dissipation substrate 101 to cover the side portions of the element portion, first emitter electrode 102, and base electrode 109. The element portion is a portion consisting of second emitter electrode 103, emitter layer 104, base layer 105, collector layer 106, and collector contact layer 107.

[0038] This heterojunction bipolar transistor also includes an emitter contact electrode 112 formed on and in contact with the first emitter electrode 102 around the above-mentioned element portion and penetrating the protective layer 110, and an emitter wiring 113 connected to the emitter contact electrode 112 and formed on the protective layer 110.

[0039] This heterojunction bipolar transistor also includes a heat dissipation structure 114 made of metal, one end of which is in contact with the heat dissipation substrate 101 around the element portion and which is formed penetrating the protective layer 110. The heat dissipation structure 114 is formed in a columnar shape.

[0040] This heterojunction bipolar transistor also includes a collector wiring 115 formed on protective layer 110 in contact with heat dissipation structure 114 and collector electrode 108, a base contact electrode 116 connected to base electrode 109 and penetrating protective layer 110, and a base wiring 117 connected to base contact electrode 116 and formed on protective layer 110.

[0041] This heterojunction bipolar transistor also includes an insulating layer 118 that is made of an insulating material having a higher thermal conductivity than the collector layer 106 and the emitter layer 104 and that is formed on the periphery of the element portion.

[0042] Here, in this example, a plurality of element parts are provided on the first emitter electrode 102, and each of the plurality of element parts is formed in a rectangular shape in a plan view and is arranged in the direction of the short side (short side) of the rectangle. This is a so-called multi-finger structure. In the embodiment, a configuration is provided in which a plurality of emitter layers 104 (second emitter electrode 103) and collector layers 106 (collector contact layer 107, collector electrode 108) are provided. Note that FIG. 1A shows a cross section in a direction parallel to the short side of the element part having a rectangular shape in a plan view described above, and FIG. 1B shows a cross section in a direction parallel to the long side (long side) of the element part having a rectangular shape in a plan view described above. In the case of a multi-finger structure, the emitter is divided, but in addition to this, by dividing the collector as well, an increase in parasitic capacitance can be suppressed, which is advantageous in terms of high frequency characteristics.

[0043] In addition, in the multiple element portions, the collector layer 106 is formed to have a larger area than the emitter layer 104. In each element portion, the collector layer 106 and the emitter layer 104 are arranged so that their centers overlap in a plan view. As the current flows from the emitter layer 104 to the collector layer 106, the current spreads out after leaving the emitter layer 104, so the collector layer 106 is formed to have a larger area.

[0044] According to the embodiment, heat generated in the element portion is dissipated to the heat dissipation substrate 101 via the second emitter electrode 103 and the first emitter electrode 102. In addition, the heat is also dissipated from the collector layer 106 side to the heat dissipation substrate 101 via the collector electrode 108, which is made of a metal with high thermal conductivity, the collector wiring 115, and the heat dissipation structure 114. As a result, according to the embodiment, it is possible to improve the dissipation of heat generated in the element portion compared to the conventional structure.

[0045] Furthermore, as described below, the crystal layers constituting the element portion are formed by epitaxial growth in the same layering order as in conventional heterojunction bipolar transistors, thereby making it possible to avoid degradation of crystal quality due to epitaxial growth.

[0046] Furthermore, the manufacturing process of the heterojunction bipolar transistor according to the embodiment requires only one bonding process, which is to bond the element portion (second emitter electrode 103, emitter layer 104, base layer 105, collector layer 106, layer to be collector contact layer 107, and base electrode 109) to the heat dissipation substrate after forming the element portion. Therefore, deterioration of crystal quality and yield caused by the bonding process can be suppressed compared to the case where substrate bonding is performed twice.

[0047] As described later, in the manufacture of the heterojunction bipolar transistor according to the embodiment, the element portion and the heat dissipation substrate are bonded via an adhesive metal layer made of Au or Cu, which has high thermal conductivity. In this case, a relatively high bonding pressure is required due to the high Young's modulus compared to the case of bonding using a resin layer such as benzocyclobutene (BCB). However, according to the embodiment, since the metal structures for constituting the emitter contact electrode 112 and the heat dissipation structure 114 are formed around the element portion, the bonding load is suppressed from concentrating locally on the crystal layer constituting the element portion through the second emitter electrode 103, and it is possible to prevent these from being destroyed in the bonding process.

[0048] Furthermore, in the heterojunction bipolar transistor according to the embodiment, heat can be dissipated from the first emitter electrode 102 toward the heat dissipation substrate 101 directly below, so there is no need to diffuse heat in the short side direction of the emitter as in Non-Patent Document 2. Therefore, according to the embodiment, as far as the accuracy of the processing technology allows, it is possible to form a so-called multi-finger structure in which the emitter layer 104 and the second emitter electrode 103 are densely arranged in parallel without sacrificing heat dissipation. This makes it possible to obtain a heterojunction bipolar transistor that combines high heat dissipation and high output performance.

[0049] Furthermore, since the heterojunction bipolar transistor according to the embodiment has a collector-up structure, it is relatively easy to selectively process only the area of ​​collector layer 106 to be smaller than base layer 105. This makes it possible to reduce the collector parasitic capacitance without reducing the contact area between base electrode 109 and base layer 105 (without increasing the base contact resistance), thereby improving the high frequency characteristics.

[0050] As described above, according to the embodiment, it is possible to improve the heat dissipation by suppressing the deterioration of the crystal quality and the decrease of the integration density of the InP-based HBT. Also, according to the embodiment, it is possible to form an HBT with a multi-finger structure having high heat dissipation properties in a single bonding process, and it is possible to obtain the excellent effect of improving the high-speed and high-output performance and the long-term reliability.

[0051] Next, a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention will be described with reference to Figures 2A to 2T. This method is a method for manufacturing the above-mentioned heterojunction bipolar transistor. In Figures 2A to 2F and 2H to 2L, (a) shows a cross section in a direction parallel to a short side of an element portion having a rectangular shape in a plan view, and (b) shows a cross section in a direction parallel to a long side of an element portion having a rectangular shape in a plan view.

[0052] First, as shown in FIG. 2A, an etch stop layer 122, a collector contact formation layer 127, a collector formation layer 126, a base formation layer 125, and an emitter formation layer 124, each of which is made of a compound semiconductor, are crystal-grown in this order on a growth substrate 121 made of InP (first step).

[0053] For example, the etch stop layer 122 may be made of a laminated structure of a layer of non-doped InGaAs and a layer of non-doped InP. The collector contact forming layer 127 may be made of n-type InGaAs doped with a high concentration of Si. The collector forming layer 126 may be made of n-type InP doped with a low concentration of Si. The base forming layer 125 may be made of p-type GaAsSb doped with a high concentration of C. The emitter forming layer 124 may be made of n-type InP doped with a low concentration of Si.

[0054] Each of the layers of the III-V compound semiconductors described above can be formed by crystal (epitaxial) growth using, for example, metalorganic vapor phase deposition or molecular beam epitaxy. Each of the crystal layers described above is epitaxially grown in a lattice-matched state on the growth substrate 121 made of InP, so that good crystallinity with few dislocations and defects can be obtained. Although not shown, an emitter cap-forming layer made of InGaAs with a high In composition and having a thickness equal to or less than the critical film thickness can be formed on the emitter-forming layer 124 to reduce the contact resistance with the emitter electrode.

[0055] 2B, a second emitter electrode 103 is formed on the emitter-forming layer 124. The emitter-forming layer 124, the base-forming layer 125, and the collector-forming layer 126 are processed to form the emitter layer 104, the base layer 105, and the collector layer 106. A base electrode 109 is formed on the base layer 105 around the emitter layer 104. This forms an element portion (second step).

[0056] The number of second emitter electrodes 103 and emitter layers 104 arranged in parallel can be appropriately selected according to the amount of output current required in the integrated circuit. Each layer and electrode can be formed by utilizing known semiconductor patterning techniques, film formation and etching techniques, etc. The base electrode 109 forms a portion that becomes a so-called base pad electrode, which is wider on one side of the emitter longitudinal direction than the other side. This is used to facilitate connection to the base wiring, as described later.

[0057] Next, as shown in FIG. 2C, a first structure 131 made of metal is formed on the growth substrate 121 around the above-mentioned element portion (third step). The first structure 131 is formed in a region excluding the element portion and the periphery of the element portion. The first structure 131 is used as a layer for dispersing pressure during bonding. In addition, since the first structure 131 constitutes a part of a heat dissipation structure that will later become a heat dissipation path, it is desirable for the first structure 131 to be made of a material with high thermal conductivity. Specifically, the first structure 131 can be made of a metal material such as Au or Cu.

[0058] Furthermore, since the distance between first structure 131 and the element portion in plan view affects the area and parasitic capacitance of the final HBT, an optimal distance is set from the standpoint of processing accuracy and electrical characteristics.

[0059] In addition, the thickness (height) of the first structure 131 is made equal to the sum of the thicknesses of the second emitter electrode 103, the emitter layer 104, the base layer 105, and the collector layer 106. As a result, as described later, the bonding pressure applied when bonding the growth substrate 121 and the heat dissipation substrate 101 is applied evenly to the second emitter electrode 103 and the first structure 131, making it possible to suppress deterioration of the crystal quality of the element portion and cracks caused by excessive pressure concentration.

[0060] 2D, a first insulating layer 132 made of an insulating material having a higher thermal conductivity than the collector layer 106 and the emitter layer 104 is formed on (a part of) the peripheral surface of the element portion (step 15). In this example, the first insulating layer 132 is formed on the collector contact formation layer 127 over the entire area including the element portion.

[0061] As described later, the first insulating layer 132 has a role of assisting the thermal conduction of the element portion and a role of protecting the element portion from an etchant when the first structure 131 is etched to form a part of the heat dissipation structure. Therefore, the material of the first insulating layer 132 is preferably silicon nitride film (SiN) or alumina (Al2O3), which has a relatively high thermal conductivity and high chemical stability. The first insulating layer 132 made of these materials can be formed by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the first insulating layer 132 depends on the dimensions and film quality of the element portion, so the thickness that can obtain the above-mentioned effect is appropriately set. Typically, the first insulating layer 132 has a thickness of about 10 nm to 100 nm, which is sufficient to obtain the above-mentioned effect.

[0062] Next, as shown in FIG. 2E, a first protective layer 133 is formed to fill the periphery of the element portion, expose one end side of the first structure 131, and have a flattened surface with the second emitter electrode 103 exposed (fourth step).

[0063] For example, benzocyclobutene (BCB) is applied to the entire surface of the growth substrate 121 to form a coating film, and after the upper surface of the coating film is flattened, the coating film is etched back. In the etch back, a dry etching method is used to remove the second emitter electrode 103 and the first insulating layer 132 on the first structure 131 together with a part of the coating film. At this time, if the dry etching time is extended in order to reliably expose the surface of the second emitter electrode 103, the height of the formation region of the first protective layer 133 on the element portion becomes low, and a situation occurs in which the region where the first protective layer 133 is formed is not bonded to the heat dissipation substrate 101.

[0064] Even in this state, it is possible to obtain the effects of the present invention. However, for example, by using chemical mechanical polishing instead of dry etching, the surface of the second emitter electrode 103 and the surface of the first protective layer 133 can be planarized to be flush with each other (the surface of the second emitter electrode 103 and the surface of the first protective layer 133 form the same plane), thereby suppressing the occurrence of unbonded regions.

[0065] Next, as shown in FIG. 2F, a first adhesive metal layer 134 is formed on the planarized first protective layer 133 (step 5). Also, as shown in FIG. 2G, a heat dissipation substrate 101 is prepared, which is made of an insulating material having a higher thermal conductivity than InP and has a second adhesive metal layer 135 formed on its surface (step 6). The heat dissipation substrate 101 can be made of a material having a higher thermal conductivity than InP and high insulating properties, such as high-resistance Si, SiC, AlN, or diamond. Each adhesive metal layer is used as a heat dissipation structure and electrical wiring, as described later, so it is desirable to make it of a metal that is relatively easy to bond and has high thermal conductivity and high electrical conductivity.

[0066] For example, the first adhesive metal layer 134 and the second adhesive metal layer 135 can be made of Au or Cu. In order to improve adhesion with the first protective layer 133 made of a resin such as BCB and to suppress thermal diffusion of Au or Cu to the element portion, a layer made of Ti, Mo, Ni, W or a compound thereof can be inserted between the first protective layer 133 and the first adhesive metal layer 134.

[0067] As described below, the thicknesses of the first adhesive metal layer 134 and the second adhesive metal layer 135 can be set taking into account the ease of processing and the electrical resistance in forming the first emitter electrode 102. Typically, if these thicknesses are about 100 nm to 500 nm, they do not affect the processing ability and a sufficiently low electrical resistance can be obtained.

[0068] 2H, the first adhesive metal layer 134 of the growth substrate 121 and the second adhesive metal layer 135 of the heat dissipation substrate 101 are brought into contact with each other to form an adhesive metal layer that integrates the first adhesive metal layer 134 and the second adhesive metal layer 135, thereby bonding the growth substrate 121 and the heat dissipation substrate 101 together (seventh step). For example, the above-mentioned bonding can be achieved by surface activation bonding, atomic diffusion bonding, or the like.

[0069] As long as the outermost surfaces of the first adhesive metal layer 134 and the second adhesive metal layer 135, which are the contact surfaces of each of them, are made of Au, they can be bonded at a temperature of 150° C. or less in any bonding technique. This temperature does not affect the crystallinity of the element portion. During bonding, a bonding pressure may be applied to correct the warping and global roughness of each substrate. This bonding pressure is distributed not only to the region where the second emitter electrode 103 is formed, but also to the region where the first structure 131 is formed. Therefore, pressure is not locally concentrated on the second emitter electrode 103, and the risk of deterioration in the crystal quality of the crystal layer constituting the element portion directly below the second emitter electrode 103 and the occurrence of cracks can be reduced.

[0070] Next, the growth substrate 121 and the etch stop layer 122 are removed, and the collector contact formation layer 127 is exposed (step 8), with the second emitter electrode 103 positioned on the heat dissipation substrate 101 side and the element portion formed on the heat dissipation substrate 101 as shown in FIG. 2I.

[0071] The growth substrate 121 can be removed by, for example, known mechanical polishing. As is well known, the growth substrate 121 can be removed by wet etching using a hydrochloric acid-based chemical solution. The etch stop layer 122 may be removed by known wet etching. By using the etch stop layer 122, the growth substrate 121 can be reliably removed, and damage to the collector contact formation layer 127 can be avoided when removing the growth substrate 121.

[0072] 2J, the collector electrode 108 is formed on the collector contact formation layer 127 (ninth step). The collector electrode 108 can be formed by using known lithography, vacuum deposition, or lift-off techniques.

[0073] The collector electrodes 108 are formed in parallel in the same number as the number of emitter layers 104 so as to coincide with the central axis of each of the multiple emitter layers 104. The width (length in the short side direction in a plan view) of each collector electrode 108 is wider than the width of each emitter layer 104, and each (adjacent) collector electrode 108 can be designed not to contact each other. In addition, the length (length in the long side direction in a plan view) of the collector electrode 108 can be designed to at least not reach directly above the first structure 131.

[0074] 2K, the collector contact formation layer 127 is processed to form the collector contact layer 107. In addition, a part of the collector layer 106 and a part of the base layer 105 are removed to form a contact hole 116a that reaches a part of the base electrode 109 (a part that becomes the base pad electrode) (tenth step).

[0075] For example, the collector contact formation layer 127 made of InGaAs can be etched using a citric acid-based etchant. By using this etching, the collector contact layer 107 can be formed. The base layer 105 made of GaAsSb can be etched using a citric acid-based etchant, and the collector layer 106 made of InP can be etched using a hydrochloric acid-based etchant. By using this etching, the contact hole 116a can be formed.

[0076] Moreover, the collector contact layer 107 and the collector layer 106 are additionally etched to divide the collector contact layer 107 and the collector layer 106 as shown in FIG. 2L. The width (length in the short side direction in plan view) of each of the collector layers 106 and the collector contact layer 107 is designed to be wider than the width of each of the emitter layers 104. As in the above, the collector contact layer 107 made of InGaAs can be etched with a citric acid-based etchant, and the collector layer 106 made of InP can be etched with a hydrochloric acid-based etchant. The base layer 105 made of GaAsSb is not etched with a hydrochloric acid-based etchant, so the collector layer 106 can be divided without removing the base layer 105.

[0077] 2M and 2N, first emitter contact electrode 136 constituting part of emitter contact electrode 112, and first heat dissipation structure 137 made of metal and constituting part of heat dissipation structure 114 are formed on first structure 131, and base contact electrode 116 is also formed (step 11). Note that Fig. 2M shows a cross section in a direction parallel to the short side of the element portion which is rectangular in plan view, and Fig. 2N shows a cross section in a direction parallel to the long side of the element portion which is rectangular in plan view.

[0078] The first emitter contact electrodes 136 are formed on the first structure 131 on both sides of the element section in the short side direction in plan view (FIG. 2M). The base contact electrode 116 is formed to fill the contact hole 116a and to be in contact with the base electrode 109 (FIG. 2N). The first heat dissipation structure 137 is formed on the first structure 131 on the side where the base contact electrode 116 is not formed as viewed from the emitter layer 104 (left side in FIG. 2N) in the long side direction in plan view. Both can be formed using a known process similar to that for forming the collector electrode 108. The first emitter contact electrode 136 facilitates the connection between the first emitter electrode 102 and the emitter wiring, and the base contact electrode 116 facilitates the connection between the base electrode 109 and the base wiring.

[0079] 2O and 2P, the first structure 131 is processed to form a second emitter contact electrode 138 connected to the first emitter contact electrode 136, thereby forming the emitter contact electrode 112. The first structure 131 is also processed to form a second heat dissipation structure 139 that constitutes a part of the heat dissipation structure 114 and is connected to the first heat dissipation structure 137. In addition, the adhesive metal layer is processed to form the first emitter electrode 102, and to form a third heat dissipation structure 140 that is connected to the second heat dissipation structure 139, thereby forming the heat dissipation structure 114 consisting of the first heat dissipation structure 137, the second heat dissipation structure 139, and the third heat dissipation structure 140 (step 12).

[0080] In forming the first emitter electrode 102 and the third heat dissipation structure 140, the adhesive metal layer outside the element formation region is completely removed. In forming the second emitter contact electrode 138 and the second heat dissipation structure 139, the first structure 131 outside the element formation region is completely removed. Note that Fig. 2O shows a cross section in a direction parallel to the short side of the element portion which is rectangular in plan view, and Fig. 2P shows a cross section in a direction parallel to the long side of the element portion which is rectangular in plan view.

[0081] For example, the second emitter contact electrode 138, the second heat dissipation structure 139, the region where the first emitter electrode 102 is to be formed, and the base contact electrode 116 are covered with a resist mask, and in this state, the first structure 131 and the adhesive metal layer are wet-etched using an appropriate etchant to form each part. If the adhesive metal layer and the first structure 131 are made of Au, for example, they can be wet-etched using an iodine-based etchant. In this etching, the first insulating layer 132 prevents the etchant from coming into contact with the element portion, and unintended etching of the element portion can be prevented.

[0082] Next, as shown in Figures 2Q and 2R, a second insulating layer 141 made of an insulating material having a higher thermal conductivity than the collector layer 106 and the emitter layer 104 is formed on a part of the peripheral surface of the element portion (step 16). Note that Figure 2Q shows a cross section parallel to the short side of the element portion having a rectangular shape in a plan view, and Figure 2R shows a cross section parallel to the long side of the element portion having a rectangular shape in a plan view. The second insulating layer 141 can improve the heat dissipation from the collector layer 106 to the collector electrode 108 by using a material having a higher thermal conductivity than the compound semiconductor constituting the element portion, such as SiN or Al2O3.

[0083] 2S and 2T, the second protective layer 142 is formed on the first protective layer 133 to form the protective layer 110 consisting of the first protective layer 133 and the second protective layer 142 (step 13). Note that Fig. 2S shows a cross section in a direction parallel to the short side of the rectangular element portion in plan view, and Fig. 2T shows a cross section in a direction parallel to the long side of the rectangular element portion in plan view.

[0084] For example, BCB is applied to the entire surface to form a coating film, and the upper surface of the coating film is flattened, and then the coating film is etched back. In the etchback, a dry etching method is used to remove the collector electrode 108, the emitter contact electrode 112, the base contact electrode 116, and the second insulating layer 141 on the heat dissipation structure 114 together with a part of the coating film, and the second protective layer 142 is formed in a state where the upper surfaces of each part are exposed.

[0085] Thereafter, the emitter wiring 113, the base wiring 117, and the collector wiring 115 are formed (fourteenth step), thereby obtaining the heterojunction bipolar transistor according to the embodiment.

[0086] In the above-described manufacturing method, an example has been shown in which the growth substrate 121 and the heat dissipation substrate 101 are bonded together by bonding via an adhesive metal layer, but this is not limited thereto, and a similar structure can be formed using other bonding techniques (joining techniques) without impairing the effects of the present invention.

[0087] For example, after forming the element portion as described with reference to Figures 2B and 2C, the first emitter contact electrode, the first heat dissipation structure, the second emitter contact electrode, and the second heat dissipation structure are formed as described with reference to Figures 2M, 2N, 2O, and 2P, and filled with a resin film, which is etched back to expose the surfaces of the second emitter contact electrode and the second heat dissipation structure. Meanwhile, the first emitter electrode and the third heat dissipation structure are formed on the heat dissipation substrate, and the resin film is also formed and etched back by CMP to flatten it. Finally, while aligning the positional relationship between the second emitter contact electrode and the first emitter electrode, and the positional relationship between the second heat dissipation structure and the third heat dissipation structure, the growth substrate and the heat dissipation substrate are bonded together by hybrid bonding via the resin film and metal parts of each, and the growth substrate is removed.

[0088] With this method, the two substrates are bonded with their surfaces planarized, thereby preventing the bonding pressure from being applied locally to the second emitter electrode and suppressing a decrease in the crystallinity of the element portion.

[0089] Although the above describes in detail the npn-type InP / GaAsSb HBT on a heat dissipation substrate, which is promising for realizing ultra-high speed integrated circuits, the same effect is also effective for other HBTs.

[0090] As described above, according to the present invention, a protective layer that covers an element portion and the like is formed on a heat dissipation substrate, and a heat dissipation structure made of metal is provided, one end of which is in contact with the heat dissipation substrate surrounding the element portion and formed by penetrating the protective layer. This makes it possible to suppress deterioration in the crystal quality and the integration density of the InP-based HBT and improve heat dissipation performance.

[0091] It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention. [Explanation of symbols]

[0092] 101...heat dissipation substrate, 102...first emitter electrode, 103...second emitter electrode, 104...emitter layer, 105...base layer, 106...collector layer, 107...collector contact layer, 108...collector electrode, 109...base electrode, 110...protective layer, 112...emitter contact electrode, 113...emitter wiring, 114...heat dissipation structure, 115...collector wiring, 116...base contact electrode, 117...base wiring, 118...insulating layer.

Claims

1. A heat dissipation substrate made of an insulating material having a higher thermal conductivity than InP; a first emitter electrode formed on the heat dissipation substrate; a second emitter electrode having an area smaller than that of the first emitter electrode and formed on the first emitter electrode; an emitter layer made of a compound semiconductor and formed on the second emitter electrode; a base layer formed on the emitter layer and made of a compound semiconductor; a collector layer formed on the base layer and made of a compound semiconductor; a collector contact layer formed on the collector layer and made of a compound semiconductor; a collector electrode formed on the collector contact layer; a base electrode formed in connection with the base layer; a protective layer formed on the heat dissipation substrate to cover the second emitter electrode, the emitter layer, the base layer, the collector layer, a side of an element portion formed by the collector contact layer, the first emitter electrode, and the base electrode; an emitter contact electrode formed on and in contact with the first emitter electrode around the element portion and penetrating the protective layer; an emitter wiring formed on the protective layer and connected to the emitter contact electrode; a heat dissipation structure having one end in contact with the heat dissipation substrate around the element portion and formed of a metal penetrating the protective layer; a collector wiring formed on the protective layer in contact with the heat dissipation structure and the collector electrode; a base contact electrode connected to the base electrode and penetrating the protective layer; a base wiring formed on the protective layer and connected to the base contact electrode; A method for manufacturing a heterojunction bipolar transistor comprising: a first step of growing an etch stop layer, a collector contact forming layer, a collector forming layer, a base forming layer, and an emitter forming layer, each of which is made of a compound semiconductor, in this order on a growth substrate made of InP; a second step of forming the element portion by forming the second emitter electrode on the emitter-forming layer, processing the emitter-forming layer, the base-forming layer, and the collector-forming layer to form the emitter layer, the base layer, and the collector layer, and forming the base electrode on the base layer around the emitter layer; a third step of forming a first structure made of a metal on the growth substrate around the element portion; a fourth step of forming a first protective layer that fills the periphery of the element portion, exposes one end of the first structure and the second emitter electrode, and has a planarized surface; a fifth step of forming a first adhesion metal layer on the planarized first protective layer; A sixth step of preparing the heat dissipation substrate, which is made of an insulating material having a thermal conductivity higher than that of InP and has a second adhesive metal layer formed on a surface thereof; a seventh step of bonding the growth substrate and the heat dissipation substrate together by forming an adhesive metal layer integral with the first adhesive metal layer and the second adhesive metal layer, and bonding the growth substrate and the heat dissipation substrate together; an eighth step of removing the growth substrate and the etch stop layer, leaving the element portion formed on the heat dissipation substrate with the second emitter electrode disposed on the heat dissipation substrate side, and exposing the collector contact formation layer; a ninth step of forming the collector electrode on the collector contact formation layer; a tenth step of processing the collector contact formation layer to form the collector contact layer, and further removing a part of the collector layer and a part of the base layer to form a contact hole reaching a part of the base electrode; an eleventh step of forming, on the first structure, a first emitter contact electrode constituting a part of the emitter contact electrode, a first heat dissipation structure made of metal and constituting a part of the heat dissipation structure, and forming the base contact electrode; a twelfth step of processing the first structure to form a second emitter contact electrode connected to the first emitter contact electrode to form the emitter contact electrode, and a second heat dissipation structure constituting a part of the heat dissipation structure and connected to the first heat dissipation structure, and processing the adhesive metal layer to form the first emitter electrode and a third heat dissipation structure connected to the second heat dissipation structure to form the heat dissipation structure consisting of the first heat dissipation structure, the second heat dissipation structure, and the third heat dissipation structure; a thirteenth step of forming a second protective layer on the first protective layer to form the protective layer consisting of the first protective layer and the second protective layer; a fourteenth step of forming the emitter wiring, the base wiring, and the collector wiring; A method for manufacturing a heterojunction bipolar transistor comprising the steps of:

2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, A method for manufacturing a heterojunction bipolar transistor, further comprising: an insulating layer formed on a peripheral surface of the element portion, the insulating layer being made of an insulating material having a higher thermal conductivity than the collector layer and the emitter layer.

3. A method for manufacturing a heterojunction bipolar transistor according to claim 1 or 2, a plurality of the element portions on the first emitter electrode; Each of the plurality of element portions is formed in a rectangular shape in a plan view and is arranged in a direction of a shorter side of the rectangle, The plurality of element portions have a collector layer formed to have a larger area than the emitter layer.

2. A method for manufacturing a heterojunction bipolar transistor comprising the steps of:

4. 2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, a fifteenth step, which is performed after the third step and before the fourth step, of forming a first insulating layer made of an insulating material having a higher thermal conductivity than the collector layer and the emitter layer on a part of a peripheral surface of the element portion; a sixteenth step, which is performed after the twelfth step and before the thirteenth step, of forming a second insulating layer made of an insulating material having a higher thermal conductivity than the collector layer and the emitter layer on a part of a peripheral surface of the element portion; The method for manufacturing a heterojunction bipolar transistor further comprises:

5. 2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, The second step includes forming a plurality of the element portions; The ninth step includes forming the collector electrode individually on each of the plurality of element portions.

2. A method for manufacturing a heterojunction bipolar transistor comprising the steps of:

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