Image sensor

Abstract

To enable efficient TDI operation while suppressing increase in circuit scale and reducing the amount of output signals.SOLUTION: An image capturing device comprises: a pixel unit that has pixel arrays 12 each including N pixel sections 11 (N is an integer of two or a greater); and circuit units 5. Each circuit unit 5 has: N charge amplifiers 31 that convert charge signals output from the pixel sections 11 to voltage signals; N A / D converters 61 each of which has an addition processing section for performing addition of the voltage signals and a holding section for holding the added signal in accordance with the addition state of the addition processing section; and a switch array 40 that switches connection state between the charge amplifiers 31 and the holding sections of the A / D converters 61. The switch array 40 switches connection state such that the holding sections of the A / D converters 61 in which the added signals corresponding to the charge signals output from the pixel sections 11 are held are switched according to an arrangement order of the N pixel sections 11.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] Some imaging elements perform a TDI (Time Delay Integration) operation to improve the S / N ratio. For example, an imaging device described in Patent Document 1 includes n (n is an integer equal to or greater than 2) light receiving elements arranged in the scanning direction of an optical system, and a TDI circuit that performs time delay integration of pixel signals output from the n light receiving elements. The TDI circuit includes p (p is an integer that satisfies p=kn, and k is a positive integer) integral capacitances, and a switching circuit network that supplies pixel signals output from the n light receiving elements to the p integral capacitances so that pixel signals at the same imaging point are supplied to the same integral capacitance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-88784 Summary of the Invention [Problem to be solved by the invention]

[0004] In the imaging device described in Patent Document 1, when the charge generated in the light receiving element is transferred to the integral capacitance, capacitance division occurs between the capacitance of the light receiving element and the integral capacitance, and the charge remains on the light receiving element side, which may result in insufficient charge transfer. In addition, the imaging element described above is required to suppress an increase in the circuit size and reduce the amount of output signals.

[0005] Therefore, an object of the present invention is to provide an image sensor capable of realizing an efficient TDI operation while suppressing an increase in the circuit size and reducing the amount of output signals. [Means for solving the problem]

[0006] The imaging element of the present invention includes a pixel unit having M pixel arrays (M is an integer of 2 or more) each including N pixel units (N is an integer of 2 or more) that perform photoelectric conversion, the N pixel units being arranged along a first direction, and the M pixel arrays being arranged along a second direction perpendicular to the first direction, and M circuit units provided corresponding to the M pixel arrays, each of the M circuit units including an operational amplifier and a capacitance unit connected between an inverting input terminal and an output terminal of the operational amplifier, and includes N A / D converters (Analog-to-Digital Converters) each including N charge amplifiers that convert charge signals output from the N pixel units of the corresponding pixel array into voltage signals, an addition processing unit that performs an addition process of the voltage signals output from any one of the N charge amplifiers, and a holding unit that holds an addition signal according to an addition state of the addition processing unit. The circuit unit has M charge amplifiers and a switch circuit that switches a connection state between the N charge amplifiers and holding units of the N A / D converters, and in each of the M circuit units, the switch circuit switches the connection state so that the holding units that hold the summed signals corresponding to the charge signals output from the pixel units are switched in accordance with the arrangement order of the N pixel units in the first direction.

[0007] In this imaging element, each of the M circuit units has N charge amplifiers, N A / D converters, and a switch circuit. In each of the M circuit units, the connection state between the charge amplifiers and the holding units of the A / D converters is switched so that the holding units of the A / D converters, which hold the summed signals corresponding to the charge signals output from the pixel units, are switched according to the arrangement order of the N pixel units along the first direction, thereby realizing the TDI operation. By realizing the TDI operation by the addition process using such an A / D converter, it is possible to suppress an increase in the circuit scale compared to, for example, a case where a memory for simply adding signals is provided in the circuit unit. In addition, it is possible to reduce the amount of output signals compared to, for example, a case where a signal is output to the outside of the imaging element and the addition process is performed outside. Furthermore, in this imaging element, the charge signals output from the pixel units are converted to voltage signals by the charge amplifiers, and the voltage signals are added in the A / D converter. This makes it possible to reduce the loss in the transfer of the charge signals from the pixel units, and to realize an efficient TDI operation. Therefore, according to this imaging device, it is possible to suppress an increase in the circuit size, reduce the amount of output signals, and realize an efficient TDI operation.

[0008] Each of the N A / D converters may be configured as a single-slope type, which makes it possible to realize an efficient TDI operation with a simple configuration.

[0009] The switch circuit may be connected between the N charge amplifiers and the addition processing section of the A / D converter. In this case, an efficient TDI operation can be achieved with a simple configuration.

[0010] The M circuit units are arranged adjacent to the corresponding pixel arrays in the first direction, and each of the M circuit units has N arrangement regions arranged in the second direction, and a charge amplifier and an A / D converter are arranged in each of the N arrangement regions, and the width of each of the N arrangement regions in the second direction may be 1 / N or less of the width of the pixel section in the second direction. In this case, the circuit units can be arranged efficiently, and an increase in the circuit size can be further suppressed.

[0011] The imaging element of the present invention comprises a pixel unit having M pixel arrays (M is an integer of 2 or more) each including N pixel units (N is an integer of 2 or more) that perform photoelectric conversion, the N pixel units being arranged along a first direction and the M pixel arrays being arranged along a second direction perpendicular to the first direction, and M circuit units provided corresponding to the M pixel arrays, each of the M circuit units including an operational amplifier and a capacitance unit connected between the inverting input terminal and the output terminal of the operational amplifier and in which a charge signal output from one of the N pixel units of the corresponding pixel array is accumulated, the imaging element further comprises N charge amplifiers that convert the charge signal into a voltage signal, and a switch circuit that switches a connection state between the N pixel units and the capacitance units of the N charge amplifiers, and in each of the M circuit units, the switch circuit switches the connection state so that the capacitance unit in which the charge signal output from the pixel unit is accumulated is switched in accordance with the arrangement order of the N pixel units along the first direction.

[0012] In this imaging element, each of the M circuit units has N charge amplifiers and a switch circuit. In each of the M circuit units, the connection state between the pixel unit and the charge amplifier is switched so that the capacitance section of the charge amplifier in which the charge signals output from the pixel unit are accumulated (added) is switched according to the arrangement order of the N pixel units along the first direction, thereby realizing the TDI operation. By realizing the TDI operation by such an addition process using the charge amplifier, it is possible to suppress an increase in the circuit scale compared to, for example, a case in which a memory for simply adding signals is provided in the circuit unit. In addition, it is possible to reduce the amount of output signals compared to, for example, a case in which signals are output to the outside of the imaging element and an addition process is performed outside. Furthermore, in this imaging element, the charge signals output from the pixel unit are accumulated and added in the capacitance section of the charge amplifier, and are converted into a voltage signal by the charge amplifier. This makes it possible to reduce loss in the transfer of the charge signals from the pixel unit, and to realize an efficient TDI operation. Therefore, according to this imaging element, it is possible to suppress an increase in the circuit scale and realize an efficient TDI operation while reducing the amount of output signals.

[0013] The M circuit units are arranged adjacent to the corresponding pixel arrays in the first direction, and each of the M circuit units has N arrangement regions arranged in the second direction, and a charge amplifier is arranged in each of the N arrangement regions, and the width of each of the N arrangement regions in the second direction may be 1 / N or less of the width of the pixel unit in the second direction. In this case, the circuit units can be arranged efficiently, and an increase in the circuit scale can be further suppressed.

[0014] Each of the N pixel units may include a surface-type photodiode, which allows the pixel unit to have a large area.

[0015] Each of the N pixel units may include a buried photodiode, which can achieve high sensitivity and low noise.

[0016] N may be an integer equal to or greater than 8. When the number of pixels is large like this, an increase in circuit size and an increase in the amount of output signals can easily become a problem, but with this image sensor, even in such a case, it is possible to suppress the increase in circuit size and reduce the amount of output signals, while achieving efficient TDI operation. Effect of the Invention

[0017] According to the present invention, it is possible to provide an imaging element capable of realizing efficient TDI operation while suppressing an increase in circuit size and reducing the amount of output signals. [Brief description of the drawings]

[0018] [Figure 1] FIG. 2 is a plan view of an image sensor according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of a pixel array and a circuit unit. [Diagram 3] FIG. 2 is a diagram showing a circuit configuration of an amplifier array. [Figure 4] FIG. 2 is a diagram showing a circuit configuration of a switch array. [Diagram 5] FIG. 2 is a diagram showing a circuit configuration of a memory array. [Figure 6] FIG. 2 is a diagram illustrating a circuit configuration of an ADC array. [Figure 7] 4 is a timing chart showing the operation of the image sensor according to the embodiment. [Figure 8] 4 is a timing chart showing the operation of the image sensor according to the embodiment. [Figure 9] 4 is a timing chart showing the operation of the image sensor according to the embodiment. [Figure 10] FIG. 1 is a diagram for explaining a TDI operation. [Figure 11] FIG. 1 is a diagram for explaining a TDI operation. [Figure 12] FIG. 11 is a circuit diagram for explaining charge transfer in a comparative example. [Figure 13] FIG. 2 is a circuit diagram for explaining charge transfer in the embodiment. [Figure 14]FIG. 13 is a diagram showing a circuit configuration of a pixel array and a circuit unit according to a first modified example. [Figure 15] FIG. 13 is a diagram showing a circuit configuration of a pixel array and an amplifier array according to a second modified example. [Figure 16] FIG. 13 is a diagram showing a circuit configuration of a switch array according to a second modified example. [Figure 17] 13 is a timing chart showing the operation of an image sensor according to a second modified example. [Figure 18] 13 is a timing chart showing the operation of an image sensor according to a second modified example. [Figure 19] FIG. 13 is a diagram showing a circuit configuration of a pixel array and a circuit unit according to a third modified example. [Figure 20] FIG. 13 is a diagram showing a circuit configuration of a switch array according to a third modified example. [Figure 21] FIG. 13 is a diagram showing a circuit configuration of an amplifier array according to a third modified example. [Figure 22] FIG. 13 is a diagram showing a circuit configuration of a switch array according to a third modified example. [Diagram 23] 13 is a timing chart showing the operation of an image sensor according to a third modified example. [Figure 24] 13 is a timing chart showing the operation of an image sensor according to a third modified example. [Diagram 25] 13 is a timing chart showing the operation of an image sensor according to a third modified example. [Figure 26] FIG. 13 is a diagram for explaining a TDI operation of a third modified example. [Figure 27] FIG. 13 is a diagram for explaining a TDI operation of a third modified example. [Figure 28] FIG. 13 is a diagram showing a circuit configuration of a pixel array and a circuit unit according to a fourth modified example. [Figure 29] 13 is a timing chart showing the operation of an image sensor according to a fourth modified example. [Diagram 30] 13 is a timing chart showing the operation of an image sensor according to a fourth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or corresponding elements are designated by the same reference numerals, and duplicated descriptions will be omitted. [Image sensor configuration]

[0020] The imaging element 1 shown in Fig. 1 is, for example, a solid-state imaging element used in an X-ray image acquisition device for acquiring an X-ray image of an object transported along a transport direction. In the X-ray image acquisition device, for example, X-rays transmitted through the object are converted into scintillation light by a scintillator, and the scintillation light is detected by the imaging element 1 to acquire an X-ray image of the object. At this time, a TDI (Time Delay Integration) operation is performed using the imaging element 1 to improve the S / N ratio in the acquired image. The TDI operation will be described later.

[0021] As shown in FIG. 1, the imaging element 1 includes a pixel unit 2, a circuit section 3, and a decoder 4. The pixel unit 2, the circuit section 3, and the decoder 4 are formed on one chip and integrated with each other. The pixel unit 2 has M pixel arrays 12 (M is an integer of 2 or more) each including N pixel sections 11 (N is an integer of 2 or more) that perform photoelectric conversion. Each pixel section 11 is formed, for example, in a rectangular shape in a plan view. The N pixel sections 11 are arranged adjacent to each other in a line along a first direction X1. The M pixel arrays 12 are arranged adjacent to each other along a second direction X2 perpendicular to the first direction X1. The A-th (A is any integer of 1 to N) pixel sections 11 of the M pixel arrays 12 are arranged along the second direction X2. That is, in the pixel unit 2, N×M pixel sections 11 are arranged in a matrix.

[0022] When used in an X-ray image acquisition device as described above, the image sensor 1 is disposed so that the first direction X1 coincides with the transport direction of the object. N may be an integer of 8 or more, or may be an integer of 16 or more. The larger N is, the more the S / N ratio can be improved by the TDI operation. In the following, an example in which N is 4 will be described, but the same applies to other values ​​of N.

[0023] Each pixel unit 11 is composed of a light receiving element capable of detecting scintillation light, for example. In this example, the light receiving element is a photodiode made of silicon, but may be a photodiode made of a compound semiconductor such as InGaAs or CdTe. In this example, the light receiving element is a surface type photodiode in which the PN junction is exposed on the surface, but may be a buried type photodiode in which the PN junction is buried inside.

[0024] The circuit section 3 includes M circuit units 5 provided corresponding to the M pixel arrays 12. In this example, the M circuit units 5 are electrically connected to the M pixel arrays 12, respectively. Specifically, the N pixel sections 11 of each of the M pixel arrays 12 are electrically connected to the M circuit units 5 by N×M wirings 6. That is, the N pixel sections 11 of one pixel array 12 are electrically connected to the corresponding circuit units 5 by N wirings 6. Each wiring 6 extends linearly along the first direction X1 so as to pass over the pixel sections 11, for example.

[0025] 2, each circuit unit 5 has an amplifier array 30, a switch array (switch circuit) 40, a memory array 50, and an ADC (Analog-to-Digital converter) array 60. Below, the configuration and operation of one circuit unit 5 and the pixel array 12 corresponding to that circuit unit 5 will be described, but the configurations and operations of the other circuit units 5 and pixel arrays 12 are similar. In addition, the four pixel sections 11 included in the pixel array 12 will also be referred to as pixel sections PD1, PD2, PD3, and PD4 in order of furthest from the circuit unit 5.

[0026] As shown in FIG. 3, the amplifier array 30 includes N charge amplifiers 31 (four in this example). Each charge amplifier 31 has an operational amplifier 32, a capacitance unit 33, and a reset switch 34. The capacitance unit 33 is a feedback capacitance and is connected between an inverting input terminal 32a and an output terminal 32c of the operational amplifier 32. The capacitance unit 33 accumulates a charge signal output from the pixel unit 11. The non-inverting input terminal 32b of the operational amplifier 32 is connected to a reference voltage Vref. The reset switch 34 is connected in parallel with the capacitance unit 33 between the inverting input terminal 32a and the output terminal 32c. The reset switch 34 is turned on and off in accordance with a reset signal RS_A to reset the charge accumulated in the capacitance unit 33.

[0027] The four charge amplifiers 31 are connected to the four pixel units 11 of the corresponding pixel array 12, respectively. More specifically, a charge signal from the pixel unit 11 is input to an inverting input terminal 32a of the operational amplifier 32. The charge amplifier 31 converts the charge signal output from the pixel unit 11 of the corresponding pixel array 12 into a voltage signal. Hereinafter, the charge amplifiers 31 that receive signals from the pixel units PD1, PD2, PD3, PD4 are also referred to as charge amplifiers CA1, CA2, CA3, CA4, respectively. The voltage signals from the charge amplifiers 31 are output to switch units SU1 to SU4, which will be described later, via an output terminal 32c.

[0028] 4, the switch array 40 includes N (four in this example) switch units 41. Each switch unit 41 includes four switches 42a, 42b, 42c, and 42d connected to the four charge amplifiers 31, respectively. An output signal from the switch unit 41 is output to memory units MR1 ​​to MR4, which will be described later. The switch array 40 is configured such that the connection states between the charge amplifiers CA1 to CA4 and the memory units MR1 ​​to MR4 are switched according to the on / off states of the switches 42a to 42d.

[0029] More specifically, in each switch unit 41, the switch 42a is turned on and off according to a switching signal SW1, the switch 42b is turned on and off according to a switching signal SW2, the switch 42c is turned on and off according to a switching signal SW3, and the switch 42d is turned on and off according to a switching signal SW4. The switch units 41 connected to the memory units MR1, MR2, MR3, and MR4 are referred to as switch units SU1, SU2, SU3, and SU4, respectively. In FIG. 4, output nodes SU1_OUT, SU2_OUT, SU3_OUT, and SU4_OUT of the switch units SU1, SU2, SU3, and SU4 are shown.

[0030] When the switching signal SW1 is on and the switching signals SW2 to SW4 are off, the charge amplifiers CA1, CA4, CA3, and CA2 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. When the switching signal SW2 is on and the switching signals SW1, SW3, and SW4 are off, the charge amplifiers CA2, CA1, CA4, and CA3 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. When the switching signal SW3 is on and the switching signals SW1, SW2, and SW4 are off, the charge amplifiers CA3, CA2, CA1, and CA4 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. When the switching signal SW4 is on and the switching signals SW1 to SW3 are off, the charge amplifiers CA4, CA3, CA2, and CA1 are connected to the memory units MR1, MR2, MR3, and MR4, respectively.

[0031] 5, the memory array 50 includes N memory units 51 (four in this example). The memory array 50 may include T memory units 51 (T is an integer equal to or greater than N). Each memory unit 51 has capacitances 52N and 52S, switches 53N, 53S, 54N and 54S, and a reset switch 55. The capacitance 52N holds a reference voltage (N level) of the voltage signal from the charge amplifier 31, and the capacitance 52S holds a signal voltage (S level) of the voltage signal from the charge amplifier 31. The difference between the signal voltage and the reference voltage is the effective signal.

[0032] The switches 53N and 53S are used to switch the connection state between the capacitors 52N and 52S and the switch units SU1 to SU4, and the switches 54N and 54S are used to switch the connection state between the capacitors 52N and 52S and the A / D converters AD1 to AD4 (described later). The switches 53N and 53S are turned on and off in response to switching signals SETN1 and SETS1, and the switches 54N and 54S are turned on and off in response to switching signals SETN2 and SETS2.

[0033] The reset switch 55 is turned on and off according to a reset signal RS_M. When the reset switch 55 is turned on, a reset voltage VRS is supplied and the voltages of the input terminals of the A / D converters AD1 to AD4 are reset. The memory array 50 is provided to change the signal transfer order because the voltage signals from the charge amplifier 31 are held in the capacitors 52N and 52S in the order of S level and N level, whereas the order of AD conversion by the ADC array 60 is N level and S level. Hereinafter, the memory units 51 connected to the switch units SU1, SU2, SU3, and SU4 (A / D converters AD1, AD2, AD3, and AD4) are also referred to as memory units MR1, MR2, MR3, and MR4, respectively. FIG. 5 shows output nodes MR1_OUT, MR2_OUT, MR3_OUT, and MR4_OUT of the memory units MR1, MR2, MR3, and MR4.

[0034] As shown in FIG. 6, the ADC array 60 includes N A / D converters 61 (four in this example). The ADC array 60 may include T A / D converters 61 (T is an integer equal to or greater than N). In this example, each A / D converter 61 is configured as a single slope type, and includes a comparator 62, a counter 63 having a bit number of B (B is an integer equal to or greater than 1), B latch switches 64, and B capacitors 65. The comparator 62 compares the output signal from the memory unit 51 with the ramp wave VRAMP. The counter 63 outputs a count value in B bits according to the output signal from the comparator 62. The latch switch 64 latches the counter value output from the counter 63. The capacitor 65 holds the count value output from the counter 63 according to the on / off state of the latch switch 64. The counter 63 operates based on a clock pulse CLK. The latch switch 64 operates based on a latch signal LS.

[0035] In the A / D converter 61, the output of the comparator 62 changes in response to the output signals from the memory units MR1 ​​to MR4 (charge signals from the pixel units PD1 to PD4, and voltage signals from the charge amplifiers CA1 to CA4), and a counter 63 counts in response to the change, thereby performing A / D conversion to convert the voltage signals into digital values.

[0036] If the A / D converters 61 connected to the memory units MR1, MR2, MR3, and MR4 are A / D converters AD1, AD2, AD3, and AD4, respectively, separate reset signals RS_C1, RS_C2, RS_C3, and RS_C4 are input to the counters 63 of the A / D converters AD1, AD2, AD3, and AD4. This makes it possible to independently reset the counters 63 of the A / D converters AD1 to AD4.

[0037] In each A / D converter 61, the counter 63 performs counting according to the received voltage signal and holds the count value. The counting performed by the counter 63 may be either counting up or counting down. Furthermore, the counter 63 performs counting according to the next input voltage signal based on the count value previously held in the counter 63, and holds the count value. That is, each counter 63 performs counting sequentially every time a voltage signal is input, and holds count values ​​according to all the input voltage signals (addition process).

[0038] The B capacitors 65 hold a voltage signal (addition signal) according to the holding state (addition state) of the count value in the corresponding counter 63. That is, holding / non-holding of the voltage signal in each capacitor 65 is determined according to the count value held in the corresponding counter 63. As a result, by reading out the holding state of the voltage signal in the B capacitors 65, a digital signal according to the count value held in the counter 63 can be obtained. In this way, in the A / D converter 61, the comparator 62 and the counter 63 function as an addition processing unit that performs addition processing of the voltage signal output from any one of the charge amplifiers CA1 to CA4, and the B capacitors 65 function as a holding unit that holds an addition signal according to the addition state of the addition processing unit. The count value held in the counter 63 is reset by input of the reset signals RS_C1 to C4. The timing of reading out the holding state of the voltage signal in the capacitor 65 is controlled by the decoder 4.

[0039] 1 again, the M circuit units 5 are arranged adjacent to (facing) the corresponding pixel arrays 12 in the first direction X1. Each circuit unit 5 has N arrangement regions R aligned in the second direction X2. In each of the arrangement regions R, one charge amplifier 31, one memory unit 51, and one A / D converter 61 described above are arranged. The width of each arrangement region R in the second direction X2 is 1 / N or less of the width of the pixel section 11 in the second direction X2. In other words, the width of the combined area of ​​the N arrangement regions R in the second direction X2 is less than the width of the pixel section 11. [TDI operation]

[0040] The TDI operation using the imaging element 1 will be described with reference to Figs. 7 to 9. In the timing chart of Fig. 7, from the top, the reset signal RS_A, the voltage signals from the charge amplifiers CA1 to CA4, the switching signals SW1 to SW4, the switching signals SETN1, SETS1, SETN2, SETS2, and the reset signal RS_M are shown with time, and the operation states of the A / D converters AD1 to AD4 are shown. In the operation states of the A / D converters AD1 to AD4, "A / D Convert: CA1" means that the voltage signal from the charge amplifier CA1 is being A / D converted, and similarly, "A / D Convert: CA2 to CA4" means that the voltage signals from the charge amplifiers CA2 to CA4 are being A / D converted. "H" means that the signal is held, and "0" means that the signal is reset. The waveforms of the voltage signals from the charge amplifiers CA1 to CA4 are just an example. These points are the same for Figs. 17, 18, 23, 24, 29, and 30 described later. The timing chart in Fig. 8 shows, from the top, the operating states of A / D converters AD1 to AD4, as well as the changes over time of the latch signal LS, the reset signals RS_C1 to C4, and the read signals D1 to D4. The read signals D1 to D4 are signals output from the decoder 4 to control the read timing of the voltage holding state in the capacitor 65. When the read signals D1, D2, D3, and D4 are turned on, the voltage holding states in the capacitor 65 of the A / D converters AD1, AD2, AD3, and AD4 are read out and converted into digital values ​​(digital signals) (Fig. 2).

[0041] As shown in FIG. 7 to FIG. 9, during the period between times T1 and T2, the switching signal SW1 is turned on and the switching signals SW2 to SW4 are turned off, and the charge amplifiers CA1, CA4, CA3, and CA2 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, when the voltage signals (voltage signals corresponding to the charge signals output from the pixel units PD4, PD3, PD2, and PD1) from the charge amplifiers CA4, CA3, CA2, and CA1 are input, counting is performed in the A / D converters AD1, AD2, AD3, and AD4, respectively, and the count values ​​are held. At time T2, the read signal D1 is turned on, and the voltage state held in the capacitance 65 of the A / D converter AD1 is read out and converted into a digital value. Before this reading, a reset signal RS_C1 is input, and the counter 63 of the A / D converter AD1 is reset.

[0042] During the period between times T2 and T3, the switching signal SW2 is turned on and the switching signals SW1, SW3, and SW4 are turned off, and the charge amplifiers CA2, CA1, CA4, and CA3 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, voltage signals (voltage signals corresponding to the charge signals output from the pixel units PD1, PD4, PD3, and PD2) from the charge amplifiers CA1, CA4, CA3, and CA2 are input, and counting is performed in the A / D converters AD1, AD2, AD3, and AD4, respectively, and the count values ​​are held. At time T3, the read signal D2 is turned on, and the voltage state held in the capacitance 65 of the A / D converter AD2 is read out and converted into a digital value. Before this reading, a reset signal RS_C2 is input, and the counter 63 of the A / D converter AD2 is reset.

[0043] During the period between times T2 and T3, the voltage signals from the charge amplifier 31 held in the capacitances 52N and 52S of the memory unit 51 during the previous period between times T1 and T2 are transferred to the A / D converters AD1 to AD4 by turning on and off the switching signals SETN1, SETS1, SETN2, and SETS2. Therefore, during the period between times T2 and T3, the A / D converters AD1, AD2, AD3, and AD4 count and A / D convert the voltage signals according to the voltage signals from the charge amplifiers CA1, CA4, CA3, and CA2 that were connected to the memory units MR1, MR2, MR3, and MR4 during the previous period between times T1 and T2. This is the same for the other periods.

[0044] During the period between times T3 and T4, the switching signal SW3 is turned on and the switching signals SW1, SW2, and SW4 are turned off, and the charge amplifiers CA3, CA2, CA1, and CA4 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, voltage signals (voltage signals corresponding to the charge signals output from the pixel units PD2, PD1, PD4, and PD3) from the charge amplifiers CA2, CA1, CA4, and CA3 are input, and counting is performed in the A / D converters AD1, AD2, AD3, and AD4, respectively. At time T4, the read signal D3 is turned on, and the voltage state held in the capacitance 65 of the A / D converter AD3 is read out and converted into a digital value. Before this reading, a reset signal RS_C3 is input, and the counter 63 of the A / D converter AD3 is reset.

[0045] During the period between times T4 and T5, the switching signal SW4 is turned on and the switching signals SW1 to SW3 are turned off, and the charge amplifiers CA4, CA3, CA2, and CA1 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, voltage signals (voltage signals corresponding to the charge signals output from the pixel units PD3, PD2, PD1, and PD4) from the charge amplifiers CA3, CA2, CA1, and CA4 are input, and counting is performed in the A / D converters AD1, AD2, AD3, and AD4, respectively. At time T5, the read signal D4 is turned on, and the voltage state held in the capacitance 65 of the A / D converter AD4 is read out and converted into a digital value. Before this reading, a reset signal RS_C4 is input, and the counter 63 of the A / D converter AD4 is reset. The operations in the periods between times T5 and T6, between times T6 and T7, between times T7 and T8, and between times T8 and T9 are similar to the operations in the periods between times T1 and T2, between times T2 and T3, between times T3 and T4, and between times T4 and T5, respectively.

[0046] By the above operation, output signals from N pixel units 11 are added in a TDI manner. In the above example, continuous TDI-like addition processing is realized by shifting the reset timing of the counters 63 in the A / D converters AD1 to AD4 by one frame at a time. One frame corresponds to the length of the period between times T1 and T2. In this addition processing, the capacitances 65 (holding units) of the A / D converters AD1 to AD4 that hold voltage signals corresponding to the charge signals output from the pixel units PD1 to PD4 are switched according to the arrangement order of the pixel units PD1 to PD4 along the first direction X1. In other words, the switch array 40 switches the connection state between the charge amplifiers CA1 to CA4 and the capacitances 65 of the A / D converters AD1 to AD4 so as to switch in this way.

[0047] 10 and 11 are diagrams for explaining the addition process by the TDI operation. In FIG. 10 and FIG. 11, an example is shown in which light (electromagnetic waves) from an object OJ transported along the transport direction (first direction X1) is detected by the image sensor 1. If the object OJ is divided into regions a to j according to the position along the transport direction, as shown in FIG. 10 and FIG. 11, signals corresponding to charge signals output from pixel units PD1 to PD4 by detecting light transmitted through the same region of the object OJ by the TDI operation are input to the same A / D converters AD1 to AD4. For example, a signal based on the detection of light from region a is input to the A / D converter AD1. Then, a voltage signal (4a) corresponding to a count value corresponding to four frames of signals is held in the capacitor 65, and the voltage signal (4a) is read out as a digital value from the A / D converter AD1 at time T6. By acquiring a count value corresponding to N frames of signals in this way, the S / N ratio in the acquired image can be improved. In the TDI operation, the timing at which the switch array 40 switches the connection states between the charge amplifiers CA1 to CA4 and the A / D converters AD1 to AD4 is synchronized with the transport (eg, transport speed) of the object OJ along the first direction X1. [Action and Effects]

[0048] In the image sensor 1, each of the M circuit units 5 has N charge amplifiers 31, N A / D converters 61, and a switch array 40 (switch circuit). In each circuit unit 5, the connection state between the charge amplifier 31 and the capacitance 65 of the A / D converter 61 is switched so that the capacitance 65 (holding section) of the A / D converter 61, which holds a voltage signal (addition signal) corresponding to the charge signal output from the pixel section 11, switches according to the arrangement order of the N pixel sections 11 in the first direction X1, thereby realizing a TDI operation. By realizing a TDI operation by an addition process using such an A / D converter 61, it is possible to suppress an increase in the circuit scale compared to, for example, a case in which a memory for simply digitally adding signals is provided in the circuit unit 5. In addition, the amount of output signals can be reduced compared to, for example, a case where signals are output outside the image sensor 1 and digital addition processing is performed outside. Furthermore, in the image sensor 1, the charge signals output from the pixel unit 11 are converted into voltage signals by the charge amplifier 31, and the voltage signals are added in the A / D converter 61. This makes it possible to reduce loss in the transfer of charge signals from the pixel unit 11, and to realize efficient TDI operation. Therefore, according to the image sensor 1, it is possible to suppress an increase in the circuit size and reduce the amount of output signals, while realizing efficient TDI operation.

[0049] With reference to Figs. 12 and 13, the reduction of loss in the transfer of a charge signal from the pixel unit 11 will be described. Fig. 12 is a circuit diagram for explaining charge transfer in a comparative example, and Fig. 13 is a circuit diagram for explaining charge transfer in the embodiment. In the comparative example shown in Fig. 12, a signal charge Q1 from the pixel unit is transferred to an integral capacitance C2 by turning on a switch SW. In this case, assuming that the capacitance on the pixel unit side (capacitance of a photodiode, etc.) is C1, the voltage V2 of the node 2 would be Q1 / C2 if completely transferred, but actually becomes Q1 / (C1+C2). After that, even if the switch SW is turned off, the charge transferred to the integral capacitance C2 becomes Q1×C2 / (C1+C2), and the charge transfer is insufficient (capacitive division).

[0050] 13, when the charge amplifier 31 is connected to the pixel unit 11, the potential of node A does not change due to the signal charge Q from the pixel unit 11, and the potential of node A continues to be the same as the reference voltage Vref due to the virtual grounding effect of the operational amplifier 32. Since the potential of node A does not change, all of the signal charge Q is stored in the capacitance unit 33, and the output voltage from the charge amplifier 31 becomes Q / Cf, making it possible to reduce loss in the transfer of the charge signal. Here, Cf is the capacitance of the capacitance unit 33.

[0051] Each A / D converter 61 is configured as a single slope type, which makes it possible to realize an efficient TDI operation with a simple configuration.

[0052] The switch array 40 is connected between the charge amplifier 31 and the comparator 62 (addition processing unit) of the A / D converter 61. This makes it possible to realize an efficient TDI operation with a simple configuration.

[0053] The width of each arrangement region R in the second direction X2 is equal to or less than 1 / N of the width of the pixel section 11 in the second direction X2. This allows the circuit units 5 to be arranged efficiently, and further suppresses an increase in the circuit scale.

[0054] Each pixel section 11 includes a surface-type photodiode, which allows the pixel section 11 to have a large area.

[0055] N is an integer equal to or greater than 8. When the number of pixels is large like this, an increase in circuit size and an increase in the amount of output signals can easily become a problem, but even in such a case, the image sensor 1 can suppress the increase in circuit size and reduce the amount of output signals, while achieving efficient TDI operation. [Variations]

[0056] The imaging element 1 may be configured as a first modified example shown in Fig. 14. In the above embodiment, the entire imaging element 1 is formed on one chip, but in the first modified example, the pixel unit 2, the circuit section 3, and the decoder 4 are formed on separate chips and are separated from each other. When in use, the pixel unit 2 is electrically connected to the circuit section 3 (amplifier array 30). With such a first modified example, as in the above embodiment, it is possible to suppress an increase in circuit size and reduce the amount of output signals while achieving efficient TDI operation.

[0057] The imaging element 1 may be configured as a second modified example shown in FIG. 15 to FIG. 18. In the second modified example, the light receiving element of each pixel unit 11 is configured by an embedded photodiode. Each pixel unit 11 has a pixel amplifier 13 in addition to the light receiving element. The pixel amplifier 13 has a capacitance 14, transistors 15 and 16, and a source follower amplifier 17. The capacitance 14 is, for example, a floating diffusion, and is an accumulation region formed on a semiconductor substrate. All signal charges of the light receiving element are transferred to the capacitance 14 and converted into a voltage. The transistor 15 is, for example, a MOS transistor, and controls the transfer of the signal from the light receiving element to the capacitance 14. The transistor 16 is, for example, a MOS transistor, and controls the reset of the capacitance 14. The source follower amplifier 17 amplifies and outputs the voltage signal from the capacitance 14. The source follower amplifier 17 is connected to the charge amplifier 31 via a coupling capacitance 18. The output signal from the source follower amplifier 17 is converted into a charge by the coupling capacitance 18, and then converted back into a voltage by the charge amplifier 31. In Fig. 15, Vr is the reset voltage of the capacitance 14, Vb1 is the bias voltage, Vb2 is the reference voltage, TRAN is the transfer signal, and RS_P is the reset signal of the capacitance 14.

[0058] 16, in the second modified example, the memory unit 51 has one capacitance 52 and one switch 53. In the second modified example, the order in which the voltage signals from the charge amplifier 31 are held in the capacitance 52 is the N level and then the S level, which is the same as the order of AD conversion by the ADC array 60, so that only one pair of the capacitance 52 and the switch 53 is provided. The switch 53 is turned on and off in accordance with a switching signal SET.

[0059] 17 and 18 are timing charts showing the operation of the image sensor 1 of the second modified example. In the second modified example as well, the switch array 40 switches the connection states between the charge amplifiers CA1-CA4 and the capacitances 65 of the A / D converters AD1-AD4 such that the capacitances 65 (storage units) of the A / D converters AD1-AD4, which hold voltage signals corresponding to the charge signals output from the pixel units PD1-PD4, are switched in accordance with the arrangement order of the pixel units PD1-PD4 in the first direction X1.

[0060] In the second modification, as in the above embodiment, it is possible to suppress an increase in the circuit size and reduce the amount of output signals while realizing an efficient TDI operation. In addition, since each pixel unit 11 includes a buried photodiode, it is possible to achieve high sensitivity and low noise.

[0061] The imaging element 1 may be configured as a third modified example shown in Fig. 19 to Fig. 27. In the third modified example, the light receiving element of each pixel section 11 is configured with a surface-type photodiode. As shown in Fig. 19, each circuit unit 5 has a switch array (switch circuit) 40A, an amplifier array 30A, and a memory array 50A.

[0062] 20, the switch array 40A is configured similarly to the switch array 40 of the above embodiment, except that it is connected between the pixel unit 11 and the amplifier array 30A. The switch array 40A is configured so that the connection states between the pixel units PD1 to PD4 and the capacitance units 33 of the charge amplifiers CA1 to CA4 are switched according to the on / off of the switches 42a to 42d.

[0063] As shown in Fig. 21, the amplifier array 30A is connected between the switch units SU1 to SU4 and the memory units MR1 ​​to MR4. Separate reset signals RS_A1, RS_AC2, RS_A3, and RS_A4 are input to the reset switches 34 of the charge amplifiers CA1, CA2, CA3, and CA4. This makes it possible to independently reset the capacitive sections 33 of the charge amplifiers CA1 to CA. Except for these points, the amplifier array 30A is configured similarly to the amplifier array 30 of the above embodiment.

[0064] As shown in FIG. 22, voltage signals from charge amplifiers CA1 to CA4 are input to the memory array 50A. Output signals from memory units MR1 ​​to MR4 are read out using, for example, a differential amplifier. In memory unit MR1, switches 53N and 53S are turned on and off according to switching signals SETN1 and SETS1, and switches 54N and 54S are turned on and off according to a read signal D1. In memory unit MR2, switches 53N and 53S are turned on and off according to switching signals SETN2 and SETS2, and switches 54N and 54S are turned on and off according to a read signal D2. In memory unit MR3, switches 53N and 53S are turned on and off according to switching signals SETN3 and SETS3, and switches 54N and 54S are turned on and off according to a read signal D3. In memory unit MR4, switches 53N and 53S are turned on and off according to switching signals SETN4 and SETS4, and switches 54N and 54S are turned on and off according to a read signal D4. The memory array 50A does not have a reset switch 55, and is reset when the differential amplifier is reset as described above. Except for these points, the memory array 50A is configured similarly to the memory array 50 of the above embodiment.

[0065] In the third modification, the M circuit units 5 are also arranged adjacent to the corresponding pixel arrays 12 in the first direction X1, and each circuit unit 5 has N arrangement regions R aligned in the second direction X2. Each circuit unit 5 may have T arrangement regions R (T is an integer equal to or greater than N). In the third modification, one charge amplifier 31 and one memory unit 51 are arranged in each arrangement region R. The width of each arrangement region R in the second direction X2 is 1 / N or less of the width of the pixel section 11 in the second direction X2.

[0066] 23 to 25 are timing charts showing the operation of the image sensor 1 of the third modified example, and Fig. 26 and Fig. 27 are diagrams for explaining the addition process by the TDI operation of the third modified example. In the third modified example, the capacitance units 33 of the charge amplifiers CA1 to CA4 in which the charge signals output from the pixel units PD1 to PD4 are accumulated are switched according to the arrangement order of the pixel units PD1 to PD4 in the first direction X1.

[0067] That is, by operating each unit as shown in FIG. 23 and FIG. 24, during the period between times T1 and T2, the charge signals output from the pixel units PD1, PD4, PD3, and PD2 are stored in the capacitance units 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively, as shown in FIG. 25. At time T2, the charge signal stored in the capacitance unit 33 of the charge amplifier CA2 is read out. During the period between times T2 and T3, the charge signals output from the pixel units PD2, PD1, PD4, and PD3 are stored in the capacitance units 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T3, the charge signal stored in the capacitance unit 33 of the charge amplifier CA3 is read out. During the period between times T3 and T4, the charge signals output from the pixel units PD3, PD2, PD1, and PD4 are stored in the capacitance units 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T4, the charge signal stored in the capacitance section 33 of the charge amplifier CA4 is read out. During the period between times T4 and T5, the charge signals output from the pixel sections PD4, PD3, PD2, and PD1 are stored in the capacitance sections 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T5, the charge signal stored in the capacitance section 33 of the charge amplifier CA1 is read out.

[0068] 26 and 27, in the TDI operation of the third modified example, charge signals output from pixel units PD1 to PD4 by detecting light that has passed through the same region of the object OJ are added (accumulated) as analog values ​​in the same charge amplifiers CA1 to CA4. For example, signals based on the detection of light from region a are added in charge amplifier CA1. Then, a charge signal (4a) obtained by adding up signals for four frames is read out from charge amplifier CA1 at time T5.

[0069] The third modification also suppresses an increase in circuit scale and reduces the amount of output signals, while realizing an efficient TDI operation. That is, in the image sensor 1 of the third modification, each of the M circuit units 5 has N charge amplifiers 31 and a switch array 40A (switch circuit). In each circuit unit 5, the connection state between the pixel unit 11 and the charge amplifier 31 is switched so that the capacitance section 33 of the charge amplifier 31 in which the charge signals output from the pixel unit 11 are accumulated (added as charges (analog values)) is switched according to the arrangement order of the N pixel units 11 along the first direction X1, thereby realizing the TDI operation. By realizing the TDI operation by analog addition processing using such a charge amplifier 31, it is possible to suppress an increase in circuit scale compared to, for example, a case in which a memory for simply adding signals digitally is provided in the circuit unit 5. In addition, it is possible to reduce the amount of output signals compared to, for example, a case in which a signal is output to the outside of the image sensor 1 and digital addition processing is performed outside. Furthermore, in the image sensor 1, the charge signals output from the pixel section 11 are accumulated in the capacitance section 33 of the charge amplifier 31, analog-added, and converted into a voltage signal by the charge amplifier 31. This makes it possible to reduce loss in the transfer of the charge signals from the pixel section 11, and to realize an efficient TDI operation. Therefore, the image sensor 1 of the third modification also makes it possible to realize an efficient TDI operation while suppressing an increase in the circuit size and reducing the amount of output signals.

[0070] Furthermore, since the width of each arrangement region R in the second direction X2 is 1 / N or less of the width of the pixel section 11 in the second direction X2, the circuit units 5 can be arranged efficiently, and the increase in the circuit scale can be further suppressed. In the third modification, a memory section having only one memory unit 51 may be provided instead of the memory array 50, and a shift register may be provided instead of the decoder 4. Even in this case, the TDI operation can be realized. However, by reading out the data using the memory array 50 having N memory units 51 as in the third modification, it is possible to change the number of frames to be added.

[0071] As a fourth modification, in the third modification, the light receiving element of each pixel unit 11 may be configured with an embedded photodiode. In the fourth modification, as shown in FIG. 28, each pixel unit 11 has a pixel amplifier 13 in addition to a light receiving element, similar to the second modification. Each pixel unit 11 is connected to a switch unit 41 via a coupling capacitance 18. A switch 19 that is turned on and off according to a reset signal RS_S is provided between the coupling capacitance 18 and the switch unit 41. A charge signal generated in the light receiving element is converted into a voltage signal by a source follower amplifier 17. The voltage signal is converted into a charge signal by passing through the coupling capacitance 18. FIG. 28 shows PD1, PD2, PD3, and PD4 as outputs from the pixel unit 11. The imaging element 1 of the fourth modification operates according to the timing charts shown in FIG. 29 and FIG. 30. According to the fourth modification, as in the third modification, it is possible to suppress an increase in the circuit size and reduce the amount of output signals, while realizing an efficient TDI operation.

[0072] The present invention is not limited to the above-mentioned embodiment and modified examples. For example, the pixel unit 11 may be one that performs photoelectric conversion, and may detect not only visible light but also infrared rays or X-rays. In the above-mentioned embodiment, the A / D converter 61 is not limited to a single slope type. The A / D converter 61 may convert an input voltage signal into a digital value and sequentially add the digital value. In the above-mentioned embodiment, the switch array 40 may be connected between the comparator 62 and the counter 63 of the A / D converter 61. Even in this case, the switch array 40 can switch the connection state between the charge amplifiers CA1 to CA4 and the capacitances 65 of the A / D converters AD1 to AD4.

[0073] In the above embodiment, counting is performed according to signals for four frames and the count value is read out as a digital value, but the number of frames to be added can be changed by changing the timing of reset signals RS_C1 to C4 input to counters 63 of A / D converters AD1 to AD4 and read signals D1 to D4 from the decoder 4. In the third and fourth modifications, as in the first modification, the pixel unit 2, the circuit section 3, and the decoder 4 may be formed on separate chips. [Explanation of symbols]

[0074] 1...imaging element, 2...pixel unit, 5...circuit unit, 11, PD1 to PD4...pixel section, 12...pixel array, 31, CA1 to CA4...charge amplifier, 32...operational amplifier, 32a...inverting input terminal, 32c...output terminal, 33...capacitor section, 40, 40A...switch array (switch circuit), 61, AD1 to AD4...A / D converter, 62...comparator (addition processing section), 63...counter (addition processing section), 65...capacitor (holding section), X1...first direction, X2...second direction.

Claims

1. a pixel unit including M pixel arrays (M is an integer of 2 or more) each including N pixel units (N is an integer of 2 or more) that perform photoelectric conversion, the N pixel units being aligned along a first direction, and the M pixel arrays being aligned along a second direction perpendicular to the first direction; M circuit units provided corresponding to the M pixel arrays, Each of the M circuit units is N charge amplifiers, each of which includes an operational amplifier and a capacitance unit connected between an inverting input terminal and an output terminal of the operational amplifier, converting charge signals output from the N pixel units of the corresponding pixel array into voltage signals; N A / D converters each including an addition processing unit that performs an addition process of the voltage signals output from the N charge amplifiers, and a holding unit that holds an addition signal corresponding to an addition state of the addition processing unit; a switch circuit for switching a connection state between the N charge amplifiers and the holding units of the N A / D converters, an image pickup device, in which, in each of the M circuit units, the switch circuit switches the connection state so that the holding section, in which the sum signal corresponding to the charge signal output from the pixel section is held, switches in accordance with the arrangement order of the N pixel sections along the first direction, and the addition processing section performs addition processing of the voltage signals output in the N charge amplifiers in accordance with the arrangement order of the N pixel sections.

2. 2. The image sensor according to claim 1, wherein each of the N A / D converters is configured as a single-slope type.

3. 3. The image sensor according to claim 1, wherein the switch circuit is connected between the N charge amplifiers and the addition processing section of the A / D converter.

4. The M circuit units are arranged adjacent to the corresponding pixel arrays in the first direction, each of the M circuit units has N placement regions arranged in the second direction, and the charge amplifier and the A / D converter are arranged in each of the N placement regions; 4. The image sensor according to claim 1, wherein a width of each of the N arrangement regions in the second direction is 1 / N or less of a width of the pixel portion in the second direction.

5. a pixel unit including M pixel arrays (M is an integer of 2 or more) each including N pixel units (N is an integer of 2 or more) that perform photoelectric conversion, the N pixel units being aligned along a first direction, and the M pixel arrays being aligned along a second direction perpendicular to the first direction; M circuit units provided corresponding to the M pixel arrays, Each of the M circuit units is N charge amplifiers each including an operational amplifier and a capacitance unit connected between an inverting input terminal and an output terminal of the operational amplifier and accumulating a charge signal output from the N pixel units of the corresponding pixel array, the charge amplifiers converting the charge signal into a voltage signal; a switch circuit for switching a connection state between the N pixel units and the capacitance units of the N charge amplifiers, an image sensor in which, in each of the M circuit units, the switch circuit switches the connection state so that the capacitive portion in which the charge signals output from the pixel portions are accumulated switches in accordance with the arrangement order of the N pixel portions along the first direction, and the charge signals output from the N pixel portions in accordance with the arrangement order of the N pixel portions are sequentially accumulated in the capacitive portion of one charge amplifier among the N charge amplifiers.

6. The M circuit units are arranged adjacent to the corresponding pixel arrays in the first direction, Each of the M circuit units has N placement regions arranged in the second direction, and the charge amplifier is placed in each of the N placement regions; The image sensor according to claim 5 , wherein a width of each of the N arrangement regions in the second direction is equal to or smaller than 1 / N of a width of the pixel unit in the second direction.

7. 7. The image sensor according to claim 1, wherein each of the N pixel portions includes a surface-type photodiode.

8. 7. The image sensor according to claim 1, wherein each of the N pixel portions includes an embedded photodiode.

9. 9. The imaging device according to claim 1, wherein N is an integer of 8 or more.

Images