High Resolution Monolithic RGB Array

Abstract

1. A light-emitting diode structure comprising: a p-type region; an n-type region; a light-emitting region for recombination of carriers injectable by the p-type region and the n-type region; and a via extending through the light-emitting region, the via defining a periphery of a light-emitting surface of at least one pixel and comprising a material configured to allow injection of carriers into the p-type region or the n-type region, wherein one of the p-type region and the n-type region is configured such that carriers generated in one of the p-type region and the n-type region diffuse through the other of the n-type region and the p-type region before recombining in the light-emitting region.

Description

[Technical field]

[0001] Light Emitting Diode Structures and Methods of Forming Light Emitting Diode Structures FIELD OF THEINVENTION The present invention relates to light emitting diode structures and methods of forming light emitting diode structures. In particular, but not exclusively, the present invention relates to high resolution monolithic arrays of light emitting diode structures. [Background technology]

[0002] Conventional red-green-blue (RGB) micro light-emitting diode (μLED) arrays of light-emitting pixels are typically realized using pick-and-place techniques or through the use of color conversion materials that are deposited or incorporated into standard planar light-emitting diode (LED) structures. However, as the pixel pitch in such arrays is reduced to very small pitches (e.g., less than 5 μm) to provide higher resolution arrays, many challenges arise.

[0003] For example, the use of pick-and-place may be impractical due to the high cost, low throughput and limited positional accuracy in transferring μLEDs. In the case of color conversion, the use of such techniques is limited by the phosphor size used for color conversion, which is typically larger than 10 μm (i.e., larger than the pixel pitch in arrays with the very small pitch required for higher resolution). Furthermore, color conversion techniques may be subject to poor reliability and inefficiency due to the small absorption coefficients associated with quantum dots (QDs). For example, a thickness of the color conversion QD material greater than 10 μm is required to sufficiently absorb the blue emission that excites the color conversion QD material, thus making the color conversion QD material unsuitable for very small pixel pitch arrays.

[0004] To avoid the need to transfer LEDs and provide high quality and efficient emission, it would be beneficial to provide a unique array of LEDs on the same substrate. One approach to construct a unique array of LEDs on the same substrate relies on selective area growth of nanowires, which are arrays of individual structures grown approximately perpendicular to a patterned growth substrate to form light-emitting structures (the light-emitting surface is defined by the cross-sectional area of ​​the nanowires by using a typical epitaxial quantum well structure grown between an epitaxial n-type doped layer and an epitaxial p-type doped layer). However, such nanowire growth is usually difficult to control and may be subject to severe limitations in the achievable light efficiency and color gamut, for example due to poor light extraction efficiency and impurity incorporation. Summary of the Invention [Means for solving the problem]

[0005] In order to alleviate at least some of the above-mentioned problems, there is provided a light emitting diode structure according to the appended claims. Further, there is provided an array of light emitting diode structures and a method of forming one or more light emitting diode structures according to the appended claims.

[0006] In one example, a light emitting diode structure is provided that includes a p-type region; an n-type region; a light emitting region for recombination of carriers injectable by the p-type region and the n-type region; and a via through the light emitting region, where the via defines a periphery of a light emitting surface of at least one pixel and includes a material configured to enable injection of carriers into the p-type region or the n-type region, one of the p-type region and the n-type region configured such that carriers generated in one of the p-type region and the n-type region diffuse through the other of the n-type region and the p-type region before recombining in the light emitting region. Advantageously, the via used to isolate the pixel is also used to enable carrier injection into the light emitting region.

[0007] Preferably, the light emitting region comprises at least one epitaxial quantum well layer. Advantageously, the epitaxial quantum well layer is grown with high crystalline quality, leading to efficient light emission.

[0008] Preferably, the p-type and n-type regions are on the same side of the light emitting region. Advantageously, carriers can diffuse into the light emitting region against the electric field of a forward biased junction, which means that no electron blocking layer is required. Furthermore, the p-type and n-type doped regions can be thin layers, and if on the same side, only a very shallow etch can be used to provide electrical isolation, thereby limiting etch damage caused by electrically isolating individual devices.

[0009] Preferably the material comprises an n-type region or at least a portion of p-type.Advantageously, the very vias used to allow carrier injection are also used to isolate the pixels.

[0010] Preferably, the material comprises a conductive material, and preferably the conductive material is a metal. Advantageously, the metal allows electrical connection to one of the p-type or n-type regions, thereby isolating the individual LED devices / pixels while allowing carrier injection. Furthermore, the metal can be highly reflective, thereby providing good optical isolation. Furthermore, deposition of the metal in the vias eliminates any need to align the metal to provide contact to one of the p-type or n-type regions, since the metal is self-aligned when deposited.

[0011] Preferably, the light emitting diode structure comprises further light emitting regions. Advantageously, the light emitting regions may be activated simultaneously or individually and may be configured to have the same or different primary peak wavelengths.

[0012] Preferably, the light emitting region and the further light emitting region are separated by a non-doped region, thereby providing a stack of light emitting regions. Advantageously, carrier injection into the various light emitting regions is realized by forming a connection through the light emitting region. Advantageously, without a p-type doping layer, there is no problem with p-type dopant diffusion, and the multiple quantum wells (MQWs) of the light emitting regions can be closer to each other without the need for tunnel junctions. Furthermore, no electron blocking layer is required in the structure.

[0013] Preferably, the via passes through both the light emitting region and the further light emitting region. Advantageously, a common connection is provided for the light emitting region, resulting in easier processing of the initial epitaxial structure.

[0014] Preferably, the light emitting region and the further light emitting region are configured to emit light of different wavelengths. Advantageously, light of different primary peak wavelengths can be emitted by the structure, which can be implemented in a multi-colour array.

[0015] Preferably, the light emitting region and the further light emitting region are arranged such that the surface areas of the light emitting region and the further light emitting region overlap. Advantageously, in plan view, there are various regions arranged to provide several light emitting surfaces based on the various light emitting regions (and which can thus be configured to provide various light emissions, e.g. of different intensity, timing or colour).

[0016] Preferably, the light emitting diode structure includes at least three light emitting regions, one of the light emitting regions emitting blue light, one of the light emitting regions emitting green light, and one of the light emitting regions emitting red light. Advantageously, the use of three light emitting regions provides increased flexibility, including the ability to provide red-green-blue (RGB) light at high resolution for color displays.

[0017] Preferably, the vias are lattice vias that define an array containing a plurality of pixels. Advantageously, the connections can be made in one processing step. Furthermore, the use of lattice vias to define the pixels means that no electrical isolation etch between pixels is required, allowing for denser pixel integration.

[0018] Preferably the grid vias are arranged to provide a common electrode which can be advantageously used to selectively control emission from individual pixels within a high resolution array of pixels.

[0019] Preferably, at least one pixel of the plurality of pixels comprises a further electrode. Preferably, the further electrode is centrally located within the periphery of the light-emitting surface of the at least one pixel. Advantageously, isolation of the pixels is achieved simultaneously with individual control of the light emission.

[0020] Preferably, at least two pixels are arranged to emit light of different wavelengths Advantageously, multiple colour outputs can be provided from a monolithic array.

[0021] Preferably, the light-emitting region and / or the further light-emitting region are formed on an undoped epitaxial layer. Advantageously, the undoped epitaxial layer allows electrical isolation of the pixel.

[0022] Preferably, the light emitting region and / or further light emitting region are formed between undoped epitaxial layers. Advantageously, the undoped epitaxial layers allow not only electrical isolation of the pixels by etching through the light emitting region and / or further light emitting region formed between the undoped epitaxial layers, but also processing of the epitaxial structure for individual pixel connections.

[0023] Preferably, the undoped epitaxial layer is formed on a barrier layer configured to block vertical carrier diffusion. Advantageously, the light emitting structure may be formed on a doped material that may form part of the substrate and / or preferred growth technique while allowing for isolation of the light emitting region such that one of the n-type and p-type regions is formed through the light emitting region.

[0024] Preferably, the light emitting diode structure is a gallium nitride (GaN) based structure. Gallium nitride is known for its properties in providing efficient light emitting diode devices with a range of primary peak wavelengths. The growth of gallium nitride structures is well developed and the growth and processing of such materials is controllable to provide high quality devices. Thus, preferably, the undoped epitaxial layer is gallium nitride.

[0025] Preferably, the barrier layer is AIGaN. Advantageously, the barrier provides a stable surface for subsequent processing steps. Additionally, the barrier layer provides an etch stop for pixel isolation by etching vias through the light emitting region.

[0026] Preferably, at least one of the n-type and p-type regions is formed in a via that is connected to a planar n-type or p-type region, respectively. Advantageously, the use of a planar region can be advantageous to provide light emission due to carrier diffusion and to reduce etch damage and loss of the active region (the region where the central via etch would otherwise be used for lateral injection of carriers into the light emitting region).

[0027] Preferably, at least one of the n-type and p-type regions is formed by selective area growth. Advantageously, selective area growth at least partially repairs etch damage. Moreover, passivation is achieved because there are no open surfaces cutting through the multi-quantum wells. is not necessary.

[0028] Preferably, the vias are etched vias. Techniques for anisotropic etching are known and allow larger scale epitaxial structures to be grown and then processed to provide light emitting diode structures with pixel peripheries defined by etched vias. This means that known techniques for growing high quality and efficient epitaxial structures can be used, as opposed to smaller scale techniques such as patterned nanowire growth.

[0029] Preferably, the light emitting surface has an area based on the diffusion length of the carriers in the light emitting region. Advantageously, the light emitting surface shape and / or size can be optimized based on the diffusion carrier length, which helps to provide uniform light emission in the micro LED.

[0030] Preferably, the light emitting surface area is 100 μm2 or less, more preferably 16 μm2 or less. Advantageously, pixel definition using vias containing n-type or p-type material allows for the formation of micro LEDs with light emitting surfaces that provide high resolution for the pixels.

[0031] Advantageously, the definition of pixels using vias allows for the formation of microLEDs with high resolution that can be formed into arrays that are suitable for connection to a backplane and thus integration into high resolution displays or other high resolution arrays, which can be monochrome or multicolor arrays.

[0032] Preferably, at least one pixel is defined in its periphery entirely by a single electrode.

[0033] Preferably, a high resolution micro LED array is provided that includes a light emitting diode structure.

[0034] Preferably the array is a multi-colour array and preferably the array has a pixel pitch of less than 10 microns, more preferably less than 4 microns.

[0035] Preferably, the micro LED light emitting diode structures and / or arrays are provided by forming multiple epitaxial layers on a substrate. Advantageously, forming multiple epitaxial layers on a substrate means that high quality structures can be provided in successive growths, thereby reducing growth times and impurities during growth.

[0036] Preferably, the plurality of epitaxial layers includes an n-type region and a light emitting region. Advantageously, such plurality of epitaxial layers includes layers of a conventional LED structure. Beneficially, the conventional LED structure (which may be terminated after p-cladding) may be used as a base for subsequent processing of a monolithic micro LED array.

[0037] Preferably, the multiple epitaxial layers are etched such that the etching penetrates the light emitting area to provide vias that define the pixel periphery. Techniques for anisotropic etching are known and allow larger scale epitaxial structures to be grown and then processed to provide light emitting diode structures with pixel peripheries defined by etched vias. This means that known techniques for growing high quality and efficient epitaxial structures can be used, as opposed to smaller scale techniques such as patterned nanowire growth.

[0038] Preferably, the conductive material is deposited or grown in the etched vias. Advantageously, the very material used to inject carriers into the light emitting region is at least one It is also used to define the periphery of the pixel's emissive surface, insulating the pixel while still providing a source of carriers to allow efficient recombination and emission across the entire emissive surface of the pixel.

[0039] Preferably, forming the further light emitting region comprises at least partially etching through at least one light emitting region to locally remove the undesired longest wavelength. Advantageously, high quality epitaxial material is provided by a shallow etch that allows exposure of a light emitting surface formed by a pn junction on one side of the exposed light emitting surface, thereby providing penetration into the locally exposed light emitting region.

[0040] Preferably, forming the further light emitting region includes at least partially etching through at least one light emitting region to locally remove the undesired longest wavelength before forming each of the n-type and p-type regions associated with the light emitting region and the further light emitting region, respectively. Advantageously, at least one of the n-type and p-type regions is deposited / grown in a single step near the exposed light emitting region or regions. Furthermore, selective area overgrowth to provide the other of the n-type and p-type regions is performed in a single step for each exposed light emitting region, thereby reducing the required processing steps.

[0041] Preferably, the micro LED light emitting diode structures and / or arrays are provided by forming multiple epitaxial layers on a substrate. Advantageously, forming multiple epitaxial layers on a substrate means that high quality structures can be provided in successive growths, thereby reducing growth times and impurities during growth.

[0042] Preferably, the plurality of epitaxial layers includes an n-type region and a light emitting region. Advantageously, such plurality of epitaxial layers includes layers of a conventional LED structure. Beneficially, the conventional LED structure can be used as a basis for subsequent processing of a monolithic micro LED array.

[0043] Further aspects of the present invention will become apparent from the specification and the accompanying claims.

[0044] A detailed description of embodiments of the present invention will now be given, by way of example only, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0045] [Figure 1A] A cross-sectional view of the epitaxial structure is shown. [Figure 1B] A cross-sectional view of the processed epitaxial structure is shown. [Figure 1C] A cross-sectional view of the processed epitaxial structure is shown. [Figure 1D] A cross-sectional view of the processed epitaxial structure is shown. [Figure 1E] A cross-sectional view of the processed epitaxial structure is shown. [Figure 1F] A cross-sectional view of the processed epitaxial structure is shown. [Figure 1G] A cross-sectional view of the processed epitaxial structure is shown. [Diagram 2] FIG. 1D shows a top view of the processed epitaxial structure of FIG. [Diagram 3] FIG. 1C shows a top view of the processed epitaxial structure of FIG. 1F. [Figure 4] A cross-sectional view of the processed epitaxial structure is shown. [Diagram 5] A cross-sectional view of the processed epitaxial structure is shown. [Figure 6] A cross-sectional view of the processed epitaxial structure is shown. [Figure 7] 1 shows a cross-sectional view of an epitaxial structure having three different light emitting regions. [Figure 8A] 8 shows a cross-sectional view of the processed epitaxial structure of FIG. 7. [Figure 8B] 8B shows a top view of the processed epitaxial structure of FIG. 8A. [Figure 9A] 8B shows a cross-sectional view of the further processed epitaxial structure of FIG. 8A. [Figure 9B] 8B shows a top view of the further processed epitaxial structure of FIG. 8A. [Figure 10A] 1 shows a light emitting structure having three different light emitting regions. [Figure 10B] 10B shows a plan view of the light-emitting structure of FIG. 10A. [Figure 11] The treated light emitting structure is shown in FIG. 10A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Light emitting diodes (LEDs) are typically formed by processing light emitting structures grown by the formation of epitaxial crystal layers on larger wafer substrates in reactors such as MOCVD (metal organic chemical vapor deposition) reactors, MBE (molecular beam epitaxy) reactors or other chemical vapor deposition reactors. For the reasons mentioned above, known methods for producing arrays of high resolution micro LEDs face difficulties in processing LEDs made by crystals grown on larger wafer substrates to provide high resolution arrays of micro LEDs. The use of nanowire LED arrays to overcome these processing problems leads to difficulties in controlling the growth process as well as generally poorer performance than that seen from conventional larger wafer substrate growth of LEDs.

[0047] The present disclosure describes microLEDs formed as part of a monolithic high-resolution array by advantageously processing light-emitting structures that can be grown on relatively large wafer substrates. Beneficially, native color pixels can be formed that are smaller, more efficient, and more resistant to degradation compared to color-converted pixels. Compared to pick-and-place assembly, processing of epitaxial structures grown directly on a wafer means that there is no requirement to transfer millions of pixels (and the associated failures in the transfer process), and therefore high throughput by forming arrays of pixels on a wafer. Compared to nanowires, processing of standard planar epitaxial deposition layer growth means that multiple quantum wells (MQWs) are formed in a manner that provides high quality growth and thus relatively high internal quantum efficiency (IQE). Furthermore, processing of epitaxial structures provides planar devices that are useful for light extraction by using standard surface patterning techniques.

[0048] Further advantages arising from the described methods and structures will become apparent in the following description. A method for providing array micro-LEDs is described below with reference to various process steps (which may include steps performed both inside and outside the growth reactor by using other processing and / or growth equipment). The methods and structures are described with reference to III-V semiconductor materials. In particular, the methods and structures are described with reference to nitride structures, including well-known gallium nitride (GaN)-based light emitting structures, to provide relatively high efficiency light emitting structures. However, in further examples, the methods and structures are applicable to light emitting structures based on other materials, particularly based on other semiconductor materials.

[0049] In the following figures, like reference numerals are used to denote aspects of structure relating to the same features or equivalent features provided by the same or similar processes.

[0050] 1A shows structure 100A, which is an epitaxial structure 100A that forms the basis of a monochrome micro LED pixel array. Such a monochrome micro LED pixel array has a plurality of individual pixels, where each pixel may be individually addressable based on how such a monochrome micro LED pixel array is connected to a power source (e.g., depending on the placement of a backplane relative to the micro LED pixel array).

[0051] Structure 100A is a GaN-based epitaxial multiple quantum well (MQW) structure (effectively an LED structure) grown by metalorganic chemical vapor deposition (MOCVD). Beneficially, known techniques can be used to provide high quality materials that can be processed to provide monolithic high resolution micro-LED arrays.

[0052] 1A shows an n-doped (n-GaN) n-type buffer region 102 on which is grown a 10% aluminum-containing AIGaN barrier layer 104. The n-type buffer region 102 is typically formed on a substrate (not shown). The AIGaN barrier layer 104 prevents vertical carrier diffusion from the n-type buffer region 102.

[0053] An undoped region 106 (GaN that is not intentionally doped) is grown on the barrier layer 104, and a GaN-based superlattice structure 108 is grown on the undoped region 106. Above the superlattice structure 108 is a light emitting region 110 having multiple quantum wells (MQWs). The n-type buffer region 102, barrier layer 104, undoped region 106, superlattice 108, and light emitting region 110 are shown in cross section as multiple epitaxial layers grown on a substrate (the substrate is not shown insofar as it is not the n-type buffer region 102 itself).

[0054] An undoped region 106 (GaN that is not intentionally doped) is grown on the barrier layer 104, and a GaN-based superlattice structure 108 is grown on the undoped region 106. Above the superlattice structure 108 is a light emitting region 110 having multiple quantum wells (MQWs). The n-type region buffer 102, barrier layer 104, undoped region 106, superlattice 108, and light emitting region 110 are shown in cross section as multiple epitaxial layers grown on a substrate (not shown).

[0055] Light emitting region 110 comprises an MQW. Additionally or alternatively, light emitting region 110 may comprise a single quantum well (SQW). Additionally or alternatively, light emitting region 110 may include one or more quantum dots. The quantum wells and quantum dots confine carriers and, in use, provide a light source based on carrier injection by n-type and p-type regions followed by emissive carrier recombination within the quantum structure when connected, for example, to a cathode and an anode, respectively.

[0056] P-type region 112, which is a p-type doped GaN layer, is shown above light emitting region 110. P-type region 112 provides a p-type region for carrier injection into light emitting region 110.

[0057] Although p-type region 112 is shown to be a p-type GaN layer, additionally or alternatively, p-type region 112 may be formed from a different material.

[0058] Light emitting region 110 includes an MQW, although in a further example, light emitting region 110 may have a single quantum well (SQW). Additionally or alternatively, light emitting region 110 may include one or more quantum dots. The quantum wells and quantum dots confine carriers and, in use, when connected to a cathode and an anode, respectively, provide a light source based on carrier recombination in the quantum structure following carrier injection by the n-type and p-type regions.

[0059] The n-type region is typically formed on a substrate, but alternatively the n-type region itself may be a free-standing substrate suitable for subsequent growth of crystalline layers. In one example, the substrate is a sapphire substrate. In a further example, the substrate is a silicon substrate or a GaN substrate.

[0060] The epitaxial structure 100A is grown by using an MOCVD reactor. Advantageously, such epitaxial structure 100A is optimized for MOCVD growth and may provide high quality growth for efficient generation of light. Additionally or alternatively, other deposition and / or growth methods, such as MBE, may be used to provide the epitaxial structure 100A.

[0061] The n-type buffer region 102 is formed from n-type gallium nitride. However, in further examples, the n-type buffer region 102 may be formed from and / or based on other materials. The barrier layer 104 is formed from aluminum gallium nitride (e.g., 10% aluminum AIGaN). Advantageously, the use of an AIGaN barrier reduces the electron barrier between pixels in a multi-pixel structure. This helps prevent leakage. However, in further examples, additionally or alternatively, barrier layer 104 may not be used or may be formed from a different material. Superlattice 108 is formed from a gallium nitride based material. Additionally or alternatively, superlattice 108 is formed from other materials. Light emitting region 110 includes at least one quantum well. Additionally or alternatively, light emitting region 110 includes additional quantum wells. Additionally or alternatively, light emitting region 110 includes quantum dots or other quantum structures. Light emitting region 110 is a gallium nitride based region, whereby at least the quantum wells are formed from a gallium nitride based material, such as indium gallium nitride (InGaN) or aluminum indium gallium nitride (AIInGaN). Additionally or alternatively, different materials are used depending on the structure being grown. The composition of the quantum wells in light emitting region 110 is determined based on the primary peak wavelength selected for emission from light emitting region 110. p-type region 112 is formed from gallium nitride. Additionally or alternatively, different materials may be used to form p-type region 112. Light emitting region 110 does not include any doping, such as silicon doping or magnesium doping via intentional doping of light emitting region 110 during growth of structure 100A. In a further example, doping is used in light emitting region 110 as long as it does not affect carrier injection to emit light through a pixel light emitting surface defined by a via through light emitting region 110. In a further example, various semiconductor layers are grown or otherwise formed to provide the necessary substructure for processing a monolithic array of micro-LEDs.

[0062] 1A, those skilled in the art will appreciate that additional layers, elimination of some layers, and substitution of layers may be used to realize the concepts described herein, depending on the particular needs of a particular implementation. The description of a layer formed on another layer indicates a positional relationship with respect to the order of growth of the layers, but does not necessarily preclude the presence of a layer between a first layer and a second layer that is described as being on top of the first layer.

[0063] Once the epitaxial structure 100A is provided, it may be processed to provide conductive regions into which carriers may be implanted into the final structure.

[0064] Thus, FIG. 1B shows a processed epitaxial structure 100B. The epitaxial structure 100A of FIG. 1A is shown with an additional mask layer 114. The mask layer 114 is formed and processed by using known techniques, including lithographic techniques, to selectively create openings and selectively expose some portions of the underlying epitaxial structure 100B (e.g., p-type region 112). Once some portions of the mask layer 114 are selectively removed, selective etching of the underlying epitaxial structure 100B is performed. Such selective etching provides vias in the epitaxial structure 100B. The vias are created by the removal of material to leave paths through the remaining material. Depending on the shape of the areas exposed in the mask layer 114 and the depth of the etch, the vias formed will have a corresponding type, which in one example is in the form of a trench via or a columnar via. Vias may be created by etching material to leave a trench, hole, or other pathway, although in further examples, vias may additionally or alternatively be created by shaping material such that the absence of material creates a via structure within another structure, as opposed to removing material. Advantageously, the via 115 is etched down to the AIGaN barrier layer 104, thereby providing improved isolation of the pixel. Advantageously, the AIGaN barrier layer 104 provides an etch stop for the etching of the via 115.

[0065] In one example, the mask layer 114 is silicon nitride. Additionally or alternatively, various materials such as silicon dioxide may be used. Advantageously, silicon nitride is an effective and controllable mask layer 114 for subsequent processing steps.

[0066] FIG. 1C shows a further processed epitaxial structure 100D having vias 115 etched through the epitaxial structure 100. The vias 115 are shown as etched through the epitaxial structure 100B into the undoped region 106 at a depth 201 from the surface of the epitaxial structure 100C. To etch the vias 115, lithographic techniques are used to pattern a mask layer and open openings in the mask layer to allow etching of the material exposed by the openings formed in the mask. The vias 115 are shown in cross section. In plan view, the vias 115 are formed in a grid structure (see, for example, the grid in FIG. 2) to define pixels, where the vias define the periphery of the light-emitting surface of each individual pixel 208 by penetrating the light-emitting region 110 to form trench vias 115 that isolate each individual pixel. The width 210 of the pixel 208 is the distance between the vias 115 shown in FIG. 1C. Although the via 115 is shown as being etched into the undoped region 106, in further examples, alternatively or additionally, the via 115 is etched to a shallower or deeper depth 201 than that shown in FIG. 1C while still penetrating the light-emitting region 110, thereby defining the periphery of the pixel.

[0067] Although the vias 115 which penetrate the light emitting region 110 of the epitaxial structure to form grooves defining the light emitting surface of the pixels 208 are shown based on etching the epitaxial structure, in further examples other techniques are used to form a light emitting region having vias which penetrate the light emitting region to define the periphery of the light emitting surface of the pixels in an array of pixels.

[0068] In one example, the vias 115 are formed by using a dry etching technique, such as a plasma-based technique. Preferably, a wet etch process is used to repair any damage caused by etching the vias 115. Additionally or alternatively, any suitable etching technique may be used to form the vias 115.

[0069] Once via 115 is formed in epitaxial structure 100C, a selective overgrowth of n-type material is formed. Figure 1D shows structure 100C of Figure 1C further processed to provide light emitting structure 100D. Via 115 is shown penetrating light emitting region 110 down to undoped region 106. Also shown is a further mask layer on mask layer 114 of Figure 1C (shown as mask layer 117 over p-type region 112 and in addition to mask layer 114). Further mask layer 117 and mask layer 114 are selectively patterned and processed to create openings 111 to expose the underlying structure through mask layers 114, 117 down to p-type region 112 using known lithography and etching techniques.

[0070] The exposed opening 111 in the mask layer 114 and the further mask layer 117 is formed centrally within the pixel periphery defined by the via 115 formed through the light emitting region 110. Additionally or alternatively, the opening 111 is in any suitable location to provide light emission. The cross-sectional shape of the opening in plan view is determined by the patterning and etching processes used to provide the opening. The opening 111 has a width of about 800 nm. In a further example, the opening 111 has a width 206 dimensioned to meet a preferred implementation for carrier injection and pixel placement. Once the opening 111 is provided, a selective area overgrowth of n-type material is provided to form an n-type region 116 for carrier injection into the light emitting region 110. The light emitting structure 100D of FIG. 1D is processed to provide the light emitting structure 100E of FIG. 1E, where the n-type region 116 is shown within the opening 111, such that the n-type region 116 is grown over the p-type region 112. Further mask layer 117 is shown removed in Figure IE. An electrical contact is made with p-type region 112 to allow carriers to be injected into light emitting region 110. This is shown in Figure IF.

[0071] FIG. 1F shows the same basic structures 100A, 100B, 100C, 100D, 100E as shown in FIGS. 1A, 1B, 1C, 1D, 1E, however, the structure 100F in FIG. 1F has been further processed. The processed epitaxial structure 100F of FIG. 1F shows deposition mask layer 114, which in one example is a silicon nitride layer, etched to provide via 115 as shown in FIGS. 1A-1E. Via 115 was etched vertically through epitaxial structure 100F down to undoped region 106. Conductive material 120 is then formed within via 115 to provide conductive regions through light emitting region 110. Such conductive material is metal and is provided by known deposition techniques combined with known lithography techniques. In one example, the conductive material is a highly reflective metal that beneficially provides a common electrode and good optical isolation within the pixel. While the metal is shown as deposited after selective area growth of n-type region 116, in further examples, alternatively or additionally, the material is deposited within the via prior to selective area overgrowth of the n-type region. In one example, the metal is deposited within the via after via 115 is etched, thus utilizing mask layer 114 to provide an opening for deposition of metal within via 115. Once epitaxial structure 100F is provided, epitaxial structure 100F is processed to form a light emitting diode device. Such overgrowth or deposition of material within via 115 may be accomplished, for example, with mask layer 114 remaining in place to prevent any growth from occurring on p-type region 112.

[0072] The n-type region 116 is shown beyond the surface of the mask layer 114. Advantageously, this allows for contact of the doped overgrowth. Although the structure 100F is not shown to scale, in one example, the structure formed on the n-type buffer region 102 may be approximately 300 nm thick 202, and the n-type region 116 extends an additional 700 nm in height 204 beyond the thickness 202 of the epitaxial structure 200. In one example, the via 115 may be approximately 800 nm wide 206. In a further example, the size of the structure is determined, for example, by the technique used and the structure desired. For example, the crystal habit of the material used may determine the growth shape of the material beyond the surface of any mask layer. By etching the openings exposed in the mask layer 114, a grating may be formed by depositing material 120 into the via 115 as shown in FIG. 2.

[0073] As indicated by the arrows, in FIG. 1F, n-type region 116 provides an effective cathode, and material 120 formed in via 115 provides an effective anode, thereby allowing injection of carriers into light-emitting region 110 when a suitable power source is used. Carriers from n-type region 116 diffuse through p-type region 112 before carriers from n-type region 116 and p-type region 112 recombine in light-emitting region 110. Advantageously, carrier injection of electrons and holes is accomplished from the same side of light-emitting region 110, thereby providing a straight-line "top" injection into the quantum wells. Carrier injection into light-emitting region 110 may be based on the carrier diffusion length of carriers injected into the multiple quantum well structure of light-emitting region 110 to provide light that may be emitted through a light-emitting surface defined by a pixel periphery formed by material 120 in via 115 etched through light-emitting region 110. A top view 300 of light-emitting structure 100F is shown in FIG. 3.

[0074] 3 shows material 120 formed in vias 115 providing a lattice via etched through the structure 100A described with respect to FIG. 1A. Also shown in the vias is an n-type region 116 formed in an opening 111 in a pixel 208 defined by material 120 in the via 115 of a common electrode provided by material 120. In one example, the opening 111 and n-type region 116 are formed centrally in each of the pixels 208 to be addressed, thereby providing a central opening 111. The n-type region 116 is shown in a central location in each of the pixels 208. Such an arrangement of p-type regions 112 that may form an independently addressable anode electrode and a common anode electrode that allows carrier injection into the individual columnar n-type regions 116 may be used to activate individual pixels 208 in a monochrome high resolution micro LED array.

[0075] FIG. 1G shows a cross-sectional view of the processed light-emitting structure described with respect to FIGS. 1A-1F. The processed light-emitting diode device structure 100G is provided by inverting the light-emitting structure of FIG. 1F to extract light through the n-type buffer region 102 and thus avoid absorption due to the p-type contact 124 (the arrows in FIG. 1G indicate the direction of light from the light-emitting surface of the pixel 208 defined by the via 115 that penetrates the light-emitting region 110). Also shown is an anode connection that forms an n-type contact 125 that connects to material formed in the via 115. The anode connection 125 forms a common electrode that follows a grid pattern such as that shown in FIGS. 2 and 3.

[0076] FIG. 1G further shows an insulating layer 122. The insulating layer 122 insulates any connections used to contact the p-type and n-type regions. Preferably, the insulating layer is silicon dioxide. A p-type contact 124 is shown to which the cathode of each pixel 208 to be addressed is connected. In addition, a mirror / barrier layer 126 is shown configured to reflect light emitted from the light-emitting region 110 out of the light-emitting surface defined by the n-type region 116 in the via 115 that defines the periphery of the pixel 208. The structure can be planarized so that the insulating layer 122, planarized so that each pixel 208 can be individually addressed, provides a surface to which the backplane may connect contacts 124, 125 in other pixels 208 and other contacts 124, 125. Advantageously, the contacts 124 can be connected to a backplane such that the contacts 124 of each pixel in the array are contacted and independently addressable.

[0077] A transparent conductive film 128, preferably indium tin oxide (ITO), is shown formed on the n-type buffer region 102 to provide electrical conductivity and efficient light extraction from the pixels 208 of the micro-LED light emitting array.

[0078] Advantageously, no electrical isolation etch is required between pixels since the metal formed in via 115 provides the common electrode. N-type region 116 is electrically isolated by design without the need for an etch. This allows for denser pixel integration while retaining good optical isolation.

[0079] Although a single pixel cross section (having width 210) is shown in Figures 2 and 3, it will be appreciated that the selective etching of the epitaxial structure 100 described with reference to Figures 1A-1G and the formation of the conductive material 120 in the trench vias provided by the selective etching will result in an electrode grid that is effectively a common electrode (in this case, an anode) for all pixels of the pixels defined by the conductive material 120 that penetrate the light emitting region 110 of the epitaxial structure 100. Advantageously, the selective area growth of the n-type material is performed by using a metal organic chemical vapor deposition (MOCVD) reactor using a relatively high temperature. Such a relatively high temperature anneals defects and passivates any open MQW surfaces. No dangling bonds within the MQW periphery are left after processing, and therefore no passivation is required. Advantageously, therefore, a further reduced non-radiative recombination is realized within the light emitting region 110. In one example, the common electrode defines at least one pixel at the periphery entirely by a single electrode, thereby isolating the pixel.

[0080] FIG. 3 shows a plan view 300 of the corresponding structure 100F shown in FIG. IF. The plan view 300 shows more pixels 208 than shown in FIG. IF. Those skilled in the art will appreciate that the number of pixels 208 that can be formed by the methods described herein is not limited to the number of pixels 208 shown in FIG. 3, and that FIG. 3 shows an example portion of a plan view 300 of a via 115 etched through an epitaxial structure having a material 120 that is conductive within the via 115. A lattice structure is used to form a common electrode, such as a common anode, by using the conductive material 120. The lattice may be used to define the pixels 208 (one of the pixels may be a common anode). 3, where the emissive surface of each pixel 208 is shown as an area in a plan view 300 of square pixels 208 defined by selectively etched vias 115 formed in a lattice matrix with conductive material 120 within the vias 115. The vias may be created by etching a material to leave a trench, hole, or other pathway, although in further examples, the vias may additionally or alternatively be created by shaping a material such that the absence of material creates a via structure within another structure, as opposed to the removal of material.

[0081] In one example, the width 210 of the pixel 208 is about 3 μm. The width 210 of the pixel 208 is preferably selected based on the carrier diffusion distance used to enable efficient light emission from the light emitting surface of the pixel 208. Advantageously, the electrodes formed by the conductive material 120 extend around the periphery of each pixel 208 and penetrate the light emitting region 110, so that no further electrical insulation of the pixel 208 is required. In a further example, the light emitting surface of each pixel 208 is less than 100 square microns. In yet a further example, the light emitting surface of each pixel 208 is less than 16 square microns. Although the pixels 208 are shown having light emitting surfaces of the same size and shape, in a further example, the array comprises a variety of pixels of different shapes and / or sizes.

[0082] Although cross-sectional views of individual pixels are shown in Figures 1A-1G, one skilled in the art will appreciate that each pixel forms part of an array of pixels. Although the array is shown (e.g., in Figures 2 and 3) as a grid having square shaped pixels, in further examples, pixels of various shapes may be provided, for example, by etching various patterns through the epitaxial structure shown in Figure 1.

[0083] Advantageously, the use of metal as the conductive material 120 in the via 115 provides optical isolation for the pixel. Metals can be highly reflective and, together with a metal layer such as the mirror / barrier layer 126 deposited on the pixel surface, can provide improved light output and good pixel contrast.

[0084] Moreover, advantageously, electrons easily propagate from n-type region 116 through p-type region 112 , thereby providing efficient recombination within light emitting region 110 .

[0085] Advantageously, only n-type material is overgrown to provide an n-type region to provide a forward bias junction. Advantageously, carriers diffuse from the p-type and n-type regions into the light emitting region against the electric field direction, thereby eliminating the need for an electron blocking layer. Advantageously, because p-type region 112 and n-type region 116 are on the same side of light emitting region 110, these relatively thin regions can be etched with a very shallow etch, thus limiting etch damage. Additionally, the protrusion of n-type region 116 is conductive, as is the buried common metal and common anode configuration.

[0086] Advantageously, the buffer thickness of the n-type buffer region 102 can be used to form light extraction features to aid in light extraction from the LED structure. The n-type buffer region 102 can be thinned as needed, which is advantageous for small pitch arrays. Advantageously, the use of vias 115 with conductive material means that any roughening etch to improve light extraction does not need to physically isolate the pixel to achieve electrical isolation, since the majority of the buffer can be insulating undoped GaN region 106. This can be facilitated, in one example, by stopping the via etch in the AIGaN barrier layer 104.

[0087] A template concept has been presented to provide a grid of vias that penetrate a light emitting area and define pixels, the vias having a p-GaN p-type region 118 with a centrally located n-type overgrowth 116 provided by n-GaN on the same side of the light emitting area 110. However, in further examples, different implementations of this concept are possible, some of which are described with respect to the following figures.

[0088] For example, monolithic high resolution micro LED arrays with pixel-defining vias may be provided by using various structures that employ carrier diffusion into the quantum well structure, where carriers from at least one of the p-type and n-type regions diffuse through the other of the n-type and p-type regions before recombining in the light emitting region.

[0089] FIG. 4 shows a cross-sectional view of a light-emitting structure 400 according to the above-mentioned concept (here, one pixel of a pixel array is defined, and the same nomenclature is used to contrast pixel 208 having pixel width 210 shown in FIGS. 2 and 3, for example). The same epitaxial structure 100F described with respect to FIG. 1F is shown. In the example of FIG. 4, instead of forming p-type regions 112 on the light-emitting region 110, n-type regions 113 are formed on the light-emitting region 110. A mask layer 114 is then deposited and processed to provide openings. The openings are etched through the mask layer 114 to form vias 115 that terminate in the undoped region 106 to provide grooves for the deposition of conductive material 120 in the vias 115. The conductive material 120 in these vias (groove vias) 115 is used to provide a common electrode grid through the light-emitting region 110 that defines pixel 208 and effectively provides a common cathode grid that allows the injection of carriers into the n-type region 113. In a method complementary to that described with respect to Figures 1 to 3, an anode may be provided in each pixel 208 by opening a central opening 111 in a further mask layer 117 and depositing / growing a p-type region 118 by overgrowth of p-type material on the n-type region 113. The patterning and etching steps are performed depending on the particular structure to be produced and may use known techniques. In the example of Figure 4, carriers from the p-type region 118 diffuse through the n-type region 113 before carriers from the n-type region 113 and the p-type region 118 recombine in the light-emitting region 110.

[0090] 5 and 6 illustrate further examples of implementations in which carriers are injected into the p-type and n-type regions such that carriers from one of the p-type and n-type regions diffuse through the other of the n-type and p-type regions before recombining in the light-emitting region.

[0091] FIG. 5 shows a processed light-emitting structure 500 based on the light-emitting structure 100E described with respect to FIG. 1E. In FIG. 5, instead of forming the conductive material 120, for example by deposition of a metal in the via 115, a further overgrowth step is used to form a p-type region 118 in the via 115. An n-type overgrowth to form an n-type region 116 in the center of the pixel 208 is used in a similar manner as described with respect to FIG. 1. An electrode forms an electrical connection with the n-type region 116 and the p-type region 112 for electrical contact with the p-type overgrowth 118 and the n-type overgrowth 116 in the via 115. The via 115 containing the p-type overgrowth material defines the pixel periphery and cooperates with the epitaxial p-type region 112 to provide carriers to recombine with carriers generated by the n-type region 116 that diffuse through the p-type region 112 before recombining in the light-emitting region 110. P-type region 112 is an epitaxial layer and p-type overgrowth 118 takes the form of a via-in-a-via 115. In a further example, additionally or alternatively, p-type region 112 and p-type overgrowth 118 are formed in various shapes while providing the benefit of carrier diffusion into light emitting region 110 from the same side of light emitting region 110.

[0092] 6 illustrates a processed light emitting structure 600 that shares the n-type layer 113 described with respect to FIG. 4. In FIG. 6, instead of forming a conductive material 120 in the via 115, an n-type region 116 is formed in the via 115 by overgrowth of n-type material to provide an n-type region 116 in the via 115 that cooperates with the n-type layer 113 to provide carriers that diffuse into the light emitting region 110 before recombining with carriers generated in the p-type region 118 that diffuse through the n-type region 113 before recombining in the light emitting region 110. Forming a p-type region 118 in the center of the pixel 208 1. Additionally, via 115 is shown as being etched down to n-type buffer region 102. In a further example, alternatively or additionally, via 115 is etched to various depths within structure 600 while penetrating light-emitting region 110, thereby defining the pixel periphery. N-type region 113 is an epitaxial layer, and n-type overgrowth 116 takes the form of via 115 within via 115. In a further example, additionally or alternatively, n-type region 113 and n-type overgrowth 116 are formed with various shapes while providing the benefit of carrier diffusion from the same side of light-emitting region 110 into light-emitting region 110.

[0093] Although monochrome high resolution micro LED arrays have been described above, it is possible to provide multi-color high resolution micro LED arrays based on etching through multiple light emitting regions as described herein.

[0094] FIG. 7 shows an epitaxial structure 700. The epitaxial structure 700 is provided in a similar manner to the epitaxial structure 100 described with reference to FIG. 1. In the example of FIG. 7, instead of having one light emitting region 110 arranged to emit light with a peak primary wavelength, the structure 700 has three light emitting regions. Furthermore, the p-type region is not grown on top of the initial structure, but is deposited / grown at a later stage. A superlattice 706 is shown on which a first light emitting region 707 is provided. An undoped region 702 is provided on the first light emitting region 707, followed by a second superlattice 708 and a second light emitting region 709. A further undoped region 704 and a third superlattice 710 are provided on the second light emitting region 709, followed by a third light emitting region 711. The first light-emitting region 707 is configured to emit a primary peak wavelength that is different from the primary peak wavelength that the second light-emitting region 709 is configured to emit, and thus different from the primary peak wavelength that the third light-emitting region 711 is configured to emit. The first light-emitting region 707 is configured to emit blue light, the second light-emitting region 709 is configured to emit green light, and the third light-emitting region 711 is configured to emit red light. This structure 700, which typically has a thickness 712 of 600 nm to 800 nm, is the epitaxial structure 700 that forms the basis for processing (which may include further growth steps) to provide a monolithic high resolution RGB micro LED array.

[0095] Advantageously, the structure 700 is formed in one growth process. Advantageously, the structure 700 is formed such that the light emitting regions 707, 709, 711 are relatively closely spaced vertically (as evidenced by the thickness 712 including the light emitting regions 707, 709, 711 and also the superlattice structure and the undoped recovery layer), so that a shallow etch can then be used to etch through and remove the light emitting regions 707, 709, 711 (some of the light emitting regions 707, 709, 711 are considered to be waste). This has been found to be particularly advantageous in the following processing to provide a high resolution monolithic color array of micro-LEDs.

[0096] The epitaxial structure 700 of FIG. 7 is processed in a manner similar to the epitaxial structure 100 of FIG. 1 to provide the processed structure 800 of FIG. 8A. FIG. 8A shows a mask layer 804 deposited on the epitaxial structure 700 and patterned by using lithographic techniques to expose the underlying epitaxial structure 700 to allow selective etching through the epitaxial structure 700 (particularly through the three light emitting regions 707, 709, 711). Selective etching through the epitaxial structure 700 (usually using dry etching techniques) provides vias 802 that can be filled by forming a conductive material 801 in the vias 802. The conductive material 801 is shown deposited in the vias 802 in FIG. 11. The conductive material 801 is deposited in the vias 802 by using known lithographic and deposition processing techniques and can be implemented at any appropriate stage during the processing of the epitaxial structure 700 to provide a multi-color light emitting device.

[0097] Vias 802 and conductive material 801 within vias 802 penetrate light emitting areas 707, 709, 711 to define the perimeter of individual pixels. This is demonstrated in plan view 800' of FIG. 8B, which shows pixels 806 (only one labeled) surrounded by conductive material 801 formed within vias 802, which are trench vias and effectively provide a common electrode for pixels 806. As shown in FIGS. 8A and 8B, the pixels defined by vias 802, which are trench vias that penetrate light emitting areas 707, 709, 711, have three distinct light emitting areas 707, 709, 711, respectively. Thus, to provide an RGB array, the pixels are selectively etched to remove undesired wavelengths within a particular pixel. This is demonstrated with reference to FIGS. 9A and 9B.

[0098] FIG. 9A shows how the undesired longest wavelengths are locally removed to leave the desired light-emitting regions for each individual pixel. In the processed epitaxial structure 900 of FIG. 9A, conductive material 801 is shown in vias 802 that form a common lattice anode that passes through all of the light-emitting regions 707, 709, 711. In the first pixel 902, the green second light-emitting region 709 and the red third light-emitting region 711 have been etched away to leave the blue first light-emitting region 707. In the second pixel 904, the red third light-emitting region 709 has been etched away to leave the blue first light-emitting region 707 and the green second light-emitting region 709. In the third pixel 906, none of the light-emitting regions 707, 709, 711 have been removed, so all remain intact. Each of the pixels 902, 904, 906 is defined by a via 802 etched through the epitaxial structure 700 and in particular through the light emitting regions 707, 709, 711. Once the pixels are etched, p-type regions 901 are formed on the epitaxial structure such that a p-type region is adjacent each respective light emitting region. Advantageously, the p-type regions are formed in a single processing growth step for each of the pixels 902, 904, 904.

[0099] 9B shows how selective etching of light emitting regions 707, 709, 711 results in pixels dedicated to emitting different wavelengths. For example, a first pixel 902 can be contacted to emit blue light. A second pixel 904 can be contacted to emit green light. A third pixel 906 can be contacted to emit red light. High resolution monolithic red, green, and blue light emitting micro LED arrays are formed by selectively contributing pixels to specific primary peak wavelength emissions.

[0100] FIG. 10A shows a thin conformal mask layer 1001 that has been patterned and opened to expose a central hole in each pixel 902, 904, 906. Once the central hole is exposed in each of the pixels 902, 904, 906 (by using lithographic techniques), the epitaxial structure 700 can be selectively etched to provide an opening in the mask layer 1001 where the n-type region 1002 is formed. Since the local longest wavelength light emitting region has been removed, the selective etch enters the desired wavelength light emitting region of each pixel. Advantageously, the generation of the structure and the processing of the structure are arranged to minimize the number of processing steps to form the resulting structure. This is demonstrated in FIG. 10B, which shows a plan view 1000′ of an array with n-type regions 1002 forming a central p-type region 1002 in each of the pixels 902, 904, 906.

[0101] In a similar manner as described above for the monochrome monolithic high resolution micro LED array, the processed light emitting structure 1000 is inverted and further processed to interface with a backplane for control of the individual pixels. Figure 11 shows a cross-sectional view of a light emitting array 1100 having three different color pixels. Shown is a first pixel 902 configured to emit light having a primary peak wavelength that is blue, a second pixel 904 configured to emit light having a primary peak wavelength that is green, and a third pixel 906 configured to emit light having a primary peak wavelength that is red.

[0102] Carrier injection into each of pixels 902, 904, 906 occurs by diffusion of carriers into the local light emitting region (711 of 906, 709 of 904, and 707 of 902). Carriers injected into n-type region 1002 diffuse through p-type region 901 before recombining in the associated light emitting region. Although the high resolution RGB micro LED array is described with reference to a common anode formed of conductive material formed in the periphery of the pixel forming a central n-type region in each individual pixel for backplane connection and in the vias defining the n-type region, those skilled in the art will appreciate that alternative implementations (e.g., those described with reference to high resolution monochrome micro LED arrays) may be applied to the high resolution RGB micro LED array (including, for example, an array in which an n-type region provided by an n-type layer is formed in place of the p-type region 901 formed by p-type layer 901, and the central n-type region 1002 is replaced by a p-type overgrowth to form the central p-type region). Furthermore, those skilled in the art will appreciate that while the examples illustrated with respect to Figures 7-11 show the formation of vias 802 that define pixel peripheries by penetrating conductive material 801 in vias 802 having p-type regions 901 formed over the light-emitting structure and light-emitting regions 707, 709, 711 having central n-type regions within each pixel, in further examples, different implementations are used (e.g., by using any of the implementations described with respect to Figures 1-6).

[0103] Advantageously, the various active regions are deposited in the same step with the formation of the layer providing the p-type region 901. Advantageously, the holes do not propagate deep into the structure and thus vertical propagation only to the nearest QW structure can be realized, thus leading to better color purity in multicolor displays. Advantageously, if the layer providing the p-type region 901 is replaced by an n-type layer and a p-type region is used centrally in the pixel instead of an n-type region, the electrons move against the potential gradient when diffusing across the p-type material and are therefore not expected to diffuse deep into the quantum well structure of the light emitting region.

[0104] While the above describes a pixel having an emitting surface that defines a pixel, where the pixel periphery is defined by vias that penetrate one or more of the emitting regions such that the pixel is configured to emit light having a primary peak wavelength, in one example, for a multi-color structure, a common via is formed through multiple emitting regions, and a portion of the emitting surface defined by the vias that form the periphery is selectively etched to form contacts by using overgrowths as described above, such that multiple different primary peak wavelengths can be emitted from the pixel. Advantageously, such a structure allows for closer integration of micro-LEDs.

[0105] Advantageously, by using the above-described structures and methods, a monolithic array of high-resolution micro LEDs is provided. Such arrays may include monochrome or multi-color arrays and are therefore applicable to multiple applications requiring high-resolution light emitting structures. Beneficially, the pixel pitch of such monolithic high-resolution micro LED arrays is less than 10 microns. In some examples, the pixel pitch of such monolithic high-resolution micro LED arrays is less than 4 microns. In further examples, the pixel pitch of such monolithic high-resolution micro LED arrays is less than 3 microns. Although the array has been described with respect to square pixels in a grid shape, other types and patterns of pixels in the array are implemented in further examples.

[0106] High quality emissive arrays are formed, at least in part, due to the use of planar epitaxial structures that are formed and processed (grown or provided) with minimal overgrowth to isolate pixels in a densely integrated array. Advantageously, vias penetrating the light emitting regions of the epitaxial structures simultaneously isolate the pixels and provide a means of improved electrical contact of all of the pixels in the array. Advantageously, the provision of stacked light emitting regions allows for the desired light emitting regions to be identified to provide improved light emitting diode structures and monolithic high resolution micro LED arrays. This means that their surfaces can be exposed for efficient processing and contact.

[0107] Although the above LED structures have been described with reference to growth by MOCVD, growth by different and / or complementary techniques may be beneficial in some instances. For example, growth by MBE may allow for cooler and / or slower growth rates that may have benefits with respect to the growth and processing steps described above. Although the processing steps above have been described in any order, those skilled in the art will appreciate that in further examples the processing steps may be performed in any order suitable to obtain the target structure.

Claims

1. p-type region; n-type region; a light emitting region for recombination of carriers injectable by the p-type region and the n-type region, the p-type region and the n-type region being on the same side of the light emitting region; and A via penetrating the light emitting region 13. A light emitting diode structure comprising: a via defining a periphery of a light emitting surface of at least one pixel and comprising a material configured to enable injection of carriers into the p-type region or the n-type region, one of the p-type region and n-type region configured such that carriers generated in the one of the p-type region and the n-type region diffuse through the other of the n-type region and p-type region before recombining in the light emitting region.

2. 10. The light emitting diode structure of claim 1, wherein the light emitting region comprises at least one epitaxial quantum well layer.

3. 3. A light emitting diode structure according to claim 1 or 2, wherein the material comprises at least a portion of the n-type region or the p-type region and / or the material comprises a conductive material.

4. A light emitting diode structure according to any one of claims 1 to 3, comprising a further light emitting region.

5. 5. The light emitting diode structure of claim 4, comprising at least three light emitting regions, one of the light emitting regions emitting blue light, one of the light emitting regions emitting green light, and one of the light emitting regions emitting red light.

6. The light emitting diode structure of any one of claims 1 to 5, wherein the vias are lattice vias defining an array including a plurality of pixels.

7. 7. A light emitting diode structure according to claim 1, wherein the light emitting region and / or the further light emitting region are formed on an undoped epitaxial layer and / or the light emitting region and / or the further light emitting region are formed between undoped epitaxial layers.

8. The light emitting diode structure of any one of claims 1 to 7, wherein at least one of the n-type region and the p-type region is formed in a via that is connected to a planar n-type region or a planar p-type region, respectively.

9. A light emitting diode structure according to any preceding claim, wherein at least one of the n-type region and the p-type region is formed by selective area growth.

10. 10. A light emitting diode structure according to any one of claims 1 to 9, wherein the vias are etched vias and / or the light emitting surface has an area based on a diffusion length of carriers in the light emitting region.

11. A light emitting diode structure according to any preceding claim, wherein the at least one pixel is generally peripherally defined by a single electrode.

12. A high resolution micro LED array comprising the light emitting diode structure according to any one of claims 1 to 11.

13. 13. The high resolution micro LED array of claim 12, which is a multi-color array.

14. 1. A method of forming a light emitting diode structure, comprising: forming a p-type region; forming an n-type region; forming a light emitting region for recombination of injectable carriers with the p-type region and the n-type region, the p-type region and the n-type region being on the same side of the light emitting region; and forming a via through said light emitting region; the via defines a periphery of a light emitting surface of at least one pixel and comprises a material configured to allow injection of carriers into the p-type region or the n-type region, one of the p-type region and n-type region configured such that carriers generated in the one of the p-type region and the n-type region diffuse through the other of the n-type region and p-type region before recombining within the light emitting region.

15. The method of claim 14 , wherein forming the light emitting region comprises forming at least one epitaxial quantum well layer.

16. 16. The method of claim 14 or 15, wherein the material comprises at least a portion of the p-type region or the n-type region, and / or the material comprises a conductive material.

17. A method according to any one of claims 14 to 16, comprising providing a further light emitting region.

18. 20. The method of claim 17, comprising at least three light-emitting regions, one of the light-emitting regions emitting blue light, one of the light-emitting regions emitting green light, and one of the light-emitting regions emitting red light.

19. The method of any one of claims 14 to 18, wherein the vias are grid vias that define a plurality of pixels.

20. The method of any one of claims 14 to 19, comprising forming the n-type and p-type regions in vias that are connected to a planar n-type or p-type region, respectively.

21. A method according to any one of claims 14 to 20, comprising forming at least one of the n-type and p-type regions by selective area growth.

22. A method according to any one of claims 14 to 21, comprising etching through the light emitting area to form the vias which define the periphery of the light emitting surface.

23. A method according to any one of claims 17 to 21 when dependent on claim 17, comprising at least partially etching through at least one light-emitting region to locally remove the undesired longest wavelength.

24. A method of forming a high resolution LED array comprising the method of any one of claims 14 to 23.

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