Reduced distortion power semiconductor devices

Abstract

Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce distortion in the power semiconductor die. By modifying the paths that define the electrodes, vias, and metal runners and patterning those material layers, distortion can be better managed to increase the reliability of the power semiconductor die.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 177,641, filed February 17, 2021.

[0002] The present disclosure relates to power semiconductor devices, and more particularly to layout methods for reducing distortion in power semiconductor devices. [Background technology]

[0003] Power semiconductor devices handle high voltages and currents and are therefore frequently subjected to large temperature fluctuations. Such large temperature fluctuations can cause large strains in the various layers of the device, potentially resulting in cracks, delamination, and failure. Thus, there is a need for power semiconductor devices with reduced strain. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a power semiconductor device includes a drift layer, an active region, an insulating layer, and a runner electrode. The runner electrode includes a conductive material disposed along a runner electrode path. The runner electrode path follows a periphery of the active region. The runner electrode includes one or more runner electrode strain relief regions, which are regions without the conductive material. The provision of the one or more strain relief regions reduces strain induced by the runner electrode, thereby improving reliability of the power semiconductor device.

[0005] In one embodiment, the power semiconductor device further includes a runner via and a metal runner. The runner via is along a runner via path and the metal runner is along the metal runner path. The runner via is an opening in the insulating layer and the runner electrode is exposed through the opening. The metal runner fills the runner via and electrically contacts the runner electrode.

[0006] In one embodiment, the runner via is segmented to provide multiple segmented runner vias separated by portions of the insulating layer. By segmenting the runner via, distortion caused by the runner via may be reduced, improving the reliability of the power semiconductor device.

[0007] In one embodiment, any of the runner electrode paths, runner via paths, and metal runner paths may be different from the others. By providing the runner electrodes, runner vias, and metal runners in this manner, the distortion caused by these layers may be reduced, thereby improving the performance of the power semiconductor device.

[0008] In one embodiment, the runner electrodes, runner vias, and metal runner paths are defined by an inner edge and an outer edge. In various embodiments, one of the inner edge or the outer edge is not parallel to the paths that define the runner electrodes, runner vias, and / or metal runner paths. By providing the runner electrodes, runner vias, and / or metal runner paths in this manner, distortion may be reduced, thereby improving the reliability of the power semiconductor device.

[0009] In one embodiment, a switching power semiconductor device includes an electrode assembly configured such that the switching power semiconductor device has a failure rate of less than 2000 ppm when subjected to a thermal cycle test, where the temperature of the switching power semiconductor device is cycled between a minimum temperature of -40°C or less and a maximum temperature of 150°C or more.

[0010] In alternative embodiments, any of the foregoing embodiments may be combined individually or together to obtain additional advantages, and / or various separate embodiments and features as described herein may be combined. Any of the various features and elements as disclosed herein may be combined with one or more of the other disclosed features and elements, unless otherwise stated herein.

[0011] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures.

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a cross-sectional view of a power semiconductor die according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a top view of a power semiconductor die according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a top view of a power semiconductor die according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a top view of a power semiconductor die according to an embodiment of the present disclosure. [Figure 5A] 1 illustrates generic features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 5B] 1 illustrates generic features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 5C] 1 illustrates generic features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 6] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 7A] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 7B]FIG. 2 is a cross-sectional view of a portion of a power semiconductor die according to one embodiment of the present disclosure. [Figure 8A] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 8B] FIG. 2 is a cross-sectional view of a portion of a power semiconductor die according to one embodiment of the present disclosure. [Figure 9A] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 9B] FIG. 2 is a cross-sectional view of a portion of a power semiconductor die according to one embodiment of the present disclosure. [Figure 10] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 11] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 12] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a top view of a corner of a power semiconductor die according to an embodiment of the present disclosure. [Figure 14] 1 illustrates some of the features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 15] 1 illustrates some of the features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 16] 1 illustrates some of the features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 17] 1 illustrates some of the features of a power semiconductor die according to one embodiment of the present disclosure. [Figure 18] 1 illustrates some of the features of a power semiconductor die according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments and show the best mode for practicing the embodiments. Upon reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically mentioned herein. These concepts and applications should be understood to be included within the scope of the present disclosure and the appended claims.

[0015] Terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0016] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "over" another element, it will be understood that it can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0017] Relative terms such as "lower" or "upper" or "top" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. It will be understood that these terms, and those described above, are intended to encompass various orientations of the device in addition to the orientation shown in the drawings.

[0018] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Furthermore, it will be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of the present specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0020] The embodiments are described herein with reference to schematic diagrams of embodiments of the present disclosure. As such, actual dimensions of layers and elements may vary and variations from the shapes of the drawings are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, a region shown or described as a square or rectangle may have rounded or curved features, and a region shown as a straight line may have some irregularities. Thus, the regions shown in the drawings are schematic, and their shapes are not intended to show the exact shape of a region of a device, and are not intended to limit the scope of the present disclosure. In addition, the size of a structure or region may be exaggerated relative to other structures or regions for purposes of explanation, and thus are provided to show the general structure of the subject matter, and may not be drawn to scale. Common elements between the drawings may be indicated with common element numbers herein and may not be re-described later.

[0021] FIG. 1 illustrates a cross-sectional view of a power semiconductor die 10 according to an embodiment of the present disclosure. The power semiconductor die 10 includes a drift layer 12 and an insulating layer 14 on the drift layer 12. The drift layer 12 includes an active area 16 in a central portion thereof. A runner electrode 18 surrounds the active area 16. The runner electrode 18 is separated from the drift layer 12 by a portion of the insulating layer 14. A metal runner 20 is on the runner electrode 18 on a surface of the insulating layer 14 opposite the drift layer 12. A runner via 22 electrically connects the metal runner 20 and the runner electrode 18 by providing an opening in the insulating layer 14 and is filled by a portion of the metal runner 20. An additional metal runner 24 is on a portion of the drift layer 12 outside the metal runner 20 on a surface of the insulating layer 14 opposite the drift layer 12. An additional runner via 26 electrically connects the additional metal runner 24 to the drift layer 12 by providing an opening in the insulating layer 14 and is filled by a portion of the additional metal runner 24. A passivation layer 27 overlies the metal runners 20 and the additional metal runners 24. The passivation layer 27 electrically insulates and protects the metal runners 20 and the additional metal runners 24 from the environment.

[0022] Although not shown, the active area 16 of the drift layer 12 includes several implanted regions that are interconnected to provide one or more power semiconductor devices such as transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), diodes, etc.). Metal runners 20 are electrically coupled to one or more of these implants by runner electrodes 18, which are coupled to one or more of the implants via an electrode mesh that extends from the runner electrodes 18 into the active area 16 but is not shown in FIG. 1. Additional metal runners 24 are electrically coupled to one or more other implants by one or more implanted regions of the drift layer 12, also not shown in FIG. 1.

[0023] In an exemplary embodiment in which the power semiconductor die 10 provides a MOSFET, the runner electrode 18 may be a runner for the gate electrode, such that a metal runner 20 is coupled to a gate contact and distributes the gate current to the gate electrode. In this example, an additional metal runner 24 is coupled to a source contact and distributes the source current to one or more implanted regions of the drift layer 12. Those skilled in the art will appreciate that additional portions of the power semiconductor die 10 not directly related to the present disclosure are not shown in FIG. 1 to avoid obscuring the drawing.

[0024] In some embodiments, drift layer 12 may include silicon carbide. However, the disclosure is not limited to a particular material system for drift layer 12. In various embodiments, drift layer 12 may include silicon, gallium nitride, gallium arsenide, or any other semiconductor material. Insulation layer 14 may include any suitable electrically insulating material. In one embodiment, insulation layer 14 includes a dielectric material such as silicon dioxide. Runner electrode 18 may include any suitable conductive material. In one embodiment, runner electrode 18 includes doped polysilicon. Metal runner 20 and additional metal runner 24 may include any suitable conductive metal, such as copper, aluminum, tin, or a metal alloy. In various embodiments, the portion of metal runner 20 that fills runner via 22 may be the same material as the portion of metal runner 20 on the surface of insulation layer 14, or may be a different material, and they may be deposited together or separately. Similarly, the portion of the additional metal runner 24 that fills the additional runner via 26 may be of the same material as the portion of the additional metal runner 24 on the surface of the insulating layer 14, or may be of a different material, and they may be deposited together or separately.

[0025] FIG. 2 shows a top view of the power semiconductor die 10 according to one embodiment of the present disclosure. In particular, the passivation layer 27 and the metal runner 20 are not shown to avoid cluttering the drawing. As shown, the runner electrode 18, the metal runner 20 (not shown but still present), and the runner via 22 surround the active area 16. The additional metal runner 24 and the additional runner via 26 surround the runner electrode 18, the metal runner 20, and the runner via 22. The reason for providing the metal runner 20 and the additional metal runner 24 around the periphery of the power semiconductor die 10 as shown is to better distribute the current around the periphery of the power semiconductor die 10, thus reducing the resistance. For example, in the above example where the power semiconductor die 10 provides a MOSFET, such that the metal runner 20 is the gate contact and the additional metal runner 24 is the source contact, it is important that the resistance of these contacts is minimized for the performance of the MOSFET. As shown in FIG. 2, an electrode mesh 28 is provided over the active area 16 and is electrically coupled to the runner electrode 18. A central electrode 30 extends over a central portion of the active area 16. A pad electrode 32 overlies the central electrode 30. A central electrode via 34 electrically couples the central electrode 30 and the pad electrode 32 to a metal contact pad, which is a metal layer disposed above the pad electrode 32 on the insulating layer 14 and is used to couple external circuitry to the power semiconductor die 10. The metal contact pad is not shown to avoid cluttering the drawing, but is disposed directly on the pad electrode 32 with a similar shape as the pad electrode 32.

[0026] Generally, there are two areas in the power semiconductor die 10 that experience high levels of distortion during thermal cycling. First, the power semiconductor die 10 experiences high levels of distortion in the area that defines the pad electrode 32. To reduce the amount of distortion in this area, the pad electrode 32 can be provided only under the central electrode via 34, as shown in FIG. 3. By significantly reducing the amount of material in the pad electrode 32, the distortion caused by the pad electrode 32 may be significantly reduced. In applications where gate capacitance needs to be controlled, the pad electrode 32 may include an inner mesh portion as a solid line boundary, as shown in FIG. 4. In both FIG. 3 and FIG. 4, the runner electrode 18 may also be narrowed to reduce its width. By reducing the amount of material in the runner electrode 18, the distortion caused by the runner electrode 18 may be reduced as well. In various embodiments, the surface area of ​​the pad electrode 32 is reduced to be less than 50% of the surface area of ​​the pad electrode 32, less than 25% of the surface area of ​​the pad electrode 32, and less than 10% of the surface area of ​​the pad electrode 32.

[0027] In addition to the pad electrodes 32, the corners of the power semiconductor die 10 also experience very high strain during thermal cycling. In particular, the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26 may all experience high strain as they approach the corners of the power semiconductor die 10. This strain may cause delamination, cracking, or even breakage of the various layers. This may result in failure of the power semiconductor die 10.

[0028] To aid in the description of further embodiments of the present disclosure, FIG. 5A illustrates a generic feature 38 of a semiconductor die according to one embodiment of the present disclosure. The generic feature 38 is defined by a path 40 that defines the general shape of the generic feature 38. The generic feature 38 also has a width that is defined as the distance between an inner edge 42I and an outer edge 42O. Material that constitutes the feature is provided between the inner edge 42I and the outer edge 42O. In the simplest case, as shown in FIG. 5A, the inner edge 42I and the outer edge 42O are provided parallel to the path 40. However, in some cases, one of the inner edge 42I or the outer edge 42O may be provided such that it is not parallel to the path 40. Thus, FIG. 5B illustrates the inner edge 42I as not parallel to the path 40, while FIG. 5C illustrates the outer edge 42O as not parallel to the path 40. In particular, at least one of the inner edge 42I and the outer edge 42O is always parallel to the path 40. Unless otherwise stated, both the inner edge 42I and the outer edge 42O can be assumed to be parallel to the path 40. In describing the following embodiments, paths and edges of various features are described but not shown in the drawings to avoid cluttering the drawings. The paths and edges are defined as described herein with respect to Figures 5A-5C. With respect to the metal runner 20 and the additional metal runner 24, their inner and outer edges are not defined by edges within the runner via 22 and the additional runner via 24, respectively, but by edges on the surface of the insulating layer 14 opposite the drift layer 12.

[0029] FIG. 6 illustrates a top view of a corner of a power semiconductor die 10 according to an embodiment of the present disclosure. The passivation layer 27 is not shown to avoid cluttering the drawing. As shown, the path of the runner electrode 18 does not follow the contour of the periphery of the power semiconductor die 10, but rather provides a gradual curve at the corner. The path of the metal runner 20 and the path of the runner via 22 overlap with the path of the runner electrode 18. Similarly, the additional metal runner 24 and the additional runner via 26 provide a gradual curve at the corner of the power semiconductor die 10 and have overlapping paths. Providing a gradual curve at the corner of the power semiconductor die 10 reduces distortion that would otherwise occur if the layers were to go around the periphery of the power semiconductor die 10 toward the corner to provide a 90 degree angle. However, even the power semiconductor die 10 illustrated in FIG. 5 is subject to a relatively high degree of distortion and may result in reliability issues during thermal cycling.

[0030] FIG. 7A illustrates a top view of a corner of a power semiconductor die 10 according to one embodiment of the present disclosure. To avoid cluttering the drawing, the passivation layer 27 and the metal runner 20 are not shown. As shown in FIG. 7, the runner electrode 18 includes multiple strain relief regions 36, which are areas of the runner electrode 18 that are not provided with conductive material. The strain relief regions 36 may be any shape and are therefore shown in FIG. 7A with a variety of shapes including ovals, radial slots, staggered slots, etc. The different shapes shown in FIG. 7A represent different embodiments that may or may not be combined, such that the strain relief regions 36 may all be the same shape or may be different shapes. As discussed above, the runner electrode 18 is defined by an inner edge and an outer edge between which the conductive material is provided. The strain relief regions 36 are provided between the inner edge and the outer edge of the runner electrode 18. In particular, the runner electrode 18 is separated from the electrode mesh 28. In the case where the electrode mesh 28 forms a grid that includes areas where no conductive material is provided, the runner electrode 18 is typically provided as a continuous layer of conductive material between the inner and outer edges. By providing the strain relief region 36 in the runner electrode 18, the strain caused by the runner electrode 18 may be interrupted, thereby reducing the overall strain, thereby improving the reliability of the power semiconductor die 10. In one embodiment, the strain relief region 36 is provided so as not to intersect with lines defining the path of any individual runners (lines of conductive material) in the electrode mesh 28. In other words, if the lines of conductive material of the electrode mesh 28 extend into the runner electrode 18, the strain relief region 36 may be provided so as not to intersect with any of these lines. This may prevent the strain relief region 36 from impeding the flow of current from the runner electrode 18 to the electrode mesh 28. In some embodiments, the insulating layer 14 may fill voids in the runner electrode 18 left by the strain relief region 36. As shown, the strain relief regions 36 may be any shape including rectangular and circular, but may also be any other shape such as a polygon or any other shape.

[0031] 7B shows a cross-sectional view through A-A' of FIG. 7A to further illustrate the strain relief regions 36. As shown, the strain relief regions 36 are areas that are not provided with the conductive material of the runner electrode 18, so that the insulating layer 14 fills the areas. They do not affect the metal runners 20.

[0032] FIG. 8A shows a top view of a corner of a power semiconductor die 10 according to an embodiment of the present disclosure. To avoid cluttering the drawing, the passivation layer 27 is not shown. As shown in FIG. 8A, the runner via 22 and the additional runner via 26 are modified to reduce distortion. This may be achieved in several ways, each of which may be used together or separately. The modifications are described herein with respect to the runner via 22, but apply equally to the additional runner via 26 or any other via. First, FIG. 8A shows that the runner via 22 may be segmented to be provided as multiple runner via sections 38. In other words, the runner via 22 is no longer provided as a continuous opening in the insulating layer 14, but rather is dispersed by portions of the insulating layer 14 that are left intact. In addition to or apart from segmenting the runner via 22, the runner via 22 may also be provided such that the path of the runner via 22 is not the same as the path of the runner electrode 18 or the path of the metal runner 20. In particular, the path of the runner via 22 may not completely overlap or be parallel to the path of the runner electrode 18 and / or the path of the metal runner 20. The path of the runner via 22 may be provided in a serpentine manner as shown, but may also be provided in any manner such that it is different from or otherwise not parallel to the path of the runner electrode 18 and / or the path of the metal runner 20. Finally, in addition to or apart from segmenting the runner via 22 and providing the runner via 22 along a different path than the runner electrode 18 and the metal runner 20, the runner via 22 may be provided in a cross-hatch pattern, where the runner via 22 provides at least one first portion that overlaps with at least one second portion. In some embodiments, the first portion is perpendicular to the second portion. Together or separately, these modifications to the runner via 22 may reduce distortion caused by the runner via 22, thereby improving the reliability of the power semiconductor die 10.

[0033] FIG. 8B shows a cross-sectional view of the power semiconductor die 10 along line B-B′ to illustrate that the runner via 22 is segmented into two separate runner via sections separated by a portion of the insulating layer 14.

[0034] 9A illustrates a top view of a corner of a power semiconductor die 10 according to one embodiment of the present disclosure. The passivation layer 27 is not shown to avoid cluttering the drawing. The embodiment illustrated in FIG. 9A combines the strain relief region 36 in the runner electrode 18 shown in FIG. 7A with the modifications to the runner via 22 shown in FIG. 8A. The combination of these modifications may further reduce the strain, thereby improving the reliability of the power semiconductor die 10.

[0035] FIG. 9B shows a cross-sectional view of the power semiconductor die 10 along line CC' to show the segmentation of the strain relief regions 36 and the runner vias 22.

[0036] FIG. 10 illustrates a top view of a corner of a power semiconductor die 10 according to an embodiment of the present disclosure. To avoid cluttering the drawing, the passivation layer 27 is not shown. In this embodiment, the path of the metal runner 20 is not the same as the path of the runner electrode 18 or the path of the runner via 22. In other words, the path of the metal runner 20 does not overlap or run parallel to the path of the runner electrode 18 or the path of the runner via 22. As shown, the path of the metal runner 20 is provided in a serpentine manner. However, the path of the metal runner 20 may be provided in any manner without departing from the principles of the present disclosure. The inner edge of the runner electrode 18 is also not parallel to the path of the runner electrode 18, but rather runs along the inner edge of the metal runner 20. Providing the metal runner 20 and the runner electrode 18 in this manner may reduce distortion, thereby improving the reliability of the power semiconductor die 10.

[0037] 11 illustrates a top view of a power semiconductor die 10 according to one embodiment of the present disclosure. To avoid cluttering the drawing, the passivation layer 27 is not shown. This embodiment essentially combines the modifications to the runner vias 22 described above with respect to FIG. 8A with the modifications to the metal runners 20 described above with respect to FIG. 10. By combining these features, distortion may be further reduced, thus further improving the reliability of the power semiconductor die 10.

[0038] 7-11 relate to the runner electrode 18, metal runner 20, and runner via 22, however, the same modifications can be made to the additional metal runner 24 and additional runner via 26. Additionally, the same modifications can be made to the center electrode 30, center electrode via 34, and pad electrode 32 to reduce distortion in these areas.

[0039] In addition to or separate from the improvements described above, the curvature of the paths of the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26 may be altered to reduce distortion. In particular, the paths defining the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26 may provide chamfered corners relative to the corners of the power semiconductor die 10, as shown in FIG. 12. Chamfering the paths of the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26 may move these layers away from the points of the power semiconductor die 10 that experience the highest distortion, thereby reducing the potential for complications and improving the reliability of the power semiconductor die 10.

[0040] In another embodiment, the paths of the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26 may be provided with a reverse radius to the corners of the power semiconductor die 10, as shown in Figure 13. Again, this may move these layers away from the points of the power semiconductor die 10 that experience the highest strain, thereby improving the reliability of the power semiconductor die 10.

[0041] In addition to or apart from the improvements described above, any of the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 24 may be provided such that their inner edges are not parallel to their outer edges. FIG. 14 illustrates an additional metal runner having an outer edge that is not parallel to its inner edge. In particular, FIG. 14 illustrates an additional metal runner 24 having a wavy or serpentine outer edge along with a straight inner edge. The present disclosure contemplates inner edges and / or outer edges having any shape. Although not shown, similar modifications can be made to the metal runner 20.

[0042] In another embodiment, the outer edges of the metal runner 20 and / or the additional metal runner 24 may be slotted as shown in Figure 15. The inner and outer edges of the metal runner 20 and / or the additional metal runner 24 may also be wavy as shown in Figure 16. Finally, the inner portions of the metal runner 20 and / or the additional metal runner 24 may be omitted to form slots or other areas where the conductive material of the metal runner and / or the additional metal runner 24 is not provided between its inner edge and its outer edge as shown in Figures 17 and 18, where Figure 17 shows the additional metal runner 24 having several areas without its conductive material and Figure 18 shows the additional metal runner 24 having a single continuous area without its conductive material.

[0043] In general, the present disclosure contemplates modifying the paths, inner edges, and outer edges of any of the runner electrodes 18, metal runners 20, runner vias 22, additional metal runners 24, and additional runner vias 26 to reduce distortion and thus improve the reliability of the power semiconductor die 10. One method of measuring the reliability of the semiconductor die 10, particularly with respect to distortion-induced failures, is the failure rate of the semiconductor die 10 when subjected to a thermal cycle test. The thermal cycle test involves cycling the temperature of the semiconductor die 10 between a minimum temperature and a maximum temperature for a given number of cycles. In one embodiment, the minimum temperature is 40° C. or less, the maximum temperature is 150° C. or more, and the number of cycles is at least 1000. In other embodiments, the thermal cycle test may be more stringent, such that one or more of the following conditions are applied: the minimum temperature is -55° C. or less, the maximum temperature is 175° C. or more, and the number of cycles is 2000 or more, 3000 or more, or even 5000 or more. One or more of the improvements described herein may enable the power semiconductor die 10 to have a failure rate of less than 2000 ppm when subjected to thermal cycling testing as described above, which is at least an order of magnitude less than a conventional power semiconductor die without the improvements of the present disclosure. In various embodiments, the improvements described herein may enable the power semiconductor die 10 to have even greater reliability, such as failure rates of less than 1000 ppm, less than 500 ppm, less than 100 ppm, and less than 20 ppm.

[0044] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein may be combined to obtain additional advantages. Any of the various embodiments as disclosed herein may be combined with one or more of the other disclosed embodiments, unless otherwise stated herein to the contrary.

[0045] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are deemed to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. a drift layer including an active region; a conductive runner electrode provided on the drift layer along a runner electrode path; a metal runner extending along a metal runner path along a perimeter of the active area; an insulating layer, a portion of the insulating layer being between the runner electrode and the metal runner; A semiconductor device comprising: A semiconductor device, wherein the width of the metal runner is less than the width of the runner electrode.

2. The semiconductor device further comprises a runner via along a runner via path, the runner via being an opening in the insulating layer, the runner electrode being exposed through the opening; 2. The semiconductor device of claim 1, wherein the runner via is segmented to provide a plurality of segmented runner vias separated by respective portions of the insulating layer.

3. The semiconductor device of claim 2 , wherein the metal runner path is not identical to the runner via path.

4. the runner electrode includes a conductive material between an inner runner electrode edge and an outer runner electrode edge; The semiconductor device of claim 1 , wherein one or more of the inner runner electrode edges and the outer runner electrode edges are not parallel to the runner electrode path.

5. The semiconductor device further comprising an electrode mesh overlying the active area and coupled to the runner electrode, the electrode mesh comprising a grid of electrode mesh runners extending between opposing sides of the inner runner electrode edges; the runner electrode includes one or more runner electrode strain relief regions, the one or more runner electrode strain relief regions being regions that are free of the conductive material; 5. The semiconductor device of claim 4, wherein the one or more runner electrode strain relief regions are disposed so as not to intersect lines defining a path of any one of the grids of the electrode mesh runners.

6. The semiconductor device of claim 1, wherein the runner electrode includes a curved corner.

7. The semiconductor device of claim 1, wherein the metal runner includes curved corners.

8. An additional runner via extending along an additional runner via path, the additional runner via being an opening in the insulating layer; an additional metal runner filling the additional runner via and electrically contacting the drift layer; The semiconductor device of claim 1 , further comprising:

9. The semiconductor device of claim 8, wherein the additional metal runner includes curved corners.

10. The semiconductor device of claim 9, wherein the additional metal runner is located outside the runner electrode.

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