Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device with low resistance, high performance and high reliability in a SiC power MISFET, which has a side surface of a trench formed on the top surface of a SiC epitaxial substrate as the channel region.SOLUTION: On the side of trench 9, a storage layer forming area 7 which is a semiconductor area of the same conductivity type as source area 6 is formed. Here, defining the boundary between an area where the depletion layer extending from body layer 5 touches the side of the trench 9 when turned off and an area where the depletion layer is away from the side of the trench 9 as a first point and defining the nearest point from the first point in the boundary between the body layer 5 and the storage layer forming area 7 as a second point, a part of the body layer 5 is located below than the second point.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device which is a power semiconductor device, and in particular to one having a trench structure. [Background technology]

[0002] Semiconductor power elements are required to have high breakdown voltage, low on-resistance, and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude higher than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by three orders of magnitude or more. In addition, because the band gap is approximately three times larger than that of Si, high temperature operation is also possible, and SiC semiconductor elements are expected to exceed the performance of Si semiconductor elements, and the development of SiC power devices is underway.

[0003] Patent Document 1 (JP 2015-72999 A) describes a semiconductor device having an n-type substrate made of silicon carbide, an n-type drift layer on the substrate, a plurality of trenches formed in a stripe pattern on the drift layer, a gate electrode formed in the trench via an insulating film, and an n-type current spreading layer formed on the drift layer and having a higher impurity concentration than the drift layer. The gate electrode constitutes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the bottom of the trench is covered with a p-type bottom layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-72999 A Summary of the Invention [Problem to be solved by the invention]

[0005] A structure having a trench increases the area of ​​the channel, and is expected to reduce the on-resistance. However, in general, there is a trade-off between on-resistance and breakdown voltage, and especially in the case of a JFET region, narrowing the JFET width increases the breakdown voltage while increasing the resistance. For this reason, the design of the JFET region is very important. Furthermore, SiC has a wider band gap and higher dielectric breakdown strength than Si, but the electric field applied to the insulating film is also larger accordingly, so technology to alleviate the electric field of the insulating film is very important. If the electric field in the insulating film is strong, a leak current occurs in the gate insulating film, leading to a decrease in the gate insulating film life or device malfunction such as dielectric breakdown of the gate insulating film. Therefore, there are technologies to improve the breakdown voltage of the gate insulating film by devising a gate insulating film formation process, and design technologies to alleviate the electric field applied to the gate insulating film. For example, it is effective to cover the bottom of the trench with a p-type layer, and there is a structure shown in Patent Document 1.

[0006] The current spreading layer described in Patent Document 1 is formed to avoid the problem that the depletion layer extending from the p-type layer narrows the current path between the p-type layers, increasing the on-resistance. Here, the potential of the p-type layer at the bottom of the trench is floating, and another p-type layer is formed between the trenches to prevent the gate insulating film from being destroyed by a surge. The presence of this p-type layer increases the cell pitch of the semiconductor device, and furthermore, a depletion layer is formed, which increases the on-resistance.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief outline of a representative embodiment of the present invention will be described below.

[0009] In one embodiment of the silicon carbide semiconductor device, in a vertical MISFET having a gate electrode embedded in a trench, an accumulation layer formation region, which is a semiconductor region of the same conductivity type as the source region, is formed on the side of the trench below the lower end of the source region. Here, when a first point is defined as a boundary between a region where a depletion layer extending from the body layer contacts the side of the trench when off and a region where the depletion layer is separated from the side of the trench, and a second point is defined as a point on the interface between the accumulation layer formation region and the body layer that is closest to the first point, a part of the body layer is located below the second point. Effect of the Invention

[0010] The effects obtained by the representative inventions among those disclosed in this application will be briefly described as follows.

[0011] According to the present invention, the performance of a silicon carbide semiconductor device can be improved. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view showing a silicon carbide semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 1 is an enlarged cross-sectional view showing a silicon carbide semiconductor device according to a first embodiment of the present invention. [Figure 4] 1 is an enlarged cross-sectional view showing a silicon carbide semiconductor device according to a first embodiment of the present invention. [Diagram 5] 1 is a conceptual cross-sectional view illustrating a shape of a semiconductor region of a silicon carbide semiconductor device according to a first embodiment of the present invention. [Figure 6] 1 is a graph showing the relationship between the concentration of an accumulation layer formation region and the on-resistance and the breakdown voltage. [Figure 7] 1 is a graph showing the relationship between breakdown voltage and on-resistance. [Figure 8] 2 is an enlarged cross-sectional view showing a silicon carbide semiconductor device according to a modified example of the first embodiment of the present invention. FIG. [Figure 9]FIG. 11 is a plan view showing a silicon carbide semiconductor device according to a second embodiment of the present invention. [Figure 10] FIG. 11 is a perspective view showing a silicon carbide semiconductor device according to a second embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view showing a silicon carbide semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In addition, in the following embodiments, the explanations of the same or similar parts are not repeated in principle, except when particularly necessary. In addition, in the drawings for explaining the embodiments, hatching may be used even in plan views or perspective views, etc., in order to make the configuration easier to understand. Furthermore, in the drawings for explaining the embodiments, hatching may be omitted in cross-sectional views in order to make the configuration easier to understand.

[0014] Also," - " and " + " is a code that indicates the relative impurity concentration of the conductivity type, n-type or p-type. For example, "n -- ", "n - ", "n", "n + ", "n ++ The concentration of n-type impurities increases in this order.

[0015] (Embodiment 1) Hereinafter, a silicon carbide semiconductor device will be described with reference to the drawings, taking as an example a SiC power MISFET (Metal Insulator Semiconductor Field Effect Transistor), that is, a trench-type MOSFET, which has a side surface inside a trench (groove, recess) as a channel region.

[0016] <Structure of Silicon Carbide Semiconductor Device> The structure of the silicon carbide semiconductor device according to the present embodiment 1 will be described with reference to Figures 1 to 5. In Figure 1, an extended portion that is a part of a source electrode is shown as a structure on a semiconductor substrate, but an insulating film and a part of a gate electrode that are other structures on the semiconductor substrate are not shown.

[0017] As shown in FIG. 1, the cell array constituting the silicon carbide semiconductor device of this embodiment has a configuration in which a plurality of unit cells having a predetermined planar layout are arranged in a matrix. In FIG. 1, one unit cell is surrounded by a dashed line. The X direction and the Y direction shown in FIG. 1 are directions along the upper surface (main surface) of the semiconductor substrate. The X direction and the Y direction are orthogonal to each other in a planar view. The silicon carbide semiconductor device has a source electrode 1 formed on the semiconductor substrate and extending in the X direction. In FIG. 1, a plurality of source electrodes 1 extending in the X direction are arranged in the Y direction, and these source electrodes 1 are integrated via a source electrode 1 (not shown) covering the cell array on the plurality of source electrodes 1 arranged in a stripe shape, and are electrically connected to each other. The source electrode 1 is a p ++ The source electrode 1 is electrically connected to a potential fixing region 14, which is a type semiconductor region. In the following description, unless otherwise specified, the term "source electrode" refers to a portion (source plug) formed in a stripe shape in a plan view, and does not include the source electrode 1 on the plurality of stripe-shaped source electrodes 1.

[0018] One unit cell is made up of n ++The semiconductor device has a source region 6, which is a type semiconductor region, a potential clamping region 14 surrounding the periphery of the source region 6, and a trench 9 formed on the upper surface of the semiconductor substrate in contact with the source region 6 and the potential clamping region 14 in a plan view. A plurality of trenches 9 are formed in contact with the source region 6, aligned in the Y direction and the X direction. A gate electrode 2 is embedded inside each trench 9 via a gate insulating film 8. In the present application, the gate electrode 2 in the trench 9 may be referred to as a trench gate electrode. The source electrode 1 extends so as to straddle the source region 6 and the potential clamping region 14 surrounding the periphery of the source region 6. In other words, the source region 6 and the potential clamping region 14 are formed directly below the extending source electrode 1.

[0019] When the trench 9 and the potential clamping region 14 are spaced apart from each other, the trench 9 is entirely surrounded by the source region 6 in a planar view. In the structure shown in Fig. 1, one unit cell has both ends in the X direction in a planar view.

[0020] One unit cell includes one source region 6 and eight trenches 9 adjacent to the source region 6. That is, one unit cell has four trenches 9 arranged in the Y direction and four trenches 9 arranged in the Y direction in parallel to the four trenches 9 in the X direction. A source electrode 1 extending in the X direction is disposed between the trenches 9 adjacent to each other in the Y direction in one unit cell. Here, an example in which eight trenches 9 are arranged is described above, but the number and arrangement of the trenches 9 formed in the unit cell are not limited to this. In a plan view, a plurality of such unit cells are arranged in the Y direction, and are arranged while being inverted in the X direction. That is, the unit cells adjacent to each other in the X direction have a planar layout that is line-symmetrical with respect to the boundary line between them. In other words, the structures of the unit cells adjacent to each other in the X direction are line-symmetrical in a plan view.

[0021] Although the trench 9 here extends in the X direction, it does not necessarily have to extend in the X direction. However, by extending the trench 9 in the X direction, the channel width of the SiC power MISFET can be easily increased. In this embodiment, the island-shaped trench gate electrodes are arranged spaced apart from each other in the Y direction, so that by extending the trench 9 in the X direction, the channel width can be easily increased and the on-resistance of the SiC power MISFET can be reduced.

[0022] As shown in Fig. 2, the silicon carbide semiconductor device of the present embodiment has an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as a SiC epitaxial substrate or a semiconductor substrate). The SiC epitaxial substrate (semiconductor substrate) is an n-type semiconductor substrate that contains silicon carbide. + The epitaxial layer is a semiconductor layer containing SiC. The upper surfaces of the silicon carbide substrate and the semiconductor substrate are parallel to each other. FIG. 2 shows drift layer 4, which is an n-type semiconductor region that mainly constitutes the epitaxial layer, and below drift layer 4 is an n-type semiconductor region. + 2 shows a drain region 12 formed of a silicon carbide substrate of a type semiconductor region. That is, in FIG. 2, the portion shown as the drain region 12 is a silicon carbide substrate.

[0023] That is, a drain region 12 is formed in the semiconductor substrate, and a drift layer 4 is formed in the semiconductor substrate on and in contact with the drain region 12. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. The drift layer 4, the body layer 5, the source region 6, the accumulation layer formation region 7, the drain region 12, and the potential fixing region 14 are formed in the epitaxial layer. The drift layer 4, the source region 6, the accumulation layer formation region 7, and the drain region 12 are n-type semiconductor regions.

[0024] A drain electrode 3 is formed in contact with the lower surface of the drain region 12, that is, the lower surface of the semiconductor substrate. That is, the lower surface of the semiconductor substrate is covered with the drain electrode 3, and the drain electrode 3 is electrically connected to the drain region 12. The drain electrode 3 is made of a laminated conductor film containing, for example, gold (Au). A source region 6 is formed on the upper surface of the semiconductor substrate (upper surface of the epitaxial layer), and a body layer 5, which is a p-type semiconductor region, is formed between the source region 6 and the drift layer 4 in contact with the lower surface of the source region 6. That is, the body layer 5 is formed from the lower end of the source region 6 to the midway depth of the epitaxial layer (drift layer 4). The source region 6 has a higher n-type impurity concentration than both the drift layer 4 and the accumulation layer formation region 7 described below, and is electrically connected to the source electrode 1.

[0025] The lower surface of the body layer 5 and the upper surface of the drift layer 4 are in contact with each other. Here, in the epitaxial layer below the body layer 5, the drift layer 4 is formed from the lower surface of the body layer 5 to the lower surface of the epitaxial layer. That is, the lower surface of the drift layer 4 is in contact with the drain region 12, i.e., the silicon carbide substrate.

[0026] A trench 9 is formed from the upper surface of the semiconductor substrate (upper surface of the epitaxial layer) to a depth intermediate the drift layer 4. That is, the trench 9 penetrates the body layer 5 and reaches the upper surface of the drift layer 4. Below the source region 6, the side surface of the trench 9 is covered with the body layer 5 which is a p-type semiconductor region. The trench 9 is formed from the upper surface of the epitaxial layer (upper surface of the semiconductor substrate) to a depth intermediate the epitaxial layer below the lower end of the source region 6.

[0027] The gate electrode 2 is completely buried in the trench 9 via a gate insulating film 8. The gate electrode 2 in the trench 9 is formed on the source region 6 via an insulating film 10 and a gate insulating film 8. An insulating film 10 is formed on the semiconductor substrate adjacent to the trench 9, and the gate insulating film 8 is formed so as to cover the inner surface of the trench 9 as well as the side and upper surface of the insulating film 10. The gate electrode 2 is formed within the trench 9 and immediately above the insulating film 10. On the semiconductor substrate, the insulating film 10, the gate insulating film 8 and the gate electrode 2 are covered with an insulating film 11. The gate electrode 2 is made of, for example, a polysilicon film, and the gate insulating film 8 and the insulating film 11 are made of, for example, a silicon oxide film.

[0028] A source electrode 1 is formed in a contact hole penetrating an insulating film 11 on a semiconductor substrate and on the insulating film 11. The source electrode 1 completely filling the contact hole and the source electrode 1 on the insulating film 11 are integrated with each other. At the bottom of the contact hole, the source electrode 1 is connected to a potential fixing region 14. The gate insulating film 8 and the insulating film 11 are made of, for example, a silicon oxide film. The insulating film 10 is a film used as a hard mask when forming the trench 9 by an etching method, and is made of, for example, a silicon nitride film.

[0029] The potential clamping region 14 is formed on the upper surface of the semiconductor substrate adjacent to the source region 6 in the Y direction. That is, the potential clamping region 14 and the source region 6 are formed from the upper surface of the semiconductor substrate to a predetermined depth. The lower surface of the potential clamping region 14 contacts the upper surface of the body layer 5. The potential clamping region 14 has a higher p-type impurity concentration than the body layer 5. The source electrode 1 embedded in an opening (connection hole) of the insulating film 11 is connected to the upper surface of the potential clamping region 14. Since the body layer 5 is electrically connected to the source electrode 1 via the potential clamping region 14, a source voltage can be applied from the source electrode 1 to the body layer 5. The source electrode 1 is formed on the insulating film 11 and in the opening of the insulating film 11. In addition, in a portion not shown in FIG. 2, a gate pad electrically connected to the gate electrode (trench gate electrode) 2 is also formed on the insulating film 11 at a distance from the source electrode 1.

[0030] As one of the main features of this embodiment, an accumulation layer formation region 7, which is an n-type semiconductor region, is formed along the surface of the trench 9 in the epitaxial layer. The accumulation layer formation region 7 is continuously formed along the side and bottom surface of the trench 9 at a position separated from the source region 6. That is, the accumulation layer formation region 7 is formed below the lower end of the source region 6. Here, the side of the trench 9 has a taper with respect to the upper surface of the semiconductor substrate. The accumulation layer formation region 7 is a semiconductor region formed by implanting n-type impurities, for example, from a direction perpendicular to the upper surface of the semiconductor substrate in which the trench 9 is formed, so that the depth of the accumulation layer formation region 7 in the direction perpendicular to the side surface of the trench 9 is greater on the lower side than on the upper side of the trench 9. That is, the formation depth of the accumulation layer formation region 7 increases from the upper side to the lower side of the trench 9. The accumulation layer formation region 7 is, for example, a semiconductor region having a width of 20 to 300 nm from the side surface of the trench 9. The width of the accumulation layer formation region 7 from the side surface of the trench 9 depends on the taper angle of the trench 9 and the formation depth of the accumulation layer formation region 7, but is preferably 300 nm or less.

[0031] A lower end of the accumulation layer formation region 7 reaches the drift layer 4. In other words, a part of the accumulation layer formation region 7 is formed within the drift layer 4 and is in contact with the drift layer 4. Therefore, the accumulation layer formation region 7 and the drift layer 4 are electrically connected to each other.

[0032] Next, the operation of the SiC power MISFET of this embodiment will be described. The SiC power MISFET has at least a drain region 12, a source region 6, a body layer 5, and a gate electrode 2. A plurality of trenches 9 are formed in a line along the upper surface of the semiconductor substrate, and the drain region 12, the source region 6, the body layer 5, and the gate electrode 2 in the vicinity of each of these trenches 9 constitute a SiC power MISFET. In this SiC power MISFET, a low on-resistance is achieved by closely arranging a plurality of trenches.

[0033] When the SiC power MISFET is in an off state (hereinafter, may be referred to as an off state), a depletion layer extends from the body layer 5, and this depletion layer reaches the side surface of the trench 9. In FIG. 3, the outline of the depletion layer extending from the body layer 5 in the off state is shown by a dashed line. The SiC power MISFET is in the off state when, for example, the gate voltage Vg is 0 V. Note that while FIG. 3 shows the depletion layer near one side surface of the trench 9, the depletion layer near the other side surface of the trench 9 is omitted. Also, FIG. 3 omits illustration of the gate electrode 2 and the interlayer insulating film (insulating film 11).

[0034] Even if most of the side of trench 9 is covered with accumulation layer formation region 7, which is an n-type semiconductor region, as in this embodiment, the depletion layer extending from body layer 5 reaches the side of trench 9 during off-state, so that the breakdown voltage is maintained and no current flows. In order for the depletion layer to reach the side of trench 9 in this way, accumulation layer formation region 7 must be formed shallow and with a lower impurity concentration than source region 6. The n-type impurity concentration of accumulation layer formation region 7 is, for example, 10 18 cm -3 The following is the result.

[0035] On the other hand, when the SiC power MISFET is in an on state (hereinafter sometimes referred to as an on state), a channel is formed in the body layer 5 adjacent to the trench 9. Specifically, the channel is mainly formed on the surface of the trench 9. As a result, a current flows from the drain region 12 to the source region 6 via the drift layer 4, the accumulation layer formation region 7, and the body layer 5 in this order. The accumulation layer formation region 7 is a region where electrons, which are carriers, are accumulated when the SiC power MISFET is on. Therefore, a current flows more easily into the epitaxial layer when the SiC power MISFET is on, compared to a case in which the accumulation layer formation region 7 is not formed on the side surface of the trench 9.

[0036] As described above, the accumulation layer formation region 7 needs to be formed shallow and with a low impurity concentration so that the depletion layer extending from the body layer 5 during off-state crosses the accumulation layer formation region 7 and reaches the side surface of the trench 9. The shape of the accumulation layer formation region 7 and the relationship with the way the depletion layer spreads will be described with reference to FIGS. 3 to 5.

[0037] 3, a boundary point between the source region 6 and the body layer 5 on the side surface of the trench 9 is designated as CH1. A boundary point between a region where the depletion layer extending from the body layer 5 contacts the side surface of the trench 9 in the off state and a region below the region where the depletion layer is separated from the side surface of the trench 9 is designated as CH2. In other words, the point CH2 is the lower end point of the region where the depletion layer extending from the body layer 5 contacts the side surface of the trench 9 in the off state.

[0038] Here, the point JC is the closest point to point CH2 on the boundary surface between the body layer 5 and the drift layer 4. At this time, the width of the accumulation layer formation region 7, which is the distance on the line connecting point CH2 and point JC, is the same as the width of the depletion layer on the line passing through point CH2, that is, distance d. Point JC is a point on the junction surface between the accumulation layer formation region 7, which is an n-type semiconductor region, and the body layer 5, which is a p-type semiconductor region. Here, a part of the body layer 5 is also formed below point JC. In other words, the boundary between the body layer 5 and the drift layer 4 is located below point JC (on the drain region 12 side). That is, the bottom surface of the body layer 5 is located below point JC.

[0039] If the accumulation layer formation region 7 is formed too deep or if the impurity concentration of the accumulation layer formation region 7 is high, the depletion layer extending from the body layer 5 during off-state does not reach the side surface of the trench 9, and therefore point CH2 and point JC do not exist. In this case, the depletion layer does not reach the side surface of the trench 9, and therefore the withstand voltage of the SiC power MISFET cannot be maintained. In this embodiment, by setting the depth and impurity concentration of the accumulation layer formation region 7 so that a part of the body layer 5 is formed below point JC, it is possible to reduce the on-resistance of the SiC power MISFET while maintaining the withstand voltage.

[0040] Further, as shown in FIG. 4, a surface S1 indicated by a dashed line and a surface S2 indicated by a two-dot dashed line are defined. The surface S1 is a surface along the channel formation region. For example, the surface S1 is a surface passing through the points CH1 and CH2 and along the X direction. The surface S2 is a surface along the junction surface between the body layer 5 and the accumulation layer formation region 7 at the point JC. At this time, the angle between the surface S1 and the surface S2 is θ1. In FIG. 4, in order to make the dashed line indicating the surface S1 easier to understand, the dashed line is shifted toward the accumulation layer formation region 7 side from the side surface of the trench 9 and the point CH2, but in reality, the dashed line overlaps with the side surface of the trench 9 and the point CH2. This is the same for FIG. 5. In addition, FIG. 5 is a conceptual cross-sectional view, and in order to make the figure easier to understand, the gate electrode and the gate insulating film are omitted, and the hatching of the epitaxial layer is omitted.

[0041] As shown in FIG. 5, when angle θ1 is at its largest, trench 9 has a V-shape. Due to the nature of surface S2, angle θ2 between surface S2 and silicon carbide substrate (or semiconductor substrate) is never an obtuse angle, and is at most 90 degrees. Therefore, consider the case when angle θ3 between surface S1 and silicon carbide substrate (or semiconductor substrate) is at its smallest. When angle θ3 is at its smallest and angle θ2 is at its largest, angle θ1 between surface S1 and surface S2 is at its largest. Here, angle θ2 is set to its maximum value of 90 degrees.

[0042] At this time, the ratio of the depth Z of the trench 9 to the width X of the trench 9 is depth Z:width X=1:2. This is because the breakdown voltage of the SiC power MISFET decreases when the depth of the trench 9 is reduced, and the on-resistance of the SiC power MISFET increases when the width of the trench 9 is increased. When the side surface of the accumulation layer formation region 7 opposite to the trench 9 side is perpendicular to the semiconductor substrate, the maximum value of the angle θ1 is θ1=atan(1 / (2×0.5))=45°. Therefore, for example, the value of the angle θ1 is 45 degrees or less. A large angle θ1 indicates a large width of the trench 9. In other words, when the angle θ1 is large, the cell pitch becomes large, and therefore the number of trenches 9 that can be arranged in the semiconductor device decreases, resulting in a high on-resistance.

[0043] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. The polarities described below may be reversed between p-type and n-type.

[0044] First, a silicon carbide substrate (wafer), i.e., a SiC bulk substrate, is prepared. The surface orientation of the upper surface of the silicon carbide substrate is the Si surface, the C surface, or another surface orientation, and the off-angle of the upper surface is 4 degrees. The silicon carbide substrate may be a substrate produced using a sublimation method, a substrate produced using a solution method, a substrate produced using a gas growth method, or a substrate on which an epitaxial layer has already been deposited. Chemical mechanical polishing (CMP) may be performed prior to the epitaxial growth process described below. The n-type impurity concentration of the silicon carbide substrate is, for example, 1×10 18 cm -3 ~1×10 21 cm -3 Here, for example, 1×10 18 cm -3 The silicon carbide substrate may be of the 4H-SiC, 6H, or 3C crystal type. It is preferable to use a wafer having an off-angle on the upper surface, but an just-angled substrate may also be used.

[0045] Next, an epitaxial layer is formed on the silicon carbide substrate by an epitaxial growth process. That is, epitaxial growth is performed by heating SiH4 and C3H8 at a temperature of 1500°C or higher using H2 as a carrier gas. In this way, an epitaxial layer is formed on the silicon carbide substrate. The impurity concentration and film thickness of the epitaxial layer at this time vary depending on the device to be manufactured. The impurity concentration is, for example, 1×10 14 cm -3 ~1×10 18 cm -3 The thickness of the epitaxial layer is, for example, from several μm to several tens of μm. Also, a high-concentration buffer layer may be formed in the silicon carbide substrate before the epitaxial layer is formed. The impurity concentration of the buffer layer is 1×10 18 cm -3 This epitaxial layer is also called a drift layer 4.

[0046] Next, a process for forming an ion implantation region will be described. The p-type implantation ions are Al (aluminum) or B (boron). The n-type implantation ions are N (nitrogen) or P (phosphorus).

[0047] A p-type body layer, a p-type junction layer, and a p-type junction layer are formed from the top surface of the drift layer 4 to a predetermined depth in the drift layer 4. ++ A potential clamp region 14 of the type, and ++ The source region 6 and the body layer 5 are formed by ion implantation. The body layer 5 may be formed by epitaxial growth. The source region 6 and the potential fixing region 14 are in contact with the upper surface of the wafer (the upper surface of the semiconductor substrate) which is a SiC epitaxial substrate.

[0048] The body layer 5 is in contact with the source region 6 and is formed deeper than the source region 6. The body layer 5 is also electrically connected to the potential fixing region 14. Note that, although the minimum configuration for operating the SiC power MISFET has been described in this embodiment, a structure adding a function such as a termination region may also be fabricated.

[0049] Next, a carbon film is deposited around the silicon carbide substrate and the semiconductor substrate made of the epitaxial layer as a cap material for the impurity activation annealing. Then, the impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. The carbon layer of the cap material is then removed by oxygen plasma ashing. This annealing has the effect of preventing the surface of the semiconductor substrate from becoming rough. After that, in order to obtain a cleaner surface, a thermal oxide film may be formed to cover the surface of the semiconductor substrate, and then the thermal oxide film may be removed using a diluted hydrofluoric acid solution.

[0050] Next, the steps of forming trench 9, accumulation layer formation region 7, and gate electrode 2 will be described.

[0051] Here, a trench 9 is formed on the upper surface of the semiconductor substrate by etching using the insulating film 10 as a hard mask, so that the trench 9 penetrates the source region 6 and the body layer 5 and has a bottom within the drift layer. After this, a process for cleaning the etched surface may be performed. For example, this process involves forming a thermal oxide film that covers the surface of the semiconductor substrate including the surface of the trench 9, and then removing the thermal oxide film using a diluted hydrofluoric acid solution.

[0052] Next, an n-type accumulation layer formation region 7 is formed. The formation method may be, for example, ion implantation, etc. The accumulation layer formation region 7 is a semiconductor region having a width of 20 to 300 nm from the side surface of the trench 9.

[0053] Next, a carbon film is deposited inside and around the trench 9 as a cap material for impurity activation annealing. The thickness of the deposited film at this time is, for example, 50 to 2000 nm. Thereafter, impurity activation annealing is performed at a temperature of, for example, 1600 to 1800° C. Thereafter, the carbon layer of the cap material is removed by oxygen plasma ashing. Thereafter, in order to obtain a cleaner surface, a thermal oxide film may be formed to cover the surface of the semiconductor substrate, and then the thermal oxide film may be removed using a diluted hydrofluoric acid solution.

[0054] Next, a gate insulating film 8 is formed on the semiconductor substrate. The thickness of the gate insulating film 8 is, for example, about 10 to 100 nm. The gate insulating film is made of, for example, a deposited oxide insulating film. Next, a gate electrode 2 is formed of an n-type polycrystalline silicon film having a thickness of about 100 to 300 nm. Thereafter, an insulating film 11, which is an interlayer film, is formed so as to cover the gate electrode 2.

[0055] Next, a contact hole for contacting the source region 6 and the potential fixing region 14 is opened in the insulating film 11. That is, the insulating film 11 is etched using a resist pattern formed on the insulating film 11 as a mask to form a contact hole (opening) exposing the upper surface of the semiconductor substrate. Next, a metal film for silicide is deposited on the semiconductor substrate, and silicide is performed by, for example, annealing at 700°C to 1000°C, thereby forming a silicide layer (not shown) that contacts the upper surface of the semiconductor substrate at the bottom of the contact hole over the upper surfaces of the source region 6 and the potential fixing region 14. The silicide layer is a source-base common contact. After that, a contact hole for contacting the gate electrode 2 is opened in the insulating film 11. That is, the insulating film 11 is etched using a resist pattern formed on the insulating film 11 as a mask to form a contact hole (opening) exposing the upper surface of the gate electrode 2.

[0056] Next, the source electrode 1 is formed by filling the connection hole on the source region 6 of the insulating film 11 and covering the upper surface of the insulating film 11. Thereafter, the lower surface of the drain region 12 on the lower surface side of the semiconductor substrate is also silicided to form a drain contact, and then the drain electrode 3 is formed. For the silicide metal film, the source electrode 1, and the drain electrode 3, materials such as Ni (nickel) or Al (aluminum) are used. Then, the entire surface of the semiconductor substrate is covered with a surface protection film made of an insulator to protect the device. Then, a process of wiring each electrode is performed, and the semiconductor device of this embodiment is completed.

[0057] <Effects of this embodiment> In the semiconductor device of this embodiment, when the SiC power MISFET is in an on state, a channel is formed in the semiconductor substrate adjacent to the trench 9, and a current flows through the channel. At this time, the accumulation layer formation region 7 is formed in the channel formation region, and the accumulation layer formation region 7 forms a carrier accumulation layer when on, so that a current flows more easily through the epitaxial layer when on compared with the case where the accumulation layer formation region 7 is not formed. Therefore, the on-resistance of the SiC power MISFET can be reduced.

[0058] On the other hand, when the SiC power MISFET is in an off state, a depletion layer extending from the body layer 5 crosses the accumulation layer formation region 7 and reaches the side surface of the trench 9, so that the breakdown voltage of the SiC power MISFET can be maintained. Moreover, most of the trench 9 is formed in the body layer 5, so that electric field concentration in the gate insulating film 8 in the trench 9 can be alleviated. Moreover, in this case, the upper end of the accumulation layer formation region 7 does not reach the source region 6, so that the breakdown voltage can be increased compared to the case where the upper end of the accumulation layer formation region 7 reaches the source region 6.

[0059] Here, the mutual relationship between the on-resistance and the breakdown voltage will be explained with reference to Figs. 6 and 7. Fig. 6 is a graph showing the relationship between the concentration of the accumulation layer formation region and the on-resistance and the breakdown voltage, with the horizontal axis showing the impurity concentration of the accumulation layer formation region and the vertical axis showing the respective reduction rates of the on-resistance and the breakdown voltage. Among the plots shown in Fig. 6, the circular plots show the on-resistance values, and the triangular plots show the breakdown voltage values. Fig. 7 is a graph showing the relationship between the breakdown voltage and the on-resistance, with the horizontal axis showing the breakdown voltage and the vertical axis showing the on-resistance.

[0060] It is desirable for the on-resistance of a SiC power MISFET to be low and for the breakdown voltage to be high, but there is a trade-off between the on-resistance and the breakdown voltage. 18 cm -3 2, the n-type impurity concentration of the accumulation layer formation region 7 shown in FIG. 2 is 1018 cm -3 It is preferable that:

[0061] 7 is a graph showing the relationship between the breakdown voltage and on-resistance of the SiC power MISFET of the comparative example (plotted with x in FIG. 7) and the relationship between the breakdown voltage and on-resistance of the SiC power MISFET of this embodiment (plotted with squares in FIG. 7). The SiC power MISFET of the comparative example differs from the structure shown in FIG. 2 in that it does not have an accumulation layer formation region and the bottom of the trench reaches the drift layer.

[0062] As shown in Fig. 7, basically, when the breakdown voltage increases, the on-resistance also increases. Here, in order to reduce the on-resistance in the SiC power MISFET of the comparative example, it is necessary to significantly reduce the breakdown voltage. In contrast, in the SiC power MISFET of the present embodiment, when the breakdown voltage is close to 1, the on-resistance can be reduced by about 20% with almost no change in the breakdown voltage. In this way, with the silicon carbide semiconductor device of the present embodiment, it is possible to achieve both a reduction in on-resistance and an assurance of the breakdown voltage.

[0063] <Modification> A modified example of the present embodiment will be described below with reference to Fig. 8. The structure of this modified example differs from the structure described with reference to Figs. 1 to 5 in that the bottom surface of trench 9 does not reach drift layer 4.

[0064] That is, here, the trench 9 is formed from the upper surface of the semiconductor substrate (the upper surface of the epitaxial layer) to the middle depth of the body layer 5. That is, the trench 9 does not penetrate the body layer 5 and does not reach the upper surface of the drift layer 4. In other words, the bottom surface (lowest surface) of the trench 9 and the upper surface (uppermost surface) of the drift layer 4 are separated from each other in a direction perpendicular to the upper surface of the semiconductor substrate. That is, the position of the lowermost surface of the trench 9 is higher than the position of the uppermost surface of the drift layer 4. Therefore, under the source region 6, the side surface and bottom surface of the trench 9 are covered with the body layer 5 which is a p-type semiconductor region. In addition, the corner portion which is the boundary portion between the side surface and the bottom surface of the trench 9 is also covered with the body layer 5.

[0065] The accumulation layer formation region 7 covering the side surface of the trench 9 is in contact with the drift layer 4. That is, the accumulation layer formation region 7 and the drift layer 4 are electrically connected. A JFET (Junction Field Effect Transistor) region 13 is formed in the region between the accumulation layer formation region 7 and the drift layer 4. When on, a current flows from the drift layer 4 through the JFET region 13 in the accumulation layer formation region 7 and the accumulation layer of the accumulation layer formation region 7 in this order, through the inversion layer of the body layer 5, and to the source region 6.

[0066] In this modification, when the SiC power MISFET is on, a current passes through the accumulation layer formation region 7, thereby reducing the on-resistance of the SiC power MISFET. On the other hand, when the SiC power MISFET is off, a depletion layer extending from the body layer 5 crosses the accumulation layer formation region 7 and reaches the side surface of the trench 9, thereby maintaining the breakdown voltage of the SiC power MISFET.

[0067] In addition, since the width of the JFET region 13 can be made very narrow, the breakdown voltage is increased. Moreover, since the corners of the trench 9 are in the body layer 5, electric field concentration at the corners is alleviated. The length W of the accumulation layer formation region 7 in the drift layer 4 is, for example, 0 to 500 nm, and from the viewpoint of increasing the breakdown voltage, a smaller length W is preferable because a depletion layer extends under the gate insulating film 8, thereby increasing the breakdown voltage.

[0068] (Embodiment 2) The structure of the silicon carbide semiconductor device according to the second embodiment will be described with reference to Figures 9 and 10. In Figure 9, an extended portion that is a part of the source electrode is shown as a structure on the semiconductor substrate, but the insulating film and part of the gate electrode that are structures on the semiconductor substrate are omitted. In Figure 10, for ease of understanding, the insulating films (gate insulating film and interlayer insulating film) and gate electrode are partially omitted.

[0069] As shown in FIG. 9, the cell array constituting the silicon carbide semiconductor device of this embodiment has a configuration in which a plurality of unit cells, each having a predetermined planar layout, are arranged in a matrix. In FIG. 9, one unit cell is surrounded by a dashed line. The silicon carbide semiconductor device is formed on a semiconductor substrate, and has a source electrode 1 extending in the Y direction. In FIG. 9, a plurality of source electrodes 1 extending in the Y direction are arranged in the X direction, and these source electrodes 1 are integrated via a source electrode 1 (not shown) that covers the cell array on the plurality of source electrodes 1 arranged in a stripe shape, and are electrically connected to each other. The source electrode 1 is formed on a p ++ The source electrode 1 is electrically connected to a potential fixing region 14, which is a type semiconductor region. In the following description, unless otherwise specified, the term "source electrode" refers to a portion (source plug) formed in a stripe shape in a plan view, and does not include the source electrode 1 on the plurality of stripe-shaped source electrodes 1.

[0070] One unit cell is made up of n ++ The semiconductor device has a source region 6, which is a type semiconductor region, a potential clamping region 14 surrounding the periphery of the source region 6, and a trench 9 formed on the upper surface of the semiconductor substrate in contact with the source region 6 and the potential clamping region 14 in a plan view. The trenches 9 are formed in a line in the Y direction at the boundary between the source region 6 and the potential clamping region 14 extending in the Y direction. In FIG. 9, the region in which the trenches 9 are lined up in the Y direction is surrounded by a dashed line. The region surrounded by the dashed line is a trench formation region in which the trenches 9 are lined up in a stripe shape. A gate electrode 2 is embedded inside each trench 9 via a gate insulating film 8. The source electrode 1 extends so as to straddle the source region 6 and the potential clamping region 14 surrounding the periphery of the source region 6. In other words, the source region 6 and the potential clamping region 14 are formed directly under the extending source electrode 1.

[0071] One unit cell comprises regions 1A and 1B aligned in the Y direction. Region 1B is formed at the end of the unit cell in the Y direction. Region 1A is a portion in which an element that operates as a MISFET is formed, and region 1B is a region that electrically connects the p-type semiconductor region and source electrode 1 to apply a source voltage to the p-type semiconductor region that constitutes the element. Here, source region 6 and trench 9 are formed only in region 1A, and source electrode 1 is connected to p-type semiconductor region 1B in region 1B. ++ The potential fixing region 14 is electrically connected to the potential fixing region 14 which is a type semiconductor region.

[0072] When the trench 9 and the potential fixing region 14 are separated from each other, the trench 9 is entirely surrounded by the source region 6 in a plan view, and for example, the source regions 6 of unit cells adjacent to each other in the X direction are connected to each other.

[0073] 9, one unit cell has both ends in the X direction in plan view, the source electrode 1 is located at one of the ends, and a potential fixing region 14 is formed on the upper surface of the epitaxial layer at the other of the ends. That is, in plan view, of both ends in the X direction of the unit cell, the end opposite to the end where the source electrode 1 is formed is separated from the source region 6. Therefore, in the X direction, the source regions 6 are connected between the first unit cell and the second unit cell adjacent to it on one side, and the source regions 6 are separated from each other between the first unit cell and the third unit cell adjacent to it on the other side.

[0074] One unit cell occupies a range from the center of one of two source electrodes 1 adjacent to each other in the X direction to the middle between the source electrodes 1. One unit cell occupies a range consisting of one adjacent source region 6 and one potential clamp region 14 among source regions 6 and potential clamp regions 14 arranged alternately in the Y direction. In plan view, a plurality of such unit cells are arranged in the Y direction, and are arranged while being inverted in the X direction. In other words, the unit cells adjacent to each other in the X direction have a planar layout that is line-symmetrical with respect to the boundary line between them. In other words, the structures of the unit cells adjacent to each other in the X direction are line-symmetrical in plan view.

[0075] Although the trench 9 here extends in the X direction, it does not necessarily have to extend in the X direction. However, by extending the trench 9 in the X direction, the channel width of the SiC power MISFET can be easily increased. It is difficult to increase the channel width in a trench-type MOSFET in which the trench gate electrode extends in the Y direction like the source electrode 1. In contrast, in this embodiment, the island-shaped trench gate electrodes are arranged spaced apart from each other in the Y direction, so that the channel width can be easily increased by extending the trench 9 in the X direction, and the on-resistance of the SiC power MISFET can be reduced.

[0076] As shown in Fig. 10, the silicon carbide semiconductor device of this embodiment has an n-type silicon carbide (SiC) epitaxial substrate (semiconductor substrate). A drain region 12 is formed in the semiconductor substrate, and a drift layer 4 is formed on and in contact with the drain region 12 in the semiconductor substrate. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. The drift layer 4, the body layer 5, the source region 6, the accumulation layer formation region 7, the current diffusion region 17, the guard region 18, the drain region 12, the JFET region 13, and the potential fixing region 14 are formed in the epitaxial layer.

[0077] A drain electrode 3 is formed in contact with the lower surface of the drain region 12, i.e., the lower surface of the semiconductor substrate. A source region 6 is formed on the upper surface of the semiconductor substrate (the upper surface of the epitaxial layer), and a body layer 5, which is a p-type semiconductor region, is formed between the source region 6 and the drift layer 4 in contact with the lower surface of the source region 6. The source region 6 has a higher n-type impurity concentration than a current diffusion region 17 described below, and is electrically connected to the source electrode 1.

[0078] Below the body layer 5, in contact with the lower surface of the body layer 5, + A current diffusion region 17, which is a type semiconductor region, is formed. A drift layer 4 is formed below the source electrode 1 extending in the Y direction, in a region adjacent to the current diffusion region 17 in the X direction. Here, in the epitaxial layer below the body layer 5, the drift layer 4 is formed from the lower surface of the body layer 5 to the lower surface of the epitaxial layer. That is, the lower surface of the drift layer 4 is in contact with the drain region 12, i.e., the silicon carbide substrate. In the unit cell, the current diffusion region 17 is formed to surround the trench 9 in a plan view.

[0079] The current diffusion region 17 is a low-resistance region for diffusing the current flowing in the drift layer 4 in the X direction and flowing the current in a wide region. That is, by forming the current diffusion region 17, it is possible to prevent the current from flowing locally. The current diffusion region 17 is formed in the region 1A shown in FIG. 9, but is not formed in the region 1B. That is, the region 1B is separated from the source region 6 and the current diffusion region 17 in a planar view. In other words, the region 1B does not overlap with the source region 6 and the current diffusion region 17 in a planar view.

[0080] A guard region 18, which is a p-type semiconductor region, is formed below the current diffusion region 17 and in contact with the lower surface of the current diffusion region 17. A trench 9 is formed from the upper surface of the semiconductor substrate (upper surface of the epitaxial layer), i.e., the upper surface of the body layer 5 of the source region 6, to a mid-depth of the guard region 18. In other words, the trench 9 penetrates the body layer 5 and does not reach the lower surface (lower end) of the guard region 18. In other words, the bottom surface of the trench 9 and the lower surface (lower end) of the guard region 18 are spaced apart from each other.

[0081] Since the bottom surface of trench 9 is located deeper than the top surface (upper end) of guard region 18, the lower ends of each of the four side surfaces of trench 9, which has a rectangular planar shape, contact guard region 18. That is, the four sides and four corners of the bottom surface of trench 9 are all covered by guard region 18. In other words, the bottom surface and the four side surfaces of trench 9 are continuously in contact with guard region 18. That is, trench 9 is surrounded by guard region 18 in plan view. In this manner, trench 9 is formed from the top surface of the epitaxial layer to a depth of the epitaxial layer below body layer 5.

[0082] Between the guard region 18 and the body layer 5, the four side surfaces of the trench 9 are in contact with the current spreading region 17 via the accumulation layer formation region 7. Therefore, when the SiC power MISFET is in an on-state, a channel can be formed on all of the four side surfaces of the trench 9.

[0083] A drift layer 4 is formed in a region adjacent to the guard region 18 in the X direction and directly below the source electrode 1 extending in the Y direction. A part of the drift layer 4 formed in the region adjacent to the guard region 18 in the X direction overlaps with the current diffusion region 17 in a plan view. That is, the drift layer 4 and the guard region 18 are arranged side by side in the X direction directly below the current diffusion region 17. That is, in a plan view, the end of the current diffusion region 17 on the source electrode 1 side is located closer to the source electrode 1 than the end of the guard region 18 on the source electrode 1 side.

[0084] As a result, in a region adjacent to the drift layer 4 in the X direction immediately below the source electrode 1, a layer made of the current diffusion region 17 and a layer made of the guard region 18 are formed to overlap each other in the vertical direction. The guard region 18 has a higher p-type impurity concentration than the body layer 5. The current diffusion region 17 and the guard region 18 are in contact with each other. Therefore, the body layer 5 and the guard region 18 are electrically connected to each other. By covering the bottom surface and corners of the trench 9 with the guard region 18 having a higher p-type impurity concentration than the body layer 5, the electric field concentration at the corners of the trench 9 can be further alleviated compared to the first embodiment.

[0085] A plurality of trenches 9 are formed in line in the Y direction, and a gate electrode 2 is completely embedded in each trench 9 via a gate insulating film 8. The gate electrodes 2 in each trench 9 are formed on the source region 6 via the gate insulating film 8, and are connected to each other by the gate electrodes 2 extending in the Y direction. That is, in a cross section along the Y direction, the gate electrodes 2 have a comb-like structure. That is, the trench gate electrodes aligned in the Y direction are connected in parallel to each other by the gate electrodes 2 above them. The lower surface, side surfaces, and upper surface of the gate electrode 2 extending in the Y direction on the source region 6 are covered with an insulating film 11.

[0086] A source electrode 1 is formed in a connection hole penetrating an insulating film 11 on a semiconductor substrate and on the insulating film 11. The source electrode 1 completely filling the connection hole and the source electrode 1 on the insulating film 11 are integrated with each other. In FIG. 10, in order to make it easier to understand the shape of the source electrode 1 in the connection hole extending in the Y direction, a part of the source electrode 1 directly above the source electrode 1 extending in the Y direction and a part of the source electrode 1 on the insulating film 11 are not shown. At the bottom of the connection hole, the source electrode 1 is connected to a potential fixing region 14.

[0087] The potential clamping region 14 is formed adjacent to the source region 6 in the Y direction. The lower surface of the potential clamping region 14 is in contact with the upper surface of the body layer 5. The potential clamping region 14 has a higher p-type impurity concentration than both the body layer 5 and the guard region 18. Since the guard region 18 is electrically connected to the source electrode 1 via the body layer 5 and the potential clamping region 14, a source voltage can be applied from the source electrode 1 to the guard region 18. In addition, since the body layer 5 is electrically connected to the source electrode 1 via the potential clamping region 14, a source voltage can be applied from the source electrode 1 to the body layer 5.

[0088] In this embodiment, the side of the trench 9 is formed at an angle with respect to the upper surface of the semiconductor substrate, and an accumulation layer formation region 7 that continuously covers the side and bottom of each trench 9 is formed in the epitaxial layer below the source region 6. Here, the bottom of the trench 9 is located below the lowermost surface of the current diffusion region 17 and reaches into the guard region 18. The bottom of the accumulation layer formation region 7 is located in the guard region 18, and the accumulation layer formation region 7 does not reach the drift layer 4 below the guard region 18. However, the accumulation layer formation region 7 formed on the side of the trench 9 is in contact with the current diffusion region 17 and is electrically connected to the drift layer 4 and the drain region 12 via the current diffusion region 17.

[0089] In the present embodiment, as in the first embodiment, a point CH1 can be defined as a contact point between the trench 9 and the bottom surface of the source region 6, and a boundary point between the accumulation layer formation region 7 and a region where a depletion layer extending from the body layer 5 contacts the side surface of the trench 9 during off-state and a region where the depletion layer is separated from the side surface of the trench 9 can be defined as CH2 (see FIG. 3). In addition, a point on the boundary surface between the body layer 5 and the accumulation layer formation region 7 that is closest to the point CH2 can be defined as a point JC (see FIG. 3). Here, although not shown in FIG. 10, the point JC is located above the bottom surface of the body layer 5. In other words, the body layer 5, which is a p-type semiconductor region, is formed below the point JC. In addition, the guard region 18, which is a p-type semiconductor region, is also formed below the point JC.

[0090] In Fig. 9, four unit cells arranged in the X direction are shown, and each unit cell is surrounded by a dashed line. As shown in Fig. 9, each of the unit cells adjacent to each other in the X direction has a structure inverted with respect to the boundary between the unit cells. Each unit cell is composed of a drain electrode 3, a drift layer 4, a body layer 5, a source region 6, a current diffusion region 17, a guard region 18, a JFET region 13, a trench 9, an insulating film 11, a gate electrode 2, a source electrode 1, and a potential fixing region 14 (see Fig. 9).

[0091] Unit cells adjacent to each other in the X direction share the source electrode 1 extending in the Y direction. Therefore, when each of the striped source electrodes 1 is formed with the minimum possible width, the cell pitch of the unit cells in the X direction can be reduced compared to when all the unit cells are arranged without being inverted in the X direction.

[0092] As shown in FIG. 10, in the drift layer 4 below the current diffusion region 17, the JFET region 13, which is an n-type or n-type semiconductor region, is formed alongside the guard region 18 in the X direction. Specifically, directly below the current diffusion region 17, the JFET region 13 is adjacent to the guard region 18, and a part of the JFET region 13 is adjacent to the current diffusion region 17 in the X direction. The JFET region 13 extends in the Y direction directly below the source electrode 1. That is, here, the source electrode 1, the trench formation region in which a plurality of trenches 9 are aligned (see FIG. 9), and the JFET region 13 extend in the Y direction in parallel with each other. In FIG. 10, the lower end of the JFET region 13 is indicated by a dashed line.

[0093] The n-type impurity concentration of the JFET region 13 is equal to or higher than the n-type impurity concentration of the drift layer 4. The n-type impurity concentration of the JFET region 13 is lower than the n-type impurity concentrations of the current diffusion region 17 and the source region 6. The JFET region 13 is a region between the guard regions 18 adjacent to each other in the X direction. That is, the JFET region 13 is a region where depletion layers extend from the opposing side surfaces of the adjacent guard regions 18 when the SiC power MISFET is in an off state, and these depletion layers contact each other. The presence of a plurality of guard regions 18 arranged in the X direction and the JFET region 13 between them makes it possible to maintain and control the withstand voltage.

[0094] When the SiC power MISFET of this embodiment is on, a current flows in the order of the drain electrode 3, the drain region 12, the drift layer 4, the JFET region 13, the current diffusion region 17, the accumulation layer formation region 7, the inversion layer of the body layer 5, the source region 6, and the source electrode 1. In Fig. 10, this current path is indicated by a thick arrow.

[0095] In this embodiment, the trench formation region, the source electrode 1 (conductive connection portion), and the JFET region 13 all extend in the same Y direction, and are formed in a stripe shape in a plan view. Here, the source electrode 1 and the JFET region 13 are arranged so as to overlap in a plan view, and extend in the Y direction with each other. That is, in the unit cell, a trench 9 is not formed between the source electrode 1 and the JFET region 13 in a plan view. Therefore, it is easier to miniaturize the unit cell compared to the case where the source electrode, the trench, and the JFET region are arranged in order in a plan view. In this way, the SiC power MISFET of this embodiment has the trench formation region, the source electrode 1 (conductive connection portion), and the JFET region 13 all extending in the same Y direction, and is provided with a plurality of trenches, current diffusion regions, and guard regions arranged in a stripe shape in the trench formation region. In such a SiC power MISFET, the same effect as that of the first embodiment can be obtained.

[0096] (Embodiment 3) 11, the accumulation layer formation region 7 formed along the side surface of the trench 9 may reach the bottom surface of the source region 6. In this case, the entire side surface of the trench 9 between the source region 6 and the drift layer 4 is covered with the accumulation layer formation region 7. Therefore, the trench 9 and the body layer 5, which is a p-type semiconductor region, are separated from each other with the accumulation layer formation region 7 therebetween. However, even if the accumulation layer formation region 7 is in contact with the source region 6 and the drift layer 4 in this way, as described in the first embodiment, when the SiC power MISFET is turned off, the depletion layer extending from the body layer 5 reaches the surface of the trench 9 via the accumulation layer formation region 7, so that the breakdown voltage is maintained.

[0097] In the semiconductor device of the third embodiment, when the SiC power MISFET is in an on state, a channel (inversion layer) is formed in the semiconductor substrate adjacent to the trench 9, and a current flows through the channel. At this time, the accumulation layer formation region 7 is formed on the side surface of the trench 9 excluding the channel, and since the accumulation layer formation region 7 forms an accumulation layer of carriers when on, a current easily flows into the epitaxial layer when on, compared with the case where the accumulation layer formation region 7 is not formed. Therefore, the on-resistance of the SiC power MISFET can be reduced. Also, since the accumulation layer formation region 7 is in contact with the source region 6, the on-resistance can be reduced compared with the first embodiment.

[0098] On the other hand, when the SiC power MISFET is in an off state, the depletion layer extending from the body layer 5 crosses the accumulation layer formation region 7 and reaches the side surface of the trench 9, so that the withstand voltage of the SiC power MISFET can be maintained. In addition, since most of the trench 9 is formed in the body layer 5, electric field concentration in the gate insulating film 8 in the trench 9 can be alleviated.

[0099] The invention made by the present inventors has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0100] For example, the materials, conductivity types, and manufacturing conditions of each part are not limited to those described in the above-mentioned embodiment, and it goes without saying that many variations are possible. Here, for convenience of explanation, the conductivity types of the semiconductor substrate and the semiconductor film have been fixed, but they are not limited to the conductivity types described in the above-mentioned embodiment.

[0101] Although an n-type SiC power MISFET has been described in the first to third embodiments, the effects of the first to third embodiments can also be obtained in a p-type SiC power MISFET in which the conductivity type of each semiconductor region is inverted. The third embodiment may be combined with a modified example of the first embodiment. [Explanation of symbols]

[0102] 1. Source electrode 2. Gate electrode 3 Drain electrode 4. Drift Layer 5. Body Layer 6 Source Area 7 Accumulation layer formation region 8 Gate insulation 9. Trench 11. Insulating film 12 Drain Region 13 JFET area 14 Potential fixing region 17 Current spreading region 18 Guard Area

Claims

1. a silicon carbide semiconductor substrate of a first conductivity type; a semiconductor layer of the first conductivity type formed on the silicon carbide semiconductor substrate and containing silicon carbide; a first semiconductor region of the first conductivity type formed on an upper surface of the semiconductor layer; a second semiconductor region of a second conductivity type different from the first conductivity type, the second semiconductor region being formed in the semiconductor layer from a lower end of the first semiconductor region to a midway depth of the semiconductor layer; a third semiconductor region of the first conductivity type formed in the semiconductor layer below the second semiconductor region; a trench formed from the upper surface of the semiconductor layer to a depth of the semiconductor layer below the lower end of the first semiconductor region; a gate electrode formed on the inner side of the trench via an insulating film; a fourth semiconductor region of the first conductivity type formed in the silicon carbide semiconductor substrate; a fifth semiconductor region of the first conductivity type formed in the semiconductor layer below the lower end of the first semiconductor region and continuously contacting a side surface and a bottom surface of the trench; having the first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor; a first point is a boundary between a first region, in which a depletion layer extending from the second semiconductor region contacts the side of the trench when the field effect transistor is off, and a second region below the first region, in which the depletion layer is spaced from the side of the trench, and a second point is a point on a boundary surface between the second semiconductor region and the fifth semiconductor region that is closest to the first point, wherein a portion of the second semiconductor region is located below the second point.

2. 2. The silicon carbide semiconductor device according to claim 1, The fifth semiconductor region is in contact with the third semiconductor region.

3. 2. The silicon carbide semiconductor device according to claim 1, A silicon carbide semiconductor device, wherein the trench reaches into the third semiconductor region.

4. 2. The silicon carbide semiconductor device according to claim 1, The trench is spaced from the third semiconductor region.

5. 2. The silicon carbide semiconductor device according to claim 1, a conductive connection portion formed on the semiconductor layer, extending in a first direction in a plan view, and electrically connected to the first semiconductor region; a sixth semiconductor region of the first conductivity type formed in the third semiconductor region and extending in the first direction; a seventh semiconductor region of the second conductivity type formed in the third semiconductor region, covering a corner portion that is an end portion of the bottom surface of the trench in a region adjacent to the sixth semiconductor region; an eighth semiconductor region of the first conductivity type formed in the third semiconductor region on the seventh semiconductor region so as to surround the trench in a plan view and having an impurity concentration higher than that of the third semiconductor region; and In a plan view, the trenches are arranged in a plurality of rows in the first direction, Each of the plurality of trenches extends in a second direction intersecting the first direction in a plan view.

6. 2. The silicon carbide semiconductor device according to claim 1, A silicon carbide semiconductor device, wherein an upper end of the fifth semiconductor region is in contact with the first semiconductor region.

7. 2. The silicon carbide semiconductor device according to claim 1, a fifth semiconductor region having a lower impurity concentration of the first conductivity type than a first semiconductor region having a lower impurity concentration of the first conductivity type; 8. The silicon carbide semiconductor device according to claim 1, a top end of the fifth semiconductor region does not reach the first semiconductor region.

Images