Semiconductor substrate with n-doped intermediate layer

Abstract

The present invention relates to a method for producing a monocrystalline semiconductor material comprising a group 13 element nitride, the method comprising the steps of: a) epitaxially depositing a first layer of group 13 element nitride, preferably gallium nitride, on a starting substrate; b) supplying a dopant gas n to epitaxially deposit a second layer of group 13 element nitride, preferably gallium nitride, on the first layer, the deposition including recessed regions of material; and c) terminating the supply of dopant gas and epitaxially depositing a third layer of group 13 element nitride, preferably gallium nitride, on the previously doped layer.

Description

[Technical field]

[0001] The present invention relates to the general technical field of manufacturing substrates and wafers made of semiconductor materials based on elements of groups 13 and 15 of the periodic table, such as gallium nitride GaN.

[0002] These wafers are used as substrates for the production of semiconductor structures such as light emitting diodes (LEDs), laser diodes (LDs), vertical transistors for power electronics, lateral transistors for power electronics or telecommunications (radio frequencies), current rectifying diodes or sensors. [Background technology]

[0003] Current processes for producing semiconductor material substrates based on nitrides of group 13 or group IIIA elements are based on gas phase deposition techniques, in particular the heteroepitaxy technique, in which crystals such as gallium nitride GaN crystals are grown on starting substrates of different nature, for example sapphire substrates.

[0004] These methods involve a system for injecting at least two different gas components that are capable of interacting prior to deposition.

[0005] For example, the following known methods can be mentioned. Metal-organic vapor phase epitaxy (MOVPE) Hydride Vapor Phase Epitaxy (HVPE) Closed-space vapor transport (CSVT) ·Ceramic Vapor Deposition

[0006] So-called 3D growth processes, i.e. lateral growth in three dimensions, can reduce dislocation densities to 10 7 / cm 2 can be reduced to less than

[0007] Under three-dimensional growth conditions, the HVPE growth front has facets perpendicular to the growth front and facets tilted to the growth front. The facets perpendicular to the growth front are those formed by the basal plane (0001), which are known to contain less oxygen than the various tilted facets that may exist (non-basal planes, with indices hkil: h≠0 and k≠0 and i≠0). This difference in n-type doping results in regions that are more resistive than others or that have different optical properties. After shaping to obtain a two-dimensional surface, for example by grinding and / or polishing, non-uniform optical and / or electrical properties can be observed.

[0008] The crystal lattice may also have macroscopic inclusions of a size greater than 10 μm, mainly consisting of twins, poled crystals or even polycrystals.

[0009] Moreover, regardless of the process in 3D or 2D growth mode, defects or contamination of the starting substrate are inevitable, resulting in depressions of the material larger than 100 μm, called pits. This type of defect, especially permanent depressions or pits, has a cross section that decreases in the direction opposite to the growth direction, and their width and depth also increase as the thickness of the deposit increases. These depressions form inverted macropyramids with a width of several hundred micrometers. At the apex of these depressions, the crystalline matrix may show crystalline defects and high dislocation densities.

[0010] Any of these defects occurring during growth can induce imperfections in the final wafer (doping non-uniformities and crystal defects, high dislocation density), which can lead to failures in the fabrication of electronic and / or optoelectronic components.

[0011] To improve the electronic properties of the substrate, US2006255339A1 proposes a 0.7×10 18 ~Approx. 3×10 18 / cm 3and a thermal conductivity of at least 1.5 W / cm.K. In this application, only the example of Si doping is described, but dopants such as Si, O, Ge, C, etc. can be used alone or in combination.

[0012] US20110175200A1 presents a HVPE growth process in which the crystals are doped with Ge by adding GeCl4 in the reactor to obtain more electronically conductive crystals, compensating for the sharp increase in resistivity observed at growth rates higher than 450 μm / h. However, such growth rates increase the surface concentration of macroscopic inclusions, degrading the crystal quality.

[0013] US9461121B2 claims a process for improving the distribution of n-dopants in typically vapor-grown GaN crystals by mixing the Ga and dopant inputs. Uniform incorporation in the reactor is achieved by premixing the dopant and Ga prior to reaction with HCl or by mixing the dopant and gallium halide in a single tube in the reactor. The uniformity of the dopant concentration is measured by micro-Raman, microwave-detected photoconductivity (MDP) or micro-photoluminescence. From the described level of uniformity and method data, it is clear that the patent is a HVPE process with 2D growth and therefore does not present a solution for 3D growth processes. Summary of the Invention [Problem to be solved by the invention]

[0014] Thus, there is a need for Group 13 or III-nitride materials, particularly substrates and wafers comprised of Group 13 or III-nitride materials, and more particularly wafers and substrates comprised of GaN having greater thicknesses, typically greater than 100 micrometers, and even greater than 400 micrometers, that are more uniform, and that simultaneously provide: ·Normally 5cm -2 Less than 4cm, preferably-2 Less than or even 1 cm -2 a low surface density of macro inclusions, Better crystalline quality, in which the X-ray diffraction (XRD) peak width at half maximum of the (002) line at an angle ω symmetrical to the GaN (0001) plane is less than 130 arcsec, preferably less than 100 arcsec, preferably less than 90 arcsec, and the X-ray diffraction (XRD) peak width at half maximum of the 201 line at an angle ω tilted to the GaN (0001) film is less than 240 arcsec, preferably less than 140 arcsec, and Improved electronic properties, typically an average electrical resistivity less than 25mohm.cm, or even less than 20mohm.cm. [Means for solving the problem]

[0015] An object of the invention is therefore a process for producing a monocrystalline semiconductor material made of Group 13 nitrides, comprising the following steps: a) depositing a first layer of a Group 13 nitride, preferably GaN, by epitaxial growth on a starting substrate. b) supplying an n-dopant gas to epitaxially deposit a second layer of a Group 13 nitride, preferably GaN, on the first layer, the deposition including a recessed region of material; c) stopping the supply of dopant gas and epitaxially depositing a third layer of a Group 13 nitride, preferably GaN, on the doped layer and in the recessed area of ​​the second layer, the deposition of this third layer filling the recessed area of ​​the second layer.

[0016] As a method of presentation, unless otherwise specified, chemical element concentrations reported in the text are atomic concentrations.

[0017] Advantageously, but optionally, the process of the invention may further comprise at least one of the following features: ·n The dopant gas comprises at least one chemical element from group 14 of the periodic table. The chemical elements in Group 14 of the periodic table are germanium, formed from solid sources of GeCl4, germane, tetramethylgermanium, and isobutylgermanium, and their derivatives; and / or silicon, formed from solid sources of silane, dichlorosilane, and silicon tetrachloride, and their derivatives. The dopant gas is mixed in the gas phase with the gallium chloride gas stream. Epitaxial growth is performed by HVPE with a growth rate of less than 450 μm / h to ensure a low surface density of macroscopic inclusions and a satisfactory crystal quality. The epitaxial deposition step is performed by HVPE. Separating the starting substrate to obtain a free-standing Group 13 nitride single crystal semiconductor material. Fabrication of free-standing Group 13 nitride single crystal semiconductor material, including: o A layer of Group 13 nitride, preferably GaN, doped with an n-dopant to a predetermined thickness and having a recessed region of material. a layer of an undoped Group 13 nitride, preferably GaN, disposed on said doped layer and in the material recessed region of said doped layer. Polishing off to obtain a given thickness of n-doped layer to form a Group 13 or Group III nitride wafer. The wafer selection step includes the following sub-steps: o Raman spectroscopy is performed to identify the lightly doped or undoped regions of the wafer, called the minimally doped regions. ○ 1×10 8 cm -2 Non-radiative defects are identified by cathodoluminescence to select wafers in which the maximum threading dislocation density or TDD exceeding 100 μm is confined to an area within a 50 μm diameter circle with its center coinciding with the center of each least doped region.

[0018] Another object of the present invention is a Group 13 nitride single crystal semiconductor material comprising: A first layer made of a Group 13 nitride, preferably GaN, having permanent defect regions corresponding to depressions or pits of decreasing cross section in the direction opposite to the growth direction. a second layer of a Group 13 nitride, preferably GaN, doped with an n-dopant to a predetermined thickness, the second layer having a recessed region of material coinciding with a permanent defect region in the first layer or coinciding with a defect region being formed in the second layer. a third layer of an undoped Group 13 nitride, preferably GaN, disposed on the doped layer and within the material recessed region of the doped layer, the deposition of the third layer filling the recessed region of the second layer;

[0019] Advantageously, but optionally, the monocrystalline semiconductor material of the present invention may further comprise at least one of the following features: The thickness of the second n-doped layer is between 100 and 2000 micrometers. The thickness of the first layer is between 100 and 1000 micrometers. The thickness of the third layer is 200-5000 micrometers. The ratio of the thickness of the second layer to the thickness of the first layer is 0.1 to 20. The n-dopant content of the second layer is 1×10 18 cm -3 Larger, 2×10 19 cm -3 Less than.

[0020] Another object of the invention is a group 13 or group III nitride wafer producible by the process described above, comprising: A layer made of a Group 13 nitride, preferably GaN, doped with an n-dopant and having a recessed region of material. A layer of undoped Group 13 nitride, preferably GaN, disposed within the material recess region of the doped layer.

[0021] The top surface of the wafer includes: a first doped region corresponding to an upper surface of the doped layer, the first doped region having a free carrier density, as measured by the Hall effect, of 1.0×10 18 cm -3 The larger, first doped region. a second lightly doped or undoped region located within the material recess of the doped layer and corresponding to an upper surface of the undoped layer, the second lightly doped or undoped region having a free carrier density, as measured by the Hall effect, of less than 8×10 17 cm -3 Less than 5 x 10 17 cm -3 A second lightly doped or undoped region, wherein the second lightly doped or undoped region is less than 0.1 μm.

[0022] Advantageously, but optionally, the Group 13 or Group III nitride wafers of the present invention may further include at least one of the following features: The first doped region includes a chemical element of Group 14 of the periodic table, germanium formed from a solid source of GeCl4, germane, tetramethylgermanium, and isobutylgermanium, and their derivatives; and / or silicon formed from a solid source of silane, dichlorosilane, and silicon tetrachloride, and their derivatives. The dopant content of the first doped region is 1×10 18 cm -3 Larger, 2×10 19 cm -3 Less than. The oxygen concentration in the first doped region is 2.0×10 18 cm -3 is less than. The oxygen supply and concentration is controlled by controlling the purity of the group III precursor and by one or more very thorough purges at residual pressures below 10 Torr followed by one or more removals of N2 from the reactor. The cumulative concentration of oxygen atoms and n-dopants in this crystal is 1.0×10 19 cm -3 is less than. The surface of the second region is less than 5%, or even less than 2% of the wafer surface. The crystal quality, as measured by the half-width of the X-ray diffraction (XRD) peak of the (002) ray at an angle ω symmetrical to the GaN (0001) plane, is less than 130 arcsec, preferably less than 100 arcsec, more preferably less than 90 arcsec, or even less than 60 arcsec, and the crystal quality, as measured by the half-width of the X-ray diffraction (XRD) peak of the 201 ray at an angle ω tilted to the GaN film (0001), is less than 240 arcsec, preferably less than 140 arcsec, or even less than 100 arcsec. · The average electrical resistivity of the wafer is less than 25mohm.cm.

[0023] Another object of the invention is the use of a group 13 or group III nitride wafer according to one of the aforementioned characteristics as a substrate for the manufacture of electronic and / or optoelectronic components, such as light emitting diodes, laser diodes, vertical transistors for power electronics, lateral transistors for power electronics or telecommunications (radio frequency), current rectifying diodes or sensors.

[0024] The present invention also relates to selecting defective areas in a Group 13 nitride single crystal semiconductor material wafer that will lead to failure of an optoelectronic component if the optoelectronic component is placed on or near such defective areas.

[0025] More particularly, another object of the present invention is a method for selecting defect regions in a wafer of Group 13 nitride single crystal semiconductor material before or after the deposition of optoelectronic components, comprising the steps of: In the first step, Raman spectroscopy is performed to identify the lightly doped or undoped regions of the wafer, called minimally doped regions; Alternatively, 1×10 8 cm -2 Identify non-radiative defects that have a maximum threading dislocation density (TDD) higher than In a second step, areas inscribed in a 50 μm diameter circle with a center coincident with the center of each minimally doped region and corresponding to areas where the optoelectronic component may have defects are selected for the following purposes: avoid placing optoelectronic components in this 50 μm diameter selected area prior to placing optoelectronic components on the wafer; and / or After the optoelectronic components are disposed on the wafer, the optoelectronic components disposed in the selected regions with a diameter of 50 μm are removed.

[0026] Further characteristics, objects and advantages of the invention will become apparent from a reading of the following detailed description, taken in conjunction with the accompanying drawings, which are given by way of non-limiting example only, and in which: [Brief description of the drawings]

[0027] [Figure 1] 1 summarizes the main steps of a substrate manufacturing process according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a schematic diagram illustrating a semiconductor material made up of a stack of layers, according to one embodiment of the present invention. [Diagram 3] FIG. 2 illustrates a slice of free-standing GaN material having a first or lightly doped or undoped layer, a second or intermediate n-doped layer, and a third or undoped top layer after separation according to one embodiment of the present invention. [Figure 4] FIG. 1 shows a cross section of a wafer after polishing a free-standing slice of material. [Diagram 5] FIG. 1 shows Raman spectra measured at the bottom of a growth pit and its surroundings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] 1 and 2, the main stages of the GaN wafer manufacturing process are shown.

[0029] In the following, the process according to the invention will be described in relation to the manufacture of gallium nitride (GaN) wafers. However, it will be readily apparent to one skilled in the art that the processes described below can be used to grow materials including layers of Group 13 nitrides other than gallium nitride GaN.

[0030] 1. Manufacturing Process The process consists of the following steps: Stage 10 of growth of a first layer 5a made of a group 13 nitride, preferentially GaN Stage 20 of formation of the isolation region 4 Step 30: Resuming epitaxy to form a thick layer 5b of undoped GaN, a thick layer 5c of n-doped GaN, and a final thick layer 5d of undoped GaN. Separation step 40 to obtain GaN crystals 5 A polishing step is performed to remove the thickness of these thick layers of undoped GaN. A finishing step 50 for forming a GaN wafer from the GaN crystal 5

[0031] 1.1. Stage 10 of growth Growth step 10 is an optional step in which GaN sublayer 5a is formed by lateral overgrowth.

[0032] The lateral overgrowth minimizes the defect density in the GaN sublayer 5a.

[0033] The approach used to reduce the dislocation density in the GaN sublayer 5a consists of the following. Initiating the island mode of GaN growth and then Promoting the coalescence of the islands to obtain the GaN sublayer 5a.

[0034] Advantageously, the lateral overgrowth is carried out on a starting substrate 1 with a non-zero truncation angle.

[0035] By using a starting substrate 1 with a non-zero truncation angle, a first GaN layer 5a can be grown with a non-zero truncation angle.

[0036] The starting substrate 1 can be selected from Si, AlN, GaN, GaAs, Al2O3 (sapphire), ZnO, SiC, LiAlO2, LiGaO2, MgAl2O4, 4H-SiC, or any other type of starting substrate known to those skilled in the art for growing gallium nitride.

[0037] The starting substrate 1 may be several hundred micrometers thick, typically 350 micrometers.

[0038] Advantageously, the starting substrate 1 may be subjected to a nitridation treatment before carrying out the deposition step, which improves the quality of the GaN crystals obtained.

[0039] The truncation angle may be between 0.1 and 5 degrees, preferentially between 0.2 and 0.8 degrees, and even more preferentially between 0.3 and 0.6 degrees (particularly to limit stacking errors).

[0040] The growth of the GaN sublayer 5a can be carried out in various variants. In particular, lateral overgrowth can be carried out based on: Use of a dielectric mask 3b having openings 3a in which the islands are formed, as described in WO 99 / 20816. The use of a dielectric layer without openings and in which islands form spontaneously, as described in EP 1 338 683.

[0041] 1.1.1. First variant of lateral overgrowth In a first variant, the growth stage 10 consists of an epitaxial lateral overgrowth (hereinafter ELO).

[0042] ELO involves depositing a thick, planar layer 2 on a starting substrate 1 .

[0043] The deposition is preferably carried out by metal-organic vapor phase epitaxy (MOVPE), for example at a temperature between 500 and 700°C, in particular 600°C.

[0044] The deposition of layer 2 reduces the stress between the starting substrate 1 and the subsequently epitaxially formed GaN sublayer 5a. In fact, the deposition of layer 2 on substrate 1 allows a "soft" transition between substrate 1 and GaN sublayer 5a, each of which has a different crystal structure.

[0045] Furthermore, as will become apparent from the following description, depositing the layer 2 facilitates the subsequent separation of the GaN crystal 5. The layer 2 is, for example, a GaN layer, an AlN layer, or an AlGaN layer.

[0046] In another step a mask 3b is formed which contains openings 3a, which may be dots or strips, that define the locations where GaN islands will later be selectively grown.

[0047] The mask 3b is, for example, SiN x The mask 3b may be made of a dielectric material such as SiO2 or TiN (SiN, Si3N4, etc.), which minimizes defects created at the edges of the mask and improves the quality of the GaN layer that is subsequently epitaxially formed on the mask. The formation of the mask 3b may be performed by any technique known to those skilled in the art. For example, the formation of the mask may consist of the following steps: Depositing a dielectric layer 3a directly on layer 2 from gaseous silane and ammonia precursors, and The dielectric layer 3a is etched by photolithography to form the openings 3a.

[0048] In this way, a starting substrate 1 coated with layer 2 and mask 3b is obtained, which not only improves the quality of the GaN sublayer 5a (by removing threading defects) but also softens the interface between the starting substrate 1 and the first GaN layer 5a.

[0049] Another step is to form GaN islands through the openings 3a in the mask. The rate of growth along the axis perpendicular to the main surface of the starting substrate 1 is kept higher than the rate of lateral growth. This results in island-like or band-like structures with triangular cross-sections (depending on the shape of the openings 3a). In these band-like structures with triangular cross-sections, the threading dislocations are bent by 90 degrees.

[0050] Lateral overgrowth then occurs, ultimately resulting in a flat ELO layer. At the end of this step in the process, the dislocation density is reduced to 10 8 cm -2 Thus, a first GaN layer 5a is obtained which has a thickness of less than 100 nm.

[0051] 1.1.2. Second variant of lateral overgrowth In a second variant, the growth stage 10 consists of a Universal lateral overgrowth (ULO), as described in EP 1 977 028 B1.

[0052] ULO involves depositing a nucleation layer on a starting substrate 1 .

[0053] The nucleation layer is for example a very thin film of silicon nitride SiN, with a thickness of the order of a few atomic planes, i.e. of the order of 10 to 20 nm. The deposition of SiN with silane and ammonia can last for 360 seconds.

[0054] A continuous buffer layer 2, for example made of GaN, is then deposited on this nucleation layer. The deposition of the GaN buffer layer 2 removes crystal defects, thereby minimizing the density of defects that will subsequently be contained in the epitaxially formed first GaN sublayer 5a, early in the process.

[0055] The thickness of this GaN buffer layer 2 may be 10 to 100 nm. The temperature during deposition may be 500 to 700°C.

[0056] Annealing is then performed at high temperatures of 900-1150 °C. Under the combined effect of the increase in temperature, a sufficient amount of hydrogen in the gaseous carriers and the presence of a very thin SiN film, the morphology of the GaN buffer layer 2 undergoes significant modification from solid-phase recrystallization by mass transport. The initially continuous GaN buffer layer 2 is then transformed into a discontinuous layer with GaN patterns. Thus, GaN patterns, or islands, with very good crystalline quality are obtained, which maintain their epitaxial relationship with the starting substrate due to the very thin nucleation layer.

[0057] The resulting exposed silicon nitride (SiN) regions act as a mask, and the GaN pattern acts as the GaN regions located at the openings formed ex situ in the mask. Lateral overgrowth is then performed, ultimately resulting in a planar ULO layer.

[0058] This method, in which the silicon nitride mask forms spontaneously and has the same dislocation bending mechanism as ELO, is called "ULO" (or "spontaneous ELO").

[0059] 1.2. Stage 20 of formation of the isolation region 4 The process further comprises the step 20 of forming an isolation region 4 .

[0060] This step 20 of forming the separation regions can be carried out in various variants. In particular, the step 20 of forming the separation regions can be carried out either: Before the growth stage 10 of the first GaN layer (first variant) After the growth stage 10 of the first GaN layer (second variant) During the growth stage 10 of the first GaN layer (third variant)

[0061] 1.2.1. First variant of the formation of the fractionation area 4 In a first variant, the step 20 for forming the isolation region 4 may consist in depositing a sacrificial intermediate layer prior to the growth stage 10 of the GaN sublayer 5a, as described in EP 1 699 951.

[0062] This intermediate layer may be Si, ZnO, TiN, SiN, TiC and serves as a sacrificial layer that is spontaneously evaporated during the subsequent epitaxial growth of the GaN sublayer 5a.

[0063] 1.2.2. Second variant of the formation of the isolation region In a second variant, the step 20 of forming the isolation region 4 comprises an implantation step carried out after the growth step 10 of the GaN sublayer 5a. This implantation makes it possible to form an embrittled region in the GaN sublayer 5a.

[0064] Implantation consists in bombarding the GaN sublayer 5a with ions to create a layer of microcavities (or bubbles) in the semiconductor at a depth close to the average penetration depth of these ions.

[0065] The implanted ions may be selected from tungsten, helium, neon, krypton, chromium, molybdenum, iron, hydrogen or boron. Preferably, the implanted ions are tungsten ions, which have the unique property of decomposing GaN.

[0066] Regarding the dose, the implanted ions are H + If so, the implant dose is 10 16 ~10 17 cm -2 and the implantation depth is 0-50 nm from the free surface (called the growth surface) of the first GaN sublayer 5a.

[0067] The implantation of the embrittling ions may be performed in one step or in successive steps. The temperature during implantation may be between 4 and 1400K.

[0068] Following implantation, annealing may be performed to repair any crystal damage caused during ion implantation. Annealing may be performed at temperatures between 500 and 1500°C.

[0069] 1.2.3. Third variant of the formation of the isolation region In a third variant, the separation region 4 can be formed during the growth stage 10 of the GaN sublayer 5a.

[0070] In particular, if the growth step is carried out according to the first variant known as ELO (i.e. the deposition of a dielectric mask 3b), the step 20 of forming the isolation regions 4 can be carried out by implantation of a buffer layer 2 before the deposition of the mask 3b.

[0071] This allows the isolation region 4 to be placed at exactly the desired depth, since the first GaN layer 5a deposited during the ELO step does not "interfere" with the ion implantation.

[0072] Of course, injection can be performed at different phases of the ELO (or ULO) stage, i.e. within the islands, during the intermediate stage when the islands have not yet fully coalesced, or after all the islands have coalesced.

[0073] 1.3. Epitaxy restart stage 30 At the end of the step 20 of forming the isolation region 4 and the step 10 of growing the GaN sublayer 5a, the process comprises a step 30 of epitaxy resumption to form a first thick undoped GaN layer 5b, a second thick n-doped GaN layer 5c, and a third thick undoped GaN layer 5d.

[0074] The process may also start directly from this step 30 by forming a thick GaN 5b layer, in which case the growth step 10 and the isolation region formation step 20 are optional. In the following description it is assumed that these steps 10 and 20 have been performed.

[0075] This epitaxial restart can be accomplished in one of the following ways: Metal-organic vapor phase epitaxy (MOVPE) Hydride Vapor Phase Epitaxy (HVPE) ·Closed Space Vapor Transport (CSVT) Liquid Phase Epitaxial Growth (LPE)

[0076] In this step, it is preferable to use the HVPE technique, which allows three main advantageous effects: The first effect is that the GaN sublayer 5a is grown thick without compromising the crystal quality (no new dislocations or cracks are generated). The second effect is that during HVPE, the dislocation density is further reduced by at least a factor of two beyond 100 μm of GaN growth (0001) (reference: https: / / doi.org / 10.1143 / APEX.5.095503). The third effect is that in the resulting thick layer of GaN 5, spontaneous separation from the starting substrate 1 at the separation region 4 may occur if sublimation or mechanical destruction occurs at the separation region 4 during HVPE growth.

[0077] More specifically, the epitaxial restart is carried out by the following process: the temperature is increased in a mixed atmosphere of nitrogen, ammonia and hydrogen. Once a stable temperature of about 1000°C is reached, the growth stage of a thick layer of GaN is started by introducing, for example, gallium chloride (GaCl) in the gas phase. GaCl and ammonia are partially pyrolyzed in the growth chamber, which is maintained at a temperature of about 1000°C. In this way, a monocrystalline GaN deposit is gradually formed at the level of the nucleation substrate (formed in the first growth stage).

[0078] It is necessary to avoid the GaN layer breaking into pieces during separation and to obtain a GaN layer that is thick enough to be easily handled without risk of breakage and therefore sufficiently resistant from a mechanical point of view. The growth continues for several hours under these experimental conditions, allowing the GaN layer to reach a thickness of at least 200 microns, and preferably more than 1 millimeter.

[0079] Growth is then finally completed by diverting the HCl flow to the outside and cooling is carried out in an atmosphere of nitrogen and ammonia.

[0080] The growth conditions for these first, second and third single crystal layers 5b, 5c and 5d are typically a growth temperature of 900 to 1200° C. and a growth rate of 50 to 500 micrometers / h, preferably 70 to 200 micrometers / h.

[0081] The thickness of the thus obtained self-supporting GaN precursor is greater than 200 μm, preferably greater than 1 mm, with a maximum thickness less than 10 mm, or even less than 5 mm.

[0082] The diameter of the free-standing GaN precursor thus obtained is greater than 50 mm, preferentially greater than 100 mm, and its maximum diameter is less than 250 mm, or even less than 200 mm.

[0083] As shown in FIG. 3, layer 5b has permanent defect areas corresponding to depressions or pits of reduced cross section in the direction opposite to the growth direction.

[0084] In a second step, doping is performed by adding an n-doping element under the same growth conditions to obtain a second single crystal GaN layer 5c on layer 5b according to the following process. The oxygen supply and concentration is controlled by controlling the purity of the group III precursors and by performing a very thorough purging of the reactor under vacuum with a residual pressure of less than 500 Torr prior to growth. In the case of germanium, the dopant gases are formed from solid sources, GeCl4, germane, tetramethylgermanium and isobutylgermanium, and their derivatives. These dopant gases are then vaporized in the reaction chamber. Preferably, these dopant gases may be premixed with the GaCl flow in the vapor phase to allow a more uniform distribution of the doping flow in the growth chamber.

[0085] For gaseous precursors, the gas tank is maintained at a pressure of 1-3 bar and a flow of carrier gas (N2 and / or H2) with a flow rate of 0.25-20 sccm is applied. In the case of silicon, it is formed from silane, dichlorosilane and silicon tetrachloride and their derivatives vaporized in the reaction chamber. For dichlorosilane (1% diluted in 99% N2 (or H2)), a flow of 1-20 sccm is applied. Preferably, these dopant gases may be mixed with the GaCl flow in the gas phase to allow a more uniform distribution of the doping flow in the growth chamber. Silicon and germanium can be introduced simultaneously, making it a three-dopant system.

[0086] Typically, the thickness of this first single crystal GaN layer 5b is 100 to 1000 micrometers.

[0087] The permanent defect regions 6 in layer 5b become defects which also propagate into layer 5c, so that during the growth of the second doped layer 5c, depressions form in the material of layer 5c with concave areas coinciding with the defect regions in layer 5b.

[0088] Other forms of material recession may also occur, associated with inclusions or nucleations that locally modify the growth rate, without reaching the upper surface of layer 5b or even 5c.

[0089] In a third step, the supply of the n-dopant gas is stopped but the growth conditions are maintained to obtain a third single crystal GaN layer 5d having a thickness of typically 200-5000 micrometers on the previously formed doped layer 5c having a thickness of typically 100-2000 micrometers.

[0090] Due to the thickness of the resulting monocrystalline layer and the growth mode of GaN 5d, the recessed areas of layer 5c are filled by the deposition of this third layer.

[0091] 1.4. Separation stage 40 A separation step 40 is also carried out according to a variant in which a step 20 of forming the separation regions 4 is carried out.

[0092] In the case of ion implantation, the spontaneous separation stage 40 is induced by the thermal cycles to which the thick GaN layer 5 is subjected (high temperature epitaxial restart and cooling), i.e., thermal cycles which generate stresses that cause separation due to differences in the thermal expansion coefficients between the starting substrate 1 and the thick GaN layer 5.

[0093] If a sacrificial intermediate layer has been deposited, this separation is caused during epitaxy by spontaneous evaporation of this intermediate layer or by mechanical destruction at the level of the so-called sacrificial layer.

[0094] In the case of post-growth separation, a laser may be used to vaporize the sacrificial layer.

[0095] A free-standing GaN crystal 5 as shown in FIG. 3 is obtained.

[0096] Such a crystal, shown in FIG. 3 (in its uncurved form), may be curved, the radius of curvature being typically greater than 5 meters and less than 25 meters, preferentially less than 20 meters. Furthermore, the dislocation density of the crystal 5 is greater than 10 7 cm -2 Less than or equal to 5×10 6 cm -2 is less than.

[0097] When GaN crystal 5 is formed on a starting substrate with a non-zero truncation angle (or miscut), GaN crystal 5 will also have a non-zero truncation angle and have a crystal plane orientation that propagates from one layer to the next. For example, in the case of a sapphire substrate 1 with a truncation angle of 4 degrees, the growth face of crystal 5 will have a truncation angle of 4 degrees across its entire surface, preferably an angle of 0.1 to 1 degree.

[0098] 1.5. Grinding stage 45 Once separated from the starting substrate 1, the GaN crystal 5 is polished. With current technology, the thickness removal can be controlled to within 10 micrometers.

[0099] 1.6. Finishing Stage 50 Next, finishing processing is performed to form a GaN wafer having an X-ray diffraction (XRD) peak half-width of the (002) line at an angle ω symmetrical to the GaN film (0001) of less than 130 arcsec, or even less than 90 arcsec, and preferably less than 60 arcsec.

[0100] The backside and sides or edges of the wafer are ground and polished to a surface finish acceptable for the application.

[0101] As shown in FIG. 3, removal polishing is performed to a thickness corresponding to that of the second n-doped layer 5c to form a group 13 or group III nitride wafer.

[0102] Thus, the present process is particularly suitable for producing slices or wafers of semiconductor material, particularly slices or wafers made from elements of Groups 13 and 15 of the Periodic Table, and more particularly slices or wafers made from Group 13 nitrides, preferably GaN, having a size greater than 5 centimeters, or even 10 centimeters, or even 15-20 centimeters.

[0103] As shown in FIG. 4, a slice or wafer 7 of semiconductor material formed in accordance with the process of the present invention comprises: A gallium surface, which is a plane perpendicular to the growth direction, has a first n-doped region 7a and a second n-doped region 7b, the n-doped region having a lower value corresponding to a high density region of crystal defects, and the density of free carriers measured by the Van der Pauw method in the first n-doped region 7a is 1.0×10 18 cm -3 The second region 7b, which is a larger, lightly n-doped or non-n-doped region, corresponds to a depression in the material that corresponds to a permanent defect in the first layer described above, such as a growth pit, and has a free carrier density of 1.0×10 as measured by the Hall effect. 18 cm -3 an n-doped region, a thickness of the order of 450 micrometers, and Excellent crystal quality, with a full width at half maximum of the (002) X-ray diffraction (XRD) peak at an angle ω symmetrical to the (0001) GaN film of less than 130 arcsec, or even less than 60 arcsec; and 5cm -2 Less than, preferentially 1 cm -2 a surface density of macro-inclusions that is less than · Average electrical resistivity less than 25mohm.cm.

[0104] 1.7. Selection stage 60 The process of the present invention also includes a wafer selection stage, which may have the following sub-steps. · As shown in Figure 5, Raman spectroscopy is performed to identify lightly doped or undoped regions of the wafer (called minimally doped regions) located around the permanent defect regions. The measurements were performed on a Thermo DXRxi Raman spectrometer, a high-speed Raman imaging instrument with a maximum acquisition capacity of 600 spectra / s. In one configuration, the analysis was performed with a 532 nm laser, 10 mW power. The laser beam was focused on the sample through a microscope with a magnification level of 50x. Cathodoluminescence identifies non-luminescent defects, with a resolution of 1×10 8 cm -2 A wafer is selected in which the maximum threading dislocation density (TDD) exceeding 100 μm is confined to an area within a 50 μm diameter circle having a center coincident with the center of each of the least doped regions.

[0105] This identification makes it possible to select areas that are inscribed in a 50 μm diameter circle having a center that coincides with the center of each minimally doped region and that correspond to areas where optoelectronic components may be defective, so that before placing optoelectronic components on the wafer, placement in the selected 50 μm diameter areas can be avoided and / or after placing optoelectronic components on the wafer, optoelectronic components placed in the selected 50 μm diameter areas can be removed.

[0106] According to another possible process, for the purposes of illustration and in contrast to the process described above, the monocrystalline material according to the invention is obtained by growing it on a starting substrate or seed, for example sapphire, on which a layer of GaN nitride, preferably at least a few micrometers and less than 10 micrometers, has been previously deposited. The growth is carried out in a HVPE reactor. The epitaxial deposition is carried out under the same conditions as in step 30 described above, but continues for a longer period in order to form a layer of several mm.

[0107] The crystal is trimmed and then cut into several slices or wafers, usually with a thickness of 100-600 micrometers, using either a loose wire saw (abrasive particles in a slurry that are attached to the wire before cutting) or a fixed wire saw (abrasive particles pre-fixed on the wire). The finishing steps (grinding, polishing) are similar to the process described above.

Claims

1. 1. A process for manufacturing a Group 13 or Group III nitride wafer, comprising: a) epitaxially depositing a first layer of a Group 13 nitride, preferably gallium nitride, on a starting substrate; b) supplying an n-dopant gas to epitaxially deposit a second layer of a Group 13 nitride, preferably gallium nitride, on said first layer, said deposition including recessed regions of material; c) stopping the supply of dopant gas and epitaxially depositing a third layer of a Group 13 nitride, preferably gallium nitride, on the second layer and in the recessed area of ​​the second layer, the deposition of the third layer filling the recessed area of ​​the second layer; d) separating the starting substrate to obtain a free-standing Group 13 nitride single crystal semiconductor material; The process for producing the Group 13 or Group III nitride wafer comprises: Preparation of a free-standing Group 13 nitride single crystal semiconductor material according to d) above; and polishing away to obtain an n-doped layer of a given thickness and form said Group 13 or Group III nitride wafer. The free-standing Group 13 nitride single crystal semiconductor material is a doped layer of a Group 13 nitride, preferably gallium nitride, doped with an n-dopant to a predetermined thickness and having a recessed region of material; a layer of an undoped Group 13 nitride, preferably gallium nitride, disposed on the doped layer and within the material recessed region of the doped layer; The manufacturing process further includes a step of wafer selection; The step of selecting a wafer includes: performing Raman spectroscopy to identify lightly doped or undoped regions of the wafer, referred to as minimally doped regions; 1x10 ８ cm －２ and identifying non-radiative defects by cathodoluminescence to select wafers having a maximum threading dislocation density or TDD exceeding 100% which is confined to an area within a 20 micrometer diameter circle having a center coincident with a center of said least doped region.

2. 10. The manufacturing process of claim 1, wherein the n-dopant gas comprises at least one chemical element from Group 14 of the periodic table.

3. 3. The manufacturing process of claim 2, wherein the chemical element of Group 14 of the periodic table is germanium formed from solid sources of germanium tetrachloride, germane, tetramethylgermanium, and isobutylgermanium, and their derivatives, and / or silicon formed from solid sources of silane, dichlorosilane, and silicon tetrachloride, and their derivatives.

4. 4. The manufacturing process of claim 1, wherein the n-dopant gas is mixed with a gallium chloride gas flow in the gas phase.

5. 5. The manufacturing process according to claim 1, wherein the epitaxial deposition is carried out by hydride vapor phase epitaxy.

6. a first layer made of a Group 13 nitride, preferably gallium nitride, having permanent defect regions corresponding to depressions or pits whose cross section decreases in the direction opposite to the growth direction; a second layer of a Group 13 nitride, preferably gallium nitride, doped with an n-dopant to a predetermined thickness and having a recessed region of material coinciding with the permanent defect region of the first layer; a third layer of an undoped Group 13 nitride, preferably gallium nitride, disposed on the second layer and within the material recessed region of the second layer; The deposition of said third layer fills said recessed regions of material of said second layer.

7. The monocrystalline semiconductor material of claim 6, wherein the second layer has a thickness of 100 to 2000 micrometers.

8. The monocrystalline semiconductor material according to claim 6 or 7, wherein the first layer has a thickness of 100 to 1000 micrometers.

9. The monocrystalline semiconductor material according to any one of claims 6 to 8, wherein the third layer has a thickness of 200 to 5000 micrometers.

10. 10. The monocrystalline semiconductor material according to claim 6, wherein the ratio of the thickness of the second layer to the thickness of the first layer is 0.1 to 20.

11. The n-dopant content of the second layer is 1×10 １８ cm －３ Larger, 2 x 10 １９ cm －３ The monocrystalline semiconductor material according to claim 6 , wherein the n-th order is smaller than n-th order.

12. 1. A Group 13 or Group III nitride wafer, said wafer comprising: a doped layer made of a Group 13 nitride, preferably GaN, doped with an n-dopant and having a material recessed region; an undoped layer of a Group 13 nitride, preferably GaN, disposed in the recessed material region of the doped layer; The top surface of the wafer is a first doped region corresponding to an upper surface of the doped layer, the first doped region having a free carrier density of 1.0×10 as measured by the Hall effect; １８ cm －３ a larger first doped region; and a free carrier density of 8×10, as measured by the Hall effect, corresponding to an upper surface of the undoped layer disposed within the material recessed region of the doped layer; １７ cm －３ and a second lightly doped or undoped region having a doped atomic ratio of less than about 1.

0.

13. the first doped region comprises a chemical element of Group 14 of the Periodic Table; 13. The Group 13 or Group III nitride wafer of claim 12, wherein the chemical elements are germanium formed from solid sources of germanium tetrachloride, germane, tetramethylgermanium, and isobutylgermanium, and their derivatives, and / or silicon formed from solid sources of silane, dichlorosilane, and silicon tetrachloride, and their derivatives.

14. The n-dopant content of the first doped region is 1×10 １８ cm －３ Larger, 2 x 10 １９ cm －３ 14. The Group 13 or III nitride wafer of claim 12 or 13,

15. The oxygen concentration of the first doped region is 2.0×10 １８ cm －３ 15. The Group 13 or III nitride wafer of any one of claims 12 to 14, wherein the Nb / Si film thickness is less than 100 nm.

16. The cumulative concentration of oxygen atoms and the n-dopant in the crystal is 1.0×10 １９ cm －３ 16. The Group 13 or III nitride wafer of claim 15, wherein the Nb / Si film thickness is less than 100 nm.

17. 17. The Group 13 or III-nitride wafer of any one of claims 12 to 16, wherein a surface of the second lightly doped or undoped region is less than 5%, or less than 2% of a surface of the wafer.

18. 18. The Group 13 or III-nitride wafer of any one of claims 12 to 17, wherein the crystalline quality as measured by the half-width of the X-ray diffraction (XRD) peak of the (002) line at an angle ω symmetrical to the GaN (0001) plane is less than 130 arcsec, and the crystalline quality as measured by the half-width of the X-ray diffraction (XRD) peak of the 201 line at an angle ω tilted to the GaN (0001) film is less than 240 arcsec.

19. 19. The Group 13 or III-nitride wafer of any one of claims 12 to 18, wherein the wafer has an average electrical resistivity of less than 25 milliohm-centimeters.

20. 20. Use of a group 13 or group III nitride wafer according to any one of claims 12 to 19 as a substrate for the manufacture of optoelectronic components such as light emitting diodes, laser diodes, vertical transistors for power electronics, lateral transistors for power electronics or telecommunications (radio frequency), current rectifying diodes or sensors.

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