Semiconductor switching element driving device and driving method thereof, and power conversion device

Abstract

To reduce surge voltage when a switching element is turned off.SOLUTION: A drive unit of a semiconductor switching element has a gate drive circuit driving a voltage-drive semiconductor switching element and a gate voltage holding circuit holding gate voltage applied to the semiconductor switching element at predetermined holding voltage larger than threshold voltage of the semiconductor switching element and smaller than mirror voltage of the semiconductor switching element. The gate voltage holding circuit starts an operation of holding the gate voltage at the holding voltage after voltage between main terminals of the semiconductor switching element rises at the time of turn-off of the semiconductor switching element, before the voltage between main terminals becomes the maximum value.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a drive device and a drive method for a semiconductor switching element, and a power conversion device. [Background technology]

[0002] Semiconductor switching elements, for example, constitute inverter circuits and are used as power conversion devices by performing switching operations. Such semiconductor switching elements generate switching losses when they are turned on and off during switching operations. When the semiconductor switching element is turned off, the faster the gate drive speed is, the shorter the time required for switching becomes, so the switching losses decrease, but the surge voltage of the voltage between the main terminals increases. In addition, when the semiconductor switching element is turned off, ringing occurs, in which the voltage or current increases and decreases rapidly. When ringing occurs, electromagnetic noise increases. For this reason, from the viewpoint of ensuring insulation for the semiconductor switching element and the circuit connected to the semiconductor switching element, it is required to reduce not only the ringing of the semiconductor switching element but also the surge voltage.

[0003] Patent Document 1 discloses a device that controls the gate voltage to a value greater than a threshold value after the voltage between the main terminals of a semiconductor switching element reaches a peak value, thereby damping ringing oscillations when the switching element is turned off. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-70164 A Summary of the Invention [Problem to be solved by the invention]

[0005] The device of Patent Document 1 was unable to reduce the surge voltage that occurs when the switching element is turned off. [Means for solving the problem]

[0006] A drive device for a semiconductor switching element according to the present invention includes a gate drive circuit for driving a voltage-driven semiconductor switching element, and a gate voltage holding circuit for holding a gate voltage applied to the semiconductor switching element at a predetermined holding voltage that is greater than a threshold voltage of the semiconductor switching element and less than a mirror voltage of the semiconductor switching element, the gate voltage holding circuit starting an operation of holding the gate voltage at the holding voltage after a voltage between main terminals of the semiconductor switching element rises when the semiconductor switching element is turned off, but before the voltage between the main terminals reaches a maximum value. The gate voltage holding circuit changes the holding voltage based on a current value flowing through the semiconductor switching element so that the gate voltage when the current value of the semiconductor switching element is a first current value is set to the holding voltage lower than the gate voltage when the current value of the semiconductor switching element is a second current value larger than the first current value. . A method for driving a semiconductor switching element according to the present invention is a method for driving a voltage-driven semiconductor switching element, comprising: a step of: driving the semiconductor switching element by applying a voltage to the semiconductor switching element after a voltage between main terminals of the semiconductor switching element rises when the semiconductor switching element is turned off, and before the voltage between the main terminals reaches a maximum value; Switching Start an operation of holding the gate voltage applied to the element at a predetermined holding voltage that is greater than the threshold voltage of the semiconductor switching element and less than the mirror voltage of the semiconductor switching element. and changing the holding voltage based on a current value flowing through the semiconductor switching element so that the gate voltage when the current value of the semiconductor switching element is a first current value is set to the holding voltage lower than the gate voltage when the current value of the semiconductor switching element is a second current value larger than the first current value. . Effect of the Invention

[0007] According to the present invention, it is possible to reduce the surge voltage when a switching element is turned off. [Brief description of the drawings]

[0008] [Figure 1] 1 shows an overall configuration diagram of an electric motor control system using a power conversion device. [Diagram 2] 1 is a circuit diagram of a gate driving device according to a first embodiment. [Diagram 3] FIG. 1 is a circuit diagram of a gate driving device according to a comparative example. [Figure 4] 1A through 1G are diagrams showing examples of waveforms when a semiconductor switching element is turned off. [Diagram 5] 13A to 13G are diagrams showing another example 1 of waveforms when a semiconductor switching element is turned off. [Figure 6] 13A to 13G are diagrams showing another example 2 of waveforms when a semiconductor switching element is turned off. [Figure 7] FIG. 4 is a circuit diagram of a gate driving device according to a modified example of the first embodiment. [Figure 8] FIG. 5 is a circuit diagram of a gate driving device according to a second embodiment. [Figure 9] 11A and 11B are diagrams illustrating current dependences of a mirror voltage and a threshold voltage of a semiconductor switching element. [Figure 10] 5A and 5B are diagrams illustrating temperature dependences of a mirror voltage and a threshold voltage of a semiconductor switching element. [Figure 11] FIG. 11 is a circuit diagram of a gate driving device according to a modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a first embodiment and a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the semiconductor switching element constitutes, for example, an inverter circuit, and is used as a power conversion device by performing a switching operation. The power conversion device outputs an AC current based on supplied DC power to drive an electric motor of an electric vehicle or a hybrid vehicle. In the first and second embodiments, components with the same reference numbers indicate components with the same configuration or similar functions.

[0010] [First embodiment] FIG. 1 shows an overall configuration diagram of an electric motor control system using a power conversion device 1000. The power conversion device 1000 outputs an AC current based on the DC power supplied from the battery 100 to drive the electric motor 300 .

[0011] The power conversion device 1000 includes an inverter circuit 200 and a command logic unit 400. Between the battery 100 and the positive electrode connecting line and the negative electrode connecting line of the inverter circuit 200, a smoothing capacitor 110 is provided.

[0012] The inverter circuit 200 includes a series circuit of semiconductor switching elements 101 consisting of upper and lower arms for three phases, UVW phases. Each of the semiconductor switching elements 101 of the upper and lower arms is composed of, for example, a MOSFET. A high potential side terminal of the MOSFET of the upper arm of each phase is connected to a first end (positive electrode connection wire) of a smoothing capacitor 110. A high potential side terminal of the MOSFET of the lower arm of each phase is connected to a low potential terminal side of the MOSFET of the upper arm of each phase. A low voltage terminal side of the MOSFET of the lower arm of each phase is connected to a second end (negative electrode connection wire) of the smoothing capacitor 110.

[0013] In each phase, a connection point between a low potential side terminal of the MOSFET of the upper arm and a high potential side terminal of the MOSFET of the lower arm is connected to one end of a winding 310 of an electric motor 300. The other end of the winding 310 of each phase is connected to a neutral point. The electric motor 300 is, for example, a permanent magnet field type synchronous motor.

[0014] The semiconductor switching element 101 is not limited to a MOSFET, but may be any voltage-driven semiconductor switching element 101 such as an IGBT. The semiconductor constituting the semiconductor switching element 101 may be silicon (Si) or a wide-gap semiconductor (such as silicon carbide (SiC) or gallium nitride (GaN)).

[0015] When the semiconductor switching element 101 is a MOSFET, it is, for example, a SiC-MOSFET. Therefore, in a MOSFET, the high potential side terminal is the drain, and the low potential side terminal is the source. A freewheeling diode (freewheeling diode) 102 is connected in inverse parallel to each MOSFET. As the freewheeling diode 102, various diodes such as a pn junction diode, a Schottky barrier diode, and a diode using both a pn junction and a Schottky junction can be used. When the semiconductor switching element 101 is a SiC-MOSFET, the freewheeling diode 102 may be replaced by a body diode of the SiC-MOSFET. In the following explanation, a case where the semiconductor switching element 101 is a MOSFET will be explained as an example.

[0016] The command logic unit 400 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate drive device 500 as a drive command signal P for the semiconductor switching element 101. As a result, the command logic unit 400 alternately turns on the semiconductor switching element 101 of the upper arm and the semiconductor switching element 101 of the lower arm in each phase to control the control amount of the electric motor 300 to the command value. The control amount is, for example, the torque of the electric motor 300.

[0017] The gate driving device 500 is provided corresponding to each semiconductor switching element 101, acquires a drive command signal P from the command logic unit 400, and turns the semiconductor switching element 101 on or off based on the acquired drive command signal P.

[0018] FIG. 2 is a circuit diagram of the gate driver 500 according to the first embodiment. Fig. 2 illustrates the semiconductor switching element 101 and its gate drive device 500 in the lower arm of the U-phase in the inverter circuit 200 shown in Fig. 1. The other semiconductor switching elements 101 and their gate drive devices 500 in the upper arm of the U-phase, and the upper and lower arms of the V-phase and W-phase have the same configuration. Below, the configuration and operation of the semiconductor switching element 101 and its gate drive device 500 in the lower arm of the U-phase will be described, but the configurations and operations of the other semiconductor switching elements 101 and their gate drive devices 500 are also similar.

[0019] The gate driver 500 includes a positive power supply 4, a first MOSFET 5, an on-side gate resistor 6, a buffer circuit 7, a negative power supply 8, and a gate voltage holding circuit 9. The gate voltage holding circuit 9 is composed of an OFF-side gate resistor 10, a second MOSFET 11, a gate voltage pull-up MOSFET 12, a gate voltage pull-up resistor 13, and a hold circuit .

[0020] An output section 1 of the gate driver 500 is connected to a gate terminal G of the semiconductor switching element 101. A reference potential 2 of the gate driver 500 is connected to a source terminal S of the semiconductor switching element 101. In addition, an input section 3 of the gate driver 500 is connected to a command logic section 400.

[0021] The source of the first MOSFET 5 and the source of the gate voltage pull-up MOSFET 12 are connected to the positive-side power supply 4. The drain of the first MOSFET 5 is connected to one end of the ON-side gate resistor 6, and the drain of the second MOSFET 11 is connected to one end of the OFF-side gate resistor 10. The other end of the ON-side gate resistor 6 and the other end of the OFF-side gate resistor 10 are both connected to the output section 1 of the gate driver 500.

[0022] The source of the second MOSFET 11 is connected to the negative power supply 8. The gate of the first MOSFET 5 and the gate of the second MOSFET 11 are both connected to the output part of the buffer circuit 7, and the input part of the buffer circuit 7 is connected to the input part 3 of the gate driver 500.

[0023] The drain of the gate voltage pull-up MOSFET 12 is connected to the output 1 of the gate driver 500 via a gate voltage pull-up resistor 13. The output R of the hold circuit 14 is connected to the gate of the gate voltage pull-up MOSFET 12, and the input Q of the hold circuit 14 is connected to a detection circuit 15.

[0024] The detection circuit 15 is composed of a capacitor 16, a resistor 17, and a comparator 18. In the differentiation circuit composed of the capacitor 16 and the resistor 17, one end of the capacitor 16 is connected to the drain terminal D of the MOSFET, and one end of the resistor 17 is connected to the source terminal S of the semiconductor switching element 101. The other end of the capacitor 16 and the other end of the resistor 17 are both connected to a first input terminal of the comparator 18, and the second input terminal of the comparator 18 is connected to a voltage source of the reference voltage Vref. The output terminal of the comparator 18 is connected to an input Q of the hold circuit 14 in the gate voltage holding circuit 9.

[0025] The drive command signal P is input from the command logic unit 400 to the gate driver 500. While the drive command signal P is being input, the gate driver 500 operates the buffer circuit 7 to turn on the first MOSFET 5 and turn off the second MOSFET 11. This causes a current (gate current) to flow from the positive power supply 4 to the gate of the semiconductor switching element 101 via the on-side gate resistor 6. At this time, the capacitance between the gate and source (between the GS terminals) of the semiconductor switching element 101 is charged and a voltage (for example, +18 V) exceeding the threshold voltage of the semiconductor switching element 101 is applied, turning on the semiconductor switching element 101 and causing a current to flow through the semiconductor switching element 101 (turning on). The turn-on switching speed is controlled by adjusting the resistance value (Ron) of the on-side gate resistor 6.

[0026] Furthermore, while the drive command signal P is not input from the command logic unit 400, the gate driver 500 operates the buffer circuit 7 to turn off the first MOSFET 5 and turn on the second MOSFET 11. This causes a gate current to flow from the gate of the semiconductor switching element 101 to the negative power supply 8 via the OFF-side gate resistor 10. At this time, the capacitance between the GS terminals of the semiconductor switching element 101 is discharged and a voltage (e.g., −5V) lower than the threshold voltage of the semiconductor switching element 101 is applied, turning off the semiconductor switching element 101 and cutting off the current of the semiconductor switching element 101 (turning off). The switching speed of the turn-off is controlled by adjusting the resistance value (Roff) of the OFF-side gate resistor 10. The potential of the negative power supply 8 does not necessarily have to be negative, and may be, for example, a reference potential (0V).

[0027] In this manner, the gate drive circuit for driving the voltage-driven semiconductor switching element 101 in response to the drive command signal P from the command logic unit 400 is composed of the first MOSFET 5, the ON-side gate resistor 6, the second MOSFET 11, and the OFF-side gate resistor 10.

[0028] Although the details will be described later, the detection circuit 15 detects the rising of the drain-source voltage (VDS) of the semiconductor switching element 101 by comparing it with the reference voltage Vref of the comparator 18 when the semiconductor switching element 101 is turned off. When the rising of the drain-source voltage (VDS) is detected, the detection circuit 15 outputs a detection signal to the input Q of the hold circuit 14. After the detection signal is input from the detection circuit 15, that is, after the rise of the main terminal voltage, which is the drain-source voltage (VDS) of the semiconductor switching element 101 when the semiconductor switching element 101 is turned off, the gate voltage holding circuit 9 starts an operation of holding the main terminal voltage at a predetermined holding voltage before the main terminal voltage becomes a maximum value. That is, when the gate voltage holding circuit 9 starts an operation, the gate voltage raising MOSFET 12 is turned on. As a result, the gate voltage applied to the semiconductor switching element 101 is held at a predetermined holding voltage Vkeep that is higher than the threshold voltage of the semiconductor switching element 101 and lower than the mirror voltage of the semiconductor switching element 101.

[0029] FIG. 3 is a circuit diagram of a gate driver 500 according to a comparative example. The gate drive device 500 according to the comparative example has a configuration in which the gate voltage holding circuit 9 and the detection circuit 15 are removed from the circuit diagram of the gate drive device 500 according to the present embodiment shown in Fig. 2. For comparison with the present embodiment, this comparative example shows a gate drive device 500 to which the present embodiment is not applied. The same reference numbers are used for the same components as those of the present embodiment shown in Fig. 2, and their description will be simplified.

[0030] When a drive command signal P is input from the command logic unit 400 to the gate driver 500, the first MOSFET 5 is turned on and the second MOSFET 11 is turned off. Then, the semiconductor switching element 101 is turned on to allow a current to flow through the semiconductor switching element 101 (turned on).

[0031] Furthermore, while the drive command signal P is not being input from the command logic unit 400, the first MOSFET 5 is turned off and the second MOSFET 11 is turned on. Then, the semiconductor switching element 101 is turned off to cut off the current of the semiconductor switching element 101 (turned off).

[0032] Figures 4(A), 4(B), 4(C), 4(D), 4(E), 4(F), and 4(G) are diagrams showing examples of waveforms when the semiconductor switching element 101 is turned off. The solid lines in each of Figures 4(B), 4(C), 4(D), and 4(E) show waveforms in the gate driver 500 of Figure 3, which is a comparative example. The dashed lines in each of these diagrams show waveforms in the gate driver 500 of Figure 2, which is the present embodiment, and mainly show the differences from the comparative example.

[0033] 4(A) shows the gate-off command P from the command logic unit 400, FIG. 4(B) shows the gate current of the semiconductor switching element 101, FIG. 4(C) shows the gate-source voltage of the semiconductor switching element 101, and FIG. 4(D) shows the drain current of the semiconductor switching element 101. FIG. 4(E) shows the drain-source voltage of the semiconductor switching element 101, and FIG. 4(F) shows the output signal (V OUT 4(G) shows an ON command (R) to the gate voltage pull-up MOSFET 12. Note that Fig. 4(D) and Fig. 4(E) cross each other midway and are interchangeable.

[0034] Hereinafter, the turning-off of the semiconductor switching element 101 shown in Figures 4(A), 4(B), 4(C), 4(D), 4(E), 4(F), and 4(G) will be described with reference to Figure 2 etc.

[0035] As shown in Fig. 4(A), at time t0, a gate-off command P to turn off the semiconductor switching element 101 is input from the command logic unit 400. Then, as shown in Fig. 4(C), the gate-source voltage (VGS) of the semiconductor switching element 101 decreases. From time t1, the semiconductor switching element 101 enters a mirror period in which VGS is constant. At the same time, as shown in Fig. 4(E), the drain-source voltage (VDS) (hereinafter, the drain-source voltage may be referred to as the main terminal voltage) begins to rise.

[0036] 4(F), a voltage (VOUT) corresponding to the differentiated waveform of VDS is output in the detection circuit 15. As VDS increases, VOUT increases. When VOUT>Vref is satisfied at the comparator 18 at time t2, the detection circuit 15 detects that the semiconductor switching element 101 has been turned off, and outputs a detection signal Q to the hold circuit 14.

[0037] 4(G), at time t3 after a certain circuit delay d has elapsed, the hold circuit 14 outputs an ON command R for the gate voltage pull-up MOSFET 12. This switches the gate voltage pull-up MOSFET 12 from OFF to ON, and holds the ON state for a certain time T (hold time T). Furthermore, at time t3, when the gate voltage pull-up MOSFET 12 transitions to the ON state, the first MOSFET 5 is in the OFF state, and the second MOSFET 11 is in the ON state.

[0038] Therefore, the potential of the output section 1 of the gate driver 500 approximately coincides with the value obtained by dividing the voltage between the positive power supply 4 (voltage: Vp) and the negative power supply 8 (voltage: Vm) by the gate voltage pull-up resistor 13 (resistance value: Rlift) and the off-side gate resistor 10 (resistance value: Roff). That is, during the period from time t3 to t5 when the on command R for the gate voltage pull-up MOSFET 12 is output, the output voltage of the gate driver 500 (the voltage between the output section 1 and the reference potential 2) is held at the hold voltage Vkeep shown in the following equation (1). Vkeep=(Vp-Vm)*Roff / (Rlift+Roff)+Vm...(1)

[0039] That is, during the period from time t3 to t5, the gate voltage holding circuit 9 operates, and the absolute value of the output voltage of the gate driver 500 decreases from |Vm| to |Vkeep| (|Vm|>|Vkeep|).

[0040] As a result, as shown by the dashed line in Fig. 4(B), the absolute value of the gate current (IG) discharging the capacitance between the GS terminals of the semiconductor switching element 101 decreases from time t3. Therefore, the speed at which the semiconductor switching element 101 is turned off to cut off the current of the semiconductor switching element 101 also slows down after time t3. And, as shown by the dashed line in Fig. 4(E), the rate of rise (dv / dt) of the drain-source voltage (VDS) of the semiconductor switching element 101 also slows down after time t3, so that the surge voltage (Vsurge) of VDS can be reduced compared to the comparative example shown by the solid line.

[0041] In this way, in order to reduce the surge voltage, it is necessary to reduce dv / dt, and therefore the timing (time t3) at which the absolute value of the gate current is reduced must be earlier than the timing (time t4) at which VDS reaches its maximum value. In other words, the time t3 at which the gate voltage pull-up MOSFET 12 turns on and the gate voltage holding circuit 9 starts operating must precede the time t4 at which VDS reaches its maximum value.

[0042] When detecting the rise (rising) of VDS using the detection circuit 15 as in this embodiment, the rising of VDS is detected after time t1 when the semiconductor switching element 101 enters the mirror period and VDS starts to rise. The detection timing (time t2) of the rising of VDS can be set by adjusting the reference voltage Vref of the comparator 18. This sets the time t3 when the gate voltage holding circuit 9 starts to operate to precede the time t4 when VDS reaches the maximum value.

[0043] Generally, when the semiconductor switching element 101 is turned off, VDS rises continuously and smoothly, so that it is difficult to uniquely detect the rise of the voltage between the main terminals from the waveform of VDS. In this embodiment, the phenomenon that the output voltage VOUT in the detection circuit 15 increases with the rise of the VDS of the semiconductor switching element 101 is utilized, and the rise of the voltage between the main terminals is detected by detecting VOUT>Vref in the comparator 18. Therefore, the detection time t2 of the rise of the voltage between the main terminals VDS shown in FIG. 4(E) is not necessarily limited to the timing of the "inflection point A" in the figure. Specifically, the rise of the voltage between the main terminals VDS may be detected at any time within the period from the time t1 when the semiconductor switching element 101 enters the mirror period and VDS starts to rise to the time t3 when the rate of change dv / dt of the voltage between the main terminals of the semiconductor switching element 101 becomes maximum and the output signal VOUT of the detection circuit 15 shown in FIG. 4(F) becomes maximum.

[0044] Also, although it has been stated that the gate voltage hold circuit 9 needs to start operating at a timing earlier than the timing when VDS reaches its maximum value, this is not necessarily limited to operating the gate voltage hold circuit 9 at time t3. In other words, the time when the gate voltage hold circuit 9 starts operating may be set appropriately at any time during the period from time t2 when the rising edge of the main terminal voltage VDS is detected until time t4 when VDS reaches its maximum value. Figure 4(G) shows one example of this.

[0045] As shown by the dashed line in FIG. 4B, the gate voltage holding circuit 9 starts operating at time t3, and the absolute value of the gate current (IG) decreases. Also, as shown by the dashed line in FIG. 4G, the gate voltage holding circuit 9 starts operating at time t3, and the on command (R) of the gate voltage pull-up MOSFET 12 becomes high. However, as shown by the dashed line in FIG. 4C, even if the gate voltage holding circuit 9 starts operating at time t3, the gate-source voltage (VGS) of the semiconductor switching element 101 remains constant at the mirror voltage (Vmiller). That is, during the period from time t3 to t5, the output voltage of the gate driver 500 is held at Vkeep shown in formula (1), but the VGS of the semiconductor switching element 101 remains constant at Vmiller until time B when the mirror period ends, as shown by the dashed line in FIG. 4C.

[0046] After time B when the mirror period ends, VGS of the semiconductor switching element 101 is held at Vkeep instead of Vmiller until time t5. This is because VGS of the semiconductor switching element 101 during the mirror period is held at the mirror voltage of the following equation (2) that is determined by the characteristics of the semiconductor switching element 101 itself, without depending on the external gate control voltage (output voltage of the gate driver 500). Vmiller = Vth + ID / gm (2) Here, Vth is the threshold voltage of the semiconductor switching element 101 which is a MOSFET, ID is the drain current flowing through the semiconductor switching element 101, and gm is the transfer conductance of the semiconductor switching element 101.

[0047] 4(C), during the period from time B when the mirror period ends to time t5, the gate-source voltage (VGS) is held at Vkeep. At this time, Vkeep is held at a value smaller than the mirror voltage Vmiller of the semiconductor switching element 101 and larger than the threshold voltage Vth of the semiconductor switching element 101. By raising (holding) VGS at Vkeep, which is larger than Vth, for a certain period of time, a current (tail current: Itail) shown in the following equation (3) flows through the semiconductor switching element 101. Itail = gm * (Vkeep - Vth) (3)

[0048] As a result, after time t4 when VDS reaches a maximum value when the semiconductor switching element 101 is turned off, a tail current (Itail) as shown by the dashed line in FIG. 4(D) flows inside the semiconductor switching element 101, causing loss in the semiconductor switching element 101. This consumes energy stored in the parasitic inductance and parasitic capacitance in the circuits that configure the inverter circuit 200, making it possible to effectively damp ringing oscillation. As is clear from equation (3), the magnitude of the tail current (Itail) can be controlled by adjusting the value of Vkeep, and it is also possible to control the degree of damping of the ringing oscillation.

[0049] Here, ringing will be described with reference to a comparative example to which this embodiment is not applied. When a gated switching element is turned off, the voltage between the main terminals of the gated switching element rises abruptly, and the current (main current) flowing between the main terminals of the gated switching element drops abruptly. Then, an electromotive force is generated by a parasitic inductor present in the wiring in which the gated switching element is interposed. Due to this electromotive force, the voltage between the main terminals rises to a peak value immediately after the gated switching element is turned off, as shown by the solid line in FIG. 4(E), and thereafter repeats increasing and decreasing. In addition, in conjunction with the increase and decrease in the voltage between the main terminals, the main current also repeats increasing and decreasing, as shown by the solid line in FIG. 4(D). In this way, when the gated switching element is turned off, ringing occurs in the gated switching element.

[0050] Figures 5(A), 5(B), 5(C), 5(D), 5(E), 5(F), and 5(G) are diagrams showing another example 1 of waveforms when the semiconductor switching element 101 is turned off. The solid lines in each of Figures 5(B), 5(C), 5(D), and 5(E) show waveforms in the gate driver 500 of Figure 3, which is a comparative example. The dashed lines in each of these diagrams show waveforms in the gate driver 500 of Figure 2, which is the present embodiment, and mainly show the difference from the comparative example.

[0051] 5(A) shows the gate-off command P from the command logic unit 400, FIG. 5(B) shows the gate current of the semiconductor switching element 101, FIG. 5(C) shows the gate-source voltage of the semiconductor switching element 101, and FIG. 5(D) shows the drain current of the semiconductor switching element 101. FIG. 5(E) shows the drain-source voltage of the semiconductor switching element 101, and FIG. 5(F) shows the output signal (V OUT 5(G) shows an ON command (R) to the gate voltage pull-up MOSFET 12.

[0052] Compared to Figures 4(A), 4(B), 4(C), 4(D), 4(E), 4(F), and 4(G), Figures 5(C) and 5(D) are different from Figures 4(C) and 4(D). As shown in Fig. 5(C), the gate-source voltage of the semiconductor switching element 101 may change gradually from time B to time t5. For example, impedance components such as wiring inductance and parasitic resistance exist between the output section 1 of the gate driver 500 shown in Fig. 2 and the gate terminal G of the MOSFET. For this reason, even if the output voltage of the gate driver 500 is changed stepwise as shown by the dashed line in Fig. 4(C), the VGS of the semiconductor switching element 101 may change gradually as shown by the dashed line in Fig. 5(C).

[0053] In Alternative Example 1, VGS changes gradually as shown by the dashed line in FIG. 5(C), and the relationship between the operation of the gate driver 500 and the waveform is similar to that already described with reference to FIGS. 4(A), 4(B), 4(C), 4(D), 4(E), 4(F), and 4(G).

[0054] As shown by the dashed line in Fig. 5(C), the gate-source voltage of the semiconductor switching element 101, VGS, gradually decreases from Vmiller to Vkeep between time B and time t5, compared to Fig. 4(C). Therefore, as shown by the dashed line in Fig. 5(D), the tail current (Itail) flows relatively large, which has the effect of more effectively controlling the ringing vibration of the semiconductor switching element 101.

[0055] Figures 6(A), 6(B), 6(C), 6(D), 6(E), 6(F), and 6(G) are diagrams showing another example 2 of waveforms when the semiconductor switching element 101 is turned off. The solid lines in each of Figures 6(B), 6(C), 6(D), and 6(E) show waveforms in the gate driver 500 of Figure 3, which is a comparative example. The dashed lines in each of these diagrams show waveforms in the gate driver 500 of Figure 2, which is the present embodiment, and mainly show the differences from the comparative example.

[0056] 6A shows the gate-off command P from the command logic unit 400, FIG. 6B shows the gate current of the semiconductor switching element 101, FIG. 6C shows the gate-source voltage of the semiconductor switching element 101, and FIG. 6D shows the drain current of the semiconductor switching element 101. FIG. 6E shows the drain-source voltage of the semiconductor switching element 101, and FIG. 6F shows the output signal (V OUT 6(G) shows an ON command (R) to the gate voltage pull-up MOSFET 12.

[0057] Compared to Figures 4(A), 4(B), 4(C), 4(D), 4(E), 4(F), and 4(G), Figure 6(E) is different from Figure 4(E). The second modification is different from the example in Fig. 4 and the first modification in Fig. 5 in that the gate drive speed before time t3 at which the gate voltage holding circuit 9 starts to operate is made faster. The gate drive speed can be made faster, for example, by reducing the resistance value (Roff) of the OFF-side gate resistor 10 of the gate drive device 500 shown in Fig. 2. By reducing Roff, the rate of rise (dv / dt) of the drain-source voltage (VDS) of the semiconductor switching element 101 increases before time t3, as shown by the dashed line in Fig. 6(E).

[0058] This makes it possible to reduce the turn-off loss (Eoff), which is determined by the time integral of the product of VDS and drain current (ID), compared to the example in Fig. 4 and the first modified example in Fig. 5. On the other hand, since the gate voltage holding circuit 9 operates after time t3, the effect of suppressing surge voltage and ringing vibration can be obtained, similar to the example in Fig. 4 and the first modified example in Fig. 5.

[0059] In general, in power conversion devices that use the switching operation of semiconductor switching elements such as automotive inverters, the use of higher frequency switching operations allows the size of passive elements such as inductors and capacitors used in the circuit to be smaller, making it possible to miniaturize the device, and so high frequency switching has been promoted. In addition, SiC-MOSFETs, which are majority carrier devices as semiconductor switching elements, do not generate tail currents at turn-off due to minority carriers like Si-IGBTs, so they can reduce switching losses and are suitable for high frequency switching. In addition, the operating limit temperature of SiC, which is a wide band gap semiconductor, is higher than that of Si, making it possible to cool it with a small heat sink that has a large thermal resistance. In this way, SiC-MOSFETs can contribute to the miniaturization of the entire power conversion circuit, and since they are compatible with Si-IGBTs in terms of drive system, it is expected that the application of SiC-MOSFETs to automotive inverters will continue to progress in the future.

[0060] However, even though SiC-MOSFETs have low switching losses, the proportion of switching losses in total power losses increases as switching frequencies increase, making it important to further reduce switching losses. In addition, as dv / dt increases with faster switching speeds, the electromagnetic noise (EMI) generated by semiconductor switching elements increases due to surge voltages and ringing vibrations. Furthermore, as automotive inverters become more compact, the impact of electromagnetic noise on electronic devices around the semiconductor switching elements also becomes greater. As such, there is a trade-off between suppressing switching losses and reducing noise, so it is desirable for automotive inverters to have a drive unit that can optimize both.

[0061] According to this embodiment, the gate driver 500 can reduce both the ringing oscillation and the surge voltage while suppressing the turn-off loss of the semiconductor switching element 101. Therefore, the surge voltage and switching loss (heat generation) are reduced, and the electromagnetic noise generated by the semiconductor switching element 101 is also reduced, making it possible to reduce the size of the inverter circuit 200 configured with the semiconductor switching element 101, ensure the insulation of the electric motor 300, etc., and suppress the electromagnetic noise. When the electric motor 300 is mounted on a vehicle, this can contribute to improving the efficiency and reliability of the control system of an electric vehicle or hybrid vehicle.

[0062] 2 is one means for realizing the gate voltage applied to the semiconductor switching element 101 to be held at the above-mentioned hold voltage Vkeep after VDS rises when the semiconductor switching element 101 is turned off and before VDS reaches a maximum value. The detection circuit 15 is not limited to the detection circuit 15 shown in FIG. 2, and may be configured as described in the modified example described below, for example.

[0063] FIG. 7 is a circuit diagram of a gate driver 500 according to a modification of the first embodiment. As shown in Fig. 7, a timer circuit 19 is used instead of the detection circuit 15. A gate-off command P is input from a command logic unit 400 to the timer circuit 19, and a detection signal Q is output to the hold circuit 14 after a predetermined time has elapsed since the input of the gate-off command P. The same reference numerals are used to designate the same parts as those in the gate driving device 500 shown in Fig. 2, and their description will be simplified.

[0064] Explaining with reference to the waveforms in Fig. 4, at time t0, as shown in Fig. 4(A), a gate-off command P for turning off the semiconductor switching element 101 is output from the command logic unit 400. After a predetermined time has elapsed, for example, at time t2 shown in Fig. 4, the timer circuit 19 outputs a detection signal Q to the hold circuit 14. As shown in Fig. 4(G), the hold circuit 14 outputs an on command R for the gate voltage pull-up MOSFET 12 at time t3 after a certain circuit delay d has elapsed. That is, the timer circuit 19 realizes that the gate voltage applied to the semiconductor switching element 101 is held at the above-mentioned Vkeep after the rise of VDS when the semiconductor switching element 101 is turned off and before VDS reaches a maximum value.

[0065] [Second embodiment] FIG. 8 is a circuit diagram of a gate driver 500' according to the second embodiment. Fig. 8 illustrates the semiconductor switching element 101 and its gate drive device 500' in the lower arm of the U-phase in the inverter circuit 200 shown in Fig. 1. The other semiconductor switching elements 101 and their gate drive devices 500' in the upper arm of the U-phase, and the upper and lower arms of the V-phase and W-phase have the same configuration. Below, the configuration and operation of the semiconductor switching element 101 in the lower arm of the U-phase and its gate drive device 500' will be described, but the configurations and operations of the other semiconductor switching elements 101 and their gate drive devices 500' are also similar.

[0066] A gate driver 500' of the second embodiment is configured by adding a second off-side gate resistor 20, an output stage MOSFET 21, and a changeover switch 22 to a gate voltage holding circuit 9 in comparison with the gate driver 500 of the first embodiment shown in Fig. 2. A holding voltage control section 600 is also added in the second embodiment. The rest of the configuration is the same as that of the first embodiment shown in Fig. 2. The same reference numerals are used to designate the same parts as in Fig. 2, and their description will be simplified.

[0067] As shown in FIG. 8, the source of the output stage MOSFET 21 is connected to the negative side power supply 8. The drain of the output stage MOSFET 21 is connected to the output section 1 of the gate driver 500′ via the second off-side gate resistor 20. The gate of the output stage MOSFET 21 is connected to the gate of the second MOSFET 11 via the changeover switch 22. The temperature (Tj) of the semiconductor switching element 101 and the sensed values ​​of the current (ID) flowing through the semiconductor switching element 101 or the output current (ID) of the inverter circuit 200 are input to the holding voltage control section 600, and the output section of the holding voltage control section 600 is connected to the changeover switch 22. The temperature (Tj) of the semiconductor switching element 101 is acquired from a temperature sensor such as a thermistor (not shown) installed near the semiconductor switching element 101. The current (ID) flowing through the semiconductor switching element 101 or the output current (ID) of the inverter circuit 200 is acquired from a current sensor (not shown).

[0068] The holding voltage control unit 600 transmits a control signal S to the changeover switch 22 based on the input value of Tj or ID. When the changeover switch 22 receives the control signal S, the changeover switch 22 is shorted, and the gate of the second MOSFET 11 and the gate of the output stage MOSFET 21 are both connected to the output part of the buffer circuit 7. When the changeover switch 22 does not receive the control signal S, the changeover switch 22 is opened, and only the gate of the second MOSFET 11 is connected to the output part of the buffer circuit 7.

[0069] When the hold voltage control unit 600 transmits the control signal S to short-circuit the changeover switch 22, the second MOSFET 11 and the output stage MOSFET 21 are both turned on when the semiconductor switching element 101 is turned off. Therefore, when the gate voltage hold circuit 9 starts operating, the output voltage of the gate driver 500' (the voltage between the output unit 1 and the reference potential 2 in FIG. 8) is held at the hold voltage Vkeep1 shown in the following equation (4). Vkeep1=(Vp-Vm)*Roffs / (Rlift+Roffs)+Vm···(4) Here, Roffs is a combined resistance obtained by connecting the off-side gate resistance 10 (Roff) and the second off-side gate resistance 20 (Roff1) in parallel, and Roffs < Roff.

[0070] When the holding voltage control unit 600 does not transmit the control signal S and the switching switch 22 is opened, only the second MOSFET 11 is turned on when the MOSFET is turned off. Therefore, when the gate voltage holding circuit 9 starts operating, the output voltage of the gate driving device 500’ is held at the holding voltage Vkeep shown by the formula (1) described in the first embodiment.

[0071] Due to the difference in the voltage division ratio by the gate resistance of the semiconductor switching element 101, Vkeep1 when the switching switch 22 is short-circuited is smaller than Vkeep when the switching switch 22 is opened (Vkeep1 < Vkeep). That is, by opening and closing the switching switch 22 according to the sensing value of Tj or ID input to the holding voltage control unit 600, the holding voltage Vkeep during the operation of the gate voltage holding circuit 9 can be changed according to the operating conditions (temperature, current) of the semiconductor switching element 101.

[0072] FIG. 9 is a diagram showing the dependence of the mirror voltage (Vmiller) and the threshold voltage (Vth) of the semiconductor switching element 101 on the current. The horizontal axis is the current ID flowing through the semiconductor switching element 101, and the vertical axis is voltages such as the mirror voltage (Vmiller) and the threshold voltage (Vth).

[0073] As shown in the formula (2) described in the first embodiment, Vmiller increases as the current ID flowing through the semiconductor switching element 101 increases. On the other hand, the current dependency of Vth is generally small. In the first embodiment, the hold voltage Vkeep during operation of the gate voltage hold circuit 9 does not change even if the current ID changes, so it is as shown by the broken line a in FIG. 9. At this time, as is clear from FIG. 9, the difference voltage (Vkeep-Vth), which is the difference between Vkeep and Vth, also becomes approximately constant. Therefore, according to the formula (3) described in the first embodiment, the tail current (Itail) flowing inside the semiconductor switching element 101 at time B after time t4 (see FIG. 4(D)) when VDS becomes the maximum value at turn-off also becomes approximately constant. In general, the amplitude of the ringing vibration at turn-off of the semiconductor switching element 101 increases as the current ID flowing through the semiconductor switching element 101 increases, so when the current ID flowing through the semiconductor switching element 101 is large, the ringing vibration suppression effect is greater if Itail is also increased.

[0074] 9, in the second embodiment, when ID exceeds a certain current Ic, the changeover switch 22 is opened to increase Vkeep, that is, the differential voltage (Vkeep-Vth) is increased to increase Itail. When ID is equal to or less than Ic, the changeover switch 22 is short-circuited to decrease Vkeep, that is, the differential voltage (Vkeep-Vth) is reduced to also decrease Itail.

[0075] As a result, Itail is increased when the current is large and the ringing vibration becomes intense, thereby increasing the effect of suppressing the ringing vibration, and in other operating regions, Itail is not increased more than necessary, thereby preventing an excessive increase in switching loss.

[0076] 10 is a diagram showing the temperature dependence of the mirror voltage (Vmiller) and threshold voltage (Vth) of the semiconductor switching element 101. The horizontal axis represents the temperature Tj of the semiconductor switching element 101, and the vertical axis represents voltages such as the mirror voltage (Vmiller) and threshold voltage (Vth).

[0077] Generally, Vth is smaller as the temperature Tj is higher. Also, as shown in the formula (2) described in the first embodiment, Vmiller is also reduced as Vth is reduced. Therefore, as the temperature Tj of the semiconductor switching element 101 is increased, both Vmiller and Vth are reduced. In the first embodiment, the held voltage Vkeep of the gate voltage holding circuit 9 during operation does not change even if the temperature Tj is changed, and is therefore as shown by the broken line c in FIG. 10. At this time, as is clear from FIG. 10, the difference voltage (Vkeep-Vth) between Vkeep and Vth increases as the temperature increases. Therefore, according to the formula (3) described in the first embodiment, after the time t4 (see FIG. 4(D)) when VDS becomes a maximum value at the time of turn-off, the tail current (Itail) flowing inside the semiconductor switching element 101 increases as the temperature increases. If the tail current (Itail) increases when the semiconductor switching element 101 is at a high temperature, it is possible that the switching loss will increase excessively, and the heat generation amount and internal temperature of the semiconductor switching element 101 will increase.

[0078] 10, in the second embodiment, when the temperature Tj of the semiconductor switching element 101 exceeds a certain temperature Tc, the changeover switch 22 is shorted to decrease Vkeep, that is, the differential voltage (Vkeep-Vth) is reduced, and Itail is also decreased. When Tj is equal to or lower than Tc, the changeover switch 22 is opened to increase Vkeep, that is, the differential voltage (Vkeep-Vth) is raised, and Itail is also increased.

[0079] As a result, during high-temperature operation which is likely to result in an increase in switching loss of the semiconductor switching element 101 and an increase in internal temperature, Itail is reduced to prevent an excessive increase in switching loss, and in other operating regions, Itail is increased within an appropriate range, thereby achieving a sufficient ringing suppression effect.

[0080] According to this embodiment, in addition to the effects described in the first embodiment, even if the operating environment (temperature and current) of the semiconductor switching element 101 fluctuates, the surge voltage and switching loss (heat generation) are reduced, and the electromagnetic noise generated by the semiconductor switching element 101 is also reduced, thereby increasing the robustness of control against fluctuations in the operating environment.

[0081] In the gate driver 500' shown in FIG. 8, only one component group consisting of the second OFF-side gate resistor 20, the output stage MOSFET 21, and the changeover switch 22 is added to the gate voltage holding circuit 9, but this embodiment is not limited to this, and multiple components may be added in parallel. By increasing the number of components in parallel, the combination of opening and closing the changeover switches of each component group is controlled by the holding voltage control unit 600 according to the operating environment (temperature and current) of the semiconductor switching element 101. This allows the value of the holding voltage Vkeep to be changed more finely according to the operating environment (temperature and current). Specifically, the switching control of Vkeep according to the current and temperature as shown in FIG. 9 and FIG. 10 can be controlled in multiple stages by setting multiple control values ​​[Ic, Tc] instead of one stage. In addition, the switching control of Vkeep can be performed by combining multiple operating environments such as current and temperature.

[0082] In the gate driving device 500′ shown in FIG. 8, a group of components consisting of an OFF-side gate resistor 20, an output stage MOSFET 21, and a change-over switch 22 are provided in parallel with the second MOSFET 11 side in the gate voltage holding circuit 9, but this may be configured as in the modified example described below.

[0083] FIG. 11 is a circuit diagram of a gate driver 500 ″ according to a modified example of the second embodiment. A gate driver 500″ according to a modified example shown in FIG. 11 is compared with the gate driver 500′ shown in FIG. 8 in that a second ON-side gate resistor 23, an output stage MOSFET 24, and a changeover switch 25 are added to the gate voltage holding circuit 9. Furthermore, the second OFF-side gate resistor 20, the output stage MOSFET 21, and the changeover switch 22 shown in FIG. 8 are deleted. The rest of the configuration is the same as that of the second embodiment shown in FIG. 8. The same reference numerals are used to designate the same parts as in FIGS. 8 and 2, and their description will be simplified.

[0084] As shown in FIG. 11, the source of the output stage MOSFET 24 is connected to the positive-side power supply 4. The drain of the output stage MOSFET 24 is connected to the output section 1 of the gate driver 500″ via the second on-side gate resistor 23 and the changeover switch 25. The gate of the output stage MOSFET 24 is connected to the output section R of the hold circuit 14 together with the gate of the gate voltage pull-up MOSFET 12. The temperature (Tj) of the semiconductor switching element 101 and the sensed values ​​of the current (ID) flowing through the semiconductor switching element 101 or the output current (ID) of the inverter circuit 200 are input to the hold voltage control section 600, and the output section of the hold voltage control section 600 is connected to the changeover switch 25.

[0085] The hold voltage control section 600 transmits a control signal S to the changeover switch 25 based on the input value of Tj or ID. When the changeover switch 25 receives the control signal S, the changeover switch 25 shorts out the changeover switch 25, and the gate voltage pull-up MOSFET 12 and the output stage MOSFET 24 are both connected to the output section 1 of the gate driver 500". Therefore, when the gate voltage hold circuit 9 operates, the output voltage of the gate driver 500" (the voltage between the output section 1 and the reference potential 2) is held at the hold voltage Vkeep2 shown in the following equation (5). Vkeep2=(Vp-Vm)*Roff / (Rons+Roff)+Vm··(5) Here, Rons is a combined resistance of the gate voltage lift resistor 13 (Rlift) and the second on-side gate resistor 23 (Ron1) connected in parallel, and Rons <Rliftである。

[0086] Moreover, when the change-over switch 25 does not receive the control signal S, the change-over switch 25 is opened, and only the gate voltage pull-up MOSFET 12 is connected to the output section 1 of the gate driver 500". Therefore, when the gate voltage hold circuit 9 operates, the output voltage of the gate driver 500" is held at the hold voltage Vkeep shown in equation (1) described in the first embodiment.

[0087] From equations (1) and (5), due to the difference in the voltage division ratio caused by the gate resistance, Vkeep2 when the changeover switch 25 is shorted becomes larger than Vkeep when the changeover switch 25 is open (Vkeep2>Vkeep). That is, by opening and closing the changeover switch 25 according to the sensed value of Tj or ID input to the hold voltage control unit 600, the hold voltage Vkeep during operation of the gate voltage hold circuit 9 can be changed according to the operating environment (temperature, current) of the semiconductor switching element 101. The control of the changeover switch 25 in response to changes in the operating environment of the semiconductor switching element 101 is similar to the contents described with reference to Figs. 9 and 10 etc.

[0088] According to the embodiment described above, the following advantageous effects can be obtained. (1) The drive device for the semiconductor switching element 101 includes a gate drive circuit that drives the voltage-driven semiconductor switching element 101, and a gate voltage holding circuit 9 that holds the gate voltage applied to the semiconductor switching element 101 at a predetermined holding voltage Vkeep that is greater than the threshold voltage Vth of the semiconductor switching element 101 and less than the mirror voltage Vmiller of the semiconductor switching element 101, and the gate voltage holding circuit 9 starts an operation of holding the gate voltage at the holding voltage Vkeep after the voltage between the main terminals of the semiconductor switching element 101 rises when the semiconductor switching element 101 is turned off, but before the voltage between the main terminals reaches a maximum value. This makes it possible to reduce the surge voltage when the switching element is turned off.

[0089] (2) The method of driving the semiconductor switching element 101 is a method of driving a voltage-driven semiconductor switching element 101, and after the voltage between the main terminals of the semiconductor switching element 101 rises when the semiconductor switching element 101 is turned off, and before the voltage between the main terminals reaches a maximum value, an operation is started to hold the gate voltage applied to the semiconductor element at a predetermined holding voltage that is higher than the threshold voltage of the semiconductor switching element 101 and lower than the mirror voltage of the semiconductor switching element 101. This makes it possible to reduce the surge voltage when the switching element is turned off.

[0090] (Modification) The present invention can be carried out by modifying the above-described first and second embodiments as follows. (1) In the first and second embodiments, the three-phase inverter circuit 200 has been described as an example, but the present invention is not limited to this and can be applied to a power conversion device having a pair of upper and lower arms. Furthermore, the pair of upper and lower arms may be configured by a power semiconductor module in which a single arm or multiple arms are stored in a case and electrode terminals are drawn out to the outside of the case. Furthermore, the gate drive devices 500, 500', 500" may be stored (built-in) in the power semiconductor module.

[0091] The present invention is not limited to the above-described embodiments, and other forms that are conceivable within the scope of the technical concept of the present invention are also included within the scope of the present invention, so long as they do not impair the characteristics of the present invention. In addition, the present invention may be configured by combining the above-described embodiments with multiple modified examples, and is not necessarily limited to those that include all of the configurations described. In addition, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0092] 1···Output section of gate driver, 2···Reference potential, 3···Input section of gate driver, 4···Positive power supply, 5···First MOSFET, 6···ON gate resistor, 7···Buffer circuit, 8···Negative power supply, 9···Gate voltage holding circuit, 10···OFF gate resistor, 11···Second MOSFET, 12···Gate voltage raising MOSFET, 13···Gate voltage raising resistor, 14···Hold circuit, 15···Detection circuit, 16···Capacitor, 17···Resistor, 18···Comparator, 19···Typical MOSFET, 22, 25...switching switch, 23...second gate resistor, 100...battery, 101...voltage-driven semiconductor switching element (e.g., SiC-MOSFET), 102...freewheel diode, 110...smoothing capacitor, 200...inverter circuit, 300...motor, 310...motor winding, 400...command logic unit, 500, 500', 500"...gate drive device, 600...holding voltage control unit.

Claims

1. a gate drive circuit for driving a voltage-driven semiconductor switching element; a gate voltage holding circuit that holds a gate voltage applied to the semiconductor switching element at a predetermined holding voltage that is greater than a threshold voltage of the semiconductor switching element and less than a mirror voltage of the semiconductor switching element; the gate voltage holding circuit starts an operation of holding the gate voltage at the holding voltage after a voltage between main terminals of the semiconductor switching element rises when the semiconductor switching element is turned off, and before the voltage between the main terminals reaches a maximum value; The gate voltage holding circuit changes the holding voltage based on the value of the current flowing through the semiconductor switching element so that the gate voltage when the current value of the semiconductor switching element is a first current value is set to the holding voltage that is lower than the gate voltage when the current value of the semiconductor switching element is a second current value that is greater than the first current value.

2. 2. The semiconductor switching element drive device according to claim 1, a detection circuit for detecting a turn-off state of the semiconductor switching element, The gate voltage holding circuit is a drive device for a semiconductor switching element that starts the operation in response to a detection signal from the detection circuit.

3. 2. The semiconductor switching element drive device according to claim 1, a timer circuit for measuring the lapse of a predetermined time from a gate-off command to the semiconductor switching element; The gate voltage holding circuit is a drive device for a semiconductor switching element that starts the operation after the predetermined time determined by the timer circuit has elapsed.

4. 4. The semiconductor switching element drive device according to claim 1, The gate voltage holding circuit changes the holding voltage based on the temperature of the semiconductor switching element so that the gate voltage when the temperature of the semiconductor switching element is at a first temperature is set to the holding voltage higher than the gate voltage when the temperature of the semiconductor switching element is at a second temperature higher than the first temperature.

5. A driving device for a semiconductor switching element according to any one of claims 1 to 3, and an inverter circuit configured with the semiconductor switching element.

6. A method for driving a voltage-driven semiconductor switching element, comprising the steps of: after a voltage between main terminals of the semiconductor switching element rises when the semiconductor switching element is turned off, and before the voltage between the main terminals reaches a maximum value, an operation is started to hold a gate voltage applied to the semiconductor switching element at a predetermined holding voltage that is higher than a threshold voltage of the semiconductor switching element and lower than a mirror voltage of the semiconductor switching element; A method for driving a semiconductor switching element, which changes the holding voltage based on a current value flowing through the semiconductor switching element, so that the gate voltage when the current value of the semiconductor switching element is a first current value is set to the holding voltage lower than the gate voltage when the current value of the semiconductor switching element is a second current value larger than the first current value.

7. 7. The method for driving a semiconductor switching element according to claim 6, A method for driving a semiconductor switching element, comprising: changing a holding voltage based on a temperature of the semiconductor switching element, so that the gate voltage when the temperature of the semiconductor switching element is at a first temperature is set to the holding voltage higher than the gate voltage when the temperature of the semiconductor switching element is at a second temperature higher than the first temperature.

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