Semiconductor device and its manufacturing method

Abstract

The present invention provides a semiconductor device having a multilayer structure composed of a plurality of substrates, wherein: propagation of noise or heat between elements that are formed on upper and lower substrates is able to be suppressed; and deterioration of the characteristics of the elements is also able to be suppressed. This semiconductor device is provided with: a first substrate which comprises a first element layer that contains a first active element, a first wiring layer that is arranged on the first element layer, and a shield layer that is arranged on the first wiring layer and contains a conductive material; and a second substrate which comprises a second element layer that is arranged on the shield layer and contains a second active element, and a second wiring layer that is arranged on the second element layer. The first substrate and the second substrate are stacked upon each other.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Conventionally, a method is known for increasing element density in the vertical direction by stacking multiple substrates on which elements such as transistors are formed (see Patent Document 1). This method is characterized by the fact that, rather than using just one flat surface, the number of elements is increased to two or three surfaces with each stack. When used for elements with limited area, it is possible to increase the number of elements and configure a complex circuit in a small area.

[0003] In image sensors, the pixel size is fixed, and the element area formed for each pixel is limited to the pixel size. Therefore, the size of the element cannot be freely changed, and there is a limit to increasing the number of elements to complicate the circuit. Therefore, for devices such as image sensors with limited element area, increasing the element area by stacking multiple substrates is a very useful method. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-99582 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a laminated structure of a plurality of substrates, noise such as electromagnetic waves, infrared rays, and surges, as well as heat, may propagate between elements formed on upper and lower substrates, possibly deteriorating the characteristics of the elements.

[0006] The present technology aims to provide a semiconductor device and a manufacturing method thereof that can suppress the propagation of noise and heat between elements formed on upper and lower substrates in a stacked structure of multiple substrates, and can suppress deterioration of the characteristics of the elements. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present technology comprises a first substrate including a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a shield layer including a conductive material arranged on the first wiring layer, and a second substrate including a second element layer including a second active element arranged on the shield layer, and a second wiring layer arranged on the second element layer, the first substrate and the second substrate being stacked.

[0008] A manufacturing method for a semiconductor device according to another aspect of the present technology includes forming a first wiring layer on a first element layer including a first active element, and forming a shield layer including a conductive material on the first wiring layer to form a first substrate including the first element layer, the first wiring layer, and a shield layer, preparing a second substrate on which a second element layer including a second active element is formed, and forming the second element layer on the shield layer by bonding the second element layer side of the second substrate to the shield layer side of the first substrate, and forming a second wiring layer on the second element layer.

[0009] A semiconductor device according to another aspect of the present technology comprises a first substrate including a first element layer including a first active element and a first wiring layer arranged on the first element layer, and a second substrate including a second element layer including a second active element and a second wiring layer arranged on the second element layer, the first substrate and the second substrate being stacked together, and an electromagnetic shielding layer including a conductive material is provided between the first substrate and the second substrate.

[0010] A manufacturing method for a semiconductor device according to another aspect of the present technology comprises forming a first wiring layer on a first element layer including a first active element to form a first substrate including the first element layer and the first wiring layer, preparing a second substrate, forming an electromagnetic shielding layer including a conductive material on the first substrate or the second substrate, bonding the first substrate and the second substrate via the electromagnetic shielding layer, forming a second substrate including a second active element on the second substrate, and forming a second wiring layer on the second substrate.

[0011] A semiconductor device according to another aspect of the present technology comprises a first substrate including a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a photoelectric conversion unit arranged below the first element layer, and a second substrate including a second element layer including a second active element, and a second wiring layer arranged on the second element layer, wherein the first substrate and the second substrate are stacked, and a light attenuation unit is provided between the second active element and the photoelectric conversion unit, the light attenuation unit being made of a material having a higher refractive index than the surrounding area.

[0012] A manufacturing method for a semiconductor device according to another aspect of the present technology includes forming a first wiring layer on a first element layer including a first active element, and forming a photoelectric conversion section under the first element layer to form a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion section, preparing a second substrate, forming a light attenuating section on the second substrate made of a material having a higher refractive index than the surrounding area, bonding the light attenuating section sides of the first substrate and the second substrate together, forming a second element layer including a second active element on the second substrate, and forming a second wiring layer on the second substrate.

[0013] A semiconductor device according to another aspect of the present technology comprises a first substrate including a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a photoelectric conversion unit arranged below the first element layer, a second substrate including a second element layer including a second active element and a second wiring layer arranged on the second element layer, and an antireflection unit made of a material having a lower refractive index than a semiconductor material included in the second substrate, wherein the first substrate and the second substrate are stacked, and the antireflection unit is arranged at least between the second active element and the photoelectric conversion unit.

[0014] A manufacturing method for a semiconductor device according to another aspect of the present technology includes forming a first wiring layer on a first element layer including a first active element, and forming a photoelectric conversion section under the first element layer to form a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion section, preparing a second substrate, forming an antireflection section on the second substrate made of a material having a lower refractive index than a semiconductor material contained in the second substrate, bonding the antireflection section sides of the first substrate and the second substrate together, forming a second element layer including a second active element on the second substrate, and forming a second wiring layer on the second substrate. [Brief description of the drawings]

[0015] [Figure 1] 1 is a diagram illustrating an example of a schematic configuration of an imaging device according to a first embodiment of the present technology. [Diagram 2] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit of FIG. [Diagram 3] 1 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 4] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the vertical direction. [Diagram 5] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the vertical direction. [Figure 6] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the horizontal direction. [Figure 7] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the horizontal direction. [Figure 8] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the horizontal direction. [Figure 9] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging device in FIG. 1 in the horizontal direction. [Figure 10] FIG. 11 is a diagram illustrating an example of a circuit configuration of an imaging device including the imaging device according to the above embodiment and its modified example. [Figure 11] 11 is a diagram illustrating an example in which the imaging device of FIG. 10 is configured by stacking three substrates. [Figure 12] 13 is a diagram illustrating an example in which a logic circuit is formed separately on a substrate on which sensor pixels are provided and on a substrate on which a readout circuit is provided. FIG. [Figure 13] FIG. 13 is a diagram illustrating an example in which a logic circuit is formed on a third substrate. [Figure 14] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Figure 15] 15 is a diagram illustrating an example of an imaging procedure in the imaging system of FIG. 14. [Figure 16] 1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present technology. [Figure 17] 1 is a conceptual diagram of substrate lamination in a semiconductor device according to a first embodiment of the present technology. [Figure 18] 2 is an equivalent circuit diagram of a pixel region of the semiconductor device according to the first embodiment of the present technology. [Figure 19] 1 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a first embodiment of the present technology. [Figure 20] 20 is a horizontal cross-sectional view taken along the AA direction in FIG. 19. [Figure 21] 1A to 1C are cross-sectional views illustrating steps in a manufacturing method for a semiconductor device according to a first embodiment of the present technology. [Figure 22] 22A to 22D are cross-sectional views illustrating steps subsequent to FIG. 21 in the method for manufacturing the semiconductor device according to the first embodiment of the present technology. [Figure 23] 23A to 23C are cross-sectional views illustrating steps subsequent to FIG. 22 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 24]24A to 24C are cross-sectional views illustrating steps subsequent to FIG. 23 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Diagram 25] 25A to 25C are cross-sectional views illustrating steps subsequent to FIG. 24 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 26] 26A to 26C are cross-sectional views illustrating steps subsequent to FIG. 25 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 27] 27A to 27C are cross-sectional views illustrating steps subsequent to FIG. 26 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 28] 28A to 28C are cross-sectional views illustrating steps subsequent to FIG. 27 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Figure 29] 29A to 29C are cross-sectional views illustrating steps subsequent to FIG. 28 in the method for manufacturing the semiconductor device according to the first embodiment of the present technology. [Diagram 30] 30A to 30C are cross-sectional views illustrating steps subsequent to FIG. 29 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Diagram 31] 31A to 31C are cross-sectional views illustrating steps subsequent to FIG. 30 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Diagram 32] 32A to 32C are cross-sectional views illustrating steps subsequent to FIG. 31 in the manufacturing method of the semiconductor device according to the first embodiment of the present technology. [Diagram 33] 11 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a second embodiment of the present technology. FIG. [Diagram 34] 34 is a horizontal cross-sectional view taken along the AA direction in FIG. 33. [Figure 35A] 11 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a third embodiment of the present technology. FIG. [Figure 35B] 13 is a schematic diagram showing the positional relationship between an electromagnetic shielding layer 1302 and a first active element 1221 of a semiconductor device according to a third embodiment of the present technology. FIG. [Figure 36A] 7A to 7C are cross-sectional views illustrating steps in a manufacturing method of a semiconductor device according to a third embodiment of the present technology. [Figure 36B] 7A to 7C are cross-sectional views illustrating steps in a manufacturing method of a semiconductor device according to a third embodiment of the present technology. [Figure 36C]7A to 7C are cross-sectional views illustrating steps in a manufacturing method of a semiconductor device according to a third embodiment of the present technology. [Figure 36D] 7A to 7C are cross-sectional views illustrating steps in a manufacturing method of a semiconductor device according to a third embodiment of the present technology. [Figure 37] 13A to 13C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to a first modified example of the third embodiment of the present technology. [Figure 38] 13 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a second modified example of the third embodiment of the present technology. FIG. [Figure 39] FIG. 13 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to a third modification of the third embodiment of the present technology. [Figure 40A] FIG. 13 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to a fourth modified example of the third embodiment of the present technology, and is a cross-sectional view of a main part of a pixel region. [Figure 40B] 13 is a schematic diagram showing a positional relationship between an electromagnetic shielding layer 1302 and a first active element 1221 of a semiconductor device according to a fourth modification of the third embodiment of the present technology. FIG. [Figure 41A] FIG. 13 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to a fifth modified example of the third embodiment of the present technology, and is a cross-sectional view of a main part of a pixel region. [Figure 41B] 13 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to a fifth modified example of the third embodiment of the present technology, and is a schematic view showing the positional relationship between the electromagnetic shielding layer 1302 and a first active element 1221. FIG. [Diagram 42] 11 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a fourth embodiment of the present technology. FIG. [Figure 43A] FIG. 43A is a schematic diagram showing an enlarged view of the periphery of the light attenuating units 1501 and 1502, and FIG. 43A is a cross-sectional view showing the path of light incident on the light attenuating units 1501 and 1502. [Figure 43B] 15 is a schematic enlarged view of the periphery of the light attenuating units 1501 and 1502, and a schematic top view showing an example of the arrangement of the light attenuating units 1501 and 1502. FIG. [Figure 44A] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fourth embodiment of the present technology. [Figure 44B]44B is a cross-sectional view showing a process subsequent to FIG. 44A in the method for manufacturing the semiconductor device according to the fourth embodiment of the present technology. [Figure 44C] 44B in a cross-sectional view illustrating a process in the method for manufacturing a semiconductor device according to the fourth embodiment of the present technology. FIG. [Figure 45D] 44D is a cross-sectional view showing a process subsequent to FIG. 44C in the method for manufacturing the semiconductor device according to the fourth embodiment of the present technology. [Figure 45E] 45D in the manufacturing method of the semiconductor device according to the fourth embodiment of the present technology. FIG. [Fig.45F] 45E in a cross-sectional view illustrating a process in the method for manufacturing a semiconductor device according to the fourth embodiment of the present technology. FIG. [Figure 46G] 45F in a cross-sectional view illustrating a process in the method for manufacturing a semiconductor device according to the fourth embodiment of the present technology. FIG. [Fig. 46H] 46A to 46G in a cross-sectional view showing a process in the method for manufacturing the semiconductor device according to the fourth embodiment of the present technology. [Fig.47I] 46H in a cross-sectional view showing a process in the method for manufacturing a semiconductor device according to a fourth embodiment of the present technology. FIG. [Figure 47J] 47I in a cross-sectional view showing a process in the method for manufacturing a semiconductor device according to a fourth embodiment of the present technology. FIG. [Figure 48] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a first modified example of the fourth embodiment of the present technology. FIG. [Figure 49] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a second modified example of the fourth embodiment of the present technology. FIG. [Figure 50A] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second modified example of the fourth embodiment of the present technology. [Figure 50B] 50B is a cross-sectional view illustrating a process subsequent to FIG. 50A in the method for manufacturing a semiconductor device according to Modification 2 of the fourth embodiment of the present technology. [Figure 50C] 50B in a cross-sectional view illustrating a process subsequent to FIG. 50B in the method for manufacturing a semiconductor device according to Modification 2 of the fourth embodiment of the present technology. [Fig. 51D] 50C in a cross-sectional view showing a process subsequent to FIG. 50C in the method for manufacturing a semiconductor device according to Modification 2 of the fourth embodiment of the present technology. [Figure 51E] 51D in a cross-sectional view illustrating a process subsequent to FIG. 51D in the method for manufacturing a semiconductor device according to Modification 2 of the fourth embodiment of the present technology. [Fig. 51F] 51E is a cross-sectional view illustrating a process subsequent to FIG. 51E in the method for manufacturing a semiconductor device according to modified example 2 of the fourth embodiment of the present technology. [Fig. 52G] 51F in a cross-sectional view illustrating a process subsequent to FIG. 51F in the method for manufacturing a semiconductor device according to modified example 2 of the fourth embodiment of the present technology. [Fig. 52H] 52A to 52G are cross-sectional views illustrating a process subsequent to FIG. 52G in the method for manufacturing a semiconductor device according to Modification 2 of the fourth embodiment of the present technology. [Figure 53] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a third modified example of the fourth embodiment of the present technology. FIG. [Figure 54A] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a third modified example of the fourth embodiment of the present technology. [Figure 54B] 54B is a cross-sectional view illustrating a process subsequent to FIG. 54A in the method for manufacturing a semiconductor device according to Modification 3 of the fourth embodiment of the present technology. [Fig. 54C] 54B in a cross-sectional view illustrating a process subsequent to FIG. 54B in the method for manufacturing a semiconductor device according to Modification 3 of the fourth embodiment of the present technology. [Fig. 55D] 54C in a cross-sectional view showing a process subsequent to FIG. 54C in the method for manufacturing a semiconductor device according to Modification 3 of the fourth embodiment of the present technology. [Figure 55E] 55D in a cross-sectional view illustrating a process subsequent to FIG. 55D in the method for manufacturing a semiconductor device according to modified example 3 of the fourth embodiment of the present technology. [Fig. 55F] 55E in a cross-sectional view illustrating a process subsequent to FIG. 55E in the method for manufacturing a semiconductor device according to modified example 3 of the fourth embodiment of the present technology. [Figure 56] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a fourth modified example of the fourth embodiment of the present technology. FIG. [Figure 57] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a fifth modified example of the fourth embodiment of the present technology. FIG. [Figure 58] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a fifth embodiment of the present technology. FIG. [Figure 59]17 is a schematic diagram showing the positional relationship between an antireflection portion 1701 and a connection wiring 1666. FIG. [Figure 60] 11A to 11C are cross-sectional views illustrating steps in a manufacturing method of a semiconductor device according to a fifth embodiment of the present technology. [Figure 61] 61A to 61C are cross-sectional views illustrating steps subsequent to FIG. 60 in the manufacturing method of the semiconductor device according to the fifth embodiment of the present technology. [Figure 62] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a first modified example of the fifth embodiment of the present technology. FIG. [Figure 63] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first modified example of the fifth embodiment of the present technology. [Figure 64] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a second modified example of the fifth embodiment of the present technology. FIG. [Figure 65] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second modified example of the fifth embodiment of the present technology. [Figure 66] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a third modified example of the fifth embodiment of the present technology. FIG. [Figure 67] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a fourth modified example of the fifth embodiment of the present technology. FIG. [Figure 68] 13 is a partially enlarged cross-sectional view of a semiconductor device according to a fifth modified example of the fifth embodiment of the present technology. FIG. [Figure 69] FIG. 13 is a schematic configuration diagram of an electronic device according to another embodiment of the present technology. [Figure 70] 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure. [Figure 71] 71 is a plan view showing a schematic configuration of the imaging device shown in FIG. 70. [Figure 72] 72 is a schematic diagram showing a cross-sectional configuration taken along line III-III' shown in FIG. 71. [Figure 73] FIG. 71 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 70. [Figure 74] 10 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. [Figure 75] 73 is a schematic cross-sectional view illustrating an example of a specific configuration of the imaging device shown in FIG. 72. [Figure 76A] 76 is a schematic diagram illustrating an example of a planar configuration of a main part of a first substrate shown in FIG. 75. [Figure 76B] 76B is a schematic diagram showing a planar configuration of a pad portion together with a main portion of the first substrate shown in FIG. 76A. [Figure 77] 76 is a schematic diagram illustrating an example of a planar configuration of the second substrate (semiconductor layer) illustrated in FIG. 75. FIG. [Figure 78] 76 is a schematic diagram showing an example of a planar configuration of a pixel circuit and a main part of a first substrate, together with the first wiring layer shown in FIG. 75. [Figure 79] 76 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 75. [Figure 80] 76 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer illustrated in FIG. 75. [Figure 81] 76 is a schematic diagram illustrating an example of a planar configuration of the third wiring layer and the fourth wiring layer illustrated in FIG. 75. [Figure 82] FIG. 73 is a schematic diagram for explaining a path of an input signal to the imaging device shown in FIG. 72. [Figure 83] FIG. 73 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 72. [Figure 84] 78 is a schematic diagram illustrating a modified example of the planar configuration of the second substrate (semiconductor layer) shown in FIG. 77. FIG. [Figure 85] 85 is a schematic diagram showing the planar configuration of the pixel circuit shown in FIG. 84 as well as the first wiring layer and the main part of the first substrate. [Figure 86] 86 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 85. [Figure 87] 87 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 86. [Figure 88] 88 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 87. [Figure 89] FIG. 76B is a schematic diagram illustrating a modified example of the planar configuration of the first substrate shown in FIG. 76A. [Figure 90]89. FIG. 90 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. [Figure 91] 91 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 90. [Figure 92] 92 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 91. [Figure 93] 93 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 92. [Figure 94] 94 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 93. [Figure 95] 89. FIG. 91 is a schematic diagram illustrating another example of the planar configuration of the first substrate shown in FIG. [Figure 96] 96 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 95. FIG. [Figure 97] 97 is a schematic diagram showing an example of the planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 96. [Figure 98] 98 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 97. [Figure 99] 99 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 98. [Figure 100] 99 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 99. [Figure 101] 73 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 72. [Figure 102] 102 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 101. FIG. [Figure 103] 102 is a schematic diagram for explaining the signal path of a pixel signal in the imaging device shown in FIG. 101. [Figure 104] 76 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 75. [Figure 105] FIG. 74 is a diagram illustrating another example of the equivalent circuit shown in FIG. 73. [Fig. 106] FIG. 76B is a schematic plan view illustrating another example of the pixel separating portion shown in FIG. 76A etc. [Figure 107] 13 is a cross-sectional view in a thickness direction showing an example configuration of an imaging device according to a seventh embodiment of the present disclosure. FIG. [Figure 108] 13 is a cross-sectional view in a thickness direction showing an example configuration of an imaging device according to a seventh embodiment of the present disclosure. FIG. [Figure 109] 13 is a cross-sectional view in a thickness direction showing an example configuration of an imaging device according to a seventh embodiment of the present disclosure. FIG. [Figure 110] FIG. 13 is a horizontal cross-sectional view showing an example layout of a plurality of pixel units according to a seventh embodiment of the present disclosure. [Figure 111] FIG. 13 is a horizontal cross-sectional view showing an example layout of a plurality of pixel units according to a seventh embodiment of the present disclosure. [Figure 112] FIG. 13 is a horizontal cross-sectional view showing an example layout of a plurality of pixel units according to a seventh embodiment of the present disclosure. [Figure 113] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Fig. 114] 114 is a diagram showing an example of an imaging procedure of the imaging system shown in FIG. 113. [Figure 115] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Fig. 116] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 117] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 118] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the first to seventh embodiments of the present technology will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are given the same or similar symbols. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that there are parts with different dimensional relationships and ratios between the drawings. Note that the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present.

[0017] (First embodiment) [composition] 1 shows an example of a schematic configuration of an imaging device 1 according to a first embodiment of the present technology. The imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging device 1 is an imaging device with a three-dimensional structure configured by bonding together the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0018] The first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in a pixel region 13 in the first substrate 10. The second substrate 20 has a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixel 12, one for every four sensor pixels 12, on a semiconductor substrate 21. The semiconductor substrate 21 corresponds to a specific example of a "second semiconductor substrate" of the present technology. The second substrate 20 has a plurality of pixel driving lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a logic circuit 32 that processes pixel signals on a semiconductor substrate 31. The semiconductor substrate 31 corresponds to a specific example of a "third semiconductor substrate" of the present technology. The logic circuit 32 has, for example, a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs to the outside an output voltage Vout for each sensor pixel 12. In the logic circuit 32, for example, a low-resistance region made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0019] The vertical drive circuit 33, for example, sequentially selects the plurality of sensor pixels 12 on a row-by-row basis. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34, for example, performs CDS processing to extract a signal level of the pixel signal and holds pixel data according to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0020] Fig. 2 shows an example of the sensor pixels 12 and the readout circuit 22. In the following, a case will be described in which four sensor pixels 12 share one readout circuit 22 as shown in Fig. 2. Here, "shared" refers to the outputs of the four sensor pixels 12 being input to a common readout circuit 22.

[0021] Each sensor pixel 12 has components in common with one another. In Fig. 2, in order to distinguish the components of each sensor pixel 12 from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of each sensor pixel 12. In the following, when it is necessary to distinguish the components of each sensor pixel 12 from one another, an identification number is added to the end of the reference numerals of the components of each sensor pixel 12, but when it is not necessary to distinguish the components of each sensor pixel 12 from one another, the identification number at the end of the reference numerals of the components of each sensor pixel 12 is omitted.

[0022] Each sensor pixel 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of a "photoelectric conversion element" of the present technology. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 23. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0023] The floating diffusions FD of the sensor pixels 12 sharing one readout circuit 22 are electrically connected to each other and to an input terminal of the common readout circuit 22. The readout circuit 22 has, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted as necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to a power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel drive line 23 (see FIG. 1). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to a vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see FIG. 1).

[0024] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR extends from the surface of the semiconductor substrate 11 to a depth reaching the PD 41 through the well layer 42, as shown in FIG. 4 described later. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal of a voltage corresponding to the level of the charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier, and outputs a pixel signal of a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0025] The source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, the FD transfer transistor FDG is provided between the source of the reset transistor RST and the gate of the amplification transistor AMP, and the gate of the amplification transistor AMP is electrically connected to the source of the FD transfer transistor FDG.

[0026] The FD transfer transistor FDG is used to switch the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). Considering these, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0027] 3 shows an example of a connection between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. For example, as shown in FIG. 3, when four readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. In FIG. 3, in order to distinguish each vertical signal line 24, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of each vertical signal line 24.

[0028] Fig. 4 shows an example of a vertical cross-sectional configuration of the imaging device 1. Fig. 4 illustrates a cross-sectional configuration of a portion of the imaging device 1 facing the sensor pixel 12. The imaging device 1 is configured by laminating a first substrate 10, a second substrate 20, and a third substrate 30 in this order, and further includes a color filter 40 and a light receiving lens 50 on the back surface side (light incident surface side) of the first substrate 10. The color filter 40 and the light receiving lens 50 are each provided, for example, one for each sensor pixel 12. In other words, the imaging device 1 is a back-illuminated imaging device.

[0029] The first substrate 10 is formed by laminating an insulating layer 46 on the semiconductor substrate 11. The insulating layer 46 corresponds to a specific example of the "first insulating layer" of the present technology. The first substrate 10 has the insulating layer 46 as a part of an interlayer insulating film 51. The insulating layer 46 is provided in a gap between the semiconductor substrate 11 and a semiconductor substrate 21 described later. The semiconductor substrate 11 is formed of a silicon substrate. The semiconductor substrate 11 has a p-well layer 42, for example, in a part of the surface and in the vicinity thereof, and has a PD 41 of a different conductivity type from the p-well layer 42 in the other region (region deeper than the p-well layer 42). The p-well layer 42 is formed of a p-type semiconductor region. The PD 41 is formed of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The semiconductor substrate 11 has a floating diffusion FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

[0030] The first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 is configured such that the transfer transistor TR and the floating diffusion FD are provided on the surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 has an element isolation section 43 that isolates each sensor pixel 12. The element isolation section 43 is formed extending in the normal direction (direction perpendicular to the surface of the semiconductor substrate 11) of the semiconductor substrate 11. The element isolation section 43 is provided between two sensor pixels 12 adjacent to each other. The element isolation section 43 electrically isolates the sensor pixels 12 adjacent to each other. The element isolation section 43 is made of, for example, silicon oxide. The element isolation section 43 penetrates, for example, the semiconductor substrate 11. The first substrate 10 further has, for example, a p-well layer 44 that is a side surface of the element isolation section 43 and is in contact with the surface on the photodiode PD side. The p-well layer 44 is composed of a semiconductor region of a different conductivity type (specifically, p-type) from the photodiode PD. The first substrate 10 further has, for example, a fixed charge film 45 in contact with the back surface of the semiconductor substrate 11. The fixed charge film 45 is negatively charged in order to suppress the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for such insulating films include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light-receiving surface side of the semiconductor substrate 11 by the electric field induced by the fixed charge film 45. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed charge film 45, and is provided at a position facing the sensor pixel 12 via the fixed charge film 45. The light receiving lens 50 is provided, for example, in contact with the color filter 40, and is provided at a position facing the sensor pixel 12 with the color filter 40 and the fixed charge film 45 interposed therebetween.

[0031] The second substrate 20 is configured by laminating an insulating layer 52 on the semiconductor substrate 21. The insulating layer 52 corresponds to a specific example of the "third insulating layer" of the present technology. The second substrate 20 has the insulating layer 52 as a part of the interlayer insulating film 51. The insulating layer 52 is provided in the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is configured of a silicon substrate. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided on the front surface side (the third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11. That is, the second substrate 20 is bonded to the first substrate 10 face-to-back. The second substrate 20 further has an insulating layer 53 penetrating the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The insulating layer 53 corresponds to a specific example of a "second insulating layer" of the present technology. The second substrate 20 has the insulating layer 53 as a part of the interlayer insulating film 51. The insulating layer 53 is provided so as to cover the side surfaces of the through wiring 54 described later.

[0032] The laminated body made of the first substrate 10 and the second substrate 20 has an interlayer insulating film 51 and a through wiring 54 provided in the interlayer insulating film 51. The through wiring 54 corresponds to a specific example of the "first through wiring" of the present technology. The laminated body has one through wiring 54 for each sensor pixel 12. The through wiring 54 extends in the normal direction of the semiconductor substrate 21 and is provided by penetrating a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through wiring 54. Specifically, the through wiring 54 is electrically connected to the floating diffusion FD and a connection wiring 55 described later.

[0033] The stacked body made of the first substrate 10 and the second substrate 20 further has through-wires 47, 48 (see FIG. 10 described later) provided in the interlayer insulating film 51. The through-wire 48 corresponds to a specific example of the "first through-wire" of the present technology. The stacked body has one through-wire 47 and one through-wire 48 for each sensor pixel 12. The through-wires 47, 48 each extend in the normal direction of the semiconductor substrate 21, and are provided penetrating a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wires 47, 48. Specifically, the through-wire 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and the wiring in the second substrate 20. The through-wire 48 is electrically connected to the transfer gate TG and the pixel driving line 23.

[0034] The second substrate 20 has, for example, a plurality of connection parts 59 electrically connected to the readout circuit 22 and the semiconductor substrate 21 in the insulating layer 52. The second substrate 20 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57, and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided in the insulating layer 57. The wiring layer 56 further has, for example, a plurality of connection wirings 55 in the insulating layer 57, one for each of the four sensor pixels 12. The connection wirings 55 electrically connect the through wirings 54 electrically connected to the floating diffusions FD included in the four sensor pixels 12 sharing the readout circuit 22 to each other. Here, the total number of the through wirings 54, 48 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is twice the total number of the sensor pixels 12 included in the first substrate 10. Furthermore, the total number of the through wirings 54, 48, and 47 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is three times the total number of the sensor pixels 12 included in the first substrate 10.

[0035] The wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of, for example, a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30. For example, one pad electrode 58 is provided for each pixel driving line 23 and vertical signal line 24. Here, the total number of pad electrodes 58 (or the total number of connections between the pad electrodes 58 and pad electrodes 64 (described later)) is less than the total number of sensor pixels 12 included in the first substrate 10.

[0036] The third substrate 30 is configured, for example, by laminating an interlayer insulating film 61 on a semiconductor substrate 31. As described later, the third substrate 30 is bonded to the second substrate 20 with the front surfaces facing each other, so that when describing the internal configuration of the third substrate 30, the description of the top and bottom is reversed from the top and bottom direction in the drawings. The semiconductor substrate 31 is configured of a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided on the front surface side portion of the semiconductor substrate 31. The third substrate 30 further has, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30. The number of pad electrodes 64 does not necessarily need to be multiple, and even one pad electrode 64 can be electrically connected to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58 and 64 to each other. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the logic circuit 32 via the through wiring 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 with the surface of the semiconductor substrate 31 facing the surface side of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0037] [effect] Conventionally, miniaturization of the area per pixel of a two-dimensional imaging device has been achieved by introducing a microprocess and improving the mounting density. In recent years, imaging devices with a three-dimensional structure have been developed to further miniaturize imaging devices and miniaturize the area per pixel. In an imaging device with a three-dimensional structure, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel are stacked on top of each other. This makes it possible to increase the integration density of sensor pixels and increase the size of the signal processing circuit while maintaining the same chip size as before.

[0038] However, when semiconductor chips are stacked in three layers in a three-dimensional imaging device, it is not possible to bond all of the semiconductor substrates face-to-face. If semiconductor substrates are stacked in three layers without any consideration, the structure for electrically connecting the semiconductor substrates may result in an increase in chip size or an impediment to miniaturization of the area per pixel.

[0039] On the other hand, in this embodiment, the sensor pixels 12 and the readout circuit 22 are formed on different substrates (the first substrate 10 and the second substrate 20). This allows the sensor pixels 12 and the readout circuit 22 to have larger areas than when the sensor pixels 12 and the readout circuit 22 are formed on the same substrate. As a result, the photoelectric conversion efficiency can be improved and the transistor noise can be reduced. In addition, the first substrate 10 having the sensor pixels 12 and the second substrate 20 having the readout circuit 22 are electrically connected to each other by the through wiring 54 provided in the interlayer insulating film 51. This allows the chip size to be further reduced compared to when the first substrate 10 and the second substrate 20 are electrically connected to each other by bonding between pad electrodes or by through wiring (for example, TSV (Thorough Si Via)) that penetrates the semiconductor substrate. In addition, the resolution can be further increased by further miniaturizing the area per pixel. In addition, when the chip size is the same as before, the formation area of ​​the sensor pixels 12 can be expanded. In this embodiment, the readout circuit 22 and the logic circuit 32 are formed on different substrates (the second substrate 20 and the third substrate 30). This allows the areas of the readout circuit 22 and the logic circuit 32 to be enlarged compared to when the readout circuit 22 and the logic circuit 32 are formed on the same substrate. In addition, the areas of the readout circuit 22 and the logic circuit 32 are not restricted by the element isolation portion 43, so that noise characteristics can be improved. In this embodiment, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 to each other. Here, since the readout circuit 22 is formed on the second substrate 20 and the logic circuit 32 is formed on the third substrate 30, the structure for electrically connecting the second substrate 20 and the third substrate 30 to each other can be formed with a more flexible layout in terms of the arrangement, the number of contacts for connection, and the like, compared to the structure for electrically connecting the first substrate 10 and the second substrate 20 to each other. Therefore, bonding between the pad electrodes 58, 64 can be used for electrical connection between the second substrate 20 and the third substrate 30. In this manner, in the present embodiment, the substrates are electrically connected to each other in accordance with the integration degree of the substrates.This prevents the chip size from increasing and prevents miniaturization of the area per pixel from being hindered, which would otherwise be caused by the structure for electrically connecting the substrates together. As a result, it is possible to provide an imaging device 1 with a three-layer structure that has the same chip size as before and does not prevent miniaturization of the area per pixel.

[0040] In the present embodiment, the sensor pixels 12 having the photodiodes PD, the transfer transistors TR, and the floating diffusions FD are formed on the first substrate 10, and the readout circuits 22 having the reset transistors RST, the amplification transistors AMP, and the selection transistors SEL are formed on the second substrate 20. This allows the sensor pixels 12 and the readout circuits 22 to have larger areas than when they are formed on the same substrate. As a result, even when the pad electrodes 58, 64 are bonded to each other for electrical connection between the second substrate 20 and the third substrate 30, the chip size does not increase and the miniaturization of the area per pixel is not hindered. As a result, it is possible to provide an imaging device 1 having a three-layer structure that does not hinder the miniaturization of the area per pixel with the same chip size as before. Specifically, by reducing the number of transistors provided on the first substrate 10, the area of ​​the photodiodes PD of the sensor pixels 12 in particular can be enlarged. This increases the amount of saturated signal charge in photoelectric conversion, thereby improving the photoelectric conversion efficiency. In the second substrate 20, the degree of freedom in the layout of each transistor in the readout circuit 22 can be ensured. In addition, since the area of ​​each transistor can be increased, noise affecting pixel signals can be reduced by increasing the area of ​​the amplification transistor AMP in particular. Even if the pad electrodes 58, 64 are bonded to each other for electrical connection between the second substrate 20 and the third substrate 30, the chip size does not increase and miniaturization of the area per pixel is not hindered. As a result, it is possible to provide a three-layered imaging device 1 that has the same chip size as before and does not hinder miniaturization of the area per pixel.

[0041] In the present embodiment, the second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11, and the third substrate 30 is bonded to the second substrate 20 with the front surface side of the semiconductor substrate 31 facing the front surface side of the semiconductor substrate 21. By using the through wiring 54 for electrical connection between the first substrate 10 and the second substrate 20 and using bonding between the pad electrodes 58, 64 for electrical connection between the second substrate 20 and the third substrate 30, it is possible to provide an imaging device 1 with a three-layer structure that does not hinder miniaturization of the area per pixel with the same chip size as before.

[0042] In the present embodiment, the cross-sectional area of ​​the through wiring 54 is smaller than the cross-sectional area of ​​the joint between the pad electrodes 58, 64. This makes it possible to provide an imaging device 1 with a three-layer structure that does not impede miniaturization of the area per pixel while maintaining the same chip size as before.

[0043] In the logic circuit 32 of the present embodiment, a low-resistance region made of silicide formed by a salicide (self-aligned silicide) process such as CoSi2 or NiSi is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal. Here, the logic circuit 32 is provided on the third substrate 30. Therefore, the logic circuit 32 can be formed by a process different from the process for forming the sensor pixels 12 and the readout circuit 22. As a result, a high-temperature process such as thermal oxidation can be used when forming the sensor pixels 12 and the readout circuit 22. In addition, the logic circuit 32 can be made of silicide, which is a material with low heat resistance. Therefore, when a low-resistance region made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode of the logic circuit 32, the contact resistance can be reduced, and as a result, the operation speed of the logic circuit 32 can be increased.

[0044] In addition, in this embodiment, the first substrate 10 is provided with an element isolation section 43 that isolates each sensor pixel 12. However, in this embodiment, the sensor pixel 12 having the photodiode PD, the transfer transistor TR, and the floating diffusion FD is formed on the first substrate 10, and the readout circuit 22 having the reset transistor RST, the amplifying transistor AMP, and the selection transistor SEL is formed on the second substrate 20. This allows the area of ​​the sensor pixel 12 and the readout circuit 22 to be enlarged even if the area surrounded by the element isolation section 43 is reduced due to miniaturization of the area per pixel. As a result, even if the element isolation section 43 is used, the chip size does not increase and miniaturization of the area per pixel is not hindered. Therefore, it is possible to provide an imaging device 1 with a three-layer structure that has the same chip size as before and does not hinder miniaturization of the area per pixel.

[0045] Moreover, in this embodiment, the element isolation portion 43 penetrates the semiconductor substrate 11. As a result, even if the distance between the sensor pixels 12 is shortened due to miniaturization of the area per pixel, signal crosstalk between the adjacent sensor pixels 12 can be suppressed, and degradation of image quality due to reduced resolution and color mixing on a reproduced image can be suppressed.

[0046] In addition, in this embodiment, the stacked body consisting of the first substrate 10 and the second substrate 20 has three through wirings 54, 47, 48 for each sensor pixel 12. The through wiring 54 is electrically connected to the gate (transfer gate TG) of the transfer transistor TR, the through wiring 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11, and the through wiring 48 is electrically connected to the floating diffusion FD. That is, the number of through wirings 54, 47, 48 is greater than the number of sensor pixels 12 included in the first substrate 10. However, in this embodiment, the through wiring 54 with a small cross-sectional area is used for the electrical connection between the first substrate 10 and the second substrate 20. This allows the chip size to be further reduced, and the area per pixel in the first substrate 10 to be further miniaturized. As a result, it is possible to provide an imaging device 1 with a three-layer structure that does not hinder miniaturization of the area per pixel with the same chip size as before.

[0047] (Modification) Modifications of the imaging device 1 according to the above embodiment will be described below. In the following modifications, the same reference numerals are given to configurations common to the above embodiment.

[0048] [Variation A] Fig. 5 shows a modified vertical cross-sectional configuration of the imaging device 1 according to the above embodiment. Fig. 5 shows a modified cross-sectional configuration of Fig. 4. In this modified example, the transfer transistor TR has a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the well layer 42, but is formed only on the surface of the semiconductor substrate 11. Even when a planar transfer gate TG is used for the transfer transistor TR, the imaging device 1 has the same effects as the above embodiment.

[0049] [Variation B] 6 and 7 show a modified horizontal cross-sectional configuration of the imaging device 1 according to the embodiment. The upper views of FIG. 6 and FIG. 7 show a modified cross-sectional configuration at the cross-section Sec1 of FIG. 4, and the lower view of FIG. 6 shows a modified cross-sectional configuration at the cross-section Sec2 of FIG. 4. In the upper cross-sectional views of FIG. 6 and FIG. 7, a diagram showing a modified surface configuration of the semiconductor substrate 11 in FIG. 4 is superimposed on a diagram showing a modified cross-sectional configuration at the cross-section Sec1 of FIG. 4, and the insulating layer 46 is omitted. In the lower cross-sectional views of FIG. 6 and FIG. 7, a diagram showing a modified surface configuration of the semiconductor substrate 21 is superimposed on a diagram showing a modified cross-sectional configuration at the cross-section Sec2 of FIG. 4.

[0050] As shown in FIG. 6 and FIG. 7, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 (the plurality of dots arranged in a matrix in the figures) are arranged in a band shape in the first direction V1 (the left-right direction in FIG. 6 and FIG. 7) in the plane of the first substrate 10. Note that FIG. 6 and FIG. 7 illustrate a case in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V1. In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusions FD, and are shaped like a ring by the four transfer gates TG, for example.

[0051] The insulating layer 53 is composed of a plurality of blocks extending in a first direction V1. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V1 and arranged side by side in a second direction V2 perpendicular to the first direction V1 via the insulating layer 53. Each block 21A includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is, for example, not arranged directly opposite the four sensor pixels 12, but arranged shifted in the second direction V2.

[0052] 6, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in a region on the second substrate 20 shifted in the second direction V2 from a region facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0053] 7, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG in a region on the second substrate 20 shifted in the second direction V2 from a region facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD transfer transistor FDG in one block 21A.

[0054] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed shifted in the second direction V2 from a position directly opposite the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured with a common impurity region. As a result, the size of the readout circuit 22 can be reduced, or the size of other parts in the readout circuit 22 can be increased.

[0055] [Variation C] 8 shows a modified horizontal cross-sectional configuration of the imaging device 1 according to the above embodiment. In FIG. 8, a modified cross-sectional configuration of FIG.

[0056] In this modification, the semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in the first direction V1 and the second direction V2 with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of a reset transistor RST, an amplifying transistor AMP, and a selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and degradation of image quality due to a decrease in resolution and color mixing on a reproduced image can be suppressed.

[0057] [Variation D] FIG. 9 shows an example of a horizontal cross-sectional configuration of the imaging device 1 according to the above embodiment and its modified example.

[0058] In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Therefore, in this modification, one through wiring 54 is provided for every four sensor pixels 12.

[0059] In the plurality of sensor pixels 12 arranged in a matrix, the four sensor pixels 12 corresponding to an area obtained by shifting a unit area corresponding to four sensor pixels 12 sharing one floating diffusion FD in the first direction V1 by one sensor pixel 12 will be referred to as four sensor pixels 12A for convenience. In this modification, the first substrate 10 shares the through wiring 47 with each of the four sensor pixels 12A. Therefore, in this modification, one through wiring 47 is provided for each of the four sensor pixels 12A.

[0060] In this modification, the first substrate 10 has an element isolation section 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation section 43 does not completely surround the sensor pixel 12, and has gaps (unformed regions) near the floating diffusion FD (through wiring 54) and near the through wiring 47. The gaps allow four sensor pixels 12 to share one through wiring 54, and four sensor pixels 12A to share one through wiring 47. In this modification, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0061] [Variation E] 10 shows an example of a circuit configuration of the imaging device 1 according to the above embodiment and its modified example. The imaging device 1 according to this modified example is a CMOS image sensor equipped with a column-parallel ADC.

[0062] As shown in FIG. 10, the imaging device 1 of this modified example has a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion element, are two-dimensionally arranged in a matrix, as well as a vertical driving circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal driving circuit 35, a horizontal output line 37, and a system control circuit 36.

[0063] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals that serve as standards for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0064] The vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0065] Although not shown here, the sensor pixel 12 may have, for example, a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Although not shown here, the readout circuit 22 may have, for example, a three-transistor configuration that includes a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0066] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and pixel drive lines 23 are wired for each row in this pixel arrangement of m rows and n columns, and vertical signal lines 24 are wired for each column. One end of each of the pixel drive lines 23 is connected to an output terminal corresponding to each row of a vertical drive circuit 33. The vertical drive circuit 33 is composed of a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the pixel drive lines 23.

[0067] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24, and converts analog signals output for each column from each sensor pixel 12 in the pixel region 13 into digital signals and outputs them.

[0068] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as a means for generating a reference voltage Vref having a so-called ramp waveform whose level changes in a sloping manner as time passes. Note that the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0069] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK provided from the system control circuit 36 ​​under the control of a control signal CS1 provided from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column processing unit 15.

[0070] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to each operation mode, namely, a normal frame rate mode in a progressive scanning system in which information of all the sensor pixels 12 is read out, and a high frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased to N times, for example, 2 times, compared to the normal frame rate mode. This switching of the operation mode is executed under the control of control signals CS2 and CS3 provided from the system control circuit 36. Also, an external system controller (not shown) provides the system control circuit 36 ​​with instruction information for switching between the normal frame rate mode and the high frame rate mode.

[0071] The ADCs 34-1 to 34-m all have the same configuration, and the ADC 34-m will be described here as an example. The ADC 34-m includes a comparator 34A, a counting means such as an up / down counter (denoted as U / DCNT in the drawing) 34B, a transfer switch 34C, and a memory device 34D.

[0072] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with a ramp-wave reference voltage Vref supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vco becomes an “L” level.

[0073] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 provided from the system control circuit 36, a clock CK is provided from the system control circuit 36 ​​simultaneously with the DAC 18A, and the up / down counter 34B measures the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation by counting down (DOWN) or counting up (UP) in synchronization with the clock CK.

[0074] Specifically, in the normal frame rate mode, in the readout operation of a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0075] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, counting down from the previous count result during the first read operation is performed to measure the comparison time during the first read operation, and counting up during the second read operation is performed to measure the comparison time during the second read operation.

[0076] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 36, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0077] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the counting result of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0078] In this manner, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line 24 are converted into N-bit digital signals by the operation of each of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m, and stored in the memory device 34D.

[0079] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are sequentially read out to a horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0080] In addition, although not shown in the figure because it is not directly related to the present technology, it is also possible to provide a circuit or the like that performs various signal processing on the imaging data output via the horizontal output line 37 in addition to the above-mentioned components.

[0081] In the imaging device 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that it is possible to independently control the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37.

[0082] [Variation F] FIG. 11 shows an example of the imaging device of FIG. 10 configured by stacking three substrates (first substrate 10, second substrate 20, third substrate 30). In this modification, in the first substrate 10, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center, and a vertical drive circuit 33 is formed around the pixel region 13. In addition, in the second substrate 20, a readout circuit region 15 including a plurality of readout circuits 22 is formed in the center, and the vertical drive circuit 33 is formed around the readout circuit region 15. In the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed. As a result, as in the above embodiment and its modification, the chip size does not increase and the area per pixel is not hindered due to the structure that electrically connects the substrates. As a result, it is possible to provide an imaging device 1 with a three-layer structure that does not hinder the area per pixel from being reduced in size with the same chip size as before. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0083] [Variation G] FIG. 12 shows a modified example of the cross-sectional configuration of the imaging device 1 according to the above embodiment and its modified examples. In the above embodiment and its modified examples, the imaging device 1 is configured by stacking three substrates (first substrate 10, second substrate 20, third substrate 30). However, in the above embodiment and its modified examples, the imaging device 1 may be configured by stacking two substrates (first substrate 10, second substrate 20). In this case, the logic circuit 32 is formed, for example, on the first substrate 10 and the second substrate 20 as shown in FIG. 12. Here, in the circuit 32A provided on the first substrate 10 side of the logic circuit 32, a transistor having a gate structure in which a high dielectric constant film made of a material (e.g., high-k) that can withstand high-temperature processes and a metal gate electrode are stacked is provided. On the other hand, in the circuit 32B provided on the second substrate 20 side, a low-resistance region 26 made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal. This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixels 12. In addition, in the circuit 32B provided on the second substrate 20 side of the logic circuit 32, when the low resistance region 26 made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be increased.

[0084] FIG. 13 shows a modified example of the cross-sectional configuration of the imaging device 1 according to the above embodiment and its modified example. In the logic circuit 32 of the third substrate 30 according to the above embodiment and its modified example, a low-resistance region 37 made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixel 12. In addition, when the low-resistance region 37 made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32, the contact resistance can be reduced. As a result, the operation speed in the logic circuit 32 can be increased.

[0085] [Variation H] In the above-mentioned embodiment and its modified examples, the conductivity type may be reversed. For example, in the description of the above-mentioned embodiment and its modified examples, p-type may be replaced with n-type, and n-type may be replaced with p-type. Even in such a case, the same effect as the above-mentioned embodiment and its modified examples can be obtained.

[0086] (Examples) FIG. 14 shows an example of a schematic configuration of an imaging system 2 including an imaging device 1 according to the above embodiment and its modified example.

[0087] The imaging system 2 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 2 includes, for example, the imaging device 1 according to the above embodiment and its modified example, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the imaging device 1 according to the above embodiment and its modified example, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus line 147.

[0088] The imaging device 1 according to the above embodiment and its modified examples outputs image data according to incident light. The DSP circuit 141 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to the above embodiment and its modified examples. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 on a frame-by-frame basis. The display unit 143 is formed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above embodiment and its modified examples. The storage unit 144 records image data of the moving image or the still image captured by the imaging device 1 according to the above embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation commands for various functions of the imaging system 2 according to an operation by a user. The power supply unit 146 appropriately supplies various power sources that serve as operating power sources for the imaging device 1, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145 according to the above embodiment and its modified examples to these supply targets.

[0089] Next, the imaging procedure in the imaging system 2 will be described.

[0090] 15 shows an example of a flowchart of the imaging operation in the imaging system 2. The user issues an instruction to start imaging by operating the operation unit 145 (step S101). Then, the operation unit 145 transmits an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) executes imaging in a predetermined imaging method (step S103).

[0091] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 141. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 141 stores the image data that has been subjected to the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage unit 144 (step S105). In this manner, imaging is performed in the imaging system 2.

[0092] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to an imaging system 2. This allows the imaging device 1 to be made smaller or have higher definition, and therefore a small or high-definition imaging system 2 can be provided.

[0093] (More specific configuration of the first embodiment) <Configuration of Semiconductor Device> As a more specific configuration of the semiconductor device according to the first embodiment of the present technology, a back-illuminated CMOS image sensor (solid-state imaging device) is illustrated. The semiconductor device according to the first embodiment of the present technology includes a pixel region (unit cell region) 1001, a vertical drive circuit 1003, a column signal processing circuit 1004, a horizontal drive circuit 1005, an output circuit 1006, and a control circuit 1007, as shown in FIG.

[0094] The pixel region 1001 has a plurality of pixels (unit cells) 1002 arranged in a two-dimensional matrix. Each of the plurality of pixels 1002 has a photoelectric conversion unit and a plurality of pixel transistors (cell circuits). The plurality of pixel transistors may employ, for example, four transistors: a transfer transistor, a reset transistor, a selection transistor, and an amplification transistor.

[0095] The vertical drive circuit 1003 is formed of, for example, a shift register. The vertical drive circuit 1003 sequentially selects pixel drive wirings 1008a, supplies a pulse for driving the pixels 1002 to the selected pixel drive wirings 1008a, and drives each pixel 1002 row by row. That is, the vertical drive circuit 1003 sequentially selects and scans each pixel 1002 in the pixel region 1001 in the vertical direction row by row, and supplies an output signal (pixel signal) from the pixel based on a signal charge generated in a photoelectric conversion unit of each pixel 1002 to a column signal processing circuit 1004 through a vertical signal line 1008b.

[0096] The column signal processing circuit 1004 is arranged, for example, for each column of the pixels 1002, and performs signal processing such as noise removal for each pixel column on signals output from one row of the pixels 1002. For example, the column signal processing circuit 1004 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing fixed pattern noise specific to each pixel.

[0097] The horizontal drive circuit 1005 is formed of, for example, a shift register. The horizontal drive circuit 1005 sequentially outputs horizontal scanning pulses to the column signal processing circuits 1004, selects the column signal processing circuits 1004 in order, and causes the selected column signal processing circuits 1004 to output pixel signals that have been subjected to signal processing to a horizontal signal line 1009. The output circuit 1006 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuits 1004 through the horizontal signal line 1009, and outputs the processed pixel signals.

[0098] Based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal, the control circuit 1007 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 1003, the column signal processing circuit 1004, the horizontal drive circuit 1005, etc. Then, the control circuit 1007 outputs the generated clock signals and control signals to the vertical drive circuit 1003, the column signal processing circuit 1004, the horizontal drive circuit 1005, etc.

[0099] The semiconductor device according to the first embodiment of the present technology has a three-dimensional structure obtained by stacking the configuration shown in Fig. 16 as shown in Fig. 17. That is, the semiconductor device according to the first embodiment of the present technology has a stacked structure in which three substrates, a first substrate (sensor substrate) 1101, a second substrate (pixel transistor substrate) 1102, and a third substrate (logic substrate) 1103, are bonded together.

[0100] The first substrate 1101 includes a photoelectric conversion unit forming region 1101a in which a photoelectric conversion unit that photoelectrically converts incident light is formed. In addition to the photoelectric conversion unit, at least a part of a pixel transistor such as a transfer transistor that controls a signal charge resulting from photoelectric conversion may be formed in the photoelectric conversion unit forming region 1101a.

[0101] The second substrate 1102 includes a pixel transistor forming region 1102a in which at least a part of a pixel transistor that controls a signal charge obtained by photoelectric conversion is formed. The pixel transistor forming region 1102a may be formed with at least a part of pixel transistors, such as a reset transistor, a selection transistor, and an amplification transistor. Of the pixel transistors, for example, only the amplification transistor may be provided on the second substrate 1102, and either or both of the reset transistor and the selection transistor may be provided on the third substrate 1103.

[0102] The third substrate 1103 includes a logic circuit forming region 1103a in which a logic circuit for performing signal processing is formed. The logic circuit forming region 1103a may include, as the logic circuit, at least a part of the vertical drive circuit 1003, the column signal processing circuit 1004, the horizontal drive circuit 1005, the output circuit 1006, and the control circuit 1007 shown in FIG.

[0103] 17 shows an example of a laminated structure in which three substrates, a first substrate 1101, a second substrate 1102, and a third substrate 1103, are bonded together, but a laminated structure in which two substrates, a first substrate 1101 and a second substrate 1102, are bonded together may also be used. In that case, for example, a logic circuit formation region 1103a of the third substrate 1103 may be formed in the second substrate 1102, etc. Also, a laminated structure in which one or more substrates are bonded onto the third substrate 1103 may also be used.

[0104] Fig. 18 shows an example of an equivalent circuit of a pixel 1002 of the semiconductor device according to the first embodiment of the present technology. As shown by the boundary in Fig. 18 with a dashed line, the pixel 1002 is composed of a circuit including an active element provided in a first substrate 1101 and a circuit including an active element provided in a second substrate 1102. An "active element" is a semiconductor element having an amplification function or a switching function, such as a transistor.

[0105] As shown in FIG. 18, the first substrate 1101 includes, as active elements, a photodiode PD, which is a photoelectric conversion unit whose anode is grounded, and a transfer transistor T1, whose source is connected to the cathode of the photodiode PD. A floating charge accumulation region (floating diffusion region) FD is connected to the drain of the transfer transistor T1. The charge accumulation region FD is connected to the source of a reset transistor T2, which is an active element provided in the second substrate 1102, and to the gate of an amplifying transistor T3, which is an active element. A selection transistor T4 is further provided as an active element in the second substrate 1102. The source of the amplifying transistor T3 is connected to the drain of the selection transistor T4, and the drain of the amplifying transistor T3 is connected to a power supply Vdd. The source of the selection transistor T4 is connected to a vertical signal line VSL. The drain of the reset transistor T2 is connected to a power supply Vdd.

[0106] During operation of the semiconductor device according to the first embodiment, the signal charge generated by the photodiode PD is accumulated in the charge accumulation region FD via the transfer transistor T1, and the signal charge accumulated in the charge accumulation region FD is read out and applied to the gate of the amplification transistor T3. A horizontal line selection control signal is provided to the gate of the selection transistor T4 from the vertical shift register. By setting the selection control signal to a high (H) level, the selection transistor T4 becomes conductive, and a current corresponding to the potential of the charge accumulation region FD amplified by the amplification transistor T3 flows through the vertical signal line VSL. In addition, by setting the reset control signal applied to the gate of the reset transistor T2 to a high (H) level, the reset transistor T2 becomes conductive, and the signal charge accumulated in the charge accumulation region FD is reset.

[0107] Fig. 19 shows a schematic diagram of a part of the cross-sectional structure of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment has a layered structure in which three substrates, a first substrate 1101, a second substrate 1102, and a third substrate 1103, are bonded together. The semiconductor device according to the first embodiment is a back-illuminated solid-state imaging device, and light is incident from the back side (the lower side of Fig. 19).

[0108] The first substrate 1101 includes a sensor layer 1010, a first element layer 1020 including a first active element 1021 arranged on the sensor layer 1010, a first wiring layer 1030 arranged on the first element layer 1020, and a shield layer (shielding layer) 1040 arranged on the first wiring layer 1030. The second substrate 1102 includes a second element layer 1050 including second active elements 1052, 1053, 1054, and 1055 arranged on the shield layer 1040 via an interlayer insulating film 1042, and a second wiring layer 1060 arranged on the second element layer 1050. The third substrate 1103 includes a third wiring layer 1070 arranged on the second wiring layer 1060, and a third element layer 1080 including third active elements 1082 and 1083 arranged on the third wiring layer 1070.

[0109] The sensor layer 1010 has a plurality of photoelectric conversion units 1011a, 1011b, and 1011c formed on a semiconductor substrate (Si substrate) 1011 made of silicon (Si) or the like. Each of the photoelectric conversion units 1011a, 1011b, and 1011c is composed of a photodiode. The photodiode is composed of a pn junction between a p-type well region (not shown) formed on the Si substrate 1011 and an n-type charge generation region (not shown).

[0110] The adjacent photoelectric conversion units 1011a, 1011b, and 1011c are isolated from each other by an element isolation unit 1012. The element isolation unit 1012 is formed, for example, in a lattice shape when viewed from the bottom of FIG. 19. The element isolation unit 1012 has a function of electrically and optically isolating the adjacent photoelectric conversion units 1011a, 1011b, and 1011c from each other. The element isolation unit 1012 can be composed of, for example, an insulating film embedded in a groove provided in the Si substrate 1011. The insulating film may have a laminated structure of, for example, a fixed charge film such as a hafnium oxide film (HfO2 film) and a silicon oxide film (SiO2 film). Alternatively, the element isolation unit 1012 may be composed of an insulating film embedded in a groove provided in the Si substrate 1011 and a light-shielding metal film such as tungsten (W) embedded in the groove via the insulating film. Below the element isolation portion 1012, a light-shielding film (not shown) such as tungsten (W) may be disposed.

[0111] A planarization film 1091, a color filter 1092, a microlens 1093, wiring (not shown), etc. are arranged on the back surface of the sensor layer 1010. The planarization film 1091 planarizes the back surface of the photoelectric conversion units 1011a, 1011b, and 1011c. The microlens 1093 collects light incident on the photoelectric conversion units 1011a, 1011b, and 1011c. The color filter 1092 separates the light incident on the photoelectric conversion units 1011a, 1011b, and 1011c by color.

[0112] The first element layer 1020 constitutes, for example, a first cell circuit that independently extracts an electrical signal generated by photoelectric conversion of incident light by a plurality of photoelectric conversion units 1011a, 1011b, and 1011c. The first element layer 1020 includes a first active element 1021 that constitutes the first cell circuit and is formed on the surface of a Si substrate 1011. The first active element 1021 can be constituted, for example, by a transfer transistor T1 shown in FIG. 18. The transfer transistor T1 can be constituted of an active element by a MOS transistor, but more generally may be an insulated gate transistor (MIS transistor) such as a MISFET or MISSIT that includes a material other than an oxide film (SiO2 film) in its gate insulating film.

[0113] For convenience, Fig. 19 shows only the gate electrode of the first active element 1021. The gate electrode of the first active element 1021 may be, for example, a vertical gate having a T-shaped cross section. Although different from the circuit configuration shown in Fig. 18, the first element layer 1020 may further include at least one of pixel transistors such as a reset transistor T2, an amplification transistor T3, and a selection transistor T4 in addition to the transfer transistor T1.

[0114] The first wiring layer 1030 is electrically connected to the first element layer 1020. The first wiring layer 1030 has wirings 1031, 1032, 1033, and 1034 embedded in an interlayer insulating film 1035. The wirings 1031, 1032, 1033, and 1034 can be made of a metal such as copper (Cu), and the interlayer insulating film 1035 can be made of a silicon oxide film (SiO2 film). FIG. 19 illustrates a two-layer wiring structure made up of the lower wirings 1031 and 1032 and the upper wirings 1033 and 1034, but the number of layers of the wirings in the first wiring layer 1030 is not limited to this. For example, the number of layers of the wirings in the first wiring layer 1030 may be one layer or three or more layers. The lower wirings 1031 and 1032 and the upper wirings 1033 and 1034 may be electrically connected by vias (not shown).

[0115] The shield layer 1040 has a function of thermally, optically, and electromagnetically shielding between the first element layer 1020 disposed below the shield layer 1040 and the second element layer 1050 disposed above the shield layer 1040. The shield layer 1040 may have a function of blocking the transmission of infrared rays, and may have a function of forming a capacitance for preventing surges.

[0116] The shield layer 1040 may be made of a material containing a conductive material such as a metal, such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), or tungsten (W), or an alloy of these metals. If necessary, a ferromagnetic material, such as ferrite, may also be used as the material for the shield layer 1040. The shield layer 1040 may be made of other conductive materials as long as they are capable of thermal, optical, and electromagnetic shielding.

[0117] The thickness of the shield layer 1040 is, for example, about 300 nm or more and 500 nm or less, but may be less than 300 nm or may be thicker than 500 nm. Although not shown, the shield layer 1040 is connected to a ground potential via a Si substrate 1011. In FIG. 17, the shield layer 1040 is illustrated as a single layer, but may have a laminated structure in which a plurality of conductive materials made of different materials are laminated. The shield layer 1040 is provided with openings (through holes) 1041a and 1041b for passing the connection wirings 1066 and 1067 therethrough.

[0118] The second element layer 1050, for example, constitutes a second cell circuit connected to the first element layer 1020 in correspondence with each of the multiple pixels 1002. The second element layer 1050 is formed on a semiconductor substrate (Si substrate) 1051 made of Si, and has second active elements 1052, 1053, 1054, and 1055 constituting the second cell circuit. For example, each of the second active elements 1052, 1053, 1054, and 1055 can be composed of at least one of the reset transistor T2, the amplification transistor T3, and the selection transistor T4 shown in FIG. 18. Each of the reset transistor T2, the amplification transistor T3, and the selection transistor T4 can be composed of a MOS transistor, but more generally may be a MIS transistor. For convenience, FIG. 19 shows only the gate electrodes of the second active elements 1052, 1053, 1054, and 1055 in a schematic manner.

[0119] The second wiring layer 1060 is electrically connected to the second element layer 1050. The second wiring layer 1060 has wirings 1061, 1062, 1063, and 1064 embedded in an interlayer insulating film 1065. The wirings 1061, 1062, 1063, and 1064 can be made of a metal such as copper (Cu), and the interlayer insulating film 1065 can be made of a silicon oxide film (SiO2 film). FIG. 19 illustrates a two-layer wiring structure including lower wirings 1061 and 1062 and upper wirings 1063 and 1064, but the number of layers of the wirings in the second wiring layer 1060 is not limited to this. For example, the number of layers of the wirings in the second wiring layer 1060 may be one layer or three or more layers. The lower wirings 1061 and 1062 and the upper wirings 1063 and 1064 may be electrically connected by vias (not shown).

[0120] The upper end of the connection wiring 1066 is connected to the wiring 1061 in the lowest layer of the second wiring layer 1060. The connection wiring 1066 extends in the vertical direction so as to penetrate the second element layer 1050, the shield layer 1040, and the first wiring layer 1030. The connection wiring 1066 is provided so as to penetrate the opening 1041a of the shield layer 1040. The lower end of the connection wiring 1066 is connected to a contact portion (not shown) provided on the upper part of the Si substrate 1011 included in the first element layer 1020. For example, the connection wiring 1066 may electrically connect the gate electrode of the amplification transistor formed of the second active element 1053 electrically connected via the wiring 1061 to a charge accumulation region formed on the upper part of the Si substrate 1011 included in the first element layer 1020.

[0121] Moreover, the upper end of a connection wiring 1067 is connected to the wiring 1062 in the bottom layer of the second wiring layer 1060. The connection wiring 1067 extends in the vertical direction so as to penetrate the second element layer 1050 and the shield layer 1040. The connection wiring 1067 is provided so as to penetrate the opening 1041b of the shield layer 1040. The lower end of the connection wiring 1067 is connected to the wiring 1034 of the first wiring layer 1030.

[0122] FIG. 20 shows a horizontal cross-sectional view seen from the AA direction in FIG. 19. A vertical cross-sectional view seen from the BB direction in FIG. 20 corresponds to FIG. 19. As shown in FIG. 20, the connection wirings 1066, 1067 and the interlayer insulating film 1042 have a coaxial cross-sectional shape. The openings 1041a, 1041b of the shield layer 1040 have, for example, a circular cross-sectional shape, and are provided so as to surround the outer peripheral surfaces of the connection wirings 1066, 1067 via the interlayer insulating film 1042. The horizontal cross-sectional pattern of the shield layer 1040 is not limited to this. For example, the horizontal cross-sectional pattern of the shield layer 1040 may be a stripe pattern, a lattice pattern, or a dot pattern extending parallel to each other.

[0123] The third wiring layer 1070 has wirings 1071, 1072, 1073, and 1074 embedded in an interlayer insulating film 1075. The wirings 1071, 1072, 1073, and 1074 can be made of a metal such as copper (Cu). FIG. 19 illustrates a two-layer wiring structure formed by the lower wirings 1071 and 1072 and the upper wirings 1073 and 1074, but the number of layers of the wirings in the third wiring layer 1070 is not limited to this. For example, the number of layers of the wirings in the third wiring layer 1070 may be one layer or three or more layers. The wirings 1071 and 1072 in the bottom layer are electrically connected to the wirings 1063 and 1064 in the top layer of the second wiring layer 1060.

[0124] The third element layer 1080 is formed on a semiconductor substrate (Si substrate) 1081 made of Si, and has third active elements 1082 and 1083 that constitute a logic circuit. Each of the third active elements 1082 and 1083 can be composed of a MOS transistor, but more generally may be an MIS transistor. For convenience, FIG. 19 shows only the gate electrodes of the third active elements 1082 and 1083.

[0125] According to the semiconductor device of the first embodiment, by having the shield layer 1040 between the first element layer 1020 formed on the first substrate 1101 and the second element layer 1050 formed on the second substrate 1102, the first element layer 1020 disposed below the shield layer 1040 is optically, electromagnetically, and thermally shielded from the second element layer 1050 disposed above the shield layer 1040. This eliminates the mutual influence of noise and heat propagated between the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050, and can suppress noise, malfunction, and the like that affect element characteristics. As a result, deterioration of the characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 can be suppressed.

[0126] <Method of Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0127] First, a photoresist film is applied onto the Si substrate 1011, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an etching mask, a deep groove (trench) having vertical sidewalls is formed by dry etching such as reactive ion etching (RIE). Thereafter, the photoresist film is removed, and the Si substrate 1011 is cleaned. Then, an insulating film or a laminated structure of an insulating film and a metal film is embedded inside the groove by an atomic layer deposition (ALD) method or a chemical vapor deposition (CVD) method. Then, the insulating film or the metal film on the Si substrate 1011 is removed by etch-back or chemical mechanical polishing (CMP) or the like. As a result, as shown in FIG. 21, an element isolation portion 1012 is formed in a wall shape on the upper portion of the Si substrate 1011.

[0128] Next, a p-type well region and an n-type charge generation region constituting a photodiode are formed on the upper part of the Si substrate 1011 by photolithography, ion implantation, heat treatment, etc., to form photoelectric conversion units 1011a, 1011b, and 1011c. A diffusion layer such as an n-type charge accumulation region is also formed on the upper part of the Si substrate 1011. Furthermore, a gate insulating film and a gate electrode of the first active element 1021 are formed by CVD, lithography, etching, etc. As a result, the first active element 1021 is formed, and the first element layer 1020 is formed, as shown in FIG.

[0129] Next, as shown in FIG. 23, an interlayer insulating film 1035 and wirings 1031, 1032, 1033, and 1034 are alternately laminated on the Si substrate 1011 by a dual damascene method or the like, thereby forming a first wiring layer 1030.

[0130] Next, a shield layer 1040 made of a metal film is deposited on the first wiring layer 1030 by a CVD method or the like. Then, a photoresist film is applied onto the shield layer 1040, and the photoresist film is patterned by a photolithography technique. Using the patterned photoresist film as an etching mask, a part of the shield layer 1040 is selectively removed by dry etching such as RIE. Then, the photoresist film is removed. As a result, as shown in FIG. 24, openings 1041a and 1041b that expose the surface of the interlayer insulating film 1035 are formed in the shield layer 1040. Then, as shown in FIG. 25, an interlayer insulating film 1042 is deposited on the shield layer 1040 by a CVD method or the like so as to fill the openings 1041a and 1041b of the shield layer 1040.

[0131] On the other hand, as shown in Fig. 26, a Si substrate 1051 is separately prepared, and source and drain regions of second active elements 1052, 1053, 1054, and 1055 are formed on the upper part of the Si substrate 1051 by photolithography, ion implantation, heat treatment, etc. Also, gate insulating films and gate electrodes of the second active elements 1052, 1053, 1054, and 1055 are formed on the Si substrate 1051 by CVD, photolithography, etching, etc. As a result, the second active elements 1052, 1053, 1054, and 1055 are formed. After that, an interlayer insulating film 1056 is deposited on the Si substrate 1051 by CVD, etc.

[0132] Next, a support substrate 1057 is attached using an adhesive or the like to the surface (front surface) of the Si substrate 1051 on which the second active elements 1052, 1053, 1054, and 1055 are formed. Then, the surface (back surface) of the Si substrate 1051 opposite to the surface on which the second active elements 1052, 1053, 1054, and 1055 are formed is ground by CMP or the like to thin the Si substrate 1051 as shown in FIG.

[0133] Next, the surface (rear surface) of the Si substrate 1051 shown in FIG. 27 opposite to the surface on which the second active elements 1052, 1053, 1054, and 1055 are formed is opposed to the surface of the interlayer insulating film 1042 of the first substrate 1101 shown in FIG. 25, and they are bonded as shown in FIG. 28. As a bonding method, for example, after irradiating with plasma, washing with water is performed, and the wafers are bonded to each other in a wafer bonding device. However, the bonding method is not limited to this, and for example, an adhesive or the like may be used for bonding. Furthermore, the support substrate 1057 is peeled off, and the adhesive used for bonding to the support substrate 1057 is peeled off by washing.

[0134] Next, a groove for forming a connection wiring 1066 that penetrates the second element layer 1050, the shield layer 1040, and the first wiring layer 1030 and exposes the surface of the Si substrate 1011, and a groove for forming a connection wiring 1067 that penetrates the second element layer 1050 and the shield layer 1040 and exposes the surface of the wiring 1034 are formed by photoresist technology and dry etching such as RIE. Then, a metal film is deposited so as to fill the groove by a CVD method or the like, and the metal film on the interlayer insulating film 1056 is removed by etch-back or CMP or the like. As a result, as shown in FIG. 29, the connection wiring 1066 whose lower end is connected to the Si substrate 1011 and the connection wiring 1067 whose lower end is connected to the wiring 1034 are formed.

[0135] The connection wirings 1066, 1067 are formed to penetrate the openings 1041a, 1041b of the shield layer 1040. An insulating structure is formed in the Si substrate 1051 of the second element layer 1050 to surround the outer circumferential surfaces of the connection wirings 1066, 1067. If an insulating layer is formed in advance in the portions of the Si substrate 1051 of the second element layer 1050 through which the connection wirings 1066, 1067 penetrate, it is not necessary to form an insulating structure in the Si substrate 1051.

[0136] 30, an interlayer insulating film 1065 and wirings 1061, 1062, 1063, and 1064 are alternately laminated on the interlayer insulating film 1056 by a dual damascene method or the like to form a second wiring layer 1060. The wiring 1061 of the second wiring layer 1060 is formed so as to connect to the upper end of the connection wiring 1066. The wiring 1062 of the second wiring layer 1060 is formed so as to connect to the upper end of the connection wiring 1067.

[0137] On the other hand, as shown in FIG. 31, a Si substrate 1081 is separately prepared, and source and drain regions of third active elements 1082 and 1083 are formed on the upper part of the Si substrate 1081 by photolithography, ion implantation, heat treatment, etc. Furthermore, gate insulating films and gate electrodes of the third active elements 1082 and 1083 are formed by CVD, photolithography, etching, etc. As a result, the third active elements 1082 and 1083 are formed, and the third element layer 1080 is formed. Furthermore, the third wiring layer 1070 is formed by alternately stacking the interlayer insulating film 1075 and the wirings 1071, 1072, 1073, and 1074 on the Si substrate 1081 by the dual damascene method, etc. As a result, the third substrate 1103 is formed.

[0138] Next, the wires 1071, 1072 side of the third wiring layer 1070 of the third substrate 1103 shown in Fig. 31 are placed opposite the wires 1063, 1064 side of the second wiring layer 1060 of the second substrate 1102 shown in Fig. 30, and are bonded together as shown in Fig. 32. Thereafter, the Si substrate 1081 is thinned by grinding the Si substrate 1081 from the front surface side by CMP or the like.

[0139] Next, the Si substrate 1011 is ground from the backside by CMP or the like to expose the element isolation portion 1012 and isolate the photoelectric conversion portions 1011a, 1011b, and 1011c. Furthermore, wiring (not shown), a planarization film 1091, a color filter 1092, a microlens 1093, and the like are formed on the backside of the Si substrate 1011. As a result, the semiconductor device according to the first embodiment shown in FIG. 16 is completed.

[0140] According to the manufacturing method of the semiconductor device according to the first embodiment, the shield layer 1040 is formed between the first element layer 1020 and the second element layer 1050, so that the first element layer 1020 disposed below the shield layer 1040 and the second element layer 1050 disposed above it are optically, electromagnetically, and thermally shielded from each other. This makes it possible to suppress mutual propagation of noise and heat between the first element layer 1020 and the second element layer 1050. This makes it possible to manufacture a semiconductor device that can suppress deterioration of the characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050.

[0141] Second embodiment As shown in Fig. 33, the semiconductor device according to the second embodiment of the present technology is different from the semiconductor device according to the first embodiment shown in Fig. 19 in the structure of the shield layer 1040. Other configurations of the semiconductor device according to the second embodiment of the present technology are similar to those of the semiconductor device according to the first embodiment shown in Fig. 19, and therefore repeated explanations will be omitted.

[0142] 33, a planarization film, a color filter, a microlens, and the like on the back surface side of the Si substrate 1011 are omitted. As the semiconductor device according to the second embodiment of the present technology, a laminated structure in which two substrates, a first substrate 1101 and a second substrate 1102, are bonded together is exemplified, but another substrate such as the third substrate 1103 shown in FIG. 19 may be further laminated on the second substrate 1102.

[0143] In the semiconductor device according to the second embodiment of the present technology, as a part of the shield layer 1040, sheaths 1043 and 1044 are provided around the openings 1041a and 1041b of the shield layer 1040, respectively. The sheaths 1043 and 1044 are electrically connected to the shield layer 1040. As with the shield layer 1040, the sheaths 1043 and 1044 may be made of a material containing a conductive material such as a metal such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), or tungsten (W), or an alloy thereof. The sheaths 1043 and 1044 may be made of the same material as the shield layer 1040, or may be made of a different material.

[0144] The sheath portion 1043 extends in the vertical direction so as to surround the outer circumferential surface of the connection wiring 1066. The upper end of the sheath portion 1043 is located near the wiring 1061 of the second wiring layer 1060. The lower end of the sheath portion 1043 is located near the Si substrate 1011. Insulating structures are formed between the sheath portion 1043 and the connection wiring 1066 and between the sheath portion 1043 and the second element layer 1050.

[0145] The sheath portion 1044 extends in the vertical direction so as to surround the outer circumferential surface of the connection wiring 1067. The upper end of the sheath portion 1044 is located near the wiring 1062 of the second wiring layer 1060. The lower end of the sheath portion 1044 is located near the wiring 1034 of the first wiring layer 1030. Insulating structures are formed between the sheath portion 1044 and the connection wiring 1067 and between the sheath portion 1044 and the second element layer 1050.

[0146] Fig. 34 shows a horizontal cross-sectional view seen from the AA direction in Fig. 33. A vertical cross-sectional view seen from the BB direction in Fig. 34 corresponds to Fig. 33. As shown in Fig. 34, the connection wirings 1066, 1067 and the interlayer insulating film 1042 have a coaxial cross-sectional shape. The sheaths 1043, 1044 have a cylindrical cross-sectional shape, are coaxial with the connection wirings 1066, 1067, and are provided so as to surround the connection wirings 1066, 1067 via the interlayer insulating film 1042. Note that Fig. 34 illustrates a case where the sheaths 1043, 1044 have a cylindrical cross-sectional shape, but the cross-sectional pattern of the sheaths 1043, 1044 is not limited thereto.

[0147] When manufacturing the semiconductor device according to the second embodiment of the present technology, for example, after forming the second element layer 1050, a metal film to be the sheath portions 1043, 1044, an interlayer insulating film, and connection wirings 1066, 1067 are sequentially embedded in grooves penetrating the second element layer 1050 and the shield layer 1040 by dry etching such as CVD and RIE, thereby forming the connection wirings 1066, 1067 and the sheath portions 1043, 1044. Other manufacturing steps of the semiconductor device according to the second embodiment of the present technology are similar to the manufacturing steps of the semiconductor device according to the first embodiment of the present technology, so that redundant explanations will be omitted.

[0148] According to the semiconductor device according to the second embodiment of the present technology, as in the semiconductor device according to the first embodiment of the present technology, the shield layer 1040 is provided between the first element layer 1020 formed on the first substrate 1101 and the second element layer 1050 formed on the second substrate 1102, thereby optically, electromagnetically, and thermally shielding the first element layer 1020 disposed below the shield layer 1040 from the second element layer 1050 disposed above the shield layer 1040. Therefore, mutual influence of noise and heat propagated between the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 is eliminated, and noise, malfunction, and the like that affect element characteristics can be suppressed. As a result, deterioration of the characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054, and 1055 included in the second element layer 1050 can be suppressed.

[0149] Furthermore, according to the semiconductor device of the second embodiment of the present technology, by providing sheath portions 1043, 1044 as part of the shielding layer 1040 so as to extend along the outer peripheral surfaces of the connection wirings 1066, 1067, the connection wirings 1066, 1067 inside the sheath portions 1043, 1044 can propagate signals stably without being affected by capacitive coupling, etc.

[0150] Third embodiment A semiconductor device according to a third embodiment of the present technology will be described with reference to Figs. 35 and 36. The semiconductor device according to the third embodiment is a back-illuminated solid-state imaging device, and light is incident from the back side (the lower side in Fig. 35). Other configurations of the semiconductor device according to the third embodiment of the present technology are similar to those of the semiconductor device according to the first embodiment shown in Fig. 19, and therefore illustrations and descriptions of the overlapping configurations will be omitted.

[0151] As shown in Fig. 35A, the semiconductor device of this embodiment includes a semiconductor substrate 1211, a first active element 1221, a first wiring layer 1230, an opening 1241a, an interlayer insulating film 1242, a semiconductor substrate 1251, a second active element 1252, a wiring 1261, interlayer insulating films 1256 and 1265, a connection wiring 1266, an electromagnetic shielding layer 1302, and anti-diffusion layers 1301 and 1303. Fig. 35B is a schematic diagram showing the positional relationship between the electromagnetic shielding layer 1302 and the first active element 1221. In this embodiment, the electromagnetic shielding layer 1302 is formed in the entire region of each photoelectric conversion unit constituting a pixel, and the electromagnetic shielding layer 1302 covers a plurality of first active elements 1221 in a plan view.

[0152] The electromagnetic shielding layer 1302 is a layer containing a conductive material, and is formed between the first wiring layer 1230 and the interlayer insulating film 1242 so as to cover at least the first active element 1221. The electromagnetic shielding layer 1302 has a conductivity such that the potential in the electromagnetic shielding layer 1302 is constant, and has a function of electromagnetically shielding so that potential fluctuations on the first active element 1221 side do not affect the second active element 1252. A metal layer or a semiconductor layer can be used as a material constituting the electromagnetic shielding layer 1302, and it is particularly preferable to use tungsten (W), titanium (Ti), titanium nitride (TiN), carbon (C), or polycrystalline silicon (Si) in order to prevent diffusion of constituent atoms in a later process. It is preferable that a wiring or the like (not shown) is connected to the electromagnetic shielding layer 1302 to give it a fixed potential, and it is more preferable to give it a ground potential.

[0153] The diffusion prevention layers 1301 and 1303 are layers made of a dielectric material formed on the upper and lower surfaces of the electromagnetic shielding layer 1302, and prevent atoms such as oxygen taken into the electromagnetic shielding layer 1302 when the electromagnetic shielding layer 1302 is formed from diffusing into the first wiring layer 1230 and the interlayer insulating film 1242. The material constituting the diffusion prevention layers 1301 and 1303 is not limited, but may be, for example, SiN.

[0154] Next, the manufacturing method of the semiconductor device according to this embodiment will be described with reference to FIG. 36. FIG. 36 is a cross-sectional view of the manufacturing method of the semiconductor device according to this embodiment. First, as shown in FIG. 36A, a first substrate is prepared in which a first wiring layer 1230 including a first active element 1221 is formed on a semiconductor substrate 1211. Also, as shown in FIG. 36B, a substrate is prepared in which an interlayer insulating film 1242 is formed on one surface of a semiconductor substrate 1251, and a diffusion prevention layer 1303, an electromagnetic shielding layer 1302, and a diffusion prevention layer 1301 are laminated in this order on the surface of the interlayer insulating film 1242. Next, as shown in FIG. 36C, the first wiring layer 1230 and the diffusion prevention layer 1301 are bonded together. Next, as shown in FIG. 36D, a second active element 1252 is formed on the semiconductor substrate 1251, an interlayer insulating film 1256 is formed, an opening 1241a is formed to form a connection wiring 1266, and wiring 1261 and an interlayer insulating film 1265 are formed.

[0155] According to the semiconductor device according to the third embodiment of the present technology, potential fluctuations occurring when the first active element 1221 is driven are electromagnetically shielded by the electromagnetic shielding layer 1302. This makes it possible to prevent substrate bias fluctuations and reduce noise for the second active element 1252. In particular, from the viewpoint of noise reduction, it is preferable to fix the electromagnetic shielding layer 1302 to the ground potential. Furthermore, in this embodiment, even in a semiconductor device that does not have a photoelectric conversion unit on the first substrate, it is possible to prevent substrate bias fluctuations and reduce noise by the electromagnetic shielding layer 1302 provided between the first active element 1221 and the second active element 1252.

[0156] Furthermore, by using high melting point materials such as tungsten (W), titanium (Ti), titanium nitride (TiN), carbon (C), or polycrystalline silicon (Si) as the material for composing the electromagnetic shielding layer 1302, even if a process in a high temperature environment such as forming the second active element 1252 is performed after the first substrate and the second substrate are bonded together, the electromagnetic shielding layer 1302 can be prevented from diffusing into the first wiring layer 1230 or the interlayer insulating film 1242.

[0157] (Modification 1 of the third embodiment) Fig. 37 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to Modification 1 of the third embodiment. As shown in Fig. 37, in Modification 1, a first wiring layer 1230 including a first active element 1221 is formed on a semiconductor substrate 1211, and a first substrate is prepared by laminating a diffusion prevention layer 1303, an electromagnetic shielding layer 1302, and a diffusion prevention layer 1301 in this order on the surface of the first wiring layer 1230. Figs. 36A to 36D show an example in which the electromagnetic shielding layer 1302 is formed on the second substrate side and then bonded, but as shown in Fig. 37, it may be formed on the first substrate side. In this case, the surface of the interlayer insulating film 1242 on the second substrate side is exposed, and the interlayer insulating film 1242 and the diffusion prevention layer 1303 are bonded together.

[0158] In this first modification as well, potential fluctuations occurring when the first active element 1221 is driven are electromagnetically shielded by the electromagnetic shielding layer 1302, preventing substrate bias fluctuations and reducing noise to the second active element 1252.

[0159] (Modification 2 of the third embodiment) Fig. 38 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to Modification 2 of the third embodiment. As shown in Fig. 38, Modification 2 has a laminated structure including a first wiring layer 1230, an opening 1241a, an interlayer insulating film 1242, a semiconductor substrate 1251, a second active element 1252, a wiring 1261, interlayer insulating films 1256 and 1265, a connection wiring 1266, an electromagnetic shielding layer 1302, and diffusion prevention layers 1301 and 1303 on an interlayer insulating film 1265 as a third substrate.

[0160] Even in a laminated structure of three or more layers of substrates as in this modified example, by providing electromagnetic shielding layers 1302 between each active element, potential fluctuations that occur when each active element is driven can be electromagnetically shielded by the electromagnetic shielding layers 1302. This makes it possible to prevent substrate bias fluctuations and reduce noise for each active element.

[0161] (Modification 3 of the third embodiment) 39 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to Modification 3 of the third embodiment. Modification 3 differs from the third embodiment in that the electromagnetic shielding layer 1302 is selectively formed within the region of the photoelectric conversion unit, and a diffusion prevention layer 1304 is also formed around the electromagnetic shielding layer 1302. Since the region in which the electromagnetic shielding layer 1302 is formed only needs to cover at least the first active element 1221, the electromagnetic shielding layer 1302 is formed over the entire surface of the diffusion prevention layer 1303, and then the electromagnetic shielding layer 1302 is patterned using a known photolithography technique. Thereafter, the periphery of the electromagnetic shielding layer 1302 is filled in, thereby simultaneously forming the diffusion prevention layer 1304 and the diffusion prevention layer 1301.

[0162] In this modified example, the electromagnetic shielding layer 1302 is formed only in the desired area, so that the area in which wiring and connection wiring can be formed inside the first wiring layer 1230 and the interlayer insulating film 1242 is expanded, thereby improving the freedom of element design.

[0163] (Modification 4 of the third embodiment) Fig. 40 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to Modification 4 of the third embodiment, Fig. 40A is a cross-sectional view of a main part of a pixel region, and Fig. 40B is a schematic view showing the positional relationship between the electromagnetic shielding layer 1302 and a first active element 1221. As shown in Fig. 40A, the semiconductor device of Modification 4 has a stacked structure similar to that of Fig. 35A shown in the third embodiment. In Modification 4, as shown in Fig. 40B, a common electromagnetic shielding layer 1302 is formed for a plurality of photoelectric conversion units constituting a pixel, and the electromagnetic shielding layer 1302 collectively covers a plurality of first active elements 1221 included in each photoelectric conversion unit.

[0164] In this modification, the electromagnetic shielding layer 1302 is formed up to a position outside the region directly above the photoelectric conversion unit, so that it is easy to provide a fixed ground potential by connecting wiring or connection wiring to the electromagnetic shielding layer 1302. Also, the electromagnetic shielding layer 1302 may be partially extended and connected to a ground wiring.

[0165] (Fifth Modification of the Third Embodiment) Fig. 41 is a schematic cross-sectional view showing an electromagnetic shielding layer 1302 of a semiconductor device according to Modification 5 of the third embodiment, Fig. 41A is a cross-sectional view of a main part of a pixel region, and Fig. 41B is a schematic view showing the positional relationship between the electromagnetic shielding layer 1302 and a first active element 1221. As shown in Fig. 41A, in the semiconductor device of Modification 5, a connection wiring 1311 is formed penetrating the interlayer insulating films 1242, 1256, and 1265, the semiconductor substrate 1251, and the diffusion prevention layer 1303, and the lower end of the connection wiring 1311 is electrically connected to the electromagnetic shielding layer 1302. In addition, a ground potential, which is a fixed potential, is applied to the electromagnetic shielding layer 1302 via the connection wiring 1311.

[0166] Although the planar shape of the electromagnetic shielding layer 1302 in this modification is not limited, a common electromagnetic shielding layer 1302 may be formed for a plurality of photoelectric conversion units as shown in Fig. 41B. In addition, the connection wiring 1311 is not limited to being formed penetrating from the uppermost layer to the electromagnetic shielding layer 1302, and may be formed, for example, from wiring provided in each layer.

[0167] In this modification, since the connection wiring 1311 is formed in the thickness direction of the semiconductor device and electrically connected to the electromagnetic shielding layer 1302, a fixed potential can be supplied while the area of ​​the electromagnetic shielding layer 1302 is reduced.

[0168] (Fourth embodiment) A semiconductor device according to a fourth embodiment of the present technology will be described with reference to Figs. 42 and 43. The semiconductor device according to the fourth embodiment is a back-illuminated solid-state imaging device, and light is incident from the back side (the lower side in Fig. 35). Other configurations of the semiconductor device according to the fourth embodiment of the present technology are similar to those of the semiconductor device according to the first embodiment shown in Fig. 4, and therefore illustrations and descriptions of the overlapping configurations will be omitted.

[0169] Fig. 42 is a cross-sectional view of a main part of a pixel region of a semiconductor device according to a fourth embodiment of the present technology. As shown in Fig. 42, the semiconductor device according to the present embodiment is configured by stacking a first substrate 1410, a second substrate 1420, and a third substrate 1430 in this order. The first substrate 1410, the second substrate 1420, and the third substrate 1430 are provided with a semiconductor substrate 1411, a photodiode 1441, a floating diffusion FD, a transfer transistor TR, a transfer gate TG, an insulating layer 1446, light attenuating units 1501 and 1502, a semiconductor substrate 1421, a readout circuit 1422, an insulating layer 1452, a wiring layer 1462, a semiconductor substrate 1431, and a logic circuit 1432. The photodiode PD, the transfer transistor TR, and the readout circuit 1422 correspond to a photoelectric conversion unit, a first active element, and a second active element in the present technology, respectively.

[0170] The light attenuating parts 1501 and 1502 are minute structures provided in the insulating layer 1446, and are made of a material having a higher refractive index than the material constituting the insulating layer 1446. The shape of the light attenuating parts 1501 and 1502 is not limited, but FIG. 42 shows a case where they are substantially cylindrical. The light attenuating parts 1501 and 1502 are disposed between the photodiode PD and the readout circuit 1422. The material constituting the light attenuating parts 1501 and 1502 is not limited, but when the surrounding insulating layer 1446 is made of SiO2, it is preferable to make the light attenuating parts 1501 and 1502 of Si.

[0171] Fig. 43 is a schematic diagram showing an enlarged view of the periphery of the light attenuating parts 1501 and 1502, Fig. 43A is a cross-sectional view showing the path of light incident on the light attenuating parts 1501 and 1502, and Fig. 43B is a schematic top view showing an example of the arrangement of the light attenuating parts 1501 and 1502. As shown in Fig. 43A, the light attenuating parts 1501 and 1502 are made of a material with a higher refractive index than the surroundings, so that the light incident on the light attenuating parts 1501 and 1502 is totally reflected at the interface between the light attenuating parts 1501 and 1502 and the insulating layer 1446 as shown by the arrows in the figure, and the light intensity is attenuated and absorbed while being totally reflected repeatedly inside the light attenuating parts 1501 and 1502.

[0172] In general, in a semiconductor device, radiated light may be generated by hot carriers when the readout circuit 1422 or the logic circuit 1432 is driven. Since the intensity of radiated light is inversely proportional to the square of the distance, noise occurs when radiated light is incident on a photodiode PD arranged at a position close to the radiated light generation region. In the semiconductor device of this embodiment, the radiated light incident on the light attenuating parts 1501 and 1502 is attenuated inside the light attenuating parts 1501 and 1502 by repeated reflection. This reduces the intensity of radiated light caused by hot carriers reaching the photodiode PD, and reduces noise in the photodiode PD. The height of the light attenuating parts 1501 and 1502 is preferably 1.1 μm or more, and the interval between the adjacent light attenuating parts 1501 and 1502 is preferably 0.38 μm or less. By setting the height of the light attenuating parts 1501 and 1502 to 1.1 μm or more, about 90% of the radiated light that enters vertically from above and is not totally reflected can be absorbed while passing through the light attenuating parts 1501 and 1502.

[0173] Furthermore, when the insulating layer 1446 is made of SiO2 and the light attenuating parts 1501 and 1502 are made of Si, the refractive index of SiO2 is about 1.48 and the refractive index of Si is about 3.88, so the critical angle at the interface between the light attenuating parts 1501 and 1502 and the insulating layer 1446 is about 22 degrees. This increases the range over which the light incident on the light attenuating parts 1501 and 1502 is totally reflected, thereby enhancing the effects of repeated total reflection of light and light absorption.

[0174] 43A and 43B, the light attenuating portion 1501 and the light attenuating portion 1502 are formed at different depths in the insulating layer 1446 and are arranged complementarily in a plan view. As a result, the radiated light generated from the readout circuit 1422 or the logic circuit 1432 arranged above is incident on the light attenuating portion 1501 or the light attenuating portion 1502 while traveling toward the photodiode PD, so that the radiated light reaching the photodiode PD can be effectively blocked.

[0175] Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to Figures 44 to 47. First, as shown in Figure 44A, an SOI (Silicon on Insulator) substrate is prepared in which an insulating layer 1512 made of SiO2 and a semiconductor layer 1511 made of Si are formed on one surface of a semiconductor substrate 1421 made of Si. Next, as shown in Figure 44B, an insulating layer 1446 made of SiO2 is deposited on the other surface of the semiconductor substrate 1421 by a CVD method or the like. Next, as shown in Figure 44C, a resist mask 1513 is patterned on the insulating layer 1446 by using a photolithography technique, and a recess 1514 is formed in the insulating layer 1446 by etching.

[0176] Next, as shown in Fig. 45D, resist mask 1513 is peeled off, and Si is deposited on insulating layer 1446 using CVD technology and planarized by CMP technology, and recess 1514 is filled with light attenuating portion 1502. Next, as shown in Fig. 45E, Si is deposited using CVD technology to form insulating layer 1446 also on light attenuating portion 1502. Next, as shown in Fig. 45F, photolithography and etching, Si deposition and planarization, and further Si deposition are repeated to form light attenuating portion 1501 embedded in insulating layer 1446.

[0177] Next, as shown in Fig. 46G, the SOI substrate is inverted, and as shown in Fig. 46H, the insulating layer 1512 and the semiconductor layer 1511 are peeled off to form a read circuit 1422 on the semiconductor substrate 1421. Next, as shown in Fig. 47I, an insulating layer 1452 is formed on the semiconductor substrate 1421 to form a second substrate 1420, and the insulating layer 1446 of the first substrate 1410, which has been prepared separately, is bonded to the insulating layer 1446 of the second substrate 1420. Finally, as shown in Fig. 47J, the wiring layer 1462 and the insulating layer 1452 of the third substrate 1430 are bonded to obtain the semiconductor device of this embodiment shown in Fig. 42.

[0178] 44 to 47, the light attenuating parts 1501 and 1502 are formed in the insulating layer 1446 by the steps of photolithography, etching, Si deposition, and planarization, so that the light attenuating parts 1501 and 1502 can be formed at desired positions between the photodiode PD and the readout circuit 1422. Furthermore, by repeating the steps of photolithography, etching, Si deposition, and planarization as necessary, the light attenuating parts 1501 and 1502 can also have a structure of three or more layers.

[0179] According to the semiconductor device of the fourth embodiment of the present technology, the semiconductor device is provided with light attenuating sections 1501, 1502 between the photodiode PD and the readout circuit 1422, which are made of a material having a higher refractive index than the surrounding area. This makes it possible to prevent radiated light generated by hot carriers in the readout circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, thereby reducing noise.

[0180] (Modification 1 of the fourth embodiment) Fig. 48 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 1 of the fourth embodiment of the present technology. In this modification, the shapes of the light attenuating parts 1521 and 1522 are different from the example shown in Fig. 43A. As shown in Fig. 48, in the semiconductor device of this modification, the light attenuating parts 1521 and 1522 are formed as convex shapes 1521a and 1522a whose bottom parts of a substantially cylindrical shape are cone-shaped. Methods for forming the light attenuating parts 1521 and 1522 of this modification include appropriately changing the shape and film thickness of the resist mask 1513 when forming the recess 1514 shown in Fig. 44C, and changing the etching conditions for the recess 1514.

[0181] In the semiconductor device of this modification, the bottom surface portions of the light attenuating sections 1521, 1522 are formed in the convex shapes 1521a, 1522a, so that even radiant light incident from directly above is totally reflected by the convex shapes 1521a, 1522a, and the radiant light can be effectively attenuated. Here, a cone shape is shown as an example of the convex shapes 1521a, 1522a, but it is sufficient that the convex shapes are formed at an angle that can reflect the radiant light arriving from above, and they may be inclined surfaces, have minute irregularities, be mortar-shaped, or the like.

[0182] (Modification 2 of the fourth embodiment) Fig. 49 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 2 of the fourth embodiment of the present technology. This modification is different from the example shown in Fig. 43A in that the light attenuating parts 1531 are formed as quantum dots. As shown in Fig. 49, in the semiconductor device of this modification, a plurality of light attenuating parts 1531 made of quantum dots made of minute Si are formed in an insulating layer 1446. The size of the light attenuating parts 1531 is about several nm to several tens of nm in diameter, and they are three-dimensionally distributed in the insulating layer 1446. When the insulating layer 1446 is viewed from above, it is preferable that the surface density of the light attenuating parts 1531 is 1 or more.

[0183] Next, a manufacturing method of the semiconductor device of this modification will be described with reference to Figs. 50 to 52. First, as shown in Fig. 50A, an SOI substrate is prepared in which an insulating layer 1512 made of SiO2 and a semiconductor layer 1511 made of Si are formed on one surface of a semiconductor substrate 1421 made of Si. Next, as shown in Fig. 50B, an insulating layer 1446 made of SiO2 is deposited on the other surface of the semiconductor substrate 1421 by a CVD method or the like. At this time, Si-rich SiO2 is formed as the SiO2 constituting the insulating layer 1446. Although a specific method for forming the Si-rich SiO2 is not limited, for example, it may be formed at a ratio of dichlorosilane (SiH2Cl2) gas (DCS gas) and nitrous oxide (N2O) gas of 7 to 13:1 at a pressure of 0.8 to 1.5 atm. Next, as shown in Fig. 50C, the insulating layer 1446 is annealed to stack quantum dots made of Si in the insulating layer 1446 to form the light attenuating portion 1531. Although the specific annealing conditions are not limited, for example, annealing is performed in an N2 atmosphere at 1000° C. for 1 hour.

[0184] Next, the SOI substrate is inverted as shown in Fig. 51D, the insulating layer 1512 and the semiconductor layer 1511 are peeled off as shown in Fig. 51E, and the semiconductor substrate 1421 is thinned by CMP technology. Next, as shown in Fig. 51F, a read circuit 1422 is formed in the semiconductor substrate 1421, an insulating layer 1452 is formed on the semiconductor substrate 1421 to configure a second substrate 1420, and the insulating layer 1446 of the first substrate 1410, which has been prepared separately, is bonded to the insulating layer 1446 of the second substrate 1420. Finally, as shown in Fig. 51G, the wiring layer 1462 of the third substrate 1430 and the insulating layer 1452 are bonded to obtain the semiconductor device of this modified example shown in Fig. 52H.

[0185] In the semiconductor device of this modified example, by arranging a light attenuating section 1531 of Si quantum dots having a higher refractive index than the surrounding area between the photodiode PD and the readout circuit 1422, it is possible to prevent radiated light generated by hot carriers in the readout circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, thereby reducing noise.

[0186] (Modification 3 of the fourth embodiment) Fig. 53 is a partially enlarged cross-sectional view of a semiconductor device according to the third modification of the fourth embodiment of the present technology. This modification is different from the example shown in Fig. 43A in that the light attenuating portion 1542 is formed in the semiconductor substrate 1421. As shown in Fig. 3, in the semiconductor device of this modification, a recess 1541 is formed on the back surface side of the semiconductor substrate 1421, and a part of the semiconductor substrate 1421 is disposed as a convex light attenuating portion 1542 protruding into the insulating layer 1446. In this modification, the light attenuating portion 1542 is formed of Si constituting the semiconductor substrate 1421 and protrudes into the SiO2 constituting the insulating layer 1446, so that the light attenuating portion 1542 has a higher refractive index than the surrounding insulating layer 1446.

[0187] Next, a manufacturing method of the semiconductor device of this modification will be described with reference to Figures 54 and 55. First, as shown in Figure 54A, a semiconductor substrate 1421 made of Si is prepared. Next, as shown in Figure 54B, a resist mask is patterned on one side of the semiconductor substrate 1421 using photolithography technology, and a recess 1541 and a light attenuating portion 1542 are formed in the semiconductor substrate 1421 by etching. Next, as shown in Figure 54C, the resist mask is removed, and an insulating layer 1446 made of SiO2 is deposited on the semiconductor substrate 1421 by CVD or the like, and the recess 1541 is filled with the insulating layer 1446, and then planarized by CMP technology.

[0188] Next, as shown in Fig. 55D, the semiconductor substrate 1421 is inverted, and as shown in Fig. 55E, the semiconductor substrate 1421 is thinned by CMP technology. Next, as shown in Fig. 55F, the insulating layer 1446 of the first substrate 1410, which has been prepared separately, is bonded to the insulating layer 1446 of the second substrate 1420. The formation of the readout circuit 1422 and the bonding to the third substrate 1430 will not be described.

[0189] In the semiconductor device of this modification, too, radiated light is totally reflected at the interface between the insulating layer 1446 and the convex-shaped light attenuating portion 1542 formed on the semiconductor substrate 1421, and the radiated light is attenuated within the light attenuating portion 1542. This makes it possible to prevent radiated light generated by hot carriers in the readout circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, thereby reducing noise.

[0190] (Modification 4 of the fourth embodiment) Fig. 56 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 4 of the fourth embodiment of the present technology. This modification is different from the example shown in Fig. 42 in that only one layer of light attenuating portion 1501 is formed in insulating layer 1446. Also in this modification, by appropriately selecting the size and arrangement of light attenuating portion 1501, it is possible to prevent radiated light generated by hot carriers in readout circuit 1422 and logic circuit 1432 from reaching photodiode PD, thereby reducing noise.

[0191] (Fifth Modification of the Fourth Embodiment) Fig. 57 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 5 of the fourth embodiment of the present technology. This modification is different from the example shown in Fig. 42 in that a light attenuating portion 1501 formed in an insulating layer 1446 is combined with a convex light attenuating portion 1542 formed on a semiconductor substrate 1421. In this modification, too, by appropriately setting the sizes and arrangements of the light attenuating portion 1501 and the light attenuating portion 1542, it is possible to prevent radiated light generated by hot carriers in the readout circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, thereby reducing noise.

[0192] Fifth embodiment A semiconductor device according to a fifth embodiment of the present technology will be described with reference to Figs. 58 and 59. The semiconductor device according to the fifth embodiment is a back-illuminated solid-state imaging device, and light is incident from the back side (the lower side in Fig. 58). Other configurations of the semiconductor device according to the fifth embodiment of the present technology are similar to those of the semiconductor device according to the first embodiment shown in Fig. 19, and therefore illustrations and descriptions of the overlapping configurations will be omitted.

[0193] Fig. 58 is a partially enlarged cross-sectional view of the semiconductor device according to the fifth embodiment of the present technology. Fig. 59 is a schematic diagram showing the positional relationship between the antireflection portion 1701 and the connection wiring 1666. As shown in Figs. 58 and 59, the semiconductor device according to the present embodiment includes Si substrates 1611 and 1651, an element isolation portion 1612, a first wiring layer 1630, interlayer insulating films 1656 and 1665, a wiring 1661, a connection wiring 1666, and an antireflection portion 1701. As described in the first embodiment, the Si substrate 1651 includes a second active element according to the present technology, and the Si substrate 1611 includes a photoelectric conversion portion according to the present technology, but these are omitted from Fig. 58.

[0194] The antireflection portion 1701 is disposed at least between the second active element of the Si substrate 1651 and the photoelectric conversion portion of the Si substrate 1611, and has a function of reducing the reflectance of light on the rear surface of the Si substrate 1651. In the example shown in Fig. 58, the antireflection portion 1701 is provided in contact with the entire rear surface (the lower side of Fig. 58) of the Si substrate 1651, and is formed as a dielectric film having a refractive index intermediate between silicon oxide (SiO2), which is an insulating material contained in the first wiring layer 1630, and Si which constitutes the Si substrate 1651. An example of a material constituting the antireflection portion 1701 is silicon nitride (SiN).

[0195] Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIGS. 60 and 61. First, as shown in FIG. 60, a first substrate including a Si substrate 1611, an element isolation portion 1612, and a first wiring layer 1630 is prepared. In addition, a SiN film constituting an antireflection portion 1701 is formed on the back surface of a Si substrate 1651 using a CVD technique or the like, and the antireflection portion 1701 and the first wiring layer 1630 are bonded together. Next, as shown in FIG. 61, the surface of the Si substrate 1651 is scraped to thin it, and a recess 1702 is formed halfway through the first wiring layer 1630 using a photolithography technique. Thereafter, the recess 1702 and the surface of the Si substrate 1651 are filled with an interlayer insulating film 1656, and an interlayer insulating film 1665, wiring 1661, and connection wiring 1666 are formed, and the semiconductor device according to this embodiment is obtained. 60, the antireflection portion 1701 may be provided on the upper surface side of the first wiring layer 1630, instead of on the Si substrate 1651 side.

[0196] If the antireflection portion 1701 is not provided, the difference in refractive index between the SiO2 included in the first wiring layer 1630 and the Si substrate 1651 is large, so that total reflection is likely to occur at the interface between them. Since there is a distance between the Si substrates 1611 and 1651, light that is incident on the photoelectric conversion portion of the Si substrate 1611 and reflected by the Si substrate 1651 may pass through the element isolation portion 1612 and enter another photoelectric conversion portion. Light that is reflected by the back surface of the Si substrate 1651 and enters the photoelectric conversion portion is converted into an electric signal in the photoelectric conversion portion, generating noise.

[0197] In this embodiment, an antireflection portion 1701 is provided between the second active element and the photoelectric conversion portion. By making the antireflection portion 1701 out of SiN, which has an intermediate refractive index to that of Si, the refractive index difference between SiN and Si is smaller than when the antireflection portion 1701 is not provided, making it possible to suppress total reflection on the Si substrate 1651 and reduce noise in the photoelectric conversion portion.

[0198] (Modification 1 of the fifth embodiment) Fig. 62 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 1 of the fifth embodiment of the present technology. This modification is different from the example shown in Fig. 58 in that an antireflection portion 1711 is formed over an area wider than a Si substrate 1651. As shown in Fig. 62, in this modification, an antireflection portion 1711 is provided over the entire semiconductor device, and a connection wiring 1666 is provided so as to penetrate an opening provided in the antireflection portion 1711.

[0199] FIG. 63 shows a method for manufacturing a semiconductor device according to this modification. First, a first substrate including a Si substrate 1611, an element isolation portion 1612, and a first wiring layer 1630 is prepared, as in FIG. 60. In addition, a SiN film constituting an antireflection portion 1711 is formed on the rear surface of a Si substrate 1651 using a CVD technique or the like, and the antireflection portion 1711 and the first wiring layer 1630 are bonded together. Next, as shown in FIG. 63, the surface of the Si substrate 1651 is scraped to thin it, and a recess 1702 is formed up to the surface of the antireflection portion 1711 using a photolithography technique. Thereafter, the recess 1702 and the surface of the Si substrate 1651 are filled with an interlayer insulating film 1656, and an interlayer insulating film 1665, wiring 1661, and connection wiring 1666 are formed, and the semiconductor device according to this modification is obtained.

[0200] In this modified example, antireflection portion 1711 is provided between the second active element and the photoelectric conversion portion, and antireflection portion 1711 is provided over an area larger than Si substrate 1651, so that total reflection on Si substrate 1651 can be suppressed and noise in the photoelectric conversion portion can be reduced.

[0201] (Modification 2 of the fifth embodiment) Fig. 64 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 2 of the fifth embodiment of the present technology. This modification is different from the example shown in Fig. 62 in that an antireflection portion 1722 is provided on a side surface of a Si substrate 1651 in addition to an antireflection portion 1721. As shown in Fig. 64, in this modification, an antireflection portion 1721 is provided over the entire area of ​​the semiconductor device, and a connection wiring 1666 is provided so as to penetrate an opening provided in the antireflection portion 1711. In addition, an antireflection portion 1722 is provided so as to cover a side surface of the Si substrate 1651.

[0202] FIG. 65 shows a method for manufacturing a semiconductor device according to this modification. First, a first substrate including a Si substrate 1611, an element isolation portion 1612, and a first wiring layer 1630 is prepared, as in FIG. 60. In addition, a SiN film constituting an antireflection portion 1721 is formed on the rear surface of a Si substrate 1651 using a CVD technique or the like, and the antireflection portion 1721 and the first wiring layer 1630 are bonded together. Next, as shown in FIG. 61, the surface of the Si substrate 1651 is scraped to thin it, a recess 1702 is formed halfway through the first wiring layer 1630 using a photolithography technique, and the surface of the Si substrate 1651 is oxidized to form a SiO2 film. Next, as shown in FIG. 65, a SiN film is formed to form a SiN film 1723 on the SiO2 film on the surface of the Si substrate 1651, and an antireflection portion 1722 is provided on the side of the Si substrate 1651 exposed in the recess 1702. Finally, the SiN film 1723 and the recess 1702 are filled with an interlayer insulating film 1656, and the interlayer insulating film 1656, the SiN film 1723 and the SiO2 film are polished until the surface of the Si substrate 1651 is exposed. Then, the interlayer insulating film 1665, the wiring 1661, the connecting wiring 1666, etc. are formed, thereby obtaining the semiconductor device of this embodiment.

[0203] In this modified example, an antireflection portion 1721 is provided between the second active element and the photoelectric conversion portion over an area wider than the Si substrate 1651, and an antireflection portion 1722 is provided on the side of the Si substrate 1651, so that total reflection on the Si substrate 1651 can be suppressed and noise in the photoelectric conversion portion can be reduced.

[0204] (Modification 3 of the fifth embodiment) FIG. 66 is a partially enlarged cross-sectional view of a semiconductor device according to the third modification of the fifth embodiment of the present technology. This modification is different from the example shown in FIG. 58 in that the antireflection portion 1731 formed on the back surface of the Si substrate 1651 is configured to have a multi-layer structure. As shown in FIG. 66, in the semiconductor device of this modification, the antireflection portion 1731 is provided in contact with the entire back surface (the lower side of FIG. 58) of the Si substrate 1651, and has a structure in which multiple dielectric layers with different refractive indexes are laminated. The number of layers of the dielectric film constituting the antireflection portion 1731 is not limited to two layers, and may be three or more layers. The dielectric material contained in the antireflection portion 1731 is a material with a refractive index larger than that of the SiO2 contained in the first wiring layer 1630 and smaller than that of the Si of the Si substrate 1651, and is laminated so that the refractive index gradually decreases from the Si substrate 1651 side toward the first wiring layer 1630. The specific material constituting the anti-reflection portion 1731 is not limited, but examples of the material that can be used include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0205] In this modified example, an anti-reflection portion 1731 is provided between the second active element and the photoelectric conversion portion, and the refractive index gradually decreases from the Si substrate 1651 toward the first wiring layer 1630, so that total reflection on the Si substrate 1651 can be suppressed and noise in the photoelectric conversion portion can be reduced.

[0206] (Modification 4 of the fifth embodiment) Fig. 67 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 4 of the fifth embodiment of the present technology. This modification is different from the example shown in Fig. 58 in that an intermediate film 1732 having a different refractive index is provided between the rear surface of the Si substrate 1651 and the antireflection portion 1731. The intermediate film 1732 is made of a material having a smaller refractive index than the material constituting the antireflection portion 1731, and is formed thinner than the thickness of the antireflection portion 1731. The thickness of the intermediate film 1732 is not limited, but as long as the thickness is about 1 nm to several nm, even if the material has a smaller refractive index than the antireflection portion 1731, the influence on the antireflection effect of light is small.

[0207] In this modified example, an antireflection portion 1731 is also provided between the second active element and the photoelectric conversion portion, so that even if an intermediate film 1732 with a different refractive index is provided between the antireflection portion 1731 and the Si substrate 1651, total reflection at the Si substrate 1651 can be suppressed, and noise in the photoelectric conversion portion can be reduced.

[0208] (Fifth Modification of the Fifth Embodiment) Fig. 68 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 5 of the fifth embodiment of the present technology. This modification is different from the example shown in Fig. 58 in that an antireflection portion 1741 provided on the back surface of a Si substrate 1651 has an uneven structure. The antireflection portion 1741 is formed as a dielectric film having an intermediate refractive index between SiO2, which is an insulating material included in the first wiring layer 1630, and Si, which constitutes the Si substrate 1651, and has a plurality of minute unevennesses formed thereon.

[0209] In the semiconductor device of this modification, if the size of the uneven structure of antireflection section 1741 is set to be in microns, which is larger than the wavelength of light, the light that reaches antireflection section 1741 is diffusely reflected, thereby reducing the amount of light that is reflected by the rear surface of Si substrate 1651 and enters the photoelectric conversion section, thereby reducing noise. Also, if the size of the uneven structure is set to be in nanometers, which is smaller than the wavelength of light, a moth-eye structure is formed in which the refractive index gradually changes, thereby suppressing the light reflected by the rear surface of Si substrate 1651 and reducing noise caused by light entering the photoelectric conversion section.

[0210] (Other embodiments) As described above, the present technology has been described by the first to fifth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present technology. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0211] For example, the semiconductor devices according to the first to fifth embodiments of the present technology can be applied to any type of electronic device having an imaging function, such as a camera system such as a digital still camera or a video camera, or a mobile phone having an imaging function. For example, the semiconductor devices according to the first to fifth embodiments can be applied to an electronic device (camera) shown in Fig. 69. The electronic device shown in Fig. 69 is, for example, a video camera capable of taking still or moving images, and includes a semiconductor device 2200, an optical system (optical lens) 2201, a shutter device 2202, a drive unit 2204 that drives the semiconductor device 2200 and the shutter device 2202, and a signal processing unit 2203.

[0212] The semiconductor device 2200 can be any of the semiconductor devices according to the first to fifth embodiments. The optical system 2201 guides image light (incident light) from an object to a pixel region 2001 of the semiconductor device 2200. The optical system 2201 may be composed of a plurality of optical lenses. The shutter device 2202 controls a light irradiation period and a light blocking period for the semiconductor device 2200. The driving unit 204 controls a transfer operation of the semiconductor device 2200 and a shutter operation of the shutter device 2202. The signal processing unit 2203 performs various signal processing on a signal output from the semiconductor device 2200. The video signal after the signal processing is stored in a storage medium such as a memory, or is output to a monitor or the like.

[0213] According to an imaging device according to an embodiment of the present technology, the substrates are electrically connected to each other according to the integration degree of the substrates, so that the structure for electrically connecting the substrates to each other does not increase the chip size or hinder the miniaturization of the area per pixel. As a result, it is possible to provide an imaging device with a three-layer structure that has a chip size equivalent to that of the past and does not hinder the miniaturization of the area per pixel. Note that the effects of the present technology are not necessarily limited to the effects described herein, and may be any of the effects described in this specification.

[0214] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur to those skilled in the art depending on design requirements and other factors, and that such modifications are within the scope of the appended claims and their equivalents.

[0215] Although a back-illuminated CMOS image sensor has been exemplified as the semiconductor device according to the first to fifth embodiments of the present technology, the semiconductor device according to the present technology may be applied to a solid-state imaging device such as a back-illuminated CCD image sensor. Furthermore, the semiconductor device according to the present technology may be applied to various semiconductor devices other than solid-state imaging devices, such as a memory device using a semiconductor, a display device using a semiconductor, a sensor device using a semiconductor, and a computing device using a semiconductor.

[0216] For example, a semiconductor memory device such as a DRAM may be configured to have a memory cell as a unit cell instead of a pixel having a photoelectric conversion unit. Current DRAMs are one-transistor type memory cells (unit cells), but by adopting the stacked structure of this technology, a DRAM having a three-transistor type memory cell (unit cell) used in the 1970s can be configured without reducing the integration density. Furthermore, by forming the above-mentioned shield structure between the upper DRAM and the lower DRAM of a three-dimensional semiconductor memory device in which DRAMs having one-transistor type memory cells (unit cells) are stacked in multiple layers, the upper DRAM and the lower DRAM can be thermally, optically, and electromagnetically shielded from each other. Therefore, noise, malfunction, and the like can be prevented in operations in which electrical energy is concentrated, such as in high-speed DRAMs.

[0217] In addition, in the semiconductor device according to the first to fifth embodiments of the present technology, a negative charge (electrons) is used as a signal charge, but the present technology can also be applied to a case where a positive charge (hole) is used as a signal charge. When holes are used as a signal charge, the p-type region and the n-type region are reversed.

[0218] Sixth embodiment The imaging device 1 according to the sixth embodiment of the present disclosure will be described in detail below with reference to the drawings. The description will be made in the following order. 1. Embodiment (imaging device having a stacked structure of three substrates) 2. Modification 1 (Planar Configuration Example 1) 3. Modification 2 (Planar Configuration Example 2) 4. Modification 3 (Planar Configuration Example 3) 5. Modification 4 (Example in which a contact portion between substrates is provided in the center of the pixel array portion) 6. Modification 5 (Example having planar type transfer transistor) 7. Modification 6 (Example in which one pixel is connected to one pixel circuit) 8. Modification 7 (Example of the Configuration of the Pixel Separation Unit)

[0219] <1. Preferred embodiment> [Functional configuration of imaging device 1] FIG. 70 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.

[0220] The imaging device 1 in FIG. 70 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0221] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and this is repeatedly arranged in an array having a row direction and a column direction. In this specification, for convenience, the row direction may be called the H direction, and the column direction perpendicular to the row direction may be called the V direction. In the example of FIG. 70, one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (illustrated in FIG. 75, etc., which will be described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 72, which will be described later). In other words, one pixel circuit (pixel circuit 210, which will be described later) is included for each of four pixels (pixels 541A, 541B, 541C, and 541D). By operating this pixel circuit in a time-division manner, pixel signals of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged in, for example, 2 rows and 2 columns. In the pixel array section 540, a plurality of row driving signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided in addition to the pixels 541A, 541B, 541C, and 541D. The row driving signal line 542 drives the pixels 541 included in each of a plurality of pixel sharing units 539 arranged in a row direction in the pixel array section 540. The row driving signal line 542 drives each pixel arranged in a row direction among the pixel sharing units 539. As will be described in detail later with reference to FIG. 73, the pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of these transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out via the vertical signal line (column readout line) 543 from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539.

[0222] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for driving the pixels, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0223] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. In the noise processing unit, for example, a system noise level is removed from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.

[0224] The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the analog signal that has been subjected to the noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared therewith. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that controls scanning of the readout column.

[0225] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on a reference clock signal and a timing control signal input to the device.

[0226] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0227] One example of signal processing executed by the image signal processing unit 560 is a tone curve correction process that imparts more gradation to the AD converted imaging data when the data is of a dark subject, and reduces the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the imaging data is to be corrected.

[0228] The input section 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, and the like from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0229] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for taking in the signal input to the input terminal 511 into the inside of the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal taken in by the input circuit unit 512 to an amplitude that is easily used inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is composed of, for example, a serial-parallel conversion circuit. In this serial-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that, in the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on a power source supplied from the outside to the imaging device 1.

[0230] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0231] The output unit 510B outputs image data to the outside of the device. This image data is, for example, image data captured by the imaging device 1 and image data signal-processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0232] The output data conversion circuit unit 515 is configured, for example, by a parallel-serial conversion circuit, and the output data conversion circuit unit 515 converts the parallel signal used inside the imaging device 1 into a serial signal. The output amplitude change unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude can be easily used by an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit unit 517 drives a wiring outside the imaging device 1 connected to an output terminal 518. The output terminal 518 outputs data from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted.

[0233] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0234] [Schematic configuration of imaging device 1] FIG. 71 and FIG. 72 show an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 71 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, and FIG. 72 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on top of each other. FIG. 72 corresponds to the cross-sectional configuration along line III-III' shown in FIG. 71. The imaging device 1 is a three-dimensional imaging device formed by bonding three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is called the wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300) for convenience. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrow shown in FIG. 72 indicates the incident direction of the light L to the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "bottom", "lower side", or "downward", and the side opposite the light incident side may be referred to as "upper side", "upper side", or "upper". Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be referred to as the front side, and the semiconductor layer side may be referred to as the back side. Note that the description in the specification is not limited to the above names. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of the first substrate 100 having a photodiode.

[0235] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D that the pixel sharing unit 539 has. Each of these pixels 541 has a photodiode (a photodiode PD described later) and a transfer transistor (a transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described later) that the pixel sharing unit 539 has. The pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistors, or resets the photodiodes. In addition to such pixel circuits, the second substrate 200 has a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has a power supply line 544 extending in the row direction. The third substrate 300 has, for example, an input section 510A, a row driver 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driver 520 is provided, for example, in a region partially overlapping the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver 520 is provided in a region overlapping the vicinity of an end of the pixel array section 540 in the H direction in the stacking direction (FIG. 71). The column signal processing section 550 is provided, for example, in a region partially overlapping the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region overlapping the vicinity of an end portion in the V direction of the pixel array section 540 in the stacking direction (FIG. 71). Although not shown, the input section 510A and the output section 510B may be disposed in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term pixel circuits is used.

[0236] The first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E, 121E in FIG. 75 described later). The second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, 302. The second substrate 200 is provided with contact portions 201, 202, and the third substrate 300 is provided with contact portions 301, 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact parts 301 are provided, and a contact region 302R in which a plurality of contact parts 302 are provided. The contact regions 201R, 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction (FIG. 72). In other words, the contact regions 201R, 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 201R, 301R are disposed, for example, at the end in the H direction of such a region (FIG. 71). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the row driver section 520, specifically, the end in the H direction of the row driver section 520 (FIGS. 71 and 72). The contact parts 201 and 301 connect, for example, the row driving section 520 provided on the third substrate 300 and the row driving signal line 542 provided on the second substrate 200. The contact parts 201 and 301 may connect, for example, the input section 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 72).In other words, the contact regions 202R and 302R are provided, for example, in a region where the column signal processing section 550 (the third substrate 300) and the pixel array section 540 (the second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 202R and 302R are arranged, for example, at the end in the V direction of such a region (FIG. 71). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the column signal processing section 550, specifically, the end in the V direction of the column signal processing section 550 (FIGS. 71 and 72). The contact sections 202 and 302 are for connecting pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 of the pixel array section 540 to the column signal processing section 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0237] FIG. 72 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed with electrodes formed of a conductive material. The conductive material is formed of a metal material such as copper (Cu), aluminum (Al), and gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly joining wirings formed as electrodes, for example, to each other, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0238] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, as described as the contact regions 201R, 202R, 301R, and 302R in FIG. 72, the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. The electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0239] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 72). The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 71). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may contain a conductive material at least in part. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which an electrode formed as the input section 510A and / or the output section 510B is connected to a conductive material provided in the connection holes H1, H2. The conductive material provided in the connection holes H1, H2 may be embedded in a part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.

[0240] 72 shows a structure in which the input unit 510A and the output unit 510B are provided on the third substrate 300, but the present invention is not limited to this. For example, the input unit 510A and / or the output unit 510B can be provided on the second substrate 200 by sending a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input unit 510A and / or the output unit 510B can be provided on the first substrate 100 by sending a signal of the second substrate 200 to the first substrate 1000 via the wiring layers 100T and 200T.

[0241] FIG. 73 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (four pixels 541, 541A, 541B, 541C, and 541D, are shown in FIG. 73), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 5433 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, the pixel sharing unit 539 is configured to sequentially output pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating one pixel circuit 210 in a time-division manner. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of the multiple pixels 541 are output in a time-division manner by the single pixel circuit 210 is said to be "multiple pixels 541 sharing one pixel circuit 210."

[0242] The pixels 541A, 541B, 541C, and 541D have components in common with each other. Hereinafter, in order to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification number 1 is added to the end of the reference numeral of the component of the pixel 541A, the identification number 2 is added to the end of the reference numeral of the component of the pixel 541B, the identification number 3 is added to the end of the reference numeral of the component of the pixel 541C, and the identification number 4 is added to the end of the reference numeral of the component of the pixel 541D. When it is not necessary to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the components of the pixels 541A, 541B, 541C, and 541D are omitted.

[0243] The pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiodes PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (for example, ground). The photodiode PD photoelectrically converts incident light and generates a charge according to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type CMOS (Complementary Metal Oxide Semiconductor) transistors. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 (see FIG. 70) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage according to the amount of charge.

[0244] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539 .

[0245] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided extending from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 75 described later) to a depth reaching the PD, as shown in FIG. 75 described later. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as the pixel signal, a signal of a voltage according to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP configures a source follower together with a load circuit unit (see FIG. 70) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0246] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0247] It is also possible to configure the pixel circuit 210 without providing the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0248] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see FIG. 70). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the figure, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0249] FIG. 74 shows an example of a connection between a plurality of pixel sharing units 539 and a vertical signal line 543. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For the sake of simplicity, FIG. 74 shows an example in which each of the four groups has one pixel sharing unit 539, but each of the four groups may include a plurality of pixel sharing units 539. In this way, in the imaging device 1, a plurality of pixel sharing units 539 arranged in a column direction may be divided into groups including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each of the groups, so that pixel signals can be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in a column direction. In this case, pixel signals are read out sequentially in a time-division manner from the plurality of pixel sharing units 539 connected to one vertical signal line 543.

[0250] [Specific configuration of imaging device 1] FIG. 75 shows an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1. FIG. 75 is a schematic representation for making it easier to understand the positional relationship of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further has a light receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. The light receiving lens 401 is provided, for example, for each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 has a pixel array section 540 arranged in the center and a peripheral section 540B arranged outside the pixel array section 540.

[0251] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface (the surface on the wiring layer 100T side) and in the vicinity thereof, and has an n-type semiconductor region 114 in the other region (region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0252] Fig. 76A shows an example of a planar configuration of the first substrate 100. Fig. 76A mainly shows the planar configuration of the pixel separation portion 117, the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 76A together with Fig. 75.

[0253] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is composed of an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel sharing unit 539 (FIG. 76A), for example. Although details will be described later, the four floating diffusions (floating diffusions FD1, FD2, FD3, FD4) included in this pixel sharing unit 539 are electrically connected to each other via electrical connection means (pad section 120 described later) in the first substrate 100 (more specifically, in the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical means (a through electrode 120E described below). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.

[0254] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end (FIG. 76A). The VSS contact region 118 is, for example, composed of a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0255] The first substrate 100 is provided with a transfer transistor TR together with a photodiode PD, a floating diffusion FD, and a VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side (the side opposite to the light incident surface side, the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0256] The horizontal part TGb of the transfer gate TG extends from a position facing the vertical part TGa toward, for example, the center of the pixel sharing unit 539 in the H direction (FIG. 76A). This allows the H direction position of the through electrode (through electrode TGV described below) that reaches the transfer gate TG to be close to the H direction positions of the through electrodes (through electrodes 120E, 121E described below) connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration (FIG. 76A).

[0257] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed extending in a normal direction (perpendicular to the surface of the semiconductor layer 100S) of the semiconductor layer 100S. The pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape (FIGS. 76A and 76B). The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W) or the like. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separator 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separator 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S. The pixel separator 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0258] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0259] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (rear surface) side of the semiconductor layer 100S due to an electric field induced by the fixed charge film 112. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0260] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A constituting the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0261] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in this order from the semiconductor layer 100S side. The horizontal portion TGb of the transfer gate TG is provided in this wiring layer 100T, for example. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. The configuration of the wiring layer 100T is not limited to the above, and may be any configuration having wiring and an insulating film.

[0262] FIG. 76B shows the configuration of the pad sections 120 and 121 together with the planar configuration shown in FIG. 76A. The pad sections 120 and 121 are provided in selective regions on the interlayer insulating film 119. The pad section 120 is for connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. The pad section 120 is disposed, for example, in the center of the pixel sharing unit 539 in plan view for each pixel sharing unit 539 (FIG. 76B). The pad section 120 is disposed so as to straddle the pixel separating section 117, and is disposed so as to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 (FIGS. 75 and 76B). Specifically, the pad section 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) that share the pixel circuit 210 and at least a portion of the pixel separation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) that share the pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 120C for electrically connecting the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4. The connection via 120C is provided in each of the pixels 541A, 541B, 541C, 541D. For example, a portion of the pad section 120 is embedded in the connection via 120C, so that the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4 are electrically connected.

[0263] The pad portion 121 is for connecting the multiple VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel sharing unit 539 are electrically connected by the pad portion 121. The pad portion 121 is provided, for example, so as to straddle the pixel separation portion 117, and is arranged so as to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the multiple VSS contact regions 118 and at least a part of the pixel separation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 and the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the multiple pixel sharing units 539 aligned in the V direction are disposed at approximately the same position in the H direction ( FIG. 76B ).

[0264] By providing the pad section 120, it is possible to reduce the wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) in the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the wiring for supplying a potential to each VSS contact region 118 in the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0265] The pads 120 and 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pads 120 and 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pads 120 and 121 may be directly in contact with the semiconductor layer 100S. Specifically, the pads 120 and 121 may be directly connected to at least a part of each of the floating diffusion FD and / or the VSS contact region 118. Alternatively, the pads 120 and 121 may be provided at desired positions in the insulating region 2112 of the wiring layer 100T and the semiconductor layer 200S by providing connection vias 120C and 121C from each of the floating diffusion FD and / or the VSS contact region 118 connected to the pads 120 and 121.

[0266] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the number of wirings connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce the area of ​​the insulating region 212 for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210, among the second substrate 200 for forming the pixel circuit 210. Therefore, it is possible to secure a large area for the second substrate 200 for forming the pixel circuit 210. By securing the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0267] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0268] 76B, for example, the pad section 120 to which the floating diffusions FD are connected and the pad section 121 to which the VSS contact regions 118 are connected are alternately arranged in a straight line in the V direction. The pad sections 120 and 121 are formed in positions surrounded by the photodiodes PD, the transfer gates TG, and the floating diffusions FD. This allows elements other than the floating diffusions FD and the VSS contact regions 118 to be freely arranged on the first substrate 100 on which the elements are formed, and the layout of the entire chip can be made more efficient. In addition, symmetry in the layout of the elements formed in each pixel sharing unit 539 is ensured, and the variation in the characteristics of each pixel 541 can be suppressed.

[0269] The pad parts 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad parts 120 and 121 are preferably made of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason for this will be explained below. In the following explanation, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 to the semiconductor layer 200S of the second substrate 200 is called the first manufacturing method.

[0270] Here, it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond it to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (surface of the wiring layer 100T) and the surface of the second substrate 200 (surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the surfaces of the first substrate 100 and the second substrate 200 come into contact with each other at the same time. As a result, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, for example, and it is possible to manufacture a high-quality, high-performance imaging device.

[0271] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, an alignment error may occur due to a manufacturing device for bonding. In addition, the first substrate 100 and the second substrate 200 have a diameter of, for example, several tens of centimeters, and when the first substrate 100 and the second substrate 200 are bonded together, the substrates may expand and contract in microscopic regions of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates contact each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200. In the second manufacturing method, it is preferable to take measures so that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such an error occurs. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above-mentioned error. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.

[0272] On the other hand, by forming the pad parts 120, 121 from a heat-resistant conductive material, it becomes possible to use the first manufacturing method. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD and the transfer transistor TR, the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state in which the patterns of the active elements and wiring layers constituting the pixel circuits 210 have not yet been formed. Since the second substrate 200 is in a state before the patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error does not cause an error in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. When forming a pattern on the second substrate, for example, an exposure device for pattern formation performs pattern formation while using the pattern formed on the first substrate as a target for alignment. For the above reasons, errors in the bonding positions of the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0273] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, active elements are formed on the second substrate 200. After that, the through electrodes 120E, 121E and the through electrodes TGV (FIG. 75) are formed. In forming the through electrodes 120E, 121E, and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure by an exposure device. Since reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error is only a fraction (the reciprocal of the reduced exposure projection magnification) of the error in the second substrate 200 in the second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured.

[0274] The imaging device 1 manufactured using such a first manufacturing method has different characteristics from the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, they have a tapered shape with a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV makes it easy to miniaturize the pixels 541.

[0275] Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active elements are formed on the second substrate 200 after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S), the first substrate 100 is also affected by the heat treatment required for forming the active elements. For this reason, as described above, it is preferable to use a conductive material with high heat resistance for the pad parts 120, 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pad parts 120, 121 than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad parts 120, 121. This makes it possible to manufacture the imaging device 1 by using the first manufacturing method described above.

[0276] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover the pad portions 120 and 121 (FIG. 75). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 therebetween. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film.

[0277] The light receiving lens 401 faces, for example, the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 therebetween (FIG. 75). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0278] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side. The semiconductor layer 200S is made of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided across the thickness direction. The well region 211 is, for example, a p-type semiconductor region. In the second substrate 20, a pixel circuit 210 arranged for each pixel sharing unit 539 is provided. For example, the pixel circuit 210 is provided on the front surface side (the wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0279] 77 to 81 show an example of the planar configuration of the second substrate 200. FIG. 77 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S. FIG. 78 shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and each part of the first substrate 100. FIG. 79 to 81 show an example of the planar configuration of the wiring layer 200T. Hereinafter, the configuration of the second substrate 200 will be described with reference to FIG. 75 and FIG. 77 to 81. In FIG. 77 and FIG. 78, the outline of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping with the gate electrode of the amplifying transistor AMP, a boundary between the semiconductor layer 200S and the element isolation region 213 and a boundary between the element isolation region 213 and the insulating region 212 are provided on one side in the channel width direction.

[0280] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S, and an element isolation region 213 provided in a part of the thickness direction of the semiconductor layer 200S (FIG. 75). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to the two pixel circuits 210 are arranged (FIG. 78).

[0281] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S (FIG. 75). The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrodes TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0282] The through electrodes 120E, 121E are provided penetrating the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E, 121E are connected to the wirings (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described later) of the wiring layer 200T. The through electrodes 120E, 121E are provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends are connected to the pad parts 120, 121 (FIG. 75). The through electrodes 120E are for electrically connecting the pad part 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrodes 120E. The through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0283] The through electrode TGV is provided penetrating the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring 200T. This through electrode TGV is provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG (FIG. 75). Such a through electrode TGV is for electrically connecting the transfer gate TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (a part of the row driving signal line 542, specifically, the wiring TRG1, TRG2, TRG3, TRG4 in FIG. 80 described later). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 by the through electrode TGV, so that a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0284] The insulating region 212 is a region for providing the through electrodes 120E, 121E and the through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200 insulated from the semiconductor layer 200S. For example, the through electrodes 120E, 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 (pixel sharing units 539) adjacent to each other in the H direction are provided in the insulating region 212. The insulating region 212 is provided, for example, extending in the V direction (FIGS. 77 and 78). Here, the position of the through electrodes TGV in the H direction is arranged closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical part TGa by devising the arrangement of the horizontal part TGb of the transfer gate TG (FIGS. 76A and 78). For example, the through electrode TGV is disposed at approximately the same position as the through electrodes 120E, 120E in the H direction. This allows the through electrodes 120E, 121E and the through electrode TGV to be provided together in the insulating region 212 extending in the V direction. As another arrangement example, it is possible to provide the horizontal part TGb only in the region overlapping the vertical part TGa. In this case, the through electrode TGV is formed approximately directly above the vertical part TGa, and the through electrode TGV is disposed, for example, in the approximately center of each pixel 541 in the H direction and the V direction. At this time, the position of the through electrode TGV in the H direction and the position of the through electrodes 120E, 121E in the H direction are largely shifted. For example, an insulating region 212 is provided around the through electrodes TGV and the through electrodes 120E, 121E to electrically insulate them from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly separated from the positions of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This results in the semiconductor layer 200S being divided into small pieces. In contrast, a layout in which the through electrodes 120E, 121E and the through electrode TGV are collectively disposed in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. This makes it possible to secure a large area for the semiconductor element formation region in the semiconductor layer 200S.This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0285] As described with reference to FIG. 73, the pixel sharing unit 539 has a structure in which the floating diffusions FD provided in the respective pixels 541 are electrically connected to each other, and the pixels 541 share one pixel circuit 210. The floating diffusions FD are electrically connected to each other by a pad section 120 provided on the first substrate 100 (FIGS. 75 and 76B). The electrical connection section (pad section 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected to each other via one through electrode 120E. As another structural example, it is also possible to provide the electrical connection section between the floating diffusions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusions FD1, FD2, FD3, and FD4, respectively. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes becomes larger. In comparison, the structure in which the pad portion 120 is provided in the first substrate 100 (FIGS. 75 and 76B) can reduce the number of through electrodes and make the insulating region 212 smaller. Thus, a large area can be secured for the semiconductor element formation region in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0286] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In the element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the dug portion. The insulating film is made of, for example, silicon oxide. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0287] Here, with reference to Figures 76A, 76B, and 77, the difference between the outer shape (outer shape in the substrate planar direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0288] In the imaging device 1, a pixel sharing unit 539 is provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel sharing unit 539 provided on the second substrate 200 are different from each other.

[0289] 76A and 76B, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 is configured with two pixels 541 (pixels 541A and 541B) adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 is configured with four pixels 541 arranged in two rows and two columns adjacent to each other, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a two pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a two pixel pitch in the V direction (a pitch equivalent to two pixels 541).

[0290] In Fig. 77 and Fig. 78, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the outline shape of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction, and is larger than that of the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) equivalent to one pixel in the H direction, and is formed with a size equivalent to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size equivalent to adjacent pixels arranged in one row x four columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0291] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction (FIG. 77). By providing the outer shape of each pixel circuit 210 in a substantially rectangular shape as described above, it is possible to arrange four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) in one direction (the V direction in FIG. 77). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, it is also possible to provide the formation region of each pixel circuit 210 in a substantially square shape (see FIG. 90 described later). In this case, two transistors are arranged along one direction, and it becomes difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by providing the formation region of the pixel circuit 210 in a substantially rectangular shape, it becomes easier to arrange the four transistors closely to each other, and the formation region of the pixel circuit 210 can be made smaller. That is, the pixel can be miniaturized. Furthermore, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, it is possible to increase the formation area of ​​the amplification transistor AMP and suppress noise.

[0292] For example, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the surface of the semiconductor layer 200S. The VSS contact region 218 is, for example, configured of a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 therebetween (FIG. 77).

[0293] Next, with reference to Fig. 76B and Fig. 77, the positional relationship between the pixel sharing unit 539 provided on the first substrate 100 and the pixel sharing unit 539 provided on the second substrate 200 will be described. For example, one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the upper side of the paper in Fig. 76B) is connected to one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the left side of the paper in Fig. 77). For example, the other of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the lower side of the paper in Fig. 76B) is connected to the other of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the right side of the paper in Fig. 77).

[0294] For example, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and H direction. The effects obtained by this layout will be described below.

[0295] In two pixel sharing units 539 aligned in the V direction of the first substrate 100, each pad section 120 is disposed at the center of the outer shape of the pixel sharing unit 539, that is, the center of the pixel sharing unit 539 in the V direction and the H direction ( FIG. 76B ). On the other hand, since the pixel sharing unit 539 of the second substrate 200 has an outer shape that is substantially rectangular and elongated in the V direction as described above, for example, the amplification transistor AMP connected to the pad section 120 is disposed at a position shifted upward from the center of the pixel sharing unit 539 in the V direction on the paper. For example, when the internal layouts of two pixel sharing units 539 aligned in the H direction of the second substrate 200 are the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the upper side of the paper in FIG. 76 ) becomes relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the lower side of the paper surface of FIG. 76) becomes longer. Therefore, the area of ​​the wiring required to connect this amplification transistor AMP and the pad section 120 becomes larger, and there is a concern that the wiring layout of the pixel sharing unit 539 becomes complicated. This may affect the miniaturization of the imaging device 1.

[0296] In contrast, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 at least in the V direction, the distance between the amplification transistors AMP and the pad section 120 of both of these two pixel sharing units 539 can be shortened. Therefore, compared with a configuration in which the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are the same, it is easier to miniaturize the imaging device 1. Note that the planar layout of each of the multiple pixel sharing units 539 of the second substrate 200 is symmetrical within the range shown in FIG. 77, but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 78 described later is included.

[0297] In addition, it is preferable that the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are also inverted with respect to each other in the H direction. The reason for this will be described below. As shown in FIG. 78, the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are connected to the pad portions 120, 121 of the first substrate 100. For example, the pad portions 120, 121 are disposed in the center portions in the H direction of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction). Therefore, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 with respect to each other in the H direction, the distance between each of the multiple pixel sharing units 539 of the second substrate 200 and the pad portions 120, 121 can be reduced. That is, it becomes easier to miniaturize the imaging device 1.

[0298] In addition, the position of the outline of the pixel sharing unit 539 of the second substrate 200 does not have to be aligned with the position of any of the outlines of the pixel sharing unit 539 of the first substrate 100. For example, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in one pixel sharing unit 539 (for example, the left side of the paper in FIG. 78), the outline of one side in the V direction (for example, the upper side of the paper in FIG. 78) is disposed outside the outline of one side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the upper side of the paper in FIG. 76B). In addition, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in the other pixel sharing unit 539 (for example, the right side of the paper in FIG. 78), the outline of the other side in the V direction (for example, the lower side of the paper in FIG. 78) is disposed outside the outline of the other side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the lower side of the paper in FIG. 76B). In this way, by disposing the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 relative to each other, it is possible to shorten the distance between the amplification transistor AMP and the pad section 120. Therefore, it becomes easier to miniaturize the imaging device 1.

[0299] Furthermore, the positions of the outlines of the multiple pixel sharing units 539 on the second substrate 200 do not need to be aligned with each other. For example, two pixel sharing units 539 aligned in the H direction of the second substrate 200 are arranged with the positions of the outlines in the V direction shifted from each other. This makes it possible to shorten the distance between the amplification transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.

[0300] With reference to FIG. 76B and FIG. 78, the repeated arrangement of the pixel sharing units 539 in the pixel array section 540 will be described. The pixel sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 76B). For example, in the pixel array section 540 of the first substrate 100, the pixel sharing units 539 having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a two pixel pitch (a pitch equivalent to two pixels 541) in the V direction. Alternatively, the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539 in which two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array section 540 of the first substrate 100, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( FIG. 78 ). For example, the pixel array section 540 of the second substrate 200 is provided with a pair of pixel sharing units 539 including two pixel sharing units 539 each having a size equivalent to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and offset from each other in the V direction. In the pixel array section 540 of the second substrate 200, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. By repeatedly arranging the pixel sharing units 539 in this way, it is possible to arrange the pixel sharing units 539 without any gaps. This makes it easier to miniaturize the imaging device 1.

[0301] It is preferable that the amplification transistor AMP has a three-dimensional structure, such as a Fin type (FIG. 75). This increases the effective gate width, making it possible to suppress noise. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplification transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0302] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. This passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. This interlayer insulating film 222 separates the plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). The interlayer insulating film 222 is made of, for example, silicon oxide.

[0303] In the wiring layer 200T, for example, from the semiconductor layer 200S side, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact parts 201, 202 are provided in this order, and these are insulated from each other by an interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection parts are provided to connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layers below them. The connection parts are parts in which a conductive material is embedded in connection holes provided in the interlayer insulating film 222. For example, in the interlayer insulating film 222, a connection part 218V is provided to connect the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the hole diameter of such a connection part that connects elements of the second substrate 200 to each other is different from the hole diameters of the through electrodes 120E, 121E and the through electrodes TGV. Specifically, the diameter of the connection hole connecting the elements of the second substrate 200 is preferably smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV. The reason for this will be described below. The depth of the connection part (connection part 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E, 121E and the through electrode TGV. Therefore, the connection part can be filled with a conductive material more easily than the through electrodes 120E, 121E and the through electrode TGV. By making the diameter of the connection part smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV, it becomes easier to miniaturize the imaging device 1.

[0304] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E to the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0305] Next, the planar configuration of the wiring layer 200T will be described with reference to Fig. 79 to Fig. 81. Fig. 79 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Fig. 80 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Fig. 81 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0306] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) (FIG. 80). These wirings correspond to the row driving signal lines 542 described with reference to FIG. 73. The wirings TRG1, TRG2, TRG3, and TRG4 are for sending driving signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E, respectively. The wiring SELL is for sending a driving signal to the gate of the selection transistor SEL, the wiring RSTL is for sending a driving signal to the gate of the reset transistor RST, and the wiring FDGL is for sending a driving signal to the gate of the FD conversion gain switching transistor FDG, respectively. The wirings SELL, RSTL, and FDGL are each connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0307] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) (FIG. 81). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part 218V. The reference potential line VSS is also connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad part 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part.

[0308] The contact parts 201 and 202 may be provided at positions overlapping the pixel array part 540 in a plan view (for example, FIG. 72), or may be provided in the outer peripheral part 540B of the pixel array part 540 (for example, FIG. 75). The contact parts 201 and 202 are provided on the surface of the second substrate 200 (surface on the wiring layer 200T side). The contact parts 201 and 202 are made of metal such as Cu (copper) and Al (aluminum). The contact parts 201 and 202 are exposed on the surface of the wiring layer 200T (surface on the third substrate 300 side). The contact parts 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0309] 75 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Also, as shown in FIG. 72, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be arranged in the vicinity of the pixel array section 540.

[0310] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. A circuit is provided on the surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input unit 510A, the row driver 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B is provided on the surface side of the semiconductor layer 300S. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact units 301 and 302. The contact parts 301 and 302 are exposed on the surface (surface on the second substrate 200 side) of the wiring layer 300T, and the contact part 301 is in contact with the contact part 201 of the second substrate 200, and the contact part 302 is in contact with the contact part 202 of the second substrate 200. The contact parts 301 and 302 are electrically connected to circuits (for example, at least one of the input part 510A, the row driving part 520, the timing control part 530, the column signal processing part 550, the image signal processing part 560, and the output part 510B) formed in the semiconductor layer 300S. The contact parts 301 and 302 are made of metals such as Cu (copper) and aluminum (Al). For example, the external terminal TA is connected to the input part 510A via the connection hole part H1, and the external terminal TB is connected to the output part 510B via the connection hole part H2.

[0311] Here, the features of the imaging device 1 will be described.

[0312] In general, an imaging device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, and enabling the imaging device to output better image data (image information). On the other hand, increasing the size of the transistors (especially the size of the amplifying transistors) included in the pixel circuit reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal, and enabling the imaging device to output better image data (image information).

[0313] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor in the pixel circuit may be reduced, and if the size of the transistor in the pixel circuit is increased, the area of ​​the photodiode may be reduced.

[0314] To solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it possible to maximize the area of ​​the photodiode PD and to maximize the size of the transistor provided in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the S / N ratio of the pixel signal, and enables the imaging device 1 to output better image data (image information).

[0315] When realizing a structure in which a plurality of pixels 541 share one pixel circuit 210 and this is arranged to overlap the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the plurality of pixels 541. In order to secure a large area of ​​the semiconductor substrate 200 in which the pixel circuit 210 is formed, for example, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one. Similarly, for the plurality of wirings extending from the VSS contact region 118, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one.

[0316] For example, if a connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced. Similarly, if a connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced.

[0317] In order to solve these problems, for example, the imaging device 1 of this embodiment can have a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD, and the first substrate 100 can be provided with a connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541, and a connection wiring that interconnects and combines the VSS contact regions 118 provided in each of the plurality of pixels 541.

[0318] Here, when the above-mentioned second manufacturing method is used as a manufacturing method for providing the first substrate 100 with the connection wiring for connecting the floating diffusions FD of the plurality of pixels 541 to one another and the connection wiring for connecting the VSS contact regions 118 of the plurality of pixels 541 to one another, for example, the first substrate 100 and the second substrate 200 can be manufactured using an appropriate process according to the configuration of each substrate, and a high-quality, high-performance imaging device can be manufactured. In addition, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, when the above-mentioned second manufacturing method is used, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact region 118 are provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, it is preferable to make the electrodes formed on the surfaces of the two substrates large so that the electrodes can contact each other even if a positional deviation occurs between the electrodes provided on the surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together. In this case, it may become difficult to arrange the electrodes within the limited area of ​​each pixel of the imaging device 1.

[0319] In order to solve the problem of needing a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, for example, the imaging device 1 of this embodiment can use the first manufacturing method described above as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it easy to align the elements formed on the first substrate 100 and the second substrate 200, respectively, and allows the manufacturing of a high-quality, high-performance imaging device. Furthermore, it is possible to have a unique structure that is generated by using this manufacturing method. That is, the structure has a semiconductor layer 100S and wiring layer 100T of the first substrate 100 and a semiconductor layer 200S and wiring layer 200T of the second substrate 200 stacked in this order, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back, and has through electrodes 120E, 121E that pass from the surface side of the semiconductor layer 200S of the second substrate 200, through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100.

[0320] In a structure in which a first substrate 100 is provided with connection wiring that interconnects and combines the floating diffusions FD of the multiple pixels 541 into one, and connection wiring that interconnects and combines the VSS contact regions 118 of the multiple pixels 541 into one, if this structure is stacked on a second substrate 200 using the first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the influence of the heating process required when forming the active elements provided in the pixel circuit 210 will extend to the connection wiring formed on the first substrate 100.

[0321] Therefore, in order to solve the problem that the connection wiring is affected by the heat treatment when forming the active element, in the imaging device 1 of the present embodiment, it is desirable to use a conductive material with high heat resistance for the connection wiring that connects the floating diffusions FD of the respective pixels 541 to each other and combines them into one, and for the connection wiring that connects the VSS contact regions 118 of the respective pixels 541 to each other and combines them into one. Specifically, the conductive material with high heat resistance can be a material with a higher melting point than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200.

[0322] In this manner, for example, the imaging device 1 of the present embodiment has: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which through-electrodes 120E, 121E are provided from the front surface side of the semiconductor layer 200S of the second substrate 200, penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reaching the front surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the floating diffusions FD provided in each of the plurality of pixels 541 are provided. By providing a structure in which the first substrate 100 and the second substrate 200 have a connection wiring that interconnects the floating diffusions FD of the respective pixels 541 and combines them into one, and a connection wiring that interconnects the VSS contact regions 118 of the respective pixels 541 and combines them into one, and a structure in which the connection wiring is formed from a conductive material with high heat resistance, it is possible to provide the first substrate 100 with the connection wiring that interconnects the floating diffusions FD of the respective pixels 541 and combines them into one, and the connection wiring that connects the VSS contact regions 118 of the respective pixels 541 and combines them into one, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0323] [Operation of imaging device 1] Next, the operation of the imaging device 1 will be described with reference to Figs. 82 and 83. Figs. 82 and 83 are diagrams in which arrows representing the paths of each signal have been added to Fig. 72. Fig. 82 shows the paths of the input signal input from the outside to the imaging device 1, the power supply potential, and the reference potential with arrows. Fig. 83 shows the signal paths of the pixel signals output from the imaging device 1 to the outside with arrows. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the imaging device 1 via the input section 510A is transmitted to the row driver 520 of the third substrate 300, and a row drive signal is generated in the row driver 520. This row drive signal is sent to the second substrate 200 via the contact sections 301 and 201. Furthermore, this row drive signal reaches each of the pixel shared units 539 of the pixel array section 540 via a row drive signal line 542 in the wiring layer 200T. Among the row driving signals that reach the pixel sharing unit 539 of the second substrate 200, the driving signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven (FIG. 82). In addition, the power supply potential and the reference potential supplied to the input section 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuits 210 of each pixel sharing unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. Meanwhile, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539 via the through-electrode 120E. A pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 202 and 302. This pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0324] [effect] In this embodiment, the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). This allows the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 to be enlarged compared to when the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce the transistor noise of the pixel circuit 210. This improves the signal-to-noise ratio of the pixel signals, and the imaging device 1 can output better pixel data (image information). In addition, it is possible to miniaturize the imaging device 1 (in other words, reduce the pixel size and make the imaging device 1 smaller). By reducing the pixel size, the imaging device 1 can increase the number of pixels per unit area and output a high-quality image.

[0325] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by the through electrodes 120E, 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting by through wiring (for example, TSV (Thorough Si Via)) that penetrates a semiconductor layer can be considered. Compared to such methods, by providing the through electrodes 120E, 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. This reduces the pixel size, and the imaging device 1 can be made more compact. In addition, the resolution can be increased by further miniaturizing the area per pixel. When it is not necessary to reduce the chip size, the formation area of ​​the pixels 541A, 541B, 541C, 541D and the pixel circuit 210 can be expanded. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise in the transistors provided in the pixel circuits 210. This improves the signal-to-noise ratio of the pixel signals, enabling the imaging device 1 to output better pixel data (image information).

[0326] Furthermore, in the imaging device 1, the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are provided on different substrates (the second substrate 200 and the third substrate 300). This allows the area of ​​the pixel circuit 210 and the areas of the column signal processing section 550 and the image signal processing section 560 to be enlarged compared to a case in which the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are formed on the same substrate. This allows noise generated in the column signal processing section 550 to be reduced, and allows the image signal processing section 560 to be equipped with a more advanced image processing circuit. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).

[0327] In the imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. The contact sections 201, 202, 301, and 302 that connect the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 201, 202, 301, and 302 can be freely laid out without being interfered with in the layout by various wirings provided in the pixel array. This makes it possible to use the contact sections 201, 202, 301, and 302 for electrical connection between the second substrate 200 and the third substrate 300. By using the contact sections 201, 202, 301, and 302, for example, the column signal processing section 550 and the image signal processing section 560 have a high degree of freedom in layout. This makes it possible to reduce noise generated in the column signal processing unit 550 and to incorporate a more advanced image processing circuit in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signals is improved, and the imaging device 1 can output better pixel data (image information).

[0328] Furthermore, in the imaging device 1, the pixel separator 117 penetrates the semiconductor layer 100S. This makes it possible to suppress color mixing between the pixels 541A, 541B, 541C, and 541D even if the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is reduced due to miniaturization of the area per pixel. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0329] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel sharing unit 539. This allows the formation area of ​​the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, FD conversion gain switching transistor FDG) that constitute the pixel circuit 210 to be larger than when a pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by increasing the formation area of ​​the amplification transistor AMP, it is possible to suppress noise. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).

[0330] Furthermore, in the imaging device 1, the pad section 120 that electrically connects the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the four pixels (pixels 541A, 541B, 541C, 541D) is provided on the first substrate 100. This makes it possible to reduce the number of through electrodes (through electrodes 120E) that connect the first substrate 100 and the second substrate 200, compared to the case where such a pad section 120 is provided on the second substrate 200. Therefore, it is possible to reduce the insulating region 212 and ensure a sufficient size of the formation region (semiconductor layer 200S) of the transistors that constitute the pixel circuit 210. This makes it possible to reduce noise of the transistors provided in the pixel circuit 210, improve the signal-to-noise ratio of the pixel signal, and enable the imaging device 1 to output better pixel data (image information).

[0331] Modifications of the imaging device 1 according to the above embodiment will be described below. In the following modifications, components common to the above embodiment will be denoted by the same reference numerals.

[0332] <2. Variation 1> 84 to 88 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment. FIG. 84 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 77 described in the above embodiment. FIG. 85 shows a schematic configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, and corresponds to FIG. 78 described in the above embodiment. FIG. 86 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 79 described in the above embodiment. FIG. 87 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 80 described in the above embodiment. FIG. 88 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 81 described in the above embodiment.

[0333] In this modification, as shown in Fig. 85, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (e.g., the right side of the paper) is configured to be inverted only in the H direction from the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper). Also, the deviation in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is larger than the deviation (Fig. 78) described in the above embodiment. In this way, by increasing the deviation in the V direction, it is possible to reduce the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 connected thereto (the pad section 120 of the other (lower side of the paper) of the two pixel sharing units 539 arranged in the V direction shown in Fig. 76). With such a layout, in the first modification of the imaging device 1 shown in FIGS. 84 to 88, the area of ​​the two pixel sharing units 539 arranged in the H direction can be made the same as that of the pixel sharing unit 539 of the second substrate 200 described in the above embodiment without inverting the planar layouts of the two pixel sharing units 539 arranged in the H direction in the V direction. The planar layout of the pixel sharing unit 539 of the first substrate 100 is the same as the planar layout (FIGS. 76A and 76B) described in the above embodiment. Therefore, the imaging device 1 of this modification can obtain the same effect as the imaging device 1 described in the above embodiment. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0334] <3. Variation 2> 89 to 94 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment. FIG. 89 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 76A described in the above embodiment. FIG. 90 shows a schematic planar configuration of the surface vicinity of the semiconductor layer 200S of the second substrate 200, and corresponds to FIG. 77 described in the above embodiment. FIG. 91 shows a schematic configuration of the first wiring layer W1 and each part of the semiconductor layer 200S and the first substrate 100 connected to the first wiring layer W1, and corresponds to FIG. 78 described in the above embodiment. FIG. 92 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 79 described in the above embodiment. FIG. 93 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 80 described in the above embodiment. FIG. 94 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 81 described in the above embodiment.

[0335] In this modification, the outer shape of each pixel circuit 210 has a substantially square planar shape (FIG. 90, etc.). In this respect, the planar configuration of the imaging device 1 of this modification differs from the planar configuration of the imaging device 1 described in the above embodiment.

[0336] For example, the pixel sharing unit 539 of the first substrate 100 is formed over a pixel region of 2 rows x 2 columns as described in the above embodiment, and has a substantially square planar shape ( FIG. 89 ). For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1, TG3 of the pixels 541A and 541C of one pixel column extend in a direction from a position overlapping with the vertical portion TGa toward the center of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541A and 541C and toward the center of the pixel sharing unit 539), and the horizontal portions TGb of the transfer gates TG2, TG4 of the pixels 541B and 541D of the other pixel column extend in a direction from a position overlapping with the vertical portion TGa toward the outside of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pi...

Claims

1. a first substrate including a first element layer including a first active element, a first wiring layer disposed on the first element layer, and a shield layer including a conductive material disposed on the first wiring layer; a second substrate including a second element layer including a second active element disposed on the shield layer, and a second wiring layer disposed on the second element layer; The first substrate and the second substrate are laminated together, the first substrate further includes a photoelectric conversion unit disposed under the first element layer, An opening is provided in the shielding layer, a connection wiring that penetrates the opening and connects the photoelectric conversion unit or the first wiring layer to the second wiring layer, a sheath portion is provided around the opening of the shield layer, coaxially with the connection wiring, and surrounding an outer circumferential surface of the connection wiring via an interlayer insulating film; A semiconductor device, wherein the sheath portion extends along the longitudinal direction of the connection wiring above an upper surface of the shielding layer and below a lower surface of the shielding layer, and the outer peripheral surface of the sheath portion contacts the shielding layer, thereby electrically connecting the sheath portion to the shielding layer.

2. The semiconductor device according to claim 1 , further comprising a third substrate laminated on said second substrate.

3. The semiconductor device according to claim 1 , which constitutes a solid-state imaging device.

4. forming a first wiring layer on a first element layer including a first active element; forming a shield layer including a conductive material on the first wiring layer to form a first substrate including the first element layer, the first wiring layer, and the shield layer; preparing a second substrate on which a second element layer including a second active element is formed; forming the second element layer on the shield layer by bonding the second element layer side of the second substrate to the shield layer side of the first substrate; A second wiring layer is formed on the second element layer. Including, forming a photoelectric conversion unit under the first element layer of the first substrate; forming an opening in the shielding layer; forming a connection wiring that penetrates the opening and connects the photoelectric conversion unit or the first wiring layer to the second wiring layer; a sheath portion is formed around the opening of the shield layer, coaxially with the connection wiring, and surrounding an outer circumferential surface of the connection wiring via an interlayer insulating film; A method for manufacturing a semiconductor device, wherein the sheath portion extends along the longitudinal direction of the connection wiring above an upper surface of the shielding layer and below a lower surface of the shielding layer, and the outer peripheral surface of the sheath portion contacts the shielding layer, thereby electrically connecting the sheath portion to the shielding layer.

5. a first substrate including a first element layer including a first active element and a first wiring layer disposed on the first element layer; a second substrate including a second element layer including a second active element and a second wiring layer disposed on the second element layer; the first substrate and the second substrate are laminated together, and an electromagnetic shielding layer including a conductive material is provided between the first substrate and the second substrate; the electromagnetic shielding layer is selectively disposed to cover at least the first active element in a plan view; a first diffusion prevention layer made of a dielectric material provided on an upper surface of the electromagnetic shielding layer; a second diffusion prevention layer made of a dielectric material provided on a lower surface of the electromagnetic shielding layer; a third diffusion prevention layer made of a dielectric material provided around a side surface of the electromagnetic shielding layer, between the first and second diffusion prevention layers, with the same thickness as the electromagnetic shielding layer, and extending in a direction parallel to upper and lower surfaces of the electromagnetic shielding layer.

6. The semiconductor device according to claim 5 , wherein the electromagnetic shielding layer is connected to a ground potential.

7. 6. The semiconductor device according to claim 5, wherein said conductive material includes any one of tungsten, titanium, titanium nitride, carbon, and polycrystalline silicon.

8. forming a first wiring layer on a first element layer including a first active element, thereby forming a first substrate including the first element layer and the first wiring layer; Providing a second substrate; forming an electromagnetic shielding layer including a conductive material on the first substrate or the second substrate; the first substrate and the second substrate are bonded together via the electromagnetic shielding layer; forming a second element layer including a second active element on the second substrate; A second wiring layer is formed on the second element layer. Including, The electromagnetic shielding layer is selectively formed to cover at least the first active element in a plan view; forming a first diffusion prevention layer made of a dielectric material on an upper surface of the electromagnetic shielding layer; forming a second diffusion prevention layer made of a dielectric material on a lower surface of the electromagnetic shielding layer; A method for manufacturing a semiconductor device, comprising: forming a third diffusion prevention layer made of a dielectric material around a side surface of the electromagnetic shielding layer, between the first and second diffusion prevention layers, the third diffusion prevention layer having the same thickness as the electromagnetic shielding layer, and extending in a direction parallel to the top and bottom surfaces of the electromagnetic shielding layer.

9. A first substrate including a first element layer including a first active element, a first wiring layer disposed on the first element layer, and a photoelectric conversion unit disposed under the first element layer; a second substrate including a second element layer including a second active element and a second wiring layer disposed on the second element layer; the first substrate and the second substrate are laminated together, and a light attenuating section made of a material having a higher refractive index than the surroundings is provided between the second active element and the photoelectric conversion section; A semiconductor device, wherein the plurality of light attenuating portions are arranged at different depths and complementarily in a plan view.

10. 10. The semiconductor device according to claim 9, wherein said light attenuating portion is made of a silicon material formed in an interlayer insulating film.

11. The semiconductor device according to claim 9 , wherein the light attenuating portion includes a convex shape formed on the second substrate.

12. The semiconductor device according to claim 9 , wherein a bottom surface portion of said light attenuating portion is formed in a convex shape.

13. forming a first wiring layer on a first element layer including a first active element, and forming a photoelectric conversion unit under the first element layer, thereby forming a first substrate including the first element layer, the first wiring layer, and the photoelectric conversion unit; Providing a second substrate; A light attenuating portion made of a material having a refractive index higher than that of the surroundings is formed on the second substrate, The first substrate and the second substrate are bonded to each other at the light attenuation portion side, forming a second element layer including a second active element on the second substrate; A second wiring layer is formed on the second element layer. Including, A method for manufacturing a semiconductor device, comprising forming a plurality of the light attenuating portions at different depths and complementary to each other in a plan view.

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