Photoelectric conversion device

Abstract

To reduce a variation in characteristics between elements constituting a sample hold circuit to improve the accuracy of correction processing through CDS.SOLUTION: In a photoelectric conversion device, a column circuit has a sample hold circuit that holds reset signals and a sample hold circuit 44S that holds optical detection signals. The sample hold circuit has first switches S61-S6N provided between an output line 16 and unit capacities C21-C2N, and a plurality of second switches S71-S7N-1 provided between electrodes of one of the adjacent unit capacities. Electrodes of the other of the unit capacities C21-C2N of the sample hold circuit are connected with each other by wiring IL5. The second switches S71-S7N-1 are arranged along a first direction parallel to a plurality of columns, and the wiring IL5 extends along the first direction.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device equipped with a sample-and-hold unit that holds signals output from pixels. The sample-and-hold unit described in Patent Document 1 has two sample-and-hold circuits in parallel for one vertical signal line, and at least one of these two sample-and-hold circuits has at least two sampling capacitors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] The sample-and-hold unit described in Patent Document 1 may have a function of removing noise by correlated double sampling (CDS) processing. However, Patent Document 1 does not disclose any specific technology for improving the accuracy of the correction processing by CDS in the sample-and-hold unit.

[0005] An object of the present invention is to provide a photoelectric conversion device capable of improving the accuracy of correction processing by CDS. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a photoelectric conversion device having a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns, a plurality of output lines provided corresponding to the plurality of columns and through which a first signal and a second signal are output from the pixels, and a plurality of column circuits provided corresponding to the plurality of output lines, wherein each of the plurality of column circuits has a sample hold section including a first sample hold circuit that holds the first signal and a second sample hold circuit that holds the second signal, each of the first sample hold circuit and the second sample hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors, and the switch circuit has a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitors, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitors, the second electrodes of the plurality of unit capacitors of the first sample-and-hold circuit are connected to each other by a first wiring, the second electrodes of the plurality of unit capacitors of the second sample-and-hold circuit are connected to each other by a second wiring, the plurality of second switches constituting the switch circuits of the first sample-and-hold circuit and the second sample-and-hold circuit are arranged along a first direction parallel to the plurality of columns, and the first wiring and the second wiring extend along the first direction. a first capacitance section including the switch circuit and the plurality of unit capacitors of the first sample-and-hold circuit, and a second capacitance section including the switch circuit and the plurality of unit capacitors of the second sample-and-hold circuit are arranged along the first direction, the first sample-and-hold circuit further has a first amplification section connected to the first wiring, the second sample-and-hold circuit further has a second amplification section connected to the second wiring, and the first capacitance section, the second capacitance section, the first amplification section, and the second amplification section are arranged along the first direction. A photoelectric conversion device is provided. According to another aspect of the present invention, there is provided a photoelectric conversion device having a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns, a plurality of output lines provided corresponding to the plurality of columns and through which first and second signals are output from the pixels, and a plurality of column circuits provided corresponding to the plurality of output lines, wherein each of the plurality of column circuits has a sample hold section including a first sample hold circuit that holds the first signal and a second sample hold circuit that holds the second signal, each of the first sample hold circuit and the second sample hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors, and the switch circuit the path includes a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitances, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitances, the second electrodes of the plurality of unit capacitances of the first sample-and-hold circuit are connected to each other by a first wiring, the second electrodes of the plurality of unit capacitances of the second sample-and-hold circuit are connected to each other by a second wiring, the plurality of second switches constituting the switch circuits of the first sample-and-hold circuit and the second sample-and-hold circuit are arranged along a first direction parallel to the plurality of columns, and the first wiring and the second wiring extend along the first direction; There is provided a photoelectric conversion device in which a first capacitance section including the switch circuit and the multiple unit capacitances of the first sample and hold circuit, and a second capacitance section including the switch circuit and the multiple unit capacitances of the second sample and hold circuit are arranged along the first direction, the first sample and hold circuit further has a first amplification section connected to the first wiring, the second sample and hold circuit further has a second amplification section connected to the second wiring, the first capacitance section, the second capacitance section, the first amplification section, and the second amplification section are arranged along the first direction, and the first amplification section and the second amplification section are adjacent to each other, or the first capacitance section and the second capacitance section are adjacent to each other.

[0007] In addition, the present invention FurthermoreAccording to another aspect, a photoelectric conversion device includes a pixel array section in which a plurality of pixels each having a photoelectric conversion section are arranged in a plurality of columns, a plurality of output lines provided corresponding to the plurality of columns and through which a first signal and a second signal are output from the pixels, and a plurality of column circuits provided corresponding to the plurality of output lines, each of the plurality of column circuits having a sample hold section including a first sample hold circuit that holds the first signal and a second sample hold circuit that holds the second signal, Each of the second sample-and-hold circuits has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors, the switch circuit has a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitors, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitors, and the unit capacitors of the first sample-and-hold circuit and the unit capacitors of the second sample-and-hold circuit are alternately arranged adjacent to each other along a first direction parallel to the plurality of columns. the first sample-and-hold circuit further has a first amplifier connected to a first wiring that connects second electrodes of the plurality of unit capacitors to each other, the second sample-and-hold circuit further has a second amplifier connected to a second wiring that connects second electrodes of the plurality of unit capacitors to each other, and the plurality of unit capacitors of the first sample-and-hold circuit, the plurality of unit capacitors of the second sample-and-hold circuit, the first amplifier, and the second amplifier are arranged along the first direction. A photoelectric conversion device is provided. According to yet another aspect of the present invention, there is provided a photoelectric conversion device having a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns, a plurality of output lines provided corresponding to the plurality of columns and through which a first signal and a second signal are output from the pixels, and a plurality of column circuits provided corresponding to the plurality of output lines, wherein each of the plurality of column circuits has a sample hold section including a first sample hold circuit for holding the first signal and a second sample hold circuit for holding the second signal, and each of the first sample hold circuit and the second sample hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors, and the switch circuit has a plurality of first switches respectively provided between the output line and a first electrode of the plurality of unit capacitors, and and a plurality of second switches respectively provided between first electrodes of the first sample and hold circuit, the unit capacitors of the first sample and hold circuit and the unit capacitors of the second sample and hold circuit are arranged adjacent to each other and alternately along a first direction parallel to the plurality of columns, the first sample and hold circuit further has a first amplifier connected to a first wiring that connects the second electrodes of the plurality of unit capacitors to each other, the second sample and hold circuit further has a second amplifier connected to a second wiring that connects the second electrodes of the plurality of unit capacitors to each other, the plurality of unit capacitors of the first sample and hold circuit, the plurality of unit capacitors of the second sample and hold circuit, the first amplifier, and the second amplifier are arranged along the first direction, and the first amplifier and the second amplifier are adjacent to each other. Effect of the Invention

[0008] According to the present invention, a photoelectric conversion device with improved accuracy can be realized. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 3] 4 is a timing chart showing the operation of a pixel in the photoelectric conversion device according to the first embodiment of the present invention. [Figure 4] 2 is a block diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Diagram 5]1 is a circuit diagram showing an example of the configuration of an N signal sample-and-hold circuit in a photoelectric conversion device according to a first embodiment of the present invention. [Figure 6] 1 is a circuit diagram showing an example of the configuration of an S signal sample-and-hold circuit in a photoelectric conversion device according to a first embodiment of the present invention. [Figure 7] 2 is a block diagram showing an example of the configuration of a column AD conversion unit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 8] 3 is a diagram showing an example of the layout of each component and wiring of a column sample-and-hold unit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 9] 3 is a diagram showing an example of the layout of each part of a unitary capacitance section in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 10] FIG. 2 is a plan view (part 1) showing an example of the layout of a capacitance section in the photoelectric conversion device according to the first embodiment of the present invention. [Figure 11] FIG. 2 is a plan view (part 2) showing an example of the layout of a capacitance section in the photoelectric conversion device according to the first embodiment of the present invention. [Figure 12] FIG. 11 is a diagram showing an example of the layout of each component of a column sample-and-hold unit in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 13] FIG. 13 is a diagram showing an example of the layout of each component of a column sample-and-hold unit in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 14] FIG. 13 is a diagram showing an example of the layout of each component of a column sample-and-hold unit in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 15] FIG. 13 is a diagram showing an example of the layout of each component of a column sample-and-hold unit in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 16] FIG. 13 is a diagram (part 1) showing a layout example of the arrangement of each part of a unitary capacitance part in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 17] FIG. 13 is a diagram (part 2) showing a layout example of the arrangement of each part of a unitary capacitance part in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 18] FIG. 13 is a diagram (part 3) showing a layout example of the arrangement of each part of a unitary capacitance part in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 19] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a sixth embodiment of the present invention. [Figure 20] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving object according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [First embodiment] The overall configuration of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment.

[0011] 1, a photoelectric conversion device 100 according to this embodiment includes a pixel array section 10, a vertical scanning section 20, a signal processing section 30, a sample-and-hold section 40, an analog-to-digital conversion section (AD conversion section) 60, and a digital memory section 70. The photoelectric conversion device 100 further includes a horizontal scanning section 80, a digital signal processing section 82, an output section 84, and a control section 90.

[0012] The pixel array section 10 is provided with a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. For convenience, FIG. 1 shows a portion of the pixels 12 constituting the pixel array section 10. In addition to effective pixels that output pixel signals according to the amount of incident light, the pixel array section 10 may also include optical black pixels in which a photoelectric conversion section is shielded from light, dummy pixels that do not output signals, and the like. The number of pixels 12 constituting the pixel array section 10 is not particularly limited. A specific configuration example of the pixels 12 will be described later.

[0013] In each row of the pixel array section 10, a control line 14 is arranged extending in a first direction (horizontal direction in FIG. 1). The control line 14 is connected to each of the pixels 12 arranged in the first direction, and serves as a signal line common to these pixels 12. The first direction in which the control lines 14 extend may be referred to as the row direction or horizontal direction. The row direction is a direction parallel to the multiple rows. Each of the control lines 14 may include multiple signal lines for supplying multiple types of control signals to the pixels 12. The control lines 14 in each row are connected to a vertical scanning section 20.

[0014] In each column of the pixel array section 10, an output line 16 is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each of the output lines 16 is connected to the pixels 12 aligned in the second direction, and serves as a common signal line for these pixels 12. The second direction in which the output lines 16 extend may be referred to as the column direction or vertical direction. The column direction is a direction parallel to the multiple columns. The output lines 16 are connected to a signal processing section 30.

[0015] The vertical scanning unit 20 is a control unit having a function of receiving a control signal output from the control unit 90, generating a control signal for driving the pixels 12, and supplying the control signal to the pixels 12 via the control line 14. The vertical scanning unit 20 may include logic circuits such as a shift register and an address decoder. The vertical scanning unit 20 sequentially scans the pixels 12 in the pixel array unit 10 row by row, and outputs a pixel signal of each pixel 12 to the signal processing unit 30 via the output line 16.

[0016] The signal processing unit 30 has a plurality of column signal processing units 32 provided corresponding to the respective columns of the pixel array unit 10. The column signal processing unit 32 of each column is connected to the output line 16 of the corresponding column. Each of the column signal processing units 32 may include a current source that supplies a bias current to the pixels 12 via the output line 16, an amplifier, and the like.

[0017] The sample and hold unit 40 has a plurality of column sample and hold units 42 provided corresponding to the respective columns of the pixel array unit 10. Each of the column sample and hold units 42 is connected to the column signal processing unit 32 of the corresponding column. The column sample and hold unit 42 has a function of sampling and holding a signal output from the column signal processing unit 32. A specific configuration example of the column sample and hold unit 40 will be described later.

[0018] The AD conversion unit 60 has a plurality of column AD conversion units 62 provided corresponding to the respective columns of the pixel array unit 10. Each of the column AD conversion units 62 is connected to the column sample-and-hold unit 42 of the corresponding column. The column AD conversion unit 62 has a function of converting the signal output from the column sample-and-hold unit 42 from an analog signal to a digital signal.

[0019] The digital memory unit 70 has a plurality of column memory units 72 provided corresponding to the respective columns of the pixel array unit 10. Each of the column memory units 72 is connected to the column AD conversion unit 62 of the corresponding column. The column memory unit 72 has a function of holding a digital signal output from the column AD conversion unit 62.

[0020] The column signal processing unit 32, the column sample and hold unit 42, the column AD conversion unit 62, and the column memory unit 72 provided for each column of the pixel array unit 10 may be referred to as a column circuit. In other words, the signal processing unit 30, the sample and hold unit 40, the AD conversion unit 60, and the digital memory unit 70 configure a plurality of column circuits corresponding to the number of pixel columns that make up the pixel array unit 10.

[0021] The horizontal scanning unit 80 is a control unit having a function of receiving a control signal output from the control unit 90, generating a control signal for outputting the digital signal held in the digital memory unit 70, and supplying the control signal to the digital memory unit 70. The horizontal scanning unit 80 may include logic circuits such as a shift register and an address decoder. A control line of the horizontal scanning unit 80 provided corresponding to each column of the pixel array unit 10 is connected to the column memory unit 72 of the corresponding column. When the column memory unit 72 of each column receives a control signal via the control line of the corresponding column of the horizontal scanning unit 80, it outputs the held digital signal to the digital signal processing unit 82.

[0022] The digital signal processing unit (DFE: Digital Front End) 82 is a circuit unit that executes predetermined signal processing on the digital signal output from the digital memory unit 70. Examples of the processing executed by the digital signal processing unit 82 include amplification processing and correction processing.

[0023] The output unit 84 has an external interface circuit, and is a circuit unit for outputting the signal processed by the digital signal processing unit 82 to the outside of the photoelectric conversion device 100. The external interface circuit included in the output unit 84 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be used as the external interface circuit.

[0024] The control unit 90 is a circuit unit for supplying control signals for controlling the operations and timings of the vertical scanning unit 20, the signal processing unit 30, the sample and hold unit 40, the AD conversion unit 60, the digital memory unit 70, the horizontal scanning unit 80, and the output unit 84. Note that it is not necessary for all of these control signals to be supplied from the control unit 90, and at least some of these control signals may be supplied from outside the photoelectric conversion device 100.

[0025] Next, a configuration example of the pixel 12 in the photoelectric conversion device 100 according to the present embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to the present embodiment.

[0026] Each pixel 12 may be a minimum unit of a circuit that is repeatedly arranged to form an image. Each pixel 12 may be composed of a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in FIG. 2, for example. The transfer transistor M1, the reset transistor M2, the amplification transistor M3, and the selection transistor M4 may be, for example, an N-type MOS transistor, but may also be a P-type MOS transistor or other known switching elements. Each pixel 12 may have a microlens and a color filter arranged on an optical path until the incident light is guided to the photoelectric conversion unit PD. The microlens focuses the incident light on the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0027] The photoelectric conversion unit PD may be, for example, a photodiode. The photodiode constituting the photoelectric conversion unit PD has an anode connected to a ground node (GND) and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A connection node of the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 is a so-called floating diffusion unit FD. The floating diffusion unit FD includes a capacitance component (floating diffusion capacitance) and functions as a charge storage unit. This floating diffusion capacitance includes a PN junction capacitance, a wiring capacitance, and the like.

[0028] The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply voltage node (voltage VDD). The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 16.

[0029] In the case of the pixel configuration of FIG. 2, the control line 14 of each row arranged in the pixel array unit 10 includes three signal lines to which control signals PRES, PTX, and PSEL are supplied from the vertical scanning unit 20. The signal line to which the control signal PRES is supplied is connected to the gates of the reset transistors M2 of the pixels 12 belonging to the corresponding row, forming a signal line common to these pixels 12. The signal line to which the control signal PTX is supplied is connected to the gates of the transfer transistors M1 of the pixels 12 belonging to the corresponding row, forming a signal line common to these pixels 12. The signal line to which the control signal PSEL is supplied is connected to the gates of the selection transistors M4 of the pixels 12 belonging to the corresponding row, forming a signal line common to these pixels 12. When each transistor constituting the pixel 12 is an N-type transistor, when a High level (hereinafter referred to as "H level") control signal is supplied from the vertical scanning unit 20, the corresponding transistor is turned on (conductive state). Furthermore, when a low-level (hereinafter, referred to as "L level") control signal is supplied from the vertical scanning unit 20, the corresponding transistor is turned off (non-conductive state).

[0030] Next, the operation of the pixel 12 in the photoelectric conversion device 100 according to the present embodiment will be described with reference to Fig. 2 and Fig. 3. Fig. 3 is a timing chart showing the operation of the pixel in the photoelectric conversion device according to the present embodiment.

[0031] The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and accumulates the generated charge. The transfer transistor M1 functions as a transfer unit that transfers the charge held by the photoelectric conversion unit PD to the floating diffusion unit FD when it is turned on. The floating diffusion unit FD functions as a charge holding unit that holds the charge transferred from the photoelectric conversion unit PD, and becomes a voltage corresponding to the amount of charge transferred from the photoelectric conversion unit PD by charge-voltage conversion using the floating diffusion capacitance. The amplification transistor M3 is configured such that a power supply voltage is supplied to the drain, and a bias current is supplied to the source from a current source (not shown) via the output line 16 and the selection transistor M4, forming an amplification unit (source follower circuit) with the gate as an input node. The selection transistor M4 is a switch that selects the pixel 12, and when it is turned on, it connects the amplification transistor M3 to the output line 16. As a result, the amplification transistor M3 outputs a signal corresponding to the voltage of the floating diffusion unit FD to the output line 16 via the selection transistor M4. When the reset transistor M2 is turned on, it resets the floating diffusion region FD to a voltage corresponding to the power supply voltage.

[0032] Fig. 3 is a timing chart showing the operation of reading out pixel signals from the pixels 12 to the output lines 16. Fig. 3 shows the timing of the control signals PSEL, PRES, and PTX output from the vertical scanning unit 20 to one row, and the output potential VOUT output from the pixels 12 to the output lines 16 of the corresponding columns. In the period before time T1, the control signals PSEL, PRES, and PTX are assumed to be at L level. Also, it is assumed that charges corresponding to the amount of incident light are accumulated in the photoelectric conversion unit PD.

[0033] At time T1, the vertical scanning section 20 controls the control signal PSEL to change from L level to H level, thereby turning on the selection transistor M4 and connecting the source of the amplification transistor M3 to the output line 16 via the selection transistor M4.

[0034] During a predetermined period from the next time T2, the vertical scanning unit 20 controls the control signal PRES to change from L level to H level. This turns on the reset transistor M2, and the floating diffusion region FD is reset to a predetermined potential (reset potential) corresponding to the voltage VDD. This state is the reset state of the pixel 12. As a result, the output potential VOUT of the output line 16 becomes a potential corresponding to the reset potential of the floating diffusion region FD. This potential is held in the sample-and-hold unit 40 as a reset signal (also referred to as an "N signal") during the period until time T3 after the reset transistor M2 turns off and the potential of the output line 16 becomes statically settled.

[0035] During a predetermined period from the next time T3, the vertical scanning unit 20 controls the control signal PTX from L level to H level. This turns on the transfer transistor M1, the charge stored in the photoelectric conversion unit PD is transferred to the floating diffusion unit FD, and the floating diffusion unit FD has a voltage corresponding to the amount of charge transferred from the photoelectric conversion unit. This causes the output potential VOUT of the output line 16 to have a potential corresponding to the amount of charge transferred to the floating diffusion unit FD. This potential is held in the sample-and-hold unit 40 as a light detection signal (also referred to as an "S signal") during the period until time T4 after the transfer transistor M1 is turned off and the potential of the output line 16 is stabilized.

[0036] At the next time T4, the vertical scanning unit 20 controls the control signal PSEL to change from H level to L level, thereby turning off the selection transistor M4 and disconnecting the source of the amplification transistor M3 from the output line 16, and the operation of reading out the pixel signals from the pixels 12 belonging to that row to the output line 16 is completed.

[0037] Next, the sample-and-hold section 40 in the photoelectric conversion device 100 according to the present embodiment will be described with reference to FIGS.

[0038] FIG. 4 illustrates one pixel 12, a column signal processing unit 32, a column sample-and-hold unit 42, and a column AD conversion unit 62, which correspond to one of the multiple columns that make up the pixel array unit 10.

[0039] The column signal processing unit 32 has a current source 34 connected to the output line 16. The amplification transistor M3 of the pixel 12 receives a bias current supplied from the current source 34 and forms a source follower circuit.

[0040] 4, the column sample-and-hold unit 42 has an N signal sample-and-hold circuit 44N, an S signal sample-and-hold circuit 44S, and a resistor R. The N signal sample-and-hold circuit 44N has a node connected to the output line 16 and a node connected to a wiring IL1. The S signal sample-and-hold circuit 44S has a node connected to the output line 16, a node connected to a wiring IL2, and a node connected to a wiring IL3. The N signal sample-and-hold circuit 44N and the S signal sample-and-hold circuit 44S are connected via the wiring IL1, the resistor R, and the wiring IL2. The wiring IL3 is connected to the column AD conversion unit 62.

[0041] The N signal sample-and-hold circuit 44N has a function of acquiring and holding a reset signal output from the pixel 12 via the output line 16. The S signal sample-and-hold circuit 44S has a function of acquiring and holding a photodetection signal output from the pixel 12 via the output line 16. The N signal sample-and-hold circuit 44N is connected to the S signal sample-and-hold circuit 44S via a wiring IL1, a resistor R, and a wiring IL2, and supplies a current based on the held reset signal to the S signal sample-and-hold circuit 44S. The S signal sample-and-hold circuit 44S outputs a current based on the difference between the photodetection signal and the reset signal to the column AD conversion unit 62 via a wiring IL3. This allows correction processing to be performed by correlated double sampling (CDS) of the photodetection signal and the reset signal.

[0042] 5 is a circuit diagram showing a configuration example of an N signal sample-and-hold circuit 44N. As shown in FIG. 5, the N signal sample-and-hold circuit 44N has a capacitive section 46N and an amplifying section 48N.

[0043] The capacitive section 46N is made up of a plurality (N pieces) of unit capacitive sections 50N 1 ,…,50N n ,50N n+1 ,…,50N N (N is an integer of 2 or more, and n is an integer of 1 or more and less than N). 1 ~50N N-1 Each of the unit capacitance parts 50N has a switch S1, a switch S2, and a capacitance C1. N 5, in order to represent the unit capacitance section 50N to which the switch S1, the switch S2, and the capacitance C1 belong, the same consecutive numbers as those of the unit capacitance section 50N are added to these reference numerals. For example, the unit capacitance section 50N 1 The components of the switch S1 1 , switch S2 1 , capacity C1 1 It is written as follows.

[0044] The amplifier unit 48N includes an inverting amplifier 52N, a current source 54N, a transistor M5, and switches S3, S4, and S5. The transistor M5 is a P-type transistor. 1 ~S1 N , switch S2 1 ~S2 N-1 The switches S3, S4 and S5 are controlled to be on or off in response to a control signal supplied from the control unit 90.

[0045] Unit capacity: 50N 1 ~50N N In each of the unit capacitance parts 50N, one terminal of the switch S1 is connected to the output line 16. The other terminal of the switch S1 is connected to one terminal of the capacitance C1. The other terminal of the capacitance C1 is connected to the wiring IL4. 1 ~50N N One terminal of the switch S1 is commonly connected to the output line 16, and the unit capacitance section 50N 1 ~50N N The other terminals of the capacitances C1 are commonly connected to the wiring IL4. 1~50N N is connected in parallel between the output line 16 and the wiring IL4. The wiring IL4 is connected to the unit capacitance portion 50N 1 ~50N N and the amplifier unit 48N.

[0046] Unit capacity: 50N 1 ~50N N-1 The switch S2 of the unit capacitance section 50N is connected between the connection node between the switch S1 and the capacitance C1 of the adjacent unit capacitance section 50N. In other words, if n is an integer from 1 to N-1, n Switch S1 n and capacitance C1 n The connection node between n Through, unit capacity part 50N n+1 Switch S1 n+1 and capacitance C1 n+1 is connected to the connection node between

[0047] The capacitance C1 is a unit capacitance that is a constituent unit of the sampling capacitance that constitutes the N signal sample-and-hold circuit 44N. The multiple switches S1 and multiple switches S2 that constitute the capacitance section 46N constitute a switch circuit for combining the multiple capacitances C1 to constitute the sampling capacitance. The multiple switches S1 have a function of selectively switching the connection state between the output line 16 and the multiple capacitances C1. The multiple switches S2 have a function of selectively switching the connection state between one terminal of the adjacent capacitances C1.

[0048] The wiring IL4 is connected to the input node of the inverting amplifier 52N. The output node of the inverting amplifier 52N is connected to the gate of the transistor M5 via the switch S5. The switch S3 is connected between the input node and the output node of the inverting amplifier 52N. A current source 54N is connected between the power supply voltage node (voltage VDD) and the drain of the transistor M5. The source of the transistor M5 is connected to the ground node (GND). The connection node between the current source 54N and the drain of the transistor M5 is connected to the unit capacitance section 50N via the switch S4. NSwitch S1 N and capacitance C1 N The connection node between the current source 54N and the drain of the transistor M5 is connected to a wiring IL1.

[0049] The amplifier 48N is an amplifier circuit in which an inverting amplifier 52N and a source follower circuit constituted by a current source 54N and a transistor M5 are connected in series. 1 ~C1 N A current according to the voltage held in the line IL1 can be output to the line IL1.

[0050] 6 is a circuit diagram showing an example of the configuration of the S signal sample-and-hold circuit 44 S. As shown in FIG. 6, the S signal sample-and-hold circuit 44 S has a capacitive section 46 S and an amplifying section 48 S.

[0051] The capacitance section 46S is made up of a plurality (N pieces) of unit capacitance sections 50S. 1 ,…,50S n ,50S n+1 ,…,50S N (N is an integer of 2 or more, and n is an integer of 1 or more and less than N). 1 ~50S N-1 Each of the unit capacitance parts 50S has a switch S6, a switch S7, and a capacitance C2. N 6, in order to represent the unit capacitance section 50S to which the switch S6, the switch S7, and the capacitance C2 belong, the same consecutive numbers as those of the unit capacitance section 50S are added to these reference characters. For example, the unit capacitance section 50S 1 The components of the switch S6 1 , switch S7 1 , capacity C2 1 It is written as follows.

[0052] The amplifier unit 48S includes an inverting amplifier 52S, a current source 54S, a transistor M6, and switches S8, S9, and S10. The transistor M6 is a P-type transistor. 1 ~S6N , switch S7 1 ~S7 N-1 The switches S8, S9 and S10 are controlled to be on or off in response to a control signal supplied from the control unit 90.

[0053] Unit capacity 50S 1 ~50S N In each of the unit capacitance parts 50S, one terminal of the switch S6 is connected to the output line 16. The other terminal of the switch S6 is connected to one terminal of the capacitance C2. The other terminal of the capacitance C2 is connected to the wiring IL5. 1 ~50S N One terminal of the switch S6 is commonly connected to the output line 16, and the unit capacitance section 50S 1 ~50S N The other terminals of the capacitors C2 are commonly connected to the wiring IL5. 1 ~50S N is connected in parallel between the output line 16 and the wiring IL5. The wiring IL5 is 1 ~50S N and the amplifier unit 48S.

[0054] Unit capacity 50S 1 ~50S N-1 The switch S2 is connected between the connection node between the switch S6 and the capacitance C2 of the adjacent unit capacitance section 50S. In other words, if n is an integer from 1 to N-1, the unit capacitance section 50S n Switch S6 n and capacity C2 n The connection node between n Through, unit capacity part 50S n+1 Switch S6 n+1 and capacity C2 n+1 is connected to the connection node between

[0055] The capacitor C2 is a unit capacitor that is a constituent unit of the sampling capacitor that constitutes the S signal sample-and-hold circuit 44S. The multiple switches S6 and multiple switches S7 that constitute the capacitance section 46S constitute a switch circuit for combining the multiple capacitors C2 to constitute the sampling capacitor. The multiple switches S6 have a function of selectively switching the connection state between the output line 16 and the multiple capacitors C2. The multiple switches S7 have a function of selectively switching the connection state between one terminal of the adjacent capacitors C2.

[0056] The wiring IL5 is connected to the input node of the inverting amplifier 52S. The output node of the inverting amplifier 52S is connected to the gate of the transistor M6 via a switch S10. The switch S8 is connected between the input node and the output node of the inverting amplifier 52S. A current source 54S is connected between a power supply voltage node (voltage VDD) and the drain of the transistor M6. The source of the transistor M6 is connected to the wiring IL3. The connection node between the current source 54S and the drain of the transistor M6 is connected to the unit capacitance section 50S via a switch S9. N Switch S6 N and capacity C2 N The connection node between the current source 54S and the drain of the transistor M6 is connected to a wiring IL2.

[0057] The amplifier 48S is an amplifier circuit in which an inverting amplifier 52S and a source follower circuit constituted by a current source 54S and a transistor M6 are connected in series. 1 ~C2 N and a current input from the wiring IL2 can be output to the wiring IL3.

[0058] 3 to 6, an outline of the operation of the sample-and-hold unit 40 will be described. During the output period of the reset signal from time T2 to time T3 in FIG. 1 ~S1 N ,S3,S6 n+1~S6 N , S8 are turned on. During this period, the other switches are turned off. Then, switch S1 1 ~S1 N ,S3,S6 n+1 ~S6 N , S8 are turned off. These operations cause the capacitance C1 1 ~C1 N ,C2 n+1 ~C2 N A voltage based on the reset signal is held in the

[0059] After that, during the output period of the photoelectric conversion signal from time T3 to time T4 in FIG. 1 ~S2 N―1 ,S4,S5,S6 1 ~S6 n , S8 are turned on. During this period, the other switches are turned off. This operation reduces the capacitance C1 1 ~C1 N are connected in parallel, and the N signal sample-and-hold circuit 44N has a capacitance C1 1 ~C1 N Then, the switch S6 outputs a current to the wiring IL1 according to the voltage held in the 1 ~S6 n , S8 is turned off. These operations cause the capacitance C2 1 ~C2 n A voltage based on a photoelectric conversion signal is held in the pixel.

[0060] Then switch S2 1 ~S2 N―1 ,S4,S5,S7 1 ~S7 N―1 , S9, and S10 are turned on. The other switches are turned off. This operation reduces the capacitance C2 1 ~C2 N are connected in parallel, and the S signal sample-and-hold circuit 44S has a capacitance C2 1 ~C2 N IL2 and a current corresponding to the difference between the voltage held in the line IL1 and the current input from the line IL2.

[0061] By the above operation, a current signal that has been corrected by correlated double sampling of the photoelectric conversion signal and the reset signal can be output to the wiring IL3. 1 ~C2 n The photoelectric conversion signal stored in the Nn capacitors C2 n+1 ~C2 N The reset signal held in the column is weighted and averaged according to the number of capacitors. This attenuates the voltage difference between the reset signal and the photoelectric conversion signal by a factor of n / N. This makes it possible to expand the voltage range of the input signal in the column circuit.

[0062] FIG. 7 is a block diagram showing a configuration example of the column AD conversion unit 62 in the photoelectric conversion device according to this embodiment. The column AD conversion unit 62 illustrated in this embodiment is a delta-sigma type AD conversion circuit, but is not limited to this. For example, the column AD conversion unit 62 may be an AD conversion circuit of a type that compares a ramp signal with an input voltage and measures the time until the magnitude relationship is inverted using a counter. The column AD conversion unit 62 may also be a successive approximation type AD conversion circuit that obtains a digital value close to the input voltage by repeatedly comparing the output voltage of the DA conversion circuit with the input voltage. In this embodiment, a 1-bit AD conversion circuit is illustrated, but in reality, AD conversion of a number of bits greater than this may be performed.

[0063] 7, the column AD conversion unit 62 includes digital-to-analog conversion circuits (DA conversion circuits) 64a and 64b, capacitances Ca and Cb, a voltage-to-current conversion unit 66, a quantizer 68, a decimation filter DF, and buffers B1 and B2. As described above, the column AD conversion unit 62 receives the current signal processed by correlated double sampling from the column sample-and-hold unit 42 via the wiring IL3.

[0064] The wiring IL3 is connected to the output terminal of the DA conversion circuit 64a, the first terminal of the capacitance Ca, and the input terminal of the voltage-current conversion unit 66. The output terminal of the voltage-current conversion unit 66 is connected to the output terminal of the DA conversion circuit 64b, the first terminal of the capacitance Cb, and the input terminal of the quantizer 68. The output terminal of the quantizer 68 is connected to the input terminal of the decimation filter DF and the input terminal of the buffer B1. The output terminal of the buffer B1 is connected to the input terminal of the DA conversion circuit 64b and the input terminal of the buffer B2. The output terminal of the buffer B2 is connected to the input terminal of the DA conversion circuit 64a. The ground terminals of the DA conversion circuits 64a and 64b, the second terminals of the capacitances Ca and Cb, the ground terminal of the voltage-current conversion unit 66, the ground terminal of the quantizer 68, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3. The output terminal of the decimation filter DF is the output terminal of the column AD conversion unit 62.

[0065] Charge is accumulated in the capacitance Ca according to the amount of current flowing through the wiring IL3 and the passage of time. The voltage-current converter 66 outputs a current signal according to the potential of the first terminal of the capacitance Ca from the output terminal. In this way, the capacitance Ca functions as an integrator.

[0066] Charge is accumulated in the capacitance Cb according to the amount of current output from the voltage-current converter 66 and the passage of time. In this way, the capacitance Cb and the voltage-current converter 66 also function as an integrator. The quantizer 68 may be a comparison circuit. The quantizer 68 compares the potential of the first terminal of the capacitance Cb with a threshold value and outputs the comparison result. In this way, the quantizer 68 performs 1-bit analog-to-digital conversion. The quantizer 68 performs oversampling at a frequency higher than a desired sampling frequency.

[0067] The digital signal output from the quantizer 68 is input to the buffer B1. This digital signal is fed back to the DA conversion circuits 64a and 64b via the buffers B1 and B2. The DA conversion circuits 64a and 64b include a current source, a switch, and the like. The DA conversion circuit 64a performs digital-to-analog conversion to pass a current corresponding to the input digital signal, thereby extracting a charge corresponding to the digital signal from the first terminal of the capacitance Ca and passing it to the ground wiring GL3. Similarly, the DA conversion circuit 64b extracts a charge of an amount corresponding to the input digital signal from the first terminal of the capacitance Cb and passes it to the ground wiring GL3. In this way, the digital signal output from the quantizer 68 is fed back to the integrator or the input side of the quantizer 68. This feedback loop operates to reduce quantization errors in the low-frequency range.

[0068] 7, the column AD conversion unit 62 of this embodiment is likely to have a circuit arrangement extending in one direction, so the feedback wiring may be long. The provision of the buffers B1 and B2 reduces the effects of voltage drop and the like caused by the long feedback wiring. However, if the effects of the feedback wiring are tolerable, the buffers B1 and B2 do not need to be provided.

[0069] The decimation filter DF performs processing to lower the sampling frequency by thinning out the signal output from the quantizer 68. This removes noise in the high frequency range.

[0070] As described above, the column AD conversion unit 62 of this embodiment employs a delta-sigma type suitable for achieving high accuracy and high resolution, thereby making it possible to output a highly accurate digital signal.

[0071] Here, when focusing on the accuracy of the correction process by correlated double sampling of the photoelectric conversion signal and the reset signal, it is preferable that the circuit characteristics of the N signal sample-and-hold circuit 44N and the S signal sample-and-hold circuit 44S are as close as possible. Therefore, it is preferable that the N signal sample-and-hold circuit 44N and the S signal sample-and-hold circuit 44S have the same configuration. Having the same configuration may include having the same circuit configuration, and having the same structure and arrangement of each element. Having the same circuit configuration may include having the same number of unit capacitance parts 50N (capacitors C1) and the same number of unit capacitance parts 50S (capacitors C2).

[0072] Fig. 8 is a diagram showing an example layout of the arrangement of each unit and wiring in the column sample-and-hold unit 42. In the coordinate system shown in Fig. 8, the X direction corresponds to the row direction (horizontal direction), and the Y direction corresponds to the column direction (vertical direction).

[0073] As shown in FIG. 8, the N signal sample-and-hold circuit 44N and the S signal sample-and-hold circuit 44S are arranged side by side along the Y direction (column direction). In the N signal sample-and-hold circuit 44N, the capacitive section 46N and the amplifying section 48N are arranged side by side along the column direction. Similarly, in the S signal sample-and-hold circuit 44N, the capacitive section 46S and the amplifying section 48S are arranged side by side along the column direction. Looking at the column sample-and-hold section 42 as a whole, the capacitive section 46N, the amplifying section 48N, the capacitive section 46S, and the amplifying section 48N are arranged side by side along the column direction in this order. By arranging the circuit elements of the column sample-and-hold section 42 in this manner, the width of the column circuit can be narrowed and the arrangement density of the column circuit along the X direction can be increased.

[0074] In the layout example of FIG. 8, the output line 16 and the unit capacitance portion 50N 1 ~50N N and unit capacity part 50S 1 ~50S N A wiring IL6 is provided at the connection portion of the unit capacitance portion 50N so as to extend along the Y direction as a part of the output line 16.1 ~50N N and unit capacity part 50S 1 ~50S N In other words, the output line 16 is connected to the unit capacitance section 50N via the wiring IL6. 1 ~50N N and unit capacity part 50S 1 ~50S N is connected to

[0075] By configuring the connection between the output line 16 and the column sample-and-hold unit 42 in this manner, the length of the electrical path connecting the pixel 12 and the capacitance unit 46N can be made closer to the length of the electrical path connecting the pixel 12 and the capacitance unit 46S. This reduces the difference between the parasitic resistance and parasitic capacitance of the wiring between the pixel 12 and the capacitance unit 46N and the parasitic resistance and parasitic capacitance of the wiring between the pixel 12 and the capacitance unit 46S, and improves the accuracy of the correction process using correlated double sampling.

[0076] Fig. 9 shows a layout example of the arrangement of switches S1, S2 and capacitance C1 in a unit capacitance section 50N, and a layout example of the arrangement of switches S6, S7 and capacitance C2 in a unit capacitance section 50S. Fig. 9(a) and Fig. 9(c) show the layout of the arrangement of switches S1, S2 and capacitance C1 in a unit capacitance section 50N, and Fig. 9(b) and Fig. 9(d) show the layout of the arrangement of switches S6, S7 and capacitance C2 in a unit capacitance section 50S. In the coordinate system shown in Fig. 9, the X direction corresponds to the row direction (horizontal direction), and the Y direction corresponds to the column direction (vertical direction).

[0077] The switches S1, S2 and the capacitance C1 of the unit capacitance section 50N can be arranged side by side in the X direction, for example, as shown in FIG. 9(a). In this case, it is preferable that the switches S6, S7 and the capacitance C2 of the unit capacitance section 50S are arranged side by side in the X direction, similar to the switches S1, S2 and the capacitance C1 of the unit capacitance section 50N, for example, as shown in FIG. 9(b). Alternatively, the switches S1, S2 and the capacitance C1 of the unit capacitance section 50N can be arranged side by side in the Y direction, for example, as shown in FIG. 9(c). In this case, it is preferable that the switches S6, S7 and the capacitance C2 of the unit capacitance section 50S are arranged side by side in the Y direction, similar to the switches S1, S2 and the capacitance C1 of the unit capacitance section 50N, for example, as shown in FIG. 9(d).

[0078] Although the arrangement of the two switches and one capacitance constituting the unit capacitance parts 50N and 50S is not limited to this, it is preferable that the layout of the unit capacitance part 50N is the same as that of the unit capacitance part 50S. By configuring in this way, it is possible to reduce variations in element size that occur during manufacturing due to differences in layout. This reduces the variation in characteristics between the capacitance parts 46N and 46S, and improves the accuracy of the correction process by correlated double sampling.

[0079] 10 shows a specific example of a planar layout on a semiconductor substrate when the switches S1, S2 and the capacitance C1 of the unit capacitance section 50N are arranged in the X direction. n-1 ~50N n+1 Here, the unit capacitive section 50N will be described as an example, but the same applies to the case where the switches S6, S7 and the capacitor C2 of the unit capacitive section 50S are arranged side by side in the X direction.

[0080] For the sake of simplicity, only the pattern of the active region defined in the semiconductor substrate, the pattern of the gate layer constituting the gate electrode of the transistor and the electrode of the capacitor, and the first metal wiring layer are shown in Fig. 10. The rectangular area marked with an x ​​indicates a contact portion that connects the first metal wiring layer to the active region or the capacitor electrode.

[0081] An active region 112 in which a transistor constituting the switch S1 is provided, an active region 114 in which a transistor constituting the switch S2 is provided, and an active region 116 in which a capacitance C1 is provided are defined in the semiconductor substrate 110. The active regions 112, 114, and 116 are arranged side by side along the X direction.

[0082] A gate electrode 122 of a transistor constituting switch S1 is provided on active region 112 via a gate insulating film (not shown). A gate electrode 124 of a transistor constituting switch S2 is provided on active region 114 via a gate insulating film (not shown). Gate electrodes 122 and 124 are arranged to extend along the X direction. A capacitor electrode 126 is provided on active region 116 via a capacitor insulating film (not shown).

[0083] A wiring IL6 is connected to one of the main nodes (source or drain) of the transistor constituting the switch S1. The other main node (drain or source) of the transistor constituting the switch S1 is connected to one of the main nodes (source or drain) of the transistor constituting the switch S2 and a capacitor electrode 126 via a wiring 128. The wiring 128 is also connected to the other main node (drain or source) of the transistor constituting the switch S2 of the adjacent unit capacitance portion 50N. A wiring IL4 is connected to the active region 116 constituting the lower electrode of the capacitance C1.

[0084] Unit capacity: 50N n-1 ~50N n+1 The switches S1, S2, and the capacitors C1 are arranged in line along the Y direction. The wiring IL6 is arranged to extend along the Y direction. n-1 ~50N n+1 The wiring IL4 is arranged to extend along the Y direction, and is connected to one of the main nodes of the transistors constituting the switch S1 of the unit capacitance portion 50N. n-1 ~50Nn+1 These are commonly connected to the lower electrodes (active regions 116) of the capacitors C1.

[0085] Although not shown, the unit capacitance portion 50S n-1 ~50S n+1 The switches S6, S7, and the capacitors C2 are also arranged in line along the Y direction. The wiring IL6 is arranged to extend along the Y direction, and the unit capacitance section 50S n-1 ~50S n+1 Switch S 6 The wiring IL5 is arranged to extend along the Y direction, and is connected in common to one of the main nodes of the transistors constituting the unit capacitance portion 50S. n-1 ~50S n+1 Capacity C 2 are commonly connected to the bottom electrodes (active regions 116).

[0086] Unit capacity: 50N n-1 ~50N n+1 The switch S1 and the unit capacitance section 50S n-1 ~50S n+1 The switches S6 are arranged in a line along the Y direction. n-1 ~50N n+1 The switch S2 and the unit capacitance section 50S n-1 ~50S n+1 The switches S7 are arranged in a line along the Y direction. n-1 ~50N n+1 Capacity C1 and unit capacity part 50S n-1 ~50S n+1 The capacitors C2 are arranged in a line along the Y direction.

[0087] 11 shows a specific example of a planar layout on a semiconductor substrate when the switches S1, S2 and the capacitance C1 of the unit capacitance section 50N are arranged in the Y direction. n-1 ~50N n+1Here, the unit capacitive section 50N will be described as an example, but the same applies to the case where the switches S6, S7 and the capacitor C2 of the unit capacitive section 50S are arranged side by side in the Y direction.

[0088] For the sake of simplicity, only the pattern of the active region defined in the semiconductor substrate, the pattern of the gate layer constituting the gate electrode of the transistor and the electrode of the capacitor, and the first metal wiring layer are shown in Fig. 11. The rectangular area marked with an x ​​indicates a contact portion that connects the first metal wiring layer to the active region or the capacitor electrode.

[0089] An active region 112 in which a transistor constituting the switch S1 is provided, an active region 114 in which a transistor constituting the switch S2 is provided, and an active region 116 in which a capacitor C2 is provided are defined in the semiconductor substrate 110. The active regions 112, 116, and 114 are arranged side by side along the Y direction.

[0090] A gate electrode 122 of a transistor constituting switch S1 is provided on active region 112 via a gate insulating film (not shown). A gate electrode 124 of a transistor constituting switch S2 is provided on active region 114 via a gate insulating film (not shown). Gate electrodes 122 and 124 are arranged to extend along the Y direction. A capacitor electrode 126 is provided on active region 116 via a capacitor insulating film (not shown).

[0091] One of the main nodes (source or drain) of the transistor constituting the switch S1 is Wiring IL6 is connected to the active region 116 that constitutes the lower electrode of the capacitance C1. The other main node (drain or source) of the transistor that constitutes the switch S1 is connected to one main node (source or drain) of the transistor that constitutes the switch S2 and the capacitor electrode 126 via a wiring 128. The wiring 128 is also connected to the other main node (drain or source) of the transistor that constitutes the switch S2 of the adjacent unit capacitance portion 50N. A wiring IL4 is connected to the active region 116 that constitutes the lower electrode of the capacitance C1.

[0092] As shown in FIGS. 10 and 11, the switches S1, S2 and capacitances C1 of the unit capacitive portions 50Nn-1 to 50Nn+1 are arranged side by side in the Y direction. Wiring IL6 are arranged to extend along the Y direction and are commonly connected to one main node of the transistor constituting the switch S1 of the unit capacitance parts 50Nn-1 to 50Nn+1. The wiring IL4 is arranged to extend along the Y direction and is commonly connected to the lower electrodes (active regions 116) of the capacitors C1 of the unit capacitance parts 50Nn-1 to 50Nn+1.

[0093] Although not shown, the unit capacitance portion 50S n-1 ~50S n+1 The switches S6, S7, and the capacitors C2 are also arranged in line along the Y direction. The wiring IL6 is arranged to extend along the Y direction, and the unit capacitance section 50S n-1 ~50S n+1 The wiring IL5 is arranged to extend along the Y direction, and is connected to one of the main nodes of the transistors constituting the switch S6 of the unit capacitance portion 50S. n-1 ~50S n+1 These are commonly connected to the lower electrodes (active regions 116) of the capacitors C2.

[0094] That is, the unit capacitance portion 50N n-1 ~50N n+1 The switch S1 and the unit capacitance section 50S n-1 ~50S n+1 The switches S6 are arranged in a line along the Y direction. n-1 ~50N n+1 The switch S2 and the unit capacitance section 50S n-1 ~50S n+1 The switches S7 are arranged in a line along the Y direction. n-1 ~50N n+1 Capacity C1 and unit capacity part 50S n-1 ~50S n+1 The capacitors C2 are arranged in a line along the Y direction.

[0095] By configuring the column sample-and-hold unit 42 in this manner, each circuit element can be arranged efficiently, and the area efficiency of the column sample-and-hold unit 42 can be improved.

[0096] As described above, according to this embodiment, it is possible to reduce the characteristic variation between the elements constituting the N signal sample-and-hold circuit 44N and the elements constituting the S signal sample-and-hold circuit 44S, and to improve the accuracy of the correction process using correlated double sampling.

[0097] [Second embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Fig. 12. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 12 is a diagram showing an example of the layout of the arrangement of column sample-and-hold units in the photoelectric conversion device according to this embodiment.

[0098] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment, except for the layout of each unit in the column sample-and-hold unit 42. That is, in the photoelectric conversion device according to the first embodiment, the capacitive unit 46N, the amplifying unit 48N, the capacitive unit 46S, and the amplifying unit 48S are arranged in this order along the column direction. In contrast, in the photoelectric conversion device according to this embodiment, as shown in FIG. 12, the amplifying unit 48N, the capacitive unit 46N, the capacitive unit 46S, and the amplifying unit 48S are arranged in this order along the column direction.

[0099] By arranging the capacitive units 46N and 46S and the amplifying units 48N and 48S in this manner, the capacitive unit 46N and the capacitive unit 46S can be arranged adjacent to each other. Here, the capacitive unit 46N and the capacitive unit 46S being adjacent to each other means that no other circuit elements (e.g., the amplifying units 48N and 48S) are arranged between the capacitive unit 46N and the capacitive unit 46S. This can reduce the variation in characteristics between the capacitive unit 46N and the capacitive unit 46S caused by in-plane variations in element size, layout, etc. during manufacturing. In addition, when disturbances such as crosstalk and heat are received, the influence is equally received by the capacitive units 46N and 46S, so that the variation in characteristic fluctuations between the capacitive unit 46N and the capacitive unit 46S caused by the disturbances can be reduced. This can improve the accuracy of the correction process by correlated double sampling.

[0100] In addition, the capacitive section 46N and the amplifying section 48N, and the capacitive section 46S and the amplifying section 48S are arranged symmetrically with respect to the center line between the capacitive section 46N and the capacitive section 46S. This further enhances the structural symmetry of each circuit element with respect to this center line. This reduces the difference between the parasitic resistance and parasitic capacitance of the wiring connecting the pixel 12 and the capacitive section 46N and the parasitic resistance and parasitic capacitance of the wiring connecting the pixel 12 and the capacitive section 46S, and further improves the accuracy of the correction process by correlated double sampling.

[0101] Therefore, according to the above-described configuration of this embodiment, it is possible to reduce the characteristic variation between the elements constituting the N signal sample-and-hold circuit 44N and the elements constituting the S signal sample-and-hold circuit 44S, and to improve the accuracy of the correction process using correlated double sampling.

[0102] [Third embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Fig. 13. Components similar to those in the photoelectric conversion devices according to the first and second embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 13 is a diagram showing an example of the layout of the arrangement of column sample-and-hold units in the photoelectric conversion device according to this embodiment.

[0103] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment, except for the layout of each unit in the column sample-and-hold unit 42. That is, in the photoelectric conversion device according to the first embodiment, the capacitive unit 46N, the amplifying unit 48N, the capacitive unit 46S, and the amplifying unit 48S are arranged in this order along the column direction. In contrast, in the photoelectric conversion device according to this embodiment, as shown in FIG. 13, the capacitive unit 46N, the capacitive unit 46S, the amplifying unit 48N, and the amplifying unit 48S are arranged in this order along the column direction.

[0104] By arranging the capacitive units 46N, 46S and the amplifying units 48N, 48S in this manner, the capacitive unit 46N and the capacitive unit 46S can be arranged adjacent to each other. This makes it possible to reduce the variation in characteristics between the capacitive units 46N and 46S caused by in-plane variations in element size, layout, and the like during manufacturing. Furthermore, when disturbances such as crosstalk and heat are experienced, the effects are equally felt by the capacitive units 46N and 46S, so that it is possible to reduce the variation in characteristic fluctuations between the capacitive units 46N and 46S caused by the disturbances.

[0105] Similarly, the amplifier unit 48N and the amplifier unit 48S can be arranged adjacent to each other. Here, the amplifier unit 48N and the amplifier unit 48S being adjacent to each other means that no other circuit elements (e.g., the capacitance units 46N and 46S) are arranged between the amplifier unit 48N and the amplifier unit 48S. This can reduce the variation in characteristics between the amplifier unit 48N and the amplifier unit 48S caused by in-plane variations in element size, layout, and the like during manufacturing. In addition, when disturbances such as crosstalk and heat are experienced, the amplifier units 48N and 48S are equally affected, so that the variation in characteristics fluctuations between the amplifier unit 48N and the amplifier unit 48S caused by the disturbances can be reduced.

[0106] Furthermore, by arranging the amplifier units 48N and 48S adjacent to each other, the wiring IL1 connecting the amplifier unit 48N and the resistor R and the wiring IL2 connecting the amplifier unit 48S and the resistor R are shortened, thereby improving the symmetry of the wiring on the output side of the amplifier units 48N and 48S.

[0107] Therefore, according to the above-described configuration of this embodiment, it is possible to reduce the characteristic variation between the elements constituting the N signal sample-and-hold circuit 44N and the elements constituting the S signal sample-and-hold circuit 44S, and to improve the accuracy of the correction process using correlated double sampling.

[0108] In this embodiment, the amplifier units 48N, 48S are arranged downstream of the capacitive units 46N, 46S (lower side in FIG. 13), but the amplifier units 48N, 48S may be arranged upstream of the capacitive units 46N, 46S (upper side in FIG. 13). That is, the amplifier unit 48N, the amplifier unit 48S, the capacitive unit 46N, and the capacitive unit 46S may be arranged in this order along the column direction.

[0109] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Fig. 14. Components similar to those in the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 14 is a diagram showing an example of the layout of the arrangement of column sample-and-hold units in the photoelectric conversion device according to this embodiment.

[0110] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment, except for the layout of each unit in the column sample-and-hold unit 42. That is, in the photoelectric conversion device according to the first embodiment, the capacitive unit 46N, the amplifying unit 48N, the capacitive unit 46S, and the amplifying unit 48S are arranged in this order along the column direction. In contrast, in the photoelectric conversion device according to this embodiment, as shown in FIG. 14, the capacitive unit 46N, the amplifying unit 48N, the amplifying unit 48S, and the capacitive unit 46S are arranged in this order along the column direction.

[0111] By arranging the capacitive sections 46N, 46S and the amplifying sections 48N, 48S in this manner, the amplifying section 48N and the amplifying section 48S can be arranged adjacent to each other. This makes it possible to reduce the variation in characteristics between the amplifying section 48N and the amplifying section 48S caused by in-plane variations in element size, layout, and the like during manufacturing. Furthermore, when disturbances such as crosstalk or heat are experienced, the effects are equally felt by the amplifying sections 48N, 48S, so that it is possible to reduce the variation in characteristic fluctuations between the amplifying sections 48N and 48S caused by the disturbances.

[0112] Furthermore, by arranging the amplifier units 48N and 48S adjacent to each other, the wiring IL1 connecting the amplifier unit 48N and the resistor R and the wiring IL2 connecting the amplifier unit 48S and the resistor R are shortened, thereby improving the symmetry of the wiring on the output side of the amplifier units 48N and 48S.

[0113] Therefore, according to the above-described configuration of this embodiment, it is possible to reduce the characteristic variation between the elements constituting the N signal sample-and-hold circuit 44N and the elements constituting the S signal sample-and-hold circuit 44S, and to improve the accuracy of the correction process using correlated double sampling.

[0114] [Fifth embodiment] A photoelectric conversion device according to a fifth embodiment of the present invention will be described with reference to Figs. 15 to 18. Components similar to those in the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 15 is a diagram showing a layout example of the arrangement of column sample-and-hold units in the photoelectric conversion device according to this embodiment. Figs. 16 to 18 are diagrams showing a layout example of the arrangement of unit capacitance units 50 in the photoelectric conversion device according to this embodiment.

[0115] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment, except for the layout of each unit in the column sample-and-hold unit 42. That is, in the photoelectric conversion device according to the first embodiment, the capacitive unit 46N, the amplifying unit 48N, the capacitive unit 46S, and the amplifying unit 48S are arranged in this order along the column direction. In contrast, in the photoelectric conversion device according to this embodiment, as shown in FIG. 15, the capacitive unit 46, the amplifying unit 48N, and the amplifying unit 48S are arranged in this order along the column direction.

[0116] The capacitive section 46 is made up of a plurality of (N) unit capacitive sections 50 arranged in the Y direction (column direction). 1 ~50 N The plurality of unit capacitance parts 50 1 ~50 N As shown in FIG. 16, each of the unit capacitive sections 501 to 50N has a unit capacitive section 50N and a unit capacitive section 50S. The unit capacitive section 50N and the unit capacitive section 50S are similar to the unit capacitive sections 50N and 50S in the first to fourth embodiments. The switch S2 is provided between the connection node between the switch S1 and the capacitance C1 of the unit capacitive section 50N adjacent to each other across the unit capacitive section 50S. The switch S7 is provided between the connection node between the switch S6 and the capacitance C2 of the unit capacitive section 50S adjacent to each other across the unit capacitive section 50N. By arranging the unit capacitive sections 501 to 50N configured in this manner in the column direction, the unit capacitive section 50N and the unit capacitive section 50 The unit capacitive sections 50N and 50S are arranged alternately adjacent to each other along the Y direction (column direction). Here, the unit capacitive section 50N and the unit capacitive section 50S are adjacent to each other, meaning that no other circuit elements are arranged between the unit capacitive section 50N and the unit capacitive section S.

[0117] By arranging a plurality of unit capacitive sections 50 each including a unit capacitive section 50N, 50S to configure the capacitive section 46, the arrangement interval between the unit capacitive section 50N and the unit capacitive section 50S can be narrowed compared to the case where the capacitive section 46N and the capacitive section 46S are configured separately. This makes it possible to reduce the characteristic variation (e.g., capacitance error) between the unit capacitive section 50N and the unit capacitive section 50S caused by the in-plane variation of the element size, layout, etc. during manufacturing. In addition, when disturbance such as crosstalk or heat is received, even if the disturbance is local, the unit capacitive sections 50N, 50S are equally affected, so that the variation in the characteristic fluctuation between the unit capacitive section 50N and the unit capacitive section 50S caused by the disturbance can be reduced.

[0118] Moreover, from the viewpoint of reducing variations in element size due to layout (for example, the influence of the microloading effect when patterning the gate layer), it is desirable to design the unit capacitive portion 50N and the unit capacitive portion 50S with the same layout. From this viewpoint, it is advisable to arrange an element constituting the switch S2 and an element constituting the switch S7 in each of the unit capacitive portion 50N and the unit capacitive portion 50S. By configuring in this manner, the layout of the unit capacitive portion 50N and the layout of the unit capacitive portion 50S become the same, and it is possible to reduce characteristic variations due to the layout.

[0119] Switches S2 and S7 that are not necessary for configuring the circuits in Figures 5 and 6 are dummy switches, and should not be connected to other elements by the first metal wiring layer or the like. Figure 17 shows an example in which switch S7 arranged in unit capacitance section 50N and switch S2 arranged in unit capacitance section 50S are dummy switches. Figure 18 shows an example in which switches S2 and S7 arranged in unit capacitance section 50S are dummy switches. In Figures 17 and 18, the dummy switches are indicated by dotted lines.

[0120] Each of the switches S2 and S7 as dummy switches may be arranged in either the unit capacitance section 50N or the unit capacitance section 50S, and the arrangement of the dummy switches is not limited to the examples in Figures 17 and 18. That is, the dummy switch of switch S2 may be arranged in the unit capacitance section 50N, and the dummy switch of switch S7 may be arranged in the unit capacitance section 50S. Alternatively, the dummy switches of switches S2 and S7 may be arranged in the unit capacitance section 50N.

[0121] Therefore, according to the above-described configuration of this embodiment, it is possible to further reduce the characteristic variation between the elements constituting the N signal sample-and-hold circuit 44N and the elements constituting the S signal sample-and-hold circuit 44S, and to improve the accuracy of the correction process using correlated double sampling.

[0122] The layout of the switches S1, S2 and the capacitance C1 in the unit capacitance section 50N and the layout of the switches S6, S7 and the capacitance C2 in the unit capacitance section 50S are not limited to the arrangement in Fig. 16. The switches S1, S2, S6, S7 and the capacitances C1, C2 may be arranged side by side in the X direction as shown in Fig. 16, or may be arranged side by side in the Y direction as shown in Fig. 9(c) and Fig. 9(d). Alternatively, other arrangements are also possible.

[0123] 16 shows the unit capacitive section 50 including one unit capacitive section 50N and one unit capacitive section 50S, the unit capacitive section 50 may include a plurality of unit capacitive sections 50N and a plurality of unit capacitive sections 50S. For example, the unit capacitive section 50 may be configured with a unit capacitive section 50N, a unit capacitive section 50N, a unit capacitive section 50S, and a unit capacitive section 50S aligned in this order along the column direction, forming a capacitive section 46 in which two unit capacitive sections 50N and 50S are alternately arranged.

[0124] [Sixth embodiment] An imaging system according to a sixth embodiment of the present invention will be described with reference to Fig. 19. Fig. 19 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0125] The photoelectric conversion device 100 described in the first to fifth embodiments is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the imaging system. FIG. 19 illustrates a block diagram of a digital still camera as an example of these.

[0126] 19 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments, and converts the optical image formed by the lens 202 into image data.

[0127] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

[0128] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the imaging system 200, or may be removable.

[0129] Furthermore, the imaging system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0130] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0131] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to fifth embodiments is applied.

[0132] [Seventh embodiment] An imaging system and a moving object according to a seventh embodiment of the present invention will be described with reference to Fig. 20. Fig. 20 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0133] Fig. 20(a) shows an example of an imaging system related to a vehicle-mounted camera. The imaging system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, Imaging device 310 The imaging system 300 has a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the above. The imaging system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information on the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of collision using any of these pieces of distance information. The distance information acquisition means may be realized by dedicated hardware or may be realized by a software module. Also, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated circuit), or the like, or may be realized by a combination of these.

[0134] The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0135] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 20(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). A vehicle information acquisition device 320 sends instructions to the imaging system 300 or imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0136] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to devices that use object recognition widely, such as intelligent transport systems (ITS).

[0137] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0138] 2 is an example and can be modified as appropriate. For example, a charge holding section may be provided in addition to the floating diffusion section FD to provide a pixel configuration capable of performing a global electronic shutter operation.

[0139] Furthermore, the imaging systems shown in the sixth and seventh embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 19 and 20.

[0140] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0141] C1,C2…capacity IL1,IL2,IL3,IL4,IL5,IL6...Wiring S1, S2, S6, S7...Switches 10...Pixel array section 12…pixels 16…Output line 40…Sample-hold section 42…Column sample-and-hold section 44N...N signal sample-and-hold circuit 44S...S signal sample-and-hold circuit 46,46N,46S…capacity part 48N, 48S…Amplification section 50, 50N, 50S...Unit capacity 60…AD conversion section 70…Digital memory section 80...Horizontal scanning section 90...Control unit 100...Photoelectric conversion device 200,300...imaging system

Claims

1. A photoelectric conversion device comprising: a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns; a plurality of output lines provided corresponding to the plurality of columns, through which first and second signals are output from the pixels; and a plurality of column circuits provided corresponding to the plurality of output lines, each of the plurality of column circuits has a sample-and-hold unit including a first sample-and-hold circuit that holds the first signal and a second sample-and-hold circuit that holds the second signal; each of the first sample-and-hold circuit and the second sample-and-hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors; the switch circuit includes a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitors, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitors; second electrodes of the plurality of unit capacitors of the first sample-and-hold circuit are connected to each other by a first wiring, and second electrodes of the plurality of unit capacitors of the second sample-and-hold circuit are connected to each other by a second wiring; the second switches constituting the switch circuits of the first sample-and-hold circuit and the second sample-and-hold circuit are arranged along a first direction parallel to the columns, the first wiring and the second wiring extend along the first direction, a first capacitance section including the switch circuit and the plurality of unit capacitances of the first sample-and-hold circuit, and a second capacitance section including the switch circuit and the plurality of unit capacitances of the second sample-and-hold circuit are arranged along the first direction, the first sample-and-hold circuit further includes a first amplifier section connected to the first wiring; the second sample-and-hold circuit further includes a second amplifier section connected to the second wiring; The first capacitance section, the second capacitance section, the first amplification section, and the second amplification section are arranged along the first direction. A photoelectric conversion device comprising:

2. A photoelectric conversion device having a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns, a plurality of output lines corresponding to the plurality of columns and through which a first signal and a second signal are output from the pixels, and a plurality of column circuits corresponding to the plurality of output lines, each of the plurality of column circuits has a sample-and-hold unit including a first sample-and-hold circuit that holds the first signal and a second sample-and-hold circuit that holds the second signal; each of the first sample-and-hold circuit and the second sample-and-hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors; the switch circuit includes a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitors, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitors; second electrodes of the plurality of unit capacitors of the first sample-and-hold circuit are connected to each other by a first wiring, and second electrodes of the plurality of unit capacitors of the second sample-and-hold circuit are connected to each other by a second wiring; the second switches constituting the switch circuits of the first sample-and-hold circuit and the second sample-and-hold circuit are arranged along a first direction parallel to the columns, the first wiring and the second wiring extend along the first direction, a first capacitance section including the switch circuit and the plurality of unit capacitances of the first sample-and-hold circuit, and a second capacitance section including the switch circuit and the plurality of unit capacitances of the second sample-and-hold circuit are arranged along the first direction, the first sample-and-hold circuit further includes a first amplifier section connected to the first wiring; the second sample-and-hold circuit further includes a second amplifier section connected to the second wiring; the first capacitance unit, the second capacitance unit, the first amplification unit, and the second amplification unit are arranged along the first direction, The first amplifying section and the second amplifying section are adjacent to each other, or the first capacitive section and the second capacitive section are adjacent to each other. A photoelectric conversion device comprising:

3. The first amplifying section and the second amplifying section are adjacent to each other, and the first capacitance section and the second capacitance section are adjacent to each other.

3. The photoelectric conversion device according to claim 2.

4. In each of the first sample-and-hold circuit and the second sample-and-hold circuit, the plurality of unit capacitors are arranged adjacent to each other along the first direction.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

5. In each of the first sample-and-hold circuit and the second sample-and-hold circuit, a plurality of unit capacitance parts each including the first switch, the second switch, and the unit capacitance are arranged adjacent to each other along the first direction.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

6. At least one of the first amplifying section and the second amplifying section is disposed between the first capacitive section and the second capacitive section.

6. The photoelectric conversion device according to claim 1,

7. A photoelectric conversion device comprising: a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns; a plurality of output lines provided corresponding to the plurality of columns, through which first and second signals are output from the pixels; and a plurality of column circuits provided corresponding to the plurality of output lines, each of the plurality of column circuits has a sample-and-hold unit including a first sample-and-hold circuit that holds the first signal and a second sample-and-hold circuit that holds the second signal; each of the first sample-and-hold circuit and the second sample-and-hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors; the switch circuit includes a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitors, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitors; the unit capacitors of the first sample-and-hold circuit and the unit capacitors of the second sample-and-hold circuit are alternately arranged adjacent to each other along a first direction parallel to the plurality of columns; the first sample-and-hold circuit further includes a first amplifier connected to a first wiring that connects the second electrodes of the plurality of unit capacitors to each other; the second sample-and-hold circuit further includes a second amplifier connected to a second wiring that connects the second electrodes of the plurality of unit capacitors to each other; The plurality of unit capacitors of the first sample-and-hold circuit, the plurality of unit capacitors of the second sample-and-hold circuit, the first amplifier section, and the second amplifier section are arranged along the first direction. A photoelectric conversion device comprising:

8. A photoelectric conversion device having a pixel array section in which a plurality of pixels, each having a photoelectric conversion section, are arranged in a plurality of columns, a plurality of output lines corresponding to the plurality of columns and through which first and second signals are output from the pixels, and a plurality of column circuits corresponding to the plurality of output lines, each of the plurality of column circuits has a sample-and-hold unit including a first sample-and-hold circuit that holds the first signal and a second sample-and-hold circuit that holds the second signal; each of the first sample-and-hold circuit and the second sample-and-hold circuit has a plurality of unit capacitors and a switch circuit provided between the output line and the plurality of unit capacitors; the switch circuit includes a plurality of first switches respectively provided between the output line and first electrodes of the plurality of unit capacitors, and a plurality of second switches respectively provided between the first electrodes of adjacent unit capacitors; the unit capacitors of the first sample-and-hold circuit and the unit capacitors of the second sample-and-hold circuit are alternately arranged adjacent to each other along a first direction parallel to the plurality of columns; the first sample-and-hold circuit further includes a first amplifier connected to a first wiring that connects the second electrodes of the plurality of unit capacitors to each other; the second sample-and-hold circuit further includes a second amplifier connected to a second wiring that connects the second electrodes of the plurality of unit capacitors to each other; the plurality of unit capacitors of the first sample-and-hold circuit, the plurality of unit capacitors of the second sample-and-hold circuit, the first amplifier section, and the second amplifier section are arranged along the first direction, The first amplifying section and the second amplifying section are adjacent to each other. A photoelectric conversion device comprising:

9. each of the first sample-and-hold circuit and the second sample-and-hold circuit has a plurality of unit capacitance parts each including the first switch, the second switch, and the unit capacitance; The unit capacitance section of the first sample-and-hold circuit and the unit capacitance section of the second sample-and-hold circuit are disposed adjacent to each other along the first direction.

9. The photoelectric conversion device according to claim 7 or 8.

10. A planar layout of the unit capacitance section of the first sample-and-hold circuit is the same as a planar layout of the unit capacitance section of the second sample-and-hold circuit.

10. The photoelectric conversion device according to claim 9.

11. At least one of the unit capacitance section of the first sample-and-hold circuit and the unit capacitance section of the second sample-and-hold circuit is provided with a dummy switch having the same structure as a switch element constituting the second switch.

11. The photoelectric conversion device according to claim 10.

12. The length of an electrical path connecting the pixel and the first sample-and-hold circuit is the same as the length of an electrical path connecting the pixel and the second sample-and-hold circuit.

12. The photoelectric conversion device according to claim 1,

13. The number of the unit capacitances included in the first sample-and-hold circuit is the same as the number of the unit capacitances included in the second sample-and-hold circuit.

13. The photoelectric conversion device according to claim 1,

14. the first signal is a signal corresponding to incident light to the photoelectric conversion unit, The second signal is a signal based on a reset state of the pixel.

14. The photoelectric conversion device according to claim 1,

15. The sample-and-hold unit outputs a third signal according to a difference between the first signal and the second signal.

15. The photoelectric conversion device according to claim 14.

16. The column circuit further includes an AD conversion unit that converts the third signal from an analog signal to a digital signal.

16. The photoelectric conversion device according to claim 15.

17. The photoelectric conversion device according to claim 1 , a signal processing device that processes a signal output from the photoelectric conversion device; An imaging system comprising:

18. A mobile object, The photoelectric conversion device according to claim 1 , a distance information acquisition unit that acquires distance information to an object from a parallax image based on a signal output from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

Images