Imaging Devices and Equipment

Abstract

To suppress image quality deterioration while realizing various operation modes.SOLUTION: An imaging device includes: a pixel array having a plurality of pixels arranged in a matrix and outputting pixel signals corresponding to an amount of light received; a first column signal line and a second column signal line respectively provided corresponding to columns of the pixel array; a first column circuit connected to the first column signal line; a second column circuit connected to the second column signal line; a first control line for controlling the first column circuit; a second control line for controlling the second column circuit; and a switch provided between the first control line and the second control line.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to imaging devices and equipment. [Background technology]

[0002] An imaging device having a pixel array in which a plurality of pixels are formed on a semiconductor substrate is used. The imaging device described in Patent Document 1 discloses vertical lines (column signal lines) connected to a plurality of pixels in each column, and a column circuit including a current load circuit connected to the vertical lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-111376 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the imaging device described in Patent Document 1, when signals are read from the column signal lines in various operation modes, degradation of image quality may occur.

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to suppress deterioration in image quality while supporting various operation modes. [Means for solving the problem]

[0006] According to an embodiment of the present disclosure, there is provided a pixel array having a plurality of pixels arranged in a matrix and outputting pixel signals according to an amount of received light, a first column signal line and a second column signal line provided corresponding to each column of the pixel array, a first column circuit connected to the first column signal line, a second column circuit connected to the second column signal line, and a pixel circuit including the first column circuit. connected to the gate of the transistor in A first control line and the second column circuit connected to the gate of the transistor ina second control line; and a plurality of switches provided between the first control line and the second control line and controlled by a common signal. By turning on the multiple switches, the first control line and the second control line are brought into a conductive state, and by turning off the multiple switches, the first control line and the second control line are brought into a non-conductive state. An imaging device is provided. Effect of the Invention

[0007] According to the present invention, it is possible to suppress deterioration in image quality while supporting various operation modes. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram of an imaging device according to a first embodiment of the present invention. [Diagram 2] 1 is an equivalent circuit diagram of a pixel according to a first embodiment of the present invention. [Diagram 3] 1 is a schematic diagram of an imaging device according to a first embodiment of the present invention. [Figure 4] FIG. 11 is a schematic diagram of an imaging device according to a second embodiment of the present invention. [Diagram 5] FIG. 11 is a schematic diagram of an imaging device according to a third embodiment of the present invention. [Figure 6] FIG. 13 is a schematic diagram of an imaging device according to a fourth embodiment of the present invention. [Figure 7] FIG. 13 is a schematic diagram of an imaging device according to a fifth embodiment of the present invention. [Figure 8] 13 is a timing chart showing the operation of an imaging device according to a fifth embodiment of the present invention. [Figure 9] 13 is a timing chart showing the operation of an imaging device according to a fifth embodiment of the present invention. [Figure 10] FIG. 13 is a schematic diagram of an imaging device according to a sixth embodiment of the present invention. [Figure 11] FIG. 13 is a schematic diagram of an imaging device according to a seventh embodiment of the present invention. [Figure 12] FIG. 13 is a schematic diagram of an imaging device according to an eighth embodiment of the present invention. [Figure 13] 13 is a timing chart showing the operation of an imaging device according to the eighth embodiment of the present invention. [Figure 14]13 is a timing chart showing the operation of an imaging device according to the eighth embodiment of the present invention. [Figure 15] FIG. 13 is a schematic diagram of an imaging device according to a ninth embodiment of the present invention. [Figure 16] FIG. 13 is a schematic diagram of an imaging device according to a ninth embodiment of the present invention. [Figure 17] FIG. 13 is a diagram for explaining a configuration of an AD conversion circuit according to a ninth embodiment of the present invention. [Figure 18] FIG. 13 is a diagram for explaining a configuration of an AD conversion circuit according to a ninth embodiment of the present invention. [Figure 19] FIG. 23 is a block diagram showing an example of the configuration of an apparatus according to a tenth embodiment of the present invention. [Figure 20] FIG. 23 is a block diagram of equipment related to an in-vehicle camera in an eleventh embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment will be described with reference to the drawings. In the description of each embodiment, the same components as those in other embodiments will be denoted by the same reference numerals, and the description thereof may be omitted.

[0010] [First embodiment] 1 is a block diagram of an image pickup device according to this embodiment. The image pickup device is configured on a semiconductor substrate, for example, a CMOS image sensor. A pixel array 110, a vertical scanning circuit 113, a column circuit 114, a horizontal scanning circuit 115, an output circuit 116, and a timing generation circuit 112 are formed on the semiconductor substrate.

[0011] The pixel array 110 includes a plurality of pixels 10 arranged in a matrix and outputting pixel signals according to the amount of received light, and each pixel 10 includes a photoelectric conversion unit that generates and accumulates a signal charge based on incident light. In this specification, the row direction refers to the horizontal direction (direction D2) in FIG. 1, and the column direction refers to the vertical direction (direction D1) intersecting the row direction D2 in FIG. 1. FIG. 1 shows n rows and m columns of pixels 10, with rows R1 to Rn and columns C1 to Cm. Microlenses and color filters may be arranged on the pixels 10. The color filters are, for example, red, blue, and green primary color filters, and are provided on each pixel 10 according to a Bayer array.

[0012] The pixel array 110 includes an open pixel region and a light-shielding pixel region in which a light-shielding film is formed. The pixels 10 included in the open pixel region do not have a light-shielding film formed thereon, and are capable of outputting pixel signals according to incident light. The light-shielding pixel region is a horizontal optical black (HOB) pixel region disposed adjacent to the open pixel region in the row direction D2. A dark signal equivalent to a noise component is obtained from the pixels 10 in the light-shielding pixel region.

[0013] The pixel array 110 may also be provided with a ranging row in which focus detection pixels that output pixel signals for focus detection are arranged, and a plurality of imaging rows in which imaging pixels that output pixel signals for generating an image are arranged. The pixels 10 connected to the column signal line 130 and the pixels 10 connected to the column signal line 131 are arranged in two different columns. That is, the column signal lines 130 and 131 are connected to columns of the pixels 10, and the pixels 10 in the same column sequentially output pixel signals to the common column signal lines 130 and 131.

[0014] The vertical scanning circuit 113 is composed of a shift register, a gate circuit, a buffer circuit, etc., and outputs control signals to the pixels 10 via control lines 117 based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., to drive the pixels 10 for each row.

[0015] The column circuit 114 is connected to the column signal lines 130 and 131, and amplifies pixel signals on the column signal lines 130 and 131 and performs AD (Analogue to Digital) conversion. As will be described later, the column circuit 4 may include current source transistors connected to the column signal lines 130 and 131, a comparator that compares a reference signal with a pixel signal, a memory that holds a count signal according to a comparison result by the comparator, and the like.

[0016] The horizontal scanning circuit 115 includes a decoder and a shift register, and sequentially reads out the count values ​​stored in the memory of the column circuit 114 as digital signals, and outputs them to a signal processing unit provided inside or outside the chip (imaging device). The signal processing unit includes a digital signal processor, and performs digital signal processing such as digital gain, digital correlated double sampling, digital offset, and linearity correction.

[0017] The output circuit 116 includes a serial output circuit of the LVDS (Low Voltage Differential Signaling) system, and outputs the processed digital signal to the outside of the imaging device at high speed and with low power consumption.

[0018] The timing generation circuit 112 generates various control signals and drive signals based on a clock and a synchronization signal, and outputs them to the vertical scanning circuit 113, the column circuit 114, the horizontal scanning circuit 115, and the output circuit 116 via control lines. The timing generation circuit 112 may also include a reference signal output circuit that generates a reference signal (ramp signal) whose voltage changes over time, and a counter circuit that generates a count signal synchronized with the reference signal. The counter circuit starts counting at the same time as the voltage of the reference signal changes, and supplies the count signal to the column circuit 4. The column circuit 114 can hold the count signal in memory at the timing when the magnitude relationship between the pixel signal and the reference signal is inverted, and output it as a digital signal after AD conversion.

[0019] FIG. 2 is an equivalent circuit diagram of a pixel in this embodiment. The pixel 10 may include a photoelectric conversion unit 101, a transfer transistor 102, a floating diffusion 103, a source follower transistor 104, a selection transistor 105, and a reset transistor 106. In the following description, unless otherwise specified, the transistor is assumed to be an N-type MOS (Metal Oxide Semiconductor) transistor. A reference voltage (for example, a ground voltage GND) is supplied to a back gate node (not shown). In addition, the reset transistor 106 and the source follower transistor 104 are connected to a power supply voltage Vdd. Note that a P-type MOS transistor may be used instead of the N-type MOS transistor. In this case, the voltage of a control signal, such as a control signal, applied to the P-type MOS transistor is inverted with respect to the voltage of the control signal in the N-type MOS transistor.

[0020] The photoelectric conversion unit 101 is, for example, a photodiode, which performs photoelectric conversion by incident light and accumulates electric charges. Note that instead of a photodiode, a configuration that generates a photoelectric effect, such as a photoelectric conversion film made of an organic material, a photogate, etc., may be used. The number of photoelectric conversion units 101 per pixel 10 is not limited, and two, four or more photoelectric conversion units 101 may be provided so as to share one microlens. Furthermore, by configuring an embedded photodiode, dark current noise can be reduced. The photoelectric conversion unit 101 is provided with a microlens, and light collected by the microlens is incident on the photoelectric conversion unit 101.

[0021] The transfer transistor 102 is provided corresponding to the photoelectric conversion unit 101, and a control signal TX is provided to a gate node of the transfer transistor 102. When the control signal TX becomes high level, electric charges generated and accumulated in the photoelectric conversion unit 101 due to received light are transferred to the floating diffusion 103 via the transfer transistor 102.

[0022] A power supply voltage Vdd is applied to the drain node of the source follower transistor 104. The source potential of the source follower transistor 104 changes in response to fluctuations in the amount of charge transferred to the floating diffusion 103.

[0023] The selection transistor 105 is provided between the source follower transistor 104 and a column signal line 130. The selection transistors 105 of the pixels 10 in multiple rows are connected to a common column signal line 130, and a constant current source (described later) and each source follower transistor 104 form a source follower. A control signal SEL is applied to the gate node of the selection transistor 105. When the control signal SEL becomes high level, the selection transistor 105 outputs an output according to the source potential of the source follower transistor 104 to the column signal line 130.

[0024] A source node of the reset transistor 106 is connected to the floating diffusion 103, and a power supply voltage Vdd is applied to a drain node of the reset transistor 106. A control signal RES is provided to a gate node of the reset transistor 106. When the control signal RES becomes high level, the reset transistor 106 resets the potential of the floating diffusion 103.

[0025] FIG. 3 is a schematic diagram of the imaging device according to this embodiment, and is a diagram for explaining a current source transistor and a switch between a control line.

[0026] Different current source transistors 140, 141 are provided on the column signal lines 130, 131. The drain node of the first current source transistor 140 is connected to the first column signal line 130, and the source node is connected to the GND node. The gate node of the current source transistor 140 is connected to the first control line BS1. The drain node of the second current source transistor 141 is connected to the second column signal line 131, and the source node is connected to the GND node. The gate node of the current source transistor 141 is connected to the second control line BS2.

[0027] In this embodiment, a switch 150 is provided between control lines BS1 and BS2. The switch 150 is composed of a transistor, one main node of the switch 150 is connected to the control line BS1, and the other main node of the switch 150 is connected to the control line BS2. A control signal SHT is applied to a control node (gate node) of the switch 150. When the control signal SHT becomes high level, the switch 150 is turned on, and when the control signal SHT becomes low level, the switch 150 is turned off. By turning the switch 150 on or off, it is possible to perform reading in various operation modes.

[0028] When the switch 150 is off, different bias voltages are supplied to the control lines BS1 and BS2, respectively, and the amount of current in the column signal line 130 can be made different from the amount of current in the column signal line 131. For example, the potential of the control line BS2 can be set to a low level and the current source transistor 141 can be set to an off state, so that pixel columns can be thinned out and read out. In this case, the resolution decreases, but it is possible to achieve power saving. Also, the amount of current in reading out the signal of the high-sensitivity pixel 10 can be made larger than the amount of current in reading out the signal of the low-sensitivity pixel 10.

[0029] When the switch 150 is on, the control lines BS1 and BS2 are conductive, and the potential difference between the control lines BS1 and BS2 is reduced. This reduces the difference in the amount of current in each of the column signal lines 130 and 131, and makes it possible to reduce the bias voltage difference between the column signal lines 130 and 131. The reason for this will be described in detail below.

[0030] The charge generated in the photoelectric conversion unit 101 is transferred from the transfer transistor 102 to the floating diffusion 103 and converted into a signal voltage by the parasitic capacitance associated with the floating diffusion 103. The signal voltage is then output to the column signal line 130 via the source follower transistor 104 and the selection transistor 105. The source follower transistor 104 forms a source follower together with the current source transistor 140, and the signal of the floating diffusion 103 is current-amplified (buffered) by the source follower transistor 104 and appears as a voltage change on the column signal line 130.

[0031] Here, the voltage change of the column signal lines 130 and 131 may cause a fluctuation in the bias voltage of the control lines BS1 and BS2 through the parasitic capacitance of the current source transistors 140 and 141 and the coupling capacitance of the control lines BS1 and BS2. Due to the variation of the parasitic capacitance of the current source transistors 140 and 141 and the parasitic capacitance of the control lines BS1 and BS2, the bias voltages of the control lines BS1 and BS2 are different, and a difference occurs in the current values ​​of the current source transistors 140 and 141. For this reason, even if the potentials of the floating diffusions 103 of the pixels 10 of the column signal lines 130 and 131 are equal to each other, a voltage difference occurs between the column signal lines 130 and 131. For example, when an image with uniform illuminance is captured, multiple linear noises may occur in the vertical direction of the image, degrading the image quality.

[0032] In this embodiment, a switch 150 is provided between the control lines BS1 and BS2, and the control lines BS1 and BS2 are made conductive to reduce the difference in bias voltage between the control lines BS1 and BS2, thereby making it possible to suppress the above-mentioned deterioration in image quality. Therefore, in a mode in which all pixel columns are read out, the bias potential of the control lines BS1 and BS2 is at a predetermined level, and the switch 150 is driven to an on state. This makes it possible to reduce the difference in bias voltage between the columns and suppress image quality deterioration. On the other hand, in an operation mode in which different readouts are performed for each column, the switch 150 is turned off, and the current values ​​of the current source transistors 140 and 141 can be made different for each column. Therefore, according to this embodiment, it is possible to suppress image quality deterioration while realizing various operation modes.

[0033] [Second embodiment] 4 is a schematic diagram of an imaging device in this embodiment. In the first embodiment, one switch 150 is provided between the control lines BS1 and BS2, but a plurality of switches such as another switch 151 may be provided. Also, a switch may be provided for each predetermined number of columns. Although the number of elements increases, it becomes possible to apply the same bias voltage at every location on the control lines BS1 and BS2. This makes it possible to more effectively suppress deterioration in image quality.

[0034] [Third embodiment] 5 is a schematic diagram of an imaging device according to this embodiment. The following describes this embodiment, focusing on the configuration that differs from the first embodiment.

[0035] The current source transistors 140 and 141 are connected to the column signal lines 130 and 131 via the cascode transistors 200 and 201, respectively. In the column signal line 130, the drain node of the first current source transistor 140 is connected to the source node of the first cascode transistor 200, and the source node of the current source transistor 140 is connected to the GND node. The drain node of the cascode transistor 200 is connected to the column signal line 130. The gate node of the current source transistor 140 is connected to a control line BS, and the gate node of the cascode transistor 200 is connected to a control line CBS1. Similarly, in the column signal line 131, the drain node of the second current source transistor 141 is connected to the source node of the second cascode transistor 201, and the source node of the current source transistor 141 is connected to the GND node. The drain node of the cascode transistor 201 is connected to the column signal line 131. The gate node of the current source transistor 141 is connected to the control line BS, which is common to the gate node of the current source transistor 140. A control line CBS2 is connected to the gate node of the cascode transistor 201. A switch 152 is provided between the control lines CBS1 and CBS2. One main node of the switch 152 is connected to the control line CBS1, and the other main node is connected to the control line CBS2. A control signal SHT is applied to the control node (gate node) of the switch 152.

[0036] When the control signal SHT is at a low level, the switch 152 is turned off, the control lines CBS1 and CBS2 are electrically isolated, and different bias voltages can be applied to the cascode transistors 200 and 201. Therefore, similar to the first embodiment, the amount of current in the column signal line 130 and the amount of current in the column signal line 131 can be made different, thereby realizing various operation modes. On the other hand, when the control signal SHT is at a high level, the switch 152 is turned on, the control lines CBS1 and CBS2 are conductive, and the bias voltages of the control lines CBS1 and CBS2 become equal. As a result, the amount of current in each of the column signal lines 130 and 131 also becomes equal, making it possible to reduce the potential difference between the column signal lines 130 and 131. Therefore, in this embodiment as well, it is possible to suppress image quality degradation while realizing various operation modes.

[0037] [Fourth embodiment] 6 is a schematic diagram of an imaging device according to this embodiment. The following will mainly describe the configuration that differs from the third embodiment.

[0038] In this embodiment, a common control line CBS is connected to the gate nodes of the cascode transistors 200 and 201, and sample-and-hold switches 210 and 211 are provided between the gate nodes of the current-source transistors 140 and 141 and a control line (bias line) BS. One main node of the first sample-and-hold switch 210 is connected to the gate terminal of the current-source transistor 140, and the other main node is connected to the control line BS. The control node of the sample-and-hold switch 210 is connected to the control line SHBS1. One main node of the second sample-and-hold switch 211 is connected to the gate node of the current-source transistor 141, and the other main node is connected to the control line BS. The control node of the sample-and-hold switch 211 is connected to the control line SHBS2. In addition, a switch 153 is provided between the control lines SHBS1 and SHBS2, and two main nodes of the switch 153 are connected to the control lines SHBS1 and SHBS2, respectively. A control signal SHT is applied to the control node of the switch 153.

[0039] When the control signal SHT is at a low level, the switch 153 is turned off, the control lines SHBS1 and SHBS2 are electrically isolated, and the sample-and-hold switches 210 and 211 can be driven independently to be turned on or off. When the sample-and-hold switches 210 and 211 transition from on to off, the bias voltage supplied from the control line BS is held in the capacitance associated with the gate nodes of the current-source transistors 140 and 141. This makes it possible to suppress current fluctuations in the current-source transistors 140 and 141 in response to potential fluctuations of GND. By independently controlling the on or off timing of the sample-and-hold switches 210 and 211, a variety of readout modes can be realized.

[0040] When the control signal SHT is at a high level, the switch 153 is turned on, the control lines SHBS1 and SHBS2 are conductive, and the sample-and-hold switches 210 and 211 can be driven at the same timing. This makes it possible to suppress image quality degradation caused by the difference in current values ​​of the current source transistors 140 and 141. For comparison, it is assumed that the sample-and-hold switches 210 and 211 are driven while the switch 153 is kept off. In this case, due to the variation in parasitic capacitances associated with the control lines SHBS1 and SHBS2, the slope of the falling waveform when the control signal SHT transitions from a high level to a low level may differ between the control lines SHBS1 and SHBS2. This causes a difference in the potentials held at the gate terminals of the current source transistors 140 and 141 when the sample-and-hold switches 210 and 211 are turned off. As a result, image quality degradation may occur due to the difference in current values ​​of the current source transistors 140 and 141. According to this embodiment, in a mode in which the on / off timing of the sample and hold switches 210 and 211 are synchronized, by turning on the switch 153, it is possible to reduce the difference in current value between the column signal lines and suppress deterioration of image quality.

[0041] [Fifth embodiment] 7 is a schematic diagram of an image pickup apparatus according to this embodiment. The following will mainly describe the configuration different from the fourth embodiment.

[0042] The column signal lines 130 and 131 are connected to pixels 10 in different rows of the same pixel column (a common column) of the pixel array 110. For example, the column signal line 130 may be connected to a plurality of pixels 10 in odd-numbered rows, and the column signal line 131 may be connected to a plurality of pixels 10 in even-numbered rows. This allows the column circuit 4 to simultaneously read out two rows of pixels 10 via the column signal lines 130 and 131, thereby enabling a high-speed readout operation. In this embodiment, the gate nodes of the cascode transistors 200 and 201 are connected to different control lines CBS1 and CBS2, respectively. A switch 154 is provided between the control lines CBS1 and CBS2. Two main nodes of the switch 154 are connected to the control lines CBS1 and CBS2, respectively, and a control signal SHT is applied to the control node of the switch 154.

[0043] In this embodiment, it is possible to realize an operation mode using different bias voltages between rows and an operation mode using equal bias voltages between rows. The operation mode using different bias voltages between rows can be, for example, an operation mode in which the pixels 10 are read out row by row. Moreover, the operation mode using equal bias voltages between rows can be a mode in which two rows of pixels 10 are read out simultaneously. In the operation mode using equal bias voltages between rows, it is possible to suppress image quality degradation caused by differences in current values ​​between rows.

[0044] 8 is a timing chart showing the operation of the imaging device in this embodiment, illustrating an operation mode in which the column signal lines 130 and 131 are alternately used to read out signals from the pixels 10.

[0045] At time t0, the control signal SHT is at a low level, and the switch 154 is in an off state. Therefore, the control lines CBS1 and CBS2 are electrically isolated, and the bias voltages of the control lines CBS1 and CBS2 can be controlled independently. Here, the bias voltage of the control line CBS1 is at a high level, so the cascode transistor 200 is in an on state. On the other hand, the bias voltage of the control line CBS2 is at a low level, so the cascode transistor 201 is in an off state.

[0046] From time t0 to t1, the potential of the control line SHBS1 is at a high level, the sample and hold switch 210 is turned on, and the bias voltage of the control line BS1 is applied to the gate node of the current source transistor 140. At time t1, the potential of the control line SHBS1 goes from a high level to a low level, and the sample and hold switch 210 is turned off. The bias voltage of the control line BS1 is held at the gate node of the current source transistor 140, and the current of the current source transistor 140 is determined. The current flows from the source follower transistor 104 of the pixel 10 to the current source transistor 140.

[0047] Between times t1 and t2, signals from the pixels 10 are read out to the column circuit 4 via the column signal line 130. Meanwhile, since the cascode transistor 201 is off, the column signal line 131 is in a power saving state. Therefore, reading from the pixels 10 via the column signal line 131 is not performed. That is, signals from the pixels 10 in one of the odd-numbered rows are read out via the column signal line 130.

[0048] At time t2, the voltage of the control line CBS1 goes from high to low, turning off the cascode transistor 200. This puts the column signal line 130 into a power saving state, and reading from the pixel 10 via the column signal line 130 is no longer performed. On the other hand, the voltage of the control line CBS2 goes from low to high, turning on the cascode transistor 201.

[0049] From time t2 to t3, the voltage of the control line SHBS2 is at a high level, the sample and hold switch 211 is turned on, and the bias voltage of the control line BS2 is applied to the gate node of the current source transistor 141. At time t3, the voltage of the control line SHBS2 goes from a high level to a low level, and the sample and hold switch 211 is turned off. The bias voltage supplied from the control line BS2 is held at the gate node of the current source transistor 141, and the current of the current source transistor 141 is determined. The current flows from the source follower transistor 104 of the pixel 10 to the current source transistor 141.

[0050] Between times t3 and t4, signals from the pixels 10 are read out to the column circuit 4 via the column signal line 131. That is, signals from the pixels 10 in one of the even rows are read out via the column signal line 131. Meanwhile, since the cascode transistor 200 is off, the column signal line 130 is in a power saving state, and reading from the pixels 10 via the column signal line 130 is not performed.

[0051] After time t4, signals of pixels 10 in one row among odd-numbered rows and even-numbered rows are alternately read out in the same manner as in the case of ... Then, signals from the pixels 10 in one row of the even rows are read out to the column circuit 4 via the column signal line 131.

[0052] 8, it is possible to execute an operation mode in which signals of one row of pixels 10 are read out sequentially by alternately using the column signal lines 130 and 131. Furthermore, in this embodiment, it is possible to execute an operation mode in which signals of two rows of pixels 10 are read out simultaneously by using the column signal lines 130 and 131, as shown in FIG.

[0053] Fig. 9 is a timing chart showing the operation of the imaging device in this embodiment, and shows an operation mode in which signals from two rows of pixels 10 are simultaneously read out. The following describes the timing chart in Fig. 9, focusing on operations that differ from the timing chart in Fig. 8.

[0054] At time t0, the control signal SHT is at a high level, and the switch 154 is in an on state. The control lines CBS1 and CBS2 are conductive, and the bias voltages of the control lines CBS1 and CBS2 become equal. A predetermined bias voltage is supplied to the control lines CBS1 and CBS2 by a voltage generating circuit. Therefore, the voltages of the gate nodes of the cascode transistors 200 and 201 become equal to each other.

[0055] From time t0 to t1, the control lines SHBS1 and SHBS2 are at a high level, and the sample-and-hold switches 210 and 211 are turned on. As a result, the bias voltage of the control line BS1 is supplied to the gate node of the current source transistor 140, and the bias voltage of the control line BS2 is supplied to the gate node of the current source transistor 141. Here, the bias voltages of the control lines BS1 and BS2 can be set to be equal to each other. At time t1, the sample-and-hold switches 210 and 211 are turned off, and the bias voltages are held at the gate nodes of the current source transistors 140 and 141. From time t1 to t2, signals of the pixels 10 in two rows are simultaneously read out via the column signal lines 130 and 131.

[0056] Similarly, at times t2 to t3, t4 to t5, and t6 to t7, the control lines SHBS1 and SHBS2 go to high level and the sample and hold switches 210 and 211 turn on, thereby supplying a bias voltage to the gate nodes of the current source transistors 140 and 141. Furthermore, at times t3 to t4 and t5 to t6, signals from the pixels 10 in two rows are simultaneously read out via the column signal lines 130 and 131.

[0057] In an operation mode in which signals from pixels 10 in two rows are read out, the switch 154 is turned on, so that the voltages at the gate nodes of the cascode transistors 200 and 201 become equal. This makes it possible to reduce the difference in bias voltage between the column signal lines 130 and 131, thereby reducing noise between rows when reading out two rows simultaneously. Therefore, in this embodiment as well, it is possible to suppress image quality degradation while realizing a variety of operation modes.

[0058] A switch may be further provided between the control lines BS1 and BS2 and controlled to be on in the two-row readout mode, which further reduces the difference in bias voltage between the current source transistors 140 and 141, and the effect of suppressing image quality degradation becomes more pronounced.

[0059] [Sixth embodiment] 10 is a schematic diagram of an image pickup apparatus according to this embodiment. The following description will focus on the configuration that differs from the fifth embodiment.

[0060] 10 further shows a first comparator 40 and a second comparator 41. The comparators 40 and 41 constitute an AD conversion unit in the column circuit 4, and are connected to column signal lines 130 and 131, respectively.

[0061] The comparator 40 includes transistors 300, 310, 320, and 330, a first current source transistor 340, first reset switches 350 and 360, and input capacitances 370 and 380. The transistors 300 and 310 form a differential pair, and the source nodes of the transistors 300 and 310 are connected to each other. The gate node (input node) of the transistor 300 is connected to the column signal line 130 via the input capacitance 370. The gate node (input node) of the transistor 310 is connected to a control line RAMP1 via the input capacitance 380. A reference signal such as a ramp signal that changes with time is supplied from the control line RAMP1. The reset switch 350 is provided between the gate node and drain node of the transistor 300, and the reset switch 360 is provided between the gate node and drain node of the transistor 310. The gate nodes of the reset switches 350 and 360 are connected to a control line CRES1. When the voltage of the control line CRES1 goes high and the reset switches 350 and 360 are turned on, the voltages of the gate nodes of the transistors 300 and 310 are reset.

[0062] The source nodes of the transistors 300 and 310 are connected to a source node of a current source transistor 340, and the drain node of the current source transistor 340 is connected to a ground line. The gate node of the current source transistor 340 is connected to a control line COBS1, and the current source transistor 340 is controlled by a first bias voltage supplied from the control line COBS1. The transistors 320 and 330 form a current mirror circuit. The gate nodes of the transistors 320 and 330 are connected to the source node of the transistor 320. In addition, the drain nodes of the transistors 320 and 330 are connected to a power supply line. The comparator 40 compares the signal from the column signal line 130 with a reference signal from the control line RAMP1, and outputs a signal according to the comparison result from the drain nodes of the transistors 300 and 310.

[0063] The comparator 41 is configured similarly to the comparator 40, and includes transistors 301, 311, 321, and 331, a second current source transistor 341, second reset switches 351 and 361, and input capacitances 371 and 381. The gate node of the transistor 301 is connected to the column signal line 131 via the input capacitance 371. The gate node of the transistor 311 is connected to the control line RAMP2 via the input capacitance 381. The control nodes of the reset switches 351 and 361 are connected to a control line CRES2. In addition, the gate node of the current source transistor 341 is connected to a control line COBS2, and the current source transistor 341 is controlled by a second bias voltage supplied from the control line COBS2. The comparator 41 can output a comparison signal representing a comparison result between a signal from the column signal line 131 and a reference signal from the control line RAMP2 from the drain nodes of the transistors 301 and 311.

[0064] Although not shown, the imaging device further includes a reference signal circuit that generates a reference signal, a counter circuit that counts up or down a counter of a count signal in synchronization with the reference signal, and a digital memory capable of holding a multi-bit digital signal. The counter circuit starts counting the clock pulse signal at the same time as the voltage change of the reference signal starts, and outputs a count signal. The comparison signals output from the comparators 40 and 41 are input to the digital memory. The memory is a digital memory capable of holding a multi-bit digital signal, and holds the count signal at the timing when the comparison signal is inverted. The count signal held in the digital memory represents a digital signal obtained by AD converting the signals from the column signal lines 130 and 131.

[0065] FIG. 10 shows a schematic circuit arrangement on a semiconductor substrate. On the semiconductor substrate, the current load circuits 20 and 21 are arranged close to each other (adjacent to each other), and the comparators 40 and 41 are also arranged close to each other (adjacent to each other). That is, a plurality of circuits of the same type are arranged together. This makes it possible to enhance the effect of shorting the switch 154 and reduce crosstalk between the circuits. For comparison, consider a configuration in which the current load circuit 20, the comparator 40, the current load circuit 21, and the comparator 41 are arranged in this order. In this case, the distance between the control lines CBS1 and CBS2 becomes longer, and even if the switch 154 is turned on, the effect of shorting the control lines CBS1 and CBS2 is reduced. That is, the impedance between the control lines CBS1 and CBS2 becomes larger, and the effect of reducing the bias voltage difference may become insufficient.

[0066] In contrast, according to the present embodiment, the comparators 40 and 41 are arranged close to each other, so the distance between the control lines CBS1 and CBS2 is shortened, and it is possible to enhance the effect of reducing the bias voltage difference between the control lines CBS1 and CBS2 when the switch 154 is on. In the comparative example, the comparator 40 is arranged between the current load circuits 20 and 21, so the wiring that short-circuits the control lines CBS1 and CBS2 crosses the comparator 40. For this reason, the wiring is easily subjected to crosstalk from, for example, the control lines RAMP1 and RAMP2. On the other hand, according to the present embodiment, the current load circuits 20 and 21 are arranged together, so it is possible to shorten the distance between the control lines CBS1 and CBS2 short-circuited by the switch 154 compared to the comparative example. Since the length of the short-circuited wiring is shortened, it is possible to enhance the effect of the short-circuit. In addition, according to the present embodiment, the short-circuited wiring does not pass through the comparators 40 and 41, so it is possible to avoid receiving crosstalk from, for example, the control lines RAMP1 and RAMP2. Furthermore, according to this embodiment, the current load circuit 20, the current load circuit 21, the comparator 40, and the comparator 41 are arranged in sequence along the column direction D1, making it possible to arrange the column circuit 4 in a narrow area corresponding to one pixel column.

[0067] In this embodiment as well, it is possible to suppress deterioration in image quality while realizing a variety of operation modes.

[0068] [Seventh embodiment] 11 is a schematic diagram of an imaging device according to this embodiment. In this embodiment, a switch is further provided between the control lines of the comparators 40 and 41. The following will mainly describe the configuration different from the sixth embodiment.

[0069] 11, a switch 155 is provided between control lines CRES1 and CRES2, and a control line SHT2 is connected to a control node of the switch 155. A switch 156 is provided between control lines RAMP1 and RAMP2, and a control line SHT3 is connected to a control node of the switch 156. Furthermore, a switch 157 is provided between control lines COBS1 and COBS2, and a control line SHT4 is connected to a control node of the switch 157.

[0070] In an operation mode in which signals of two rows of pixels 10 are read out from the column signal lines 130 and 131, in addition to the switch 154 of the current load circuits 20 and 21, the switches 155, 156, and 157 of the comparators 40 and 41 are controlled to be on. When the switch 155 is turned on, the control lines CRES1 and CRES2 are made conductive. As a result, the voltages of the control signals applied to the control nodes of the reset switch 350 of the comparator 40 and the reset switch 351 of the comparator 41 and the timings of transition to high and low levels become equal. Furthermore, when the switch 156 is turned on, the control lines RAMP1 and RAMP2 are made conductive. As a result, the potentials of the reference signals input to the comparators 40 and 41 and the timings of change become equal. Furthermore, when the switch 157 is turned on, the control lines COBS1 and COBS2 are made conductive. As a result, the bias voltages of the current source transistor 340 of the comparator 40 and the current source transistor 341 of the comparator 41 become equal. Therefore, in this embodiment as well, it is possible to suppress deterioration in image quality while realizing a variety of operation modes.

[0071] [Eighth embodiment] 12 is a schematic diagram of an imaging device according to this embodiment. The following describes this embodiment, focusing on the configuration that differs from the seventh embodiment.

[0072] In this embodiment, twelve column signal lines 130-135, 230-235 are arranged in one pixel column, and the pixels 10 in different twelve rows in the same pixel column are connected to the twelve column signal lines 130-135, 230-235, respectively. For example, the pixels 10 in even rows may be connected to the column signal lines 130-135, and the pixels 10 in odd rows may be connected to the column signal lines 230-235. The column signal lines 130-135 are connected to the load circuit group 120, and the column signal lines 230-235 are connected to the load circuit group 121. Although twelve rows of pixels 10 are shown in FIG. 12, the pixels 10 in other rows may be connected to the load circuit groups 120, 121 in the same manner. Furthermore, the column signal lines 130 to 135 and 230 to 235 do not necessarily need to be arranged in the same pixel column, and some or all of the column signal lines 130 to 135 and 230 to 235 may be arranged in different pixel columns.

[0073] The load circuit groups 120 and 121 may be disposed symmetrically with respect to the pixel array 110. For example, the load circuit group 120 may be provided below the pixel array 110, and the load circuit group 121 may be provided above the pixel array 110. Since the load circuit group 120 and the load circuit group 121 have a similar configuration, the configuration of the load circuit group 120 will be described below.

[0074] The load circuit group 120 includes current load circuits 20 to 25, which are connected to column signal lines 130 to 135, respectively. The first current load circuit 20 (first column circuit) is connected to the first column signal line 130, and the third current load circuit 21 (third column circuit) is connected to the third column signal line 131. The second current load circuit 22 (second column circuit) is connected to the second column signal line 132, and the fourth current load circuit 23 (fourth column circuit) is connected to the fourth column signal line 133. Similarly, the current load circuit 24 is connected to the column signal line 134, and the current load circuit 25 is connected to the column signal line 135. The current load circuits 20 to 25 include cascode transistors 200 to 205, current source transistors 140 to 140, and sample hold switches 210 to 215, respectively.

[0075] Sample-and-hold switches 210 to 215 are provided between the gate nodes of the current source transistors 140 to 145 and the control lines (bias lines) BS1 to BS6, respectively. The control nodes of the sample-and-hold switches 210 to 215 are connected to the control lines SHBS1 to SHBS6, respectively.

[0076] A control line CBS1 (first control line, third control line) is connected to the gate nodes of the cascode transistors 200 and 201, a control line CBS2 (second control line, fourth control line) is connected to the gate nodes of the cascode transistors 202 and 203, and a control line CBS3 is connected to the gate nodes of the cascode transistors 204 and 205. With this configuration, a common bias voltage is applied to the current load circuits 20 and 21 from the control line CBS1, and a common bias voltage is applied to the current load circuits 22 and 23 from the control line CBS2. In addition, a common bias voltage is applied to the current load circuits 24 and 25 from the control line CBS3.

[0077] A switch 154a is provided between the control lines CBS1 and CBS2, and a switch 154b is provided between the control lines CBS2 and CBS3. One main node of the switch 154a is connected to the control line CBS1, and the other main node is connected to the control line CBS2. One main node of the switch 154b is connected to the control line CBS2, and the other main node is connected to the control line CBS3. A control signal SHT is applied to the control nodes of the switches 154a and 154b. When the switch 154a is turned on, the control lines CBS1 and CBS2 are conductive, and a common bias voltage is applied to the current load circuits 20 to 23. When the switch 154b is turned on, the control lines CBS2 and CBS3 are conductive, and a common bias voltage is applied to the current load circuits 22 to 25. Furthermore, when the switches 154a and 154b are both turned on, the control lines CBS1, CBS2, and CBS3 are made conductive, and a common bias voltage is applied to the current load circuits 20-25.

[0078] In this embodiment, it is possible to simultaneously read out 12 rows of pixels 10, thereby realizing high-speed readout operations. In addition, a mode in which the pixels 10 are read out in groups of four rows is also possible, and it is possible to suppress the difference between rows in a mode in which the pixels 10 are read out in groups of 12 rows.

[0079] FIG. 13 is a timing chart showing the operation of the imaging device in this embodiment, and shows an operation mode in which signals of the pixels 10 in every four rows among the column signal lines 130 to 135 and 230 to 235 are read out in sequence.

[0080] At time t0, the control signal SHT is at a low level, and the switches 154a and 154b are in an off state. Therefore, the control lines CBS1, CBS2, and CBS3 are electrically isolated from each other, and the bias voltages of the control lines CBS1, CBS2, and CBS3 can be controlled independently. Here, the bias voltage of the control line CBS1 is at a high level, so the cascode transistors 200 and 201 are in an on state. On the other hand, the bias voltages of the control lines CBS2 and CBS3 are at a low level, so the cascode transistors 202 to 205 are in an off state.

[0081] From time t0 to t1, the potentials of the control lines SHBS1 and SHBS2 are at a high level, the sample and hold switches 210 and 211 are turned on, and the bias voltages of the control lines BS1 and BS2 are applied to the gate nodes of the current source transistors 140 and 141, respectively. At time t1, the potentials of the control lines SHBS1 and SHBS2 change from a high level to a low level, and the sample and hold switches 210 and 211 are turned off. The bias voltages of the control lines BS1 and BS2 are held at the gate nodes of the current source transistors 140 and 141, respectively, and the currents of the current source transistors 140 and 141 are determined. The currents flow from the source follower transistor 104 of the pixel 10 through the column signal lines 130 and 131 to the current source transistors 140 and 141, respectively.

[0082] Between times t1 and t2, signals from the pixels 10 are read out to the column circuit 4 via the column signal lines 130 and 131. Meanwhile, since the cascode transistors 202 to 205 are off, the column signal lines 132 to 135 are in a power saving state. Therefore, reading from the pixels 10 via the column signal lines 132 to 135 is not performed. That is, signals from the pixels 10 in two of the even rows are read out via the column signal lines 130 and 131. Similarly, signals from the pixels 10 in two of the odd rows are read out via the column signal lines 230 and 231. In this manner, signals from the pixels 10 in four of the twelve rows are read out.

[0083] At time t2, the voltage of the control line CBS1 goes from high to low, turning off the cascode transistors 200 and 201. This puts the column signal lines 130 and 131 into a power saving state, and reading from the pixel 10 via the column signal lines 130 and 131 is no longer performed. On the other hand, the voltage of the control line CBS2 goes from low to high, turning on the cascode transistors 202 and 203.

[0084] From time t2 to t3, the voltages of the control lines SHBS3 and SHBS4 are at a high level, the sample-and-hold switches 212 and 213 are turned on, and the bias voltages of the control lines BS3 and BS4 are applied to the gate nodes of the current-source transistors 142 and 143, respectively. At time t3, the voltages of the control lines SHBS3 and SHBS4 change from a high level to a low level, and the sample-and-hold switches 212 and 213 are turned off. The bias voltages supplied from the control lines BS3 and BS4 are held at the gate nodes of the current-source transistors 142 and 143, respectively, and the currents of the current-source transistors 142 and 143 are determined. The currents flow from the source-follower transistor 104 of the pixel 10 to the current-source transistors 142 and 143.

[0085] At times t3 to t4, signals from the pixels 10 are read out to the column circuit 4 via the column signal lines 132 and 133. That is, signals from the pixels 10 in two of the odd rows are read out via the column signal lines 132 and 133. Meanwhile, the cascode transistors 200, 201, 204, and 205 are off. Therefore, the column signal lines 130, 131, 134, and 135 are in a power saving state, and reading from the pixels 10 via the column signal lines 130, 131, 134, and 135 is not performed. Similarly, signals from the pixels 10 in two of the odd rows are read out via the column signal lines 232 and 233. In this manner, signals from the pixels 10 in four of the twelve rows are read out.

[0086] From time t4 to t5, the voltages of the control lines SHBS5 and SHBS6 are at a high level, the sample and hold switches 214 and 215 are turned on, and the bias voltages of the control lines BS5 and BS6 are applied to the gate nodes of the current source transistors 144 and 145. At time t5, the voltages of the control lines SHBS5 and SHBS6 change from a high level to a low level, and the sample and hold switches 214 and 215 are turned off. The bias voltages supplied from the control lines BS5 and BS6 are held at the gate nodes of the current source transistors 142 and 143, respectively, and the currents of the current source transistors 144 and 145 are determined.

[0087] At times t5 to t6, signals from the pixels 10 are read out to the column circuit 4 via the column signal lines 134 and 135. Meanwhile, since the cascode transistors 200 to 203 are off, the column signal lines 130 to 133 are in a power saving state, and reading from the pixels 10 via the column signal lines 130 to 133 is not performed. Similarly, signals from the pixels 10 in two of the odd-numbered rows are read out via the column signal lines 234 and 235. In this manner, signals from the pixels 10 in four of the twelve rows are read out. After time t6, signals from the pixels 10 in four of the twelve rows of the column signal lines 130 to 135 and 230 to 235 are read out in sequence, similarly to times t0 to t6.

[0088] Furthermore, in this embodiment, it is also possible to simultaneously read out the pixels 10 in 12 rows of the column signal lines 130 to 135 and 230 to 235 as will be described below.

[0089] Fig. 14 is a timing chart showing the operation of the imaging device in this embodiment, and shows an operation mode in which signals of the pixels 10 in 12 rows of the column signal lines 130 to 135 and 230 to 235 are simultaneously read out. The following describes the timing chart in Fig. 14, focusing on operations that differ from the timing chart in Fig. 13.

[0090] At time t0, the control signal SHT is at a high level, and the switches 154a and 154b are in an on state. The control lines CBS1, CBS2, and CBS3 are conductive, and the bias voltages of the control lines CBS1, CBS2, and CBS3 become equal. A predetermined bias voltage is supplied to the control lines CBS1, CBS2, and CBS3 by a voltage generating circuit. Therefore, the voltages of the gate nodes of the cascode transistors 200 to 205 become equal to each other.

[0091] At time t0 to t1, the control lines SHBS1, SHBS2, and SHBS3 are at high level, and the sample-and-hold switches 210 to 215 are turned on. As a result, the bias voltages of the control lines BS1 to BS6 are supplied to the gate nodes of the current source transistors 140 to 145, respectively. Here, the bias voltages of the control lines BS1 to BS6 can be set equal to each other. At time t1, the sample-and-hold switches 210 to 215 are turned off, and the bias voltages are held at the gate nodes of the current source transistors 140 to 145. At time t1 to t2, signals of the pixels 10 in six rows are read out via the column signal lines 130 to 135. Similarly, signals of the pixels 10 in six rows are read out via the column signal lines 230 to 235. That is, signals of the pixels 10 in twelve rows are simultaneously read out via the column signal lines 130 to 135 and 230 to 235.

[0092] Similarly, at times t2 to t3, t4 to t5, and t6 to t7, the control lines SHBS1, SHBS2, and SHBS3 go to high level and the sample and hold switches 210 to 215 turn on, thereby supplying bias voltages to the gate nodes of the current source transistors 140 to 145. Furthermore, at times t3 to t4 and t5 to t6, signals from the pixels 10 in 12 rows are simultaneously read out via the column signal lines 130 to 135, and 230 to 235.

[0093] In an operation mode in which signals from the pixels 10 in 12 rows are read out, the switches 154a and 154b are turned on, so that the voltages at the gate nodes of the cascode transistors 200 to 205 become equal. This makes it possible to reduce the difference in bias voltage between the column signal lines 130 to 135, and to reduce noise between rows when reading out 12 rows simultaneously. Therefore, in this embodiment as well, it is possible to suppress deterioration in image quality while realizing various operation modes.

[0094] [Ninth embodiment] 15 and 16 are schematic diagrams of an imaging device in this embodiment, and relate to a modified example of the imaging device in the eighth embodiment. The following description will focus on configurations that differ from the eighth embodiment.

[0095] The imaging device in this embodiment is a so-called back-illuminated type, and includes a pixel substrate 1 and a circuit substrate 2 for lamination. A pixel array 110 including a plurality of pixels 10 arranged in a matrix is ​​formed on the pixel substrate 1. Furthermore, on the pixel substrate 1, control lines for driving the pixels 10 and signal lines for reading out signals from the pixels 10 are arranged.

[0096] The circuit board 2 is laminated on the pixel substrate 1. On the circuit board 2, two signal processing circuits 50 and 51 are formed side by side in the row direction D2. The signal processing circuit 50 includes AD conversion circuits (ADC) 50A and 50B, logic circuits 51A and 51B, output circuits 52A and 52B, and row selection circuits (vertical scanning circuits) 530 and 531. Similarly, the signal processing circuit 51 includes AD conversion circuits 50C and 50D, logic circuits 51C and 51D, output circuits 52C and 52D, and row selection circuits 532 and 533. The AD conversion circuits 50A and 50C may be arranged corresponding to the even-numbered column signal lines 130 to 135 in FIG. 12, and the AD conversion circuits 50B and 50D may be arranged corresponding to the odd-numbered column signal lines 230 to 235 in FIG. 12.

[0097] The row selection circuits 530 to 533 supply control signals to the pixel array 110 via the joint between the pixel substrate 1 and the circuit substrate 2, and drive the pixels 10 for each row. AD conversion circuits 50A and 50B are arranged between the row selection circuits 530 and 531, and AD conversion circuits 50C and 50D are arranged between the row selection circuits 532 and 533.

[0098] The AD conversion circuits 50A-50D include a reference signal generation circuit, a comparator, a counter, and a memory, and convert pixel signals from the pixels 10 into digital signals. The logic circuits 51A-51D can perform digital signal processing such as digital gain, digital correlated double sampling, digital offset, and linearity correction on the digital signals from the AD conversion circuits 50A-50D. The output circuits 52A-52D output the digital signals processed by the logic circuits 51A-51D to the outside of the imaging device.

[0099] The signal processing circuits 50 and 51 are connected to each other by wiring groups 540 and 541. That is, the AD conversion circuits 50A and 50C are connected to each other by the wiring group 540, and the AD conversion circuits 50B and 50D are connected to each other by the wiring group 541. The wiring groups 540 and 541 may include control lines BS, CBS, SHBS, CRES, RAMP, etc., as described below.

[0100] Fig. 17 is a diagram for explaining the configuration of the AD conversion circuit in this embodiment, and shows the AD conversion circuit 50A (first circuit area) and the AD conversion circuit 50C (second circuit area) in Fig. 16. The AD conversion circuits 50A and 50C include a load circuit group 120, comparators 40 to 45, a reference signal generation circuit 60, a counter 61, first memories 620 to 625, and second memories 630 to 635. The load circuit group 120, the comparators 40 to 45, the reference signal generation circuit 60, the counter 61, the first memories 620 to 625, and the second memories 630 to 635 are provided for each column, and constitute a column circuit.

[0101] The multiple load circuit groups 120 are arranged side by side in the row direction D2. The load circuit group 120 includes multiple current load circuits 20 to 25, which are connected to column signal lines 130 to 135, respectively (see FIG. 12). Here, the column signal lines 130 to 135 are collectively shown as one wiring. The load circuit groups 120 of the AD conversion circuits 50A and 50C are connected to each other by control lines CBS1 to CBS3. A common bias voltage is supplied to the multiple load circuit groups 120, so that the characteristic difference between the AD conversion circuits 50A and 50C can be reduced.

[0102] The inverting input nodes of the comparators 40 to 45 are connected to the column signal lines 130 to 135, respectively, and the non-inverting input nodes of the comparators 40 to 45 are connected to a control line RAMP. The control line RAMP may be provided separately for each of the comparators 40 to 45. Each of the comparators 40 to 45 compares a reference signal on the control line RAMP with a pixel signal on the column signal lines 130 to 135, and outputs a comparison signal representing a comparison result from an output node. Also, similar to FIG. 11, the comparators 40 to 45 may include one or more switches provided between a plurality of control lines CRES for a reset switch, and one or more (two or more) switches provided between a plurality of control lines CBS for a bias voltage. Furthermore, the comparators 40 to 45 may include one or more switches 156 provided between a plurality of control lines RAMP for a reference signal. The control lines RAMP, CRES, and CBS may be arranged across the AD conversion circuits 50A and 50C.

[0103] The first reference signal generating circuit 60a outputs a reference signal whose voltage changes depending on time to a control line RAMP. The control line RAMP is arranged across the AD conversion circuits 50A to 50C, and the first reference signal generating circuit 60a is shared by the AD conversion circuits 50A and 50C. A second reference signal generating circuit 60c may also be formed in the AD conversion circuit 50C. However, the reference signal generating circuit 60c is not connected to the control line RAMP and is in an inactive state. Since the AD conversion circuits 50A and 50B share one reference signal generating circuit 60a, it is possible to reduce the characteristic difference between the AD conversion circuits 50A and 50C.

[0104] The counter 61 counts up or down in synchronization with the reference signal. The counter 61 starts counting clock pulses at the same time as the reference signal generating circuit 60a starts changing in voltage, and outputs a count signal. The count signal is supplied to the first memories 620 to 625. Note that a counter may be provided for each column of the column signal lines 130 to 135, and a common clock pulse may be supplied to each counter.

[0105] The first memories 620-625 receive the comparison results from the comparators 40-45 and the count values ​​from the counter 61, and latch the count values ​​at the timing when the comparison results are inverted. The count values ​​held in the first memories 620-625 represent values ​​obtained by analog-to-digital conversion of the pixel signals. The second memories 630-635 can further hold the count values ​​transferred from the first memories 620-625. The first memories 620-625 and the second memories 630-635 can hold the count values ​​at the time of resetting the pixel 10 and the count values ​​based on the photoelectric conversion of the pixel 10, respectively. The count values ​​of the first memories 620-625 and the second memories 630-635 are output to the logic circuits 51A-51D in FIG. 16.

[0106] Although not shown in FIG. 17, the AD conversion circuits 50B and 50D can be configured similarly to the AD conversion circuits 50A and 50C.

[0107] FIG. 18 is a diagram for explaining the configuration of the AD conversion circuit in this embodiment, and shows an example of the arrangement of the switches 154a and 154b.

[0108] As described above, the AD conversion circuit 50A has a plurality of load circuit groups 120 arranged side by side in a predetermined direction, for example, the row direction D2. Each load circuit group 120 includes a plurality of current load circuits 20 to 25, and is connected to one another by control lines CBS1 to CBS3, SHT, etc. A bias circuit 550 is arranged between the plurality of load circuit groups 120. For example, the bias circuit 550 can be arranged approximately in the center of the plurality of load circuit groups 120 in the row direction D2. The bias circuit 550 supplies a predetermined bias voltage to each of the control lines CBS1 to CBS3 and SHT.

[0109] The switch 154a is provided between the control lines CBS1 and CBS2, and the switch 154b is provided between the control lines CBS2 and CBS3. A control signal SHT is applied to the control nodes of the switches 154a and 154b. In this embodiment, a plurality of switches 154a and 154b may be distributed and arranged in a plurality of load circuit groups 120. Here, the number of each of the switches 154a and 154b may be less than the number of the load circuit groups 120.

[0110] The switches 154a, 154b may be arranged for every predetermined number of load circuit groups 120, and as an example, five sets of switches 154a, 154b may be arranged at approximately equal intervals in the row direction D2 in 3000 load circuit groups 120. With such a configuration, it is possible to make the potentials of the control lines CBS1, CBS2, and CBS3 uniform at all positions of the multiple load circuit groups 120 and reduce differences between columns while suppressing the number of switches 154a, 154b and the chip area.

[0111] In addition, since the bias circuit 550 is disposed between the multiple load circuit groups 120, it is possible to reduce the influence of the parasitic resistance of each of the wiring groups 540 between the AD conversion circuits 50A and 50C and the wiring group 541 between the AD conversion circuits 50B and 50D. If the bias circuit 550 is disposed at the left end of the AD conversion circuit 50A, the wiring distance from the bias circuit 550 to the current load circuit group at the right end becomes long, and the parasitic resistance may increase. In this case, a difference occurs between the bias voltages supplied to the load circuit groups 120 at the left end and the right end, and image quality may deteriorate. According to this embodiment, by disposing the bias circuit 550 between the multiple load circuit groups 120, it is possible to reduce the influence of the parasitic resistance of the wiring groups 540 and 541.

[0112] Although not shown in FIG. 18, the bias circuit 550 may be disposed between the plurality of load circuit groups 120 in the AD conversion circuit 50C. The bias circuits 550 disposed in the AD conversion circuits 50A and 50C may be connected to each other by the wiring group 540. This makes it possible to suppress the characteristic difference between the AD conversion circuits 50A and 50C while reducing the influence of the parasitic resistance of the wiring group 540 in the AD conversion circuit 50C. Although the load circuit group 120 is described as an example in FIG. 18, a similar configuration may be adopted in a comparator group including a plurality of comparators 40 to 45. For example, the bias circuits of the comparators 40 to 45 and the reference signal generating circuit 60 may be disposed between the plurality of comparator groups. Furthermore, the bias circuit 550 disposed in the AD conversion circuit 50A is not limited to one, and may be multiple.

[0113] [Tenth embodiment] A device according to a tenth embodiment of the present invention will be described with reference to Fig. 19. Fig. 19 is a block diagram showing an example of the configuration of a device 7 according to this embodiment.

[0114] The imaging device in the above-described embodiment can be applied to various devices. Examples of the devices include digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 19 shows a block diagram of a digital still camera as an example of the device.

[0115] The device shown in FIG. 19 includes a barrier 706, a lens 702, an aperture 704, an imaging device (an example of a photoelectric conversion device) 70, a signal processing unit 708, a timing generating unit 720, an overall control / calculation unit (control device) 718, a memory unit (storage device) 710, a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 70 is configured as in the above-mentioned embodiment, and converts the optical image formed by the lens 702 into image data (image signal). Here, it is assumed that an AD (analog-digital) conversion unit is formed on the semiconductor substrate of the imaging device 70. The signal processing unit 708 performs various corrections and data compression on the imaging data output from the imaging device 70.

[0116] The timing generating unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control and calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to the recording medium 714, and the recording medium 714 is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. The device 7 may further include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device includes at least a photoelectric conversion device. Furthermore, the device includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (for example, a robot arm) that operates by receiving a signal from the photoelectric conversion device.

[0117] In this embodiment, the imaging device 70 and the AD conversion unit are provided on different semiconductor substrates, but the imaging device 70 and the AD conversion unit may be formed on the same semiconductor substrate. Also, the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate.

[0118] Moreover, each pixel may include a plurality of photoelectric conversion units. The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and to acquire distance information from the imaging device 70 to the subject.

[0119] [Eleventh embodiment] FIG. 20(a) and FIG. 20(b) are block diagrams of devices related to the vehicle-mounted camera in this embodiment. The device 8 has an imaging device (an example of a photoelectric conversion device) 80 of the above-mentioned embodiment. The device 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 80, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the device 8. The device 8 also has a distance measurement unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of these distance information to determine the possibility of a collision. The distance information acquisition means may be realized by dedicated hardware or may be realized by a software module. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0120] The device 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. In addition, the device 8 is connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. In addition, the device 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, etc., and applying vibrations to a seat belt or steering wheel. The device 8 functions as a control means that controls the operation of controlling the vehicle as described above.

[0121] In this embodiment, the surroundings of the vehicle, for example the front or rear, are captured by the device 8. FIG. 20(b) shows the device when capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends instructions to the device 8 or the imaging device 80 to perform the operations described in the first to fifth embodiments. This configuration can further improve the accuracy of distance measurement.

[0122] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, in addition to moving bodies.

[0123] [Modified embodiment] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention.

[0124] For example, in the above-described embodiment, the pixel array 110 and the column circuit 114 may be formed on different semiconductor substrates. Furthermore, the control lines that are made conductive or non-conductive by the switches are not limited to the examples in the above-described embodiment.

[0125] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0126] 110 pixel array 114 column circuit 20, 21 Current load circuit 40, 41 Comparator 50A~50D AD conversion circuit 120, 121 Load circuit group 200, 201 Cascode transistor 210, 211 Sample and hold transistor 340, 341 Current source transistor 350, 351, 360, 361 Reset transistor

Claims

1. a pixel array having a plurality of pixels arranged in a matrix and outputting pixel signals according to the amount of received light; a first column signal line and a second column signal line provided corresponding to each column of the pixel array; a first column circuit connected to the first column signal line; a second column circuit connected to the second column signal line; a first control line connected to a gate of a transistor included in the first column circuit; a second control line connected to a gate of a transistor included in the second column circuit; a plurality of switches electrically connected between the first control line and the second control line, the plurality of switches being controlled by a common signal; An imaging device in which the first control line and the second control line are brought into a conductive state by turning on multiple switches, and the first control line and the second control line are brought into a non-conductive state by turning off multiple switches.

2. 2. The imaging device according to claim 1, wherein the plurality of pixels connected to the first column signal line and the plurality of pixels connected to the second column signal line are arranged in two different columns in the pixel array.

3. 2. The imaging device according to claim 1, wherein the plurality of pixels connected to the first column signal line and the plurality of pixels connected to the second column signal line are arranged in a common column in the pixel array.

4. 4. The imaging device according to claim 1, wherein when a signal is read out from either the first column signal line or the second column signal line, the switches are turned off.

5. 4. The image pickup device according to claim 1, wherein the switches are turned on when signals are read out from the first column signal line and the second column signal line.

6. 4. The image pickup device according to claim 3, wherein when signals of a plurality of rows are simultaneously read out from the first column signal line and the second column signal line, a plurality of the switches are turned on.

7. the first column circuit reads out a signal from a pixel connected to the first column signal line among the plurality of pixels; the second column circuit reads out signals from pixels connected to the second column signal line among the plurality of pixels; 7. The imaging device according to claim 1, wherein a plurality of the switches are used to switch the first column circuit and the second column circuit from one of a plurality of operation modes to another operation mode.

8. 8. The imaging device of claim 7, wherein the multiple operating modes include a first operating mode in which the first control line and the second control line are electrically connected by turning on the multiple switches, and a second operating mode in which the first control line and the second control line are not electrically connected by turning off the multiple switches.

9. 9. The imaging device according to claim 8, wherein in the first operation mode, a potential difference between the first control line and the second control line is smaller than that in the second operation mode.

10. the first column circuit includes a first sample-and-hold switch provided between a gate node of a first current source transistor and a bias line; the second column circuit includes a second sample-and-hold switch provided between a gate node of a second current source transistor and the bias line; the first operation mode controls the first sample-and-hold switch and the second sample-and-hold switch at the same timing; 9. The imaging device according to claim 8, wherein in the second operation mode, the first sample-and-hold switch and the second sample-and-hold switch are controlled independently of each other.

11. the first column circuit includes a first comparator that compares a signal of the first column signal line with a first reference signal that changes over time; the second column circuit includes a second comparator that compares a signal of the second column signal line with a second reference signal that changes over time; 9. The imaging device according to claim 8, wherein in the first operating mode, a difference in bias voltage between a current source transistor of the first comparator and a current source transistor of the second comparator is smaller than that in the second operating mode.

12. the first column circuit includes a first current load circuit connected to the first column signal line; 7. The image pickup device according to claim 1, wherein the second column circuit includes a second current load circuit connected to the second column signal line.

13. the first control line is connected to a gate node of a first current source transistor of the first current load circuit; 13. The imaging device according to claim 12, wherein the second control line is connected to a gate node of a second current source transistor included in the second current load circuit.

14. the first current load circuit includes a first current source transistor and a first transistor provided between the first current source transistor and the first column signal line, the first transistor being cascode-connected to the first current source transistor, and the first control line being connected to a gate node of the first transistor; 13. The imaging device according to claim 12, wherein the second current load circuit comprises a second current source transistor and a second transistor provided between the second current source transistor and the second column signal line, the second transistor being cascode-connected to the second current source transistor, and the second control line being connected to a gate node of the second transistor.

15. the first column circuit includes a first sample-and-hold switch provided between a gate node of a first current source transistor of the first current load circuit and a bias line; 13. The imaging device according to claim 12, wherein the second column circuit includes a second sample-and-hold switch provided between a gate node of a second current source transistor of the second current load circuit and the bias line.

16. the first control line is connected to a gate node of the first sample-and-hold switch; 16. The imaging device according to claim 15, wherein the second control line is connected to a gate node of the second sample-and-hold switch.

17. the first column circuit includes a first comparator that compares a signal of the first column signal line with a first reference signal that changes over time; 13. The image pickup device according to claim 12, wherein the second column circuit includes a second comparator that compares the signal of the second column signal line with a second reference signal that changes over time.

18. 18. The imaging device according to claim 17, wherein the first current load circuit and the second current load circuit are disposed adjacent to each other, and the first comparator and the second comparator are disposed adjacent to each other.

19. 20. The imaging device according to claim 18, wherein the first current load circuit, the second current load circuit, the first comparator, and the second comparator are arranged in sequence in a column direction.

20. 20. The imaging device according to claim 19, wherein the first reference signal is supplied to the first control line, and the second reference signal is supplied to the second control line.

21. the first control line is connected to a gate node of a first reset switch that resets an input node of the first comparator; 18. The imaging device according to claim 17, wherein the second control line is connected to a gate node of a second reset switch that resets an input node of the second comparator.

22. 18. The imaging device according to claim 17, wherein the first control line supplies a first bias voltage to the first comparator, and the second control line supplies a second bias voltage to the second comparator.

23. a third column signal line and a fourth column signal line provided corresponding to the columns of the pixel array, respectively; a third column circuit connected to the third column signal line; a fourth column circuit connected to the fourth column signal line; a third control line for controlling the third column circuit; a fourth control line that controls the fourth column circuit; the third control line is connected to the first control line; 17. The imaging device according to claim 1, wherein the fourth control line is connected to the second control line.

24. 24. The imaging device according to claim 23, wherein a set of the first column signal line, the second column signal line, the third column signal line and the fourth column signal line is provided in each of odd-numbered rows and even-numbered rows of the pixel array.

25. a first circuit area including a plurality of the first column circuits and a plurality of the second column circuits; a second circuit area including a plurality of the first column circuits and a plurality of the second column circuits; the first control line to which the first reference signal is supplied and the second control line to which the second reference signal is supplied are arranged from the first circuit area to the second circuit area; the first circuit area includes a first reference signal generating circuit connected to the first control line and the second control line; 21. The imaging device according to claim 20, wherein the second circuit area includes a second reference signal generating circuit that is not connected to the first control line and the second control line.

26. 26. The imaging device according to claim 25, further comprising a row selection circuit arranged between the first circuit area and the second circuit area, the row selection circuit selecting a row of the pixel array.

27. a plurality of circuit groups each including the first column circuit and the second column circuit and arranged in a predetermined direction; a bias circuit for supplying a predetermined voltage to each of the first control line and the second control line; 27. The image pickup apparatus according to claim 1, wherein the bias circuit is disposed between a plurality of the circuit groups.

28. 28. The image pickup apparatus according to claim 27, wherein the bias circuit is disposed approximately in the center of the plurality of circuit groups in the predetermined direction.

29. 28. The image pickup apparatus according to claim 27, wherein the number of the switches is two or more and is smaller than the number of the circuit groups.

30. An imaging device according to any one of claims 1 to 29, A control device for controlling the imaging device; a processing device that processes a signal output from the imaging device; a display device for displaying information obtained by the imaging device; a storage device that stores information obtained by the imaging device; and and a mechanical device that operates based on information obtained by the imaging device.

31. The pixel includes a plurality of photoelectric conversion units, 31. The device according to claim 30, wherein the processing device processes the image signals generated by the plurality of photoelectric conversion units, respectively, and obtains distance information from the imaging device to a subject.

Images