MEMORY STRUCTURES AND METHODS FOR FORMING SAME - Patent application

Abstract

To provide a device structure.SOLUTION: A device structure includes: a conductive feature disposed in a first dielectric layer, a ferroelectric tunnel junction stack that includes a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer located over the bottom electrode layer, and a top electrode layer located on the ferroelectric layer, the ferroelectric tunnel junction stack being disposed over the conductive feature; a spacer disposed along sidewalls of the ferroelectric tunnel junction stack; a second dielectric layer disposed over the spacer and the ferroelectric tunnel junction stack; and a contact via extending through the second dielectric layer. The top electrode layer is formed of a conductive metal oxide.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to memory structures and methods for forming the same. [Background technology]

[0002] The integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and designs have resulted in multiple generations of ICs, with each generation of circuits being smaller and more complex than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometric dimensions (i.e., the smallest assemblies (or wires) that can be produced by a manufacturing process) have decreased. Such size reduction processes typically provide benefits through increased production efficiency and associated cost reductions.

[0003] Dimensional shrinking processes prompt circuit designers to move devices from the front-end-of-line (FEOL) levels to the back-end-of-line (BEOL) levels where the interconnect structures reside. As an example, ferroelectric-based memory devices can be formed at the BEOL levels. Forming ferroelectric-based memory devices at the BEOL levels is not without challenges. Although conventional processes and structures of ferroelectric-based memory devices are generally sufficient for the intended goals of current memory devices, these conventional processes and structures do not appear to be satisfactory in all respects. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 20100264123 Summary of the Invention

[0005] According to some embodiments of the present disclosure, a device structure includes a conductive feature disposed in a first dielectric layer, a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer located above the bottom electrode layer, and a top electrode layer located on the ferroelectric layer, the device structure further comprising a ferroelectric tunnel junction stack disposed above the conductive feature, spacers disposed along a plurality of sidewalls of the ferroelectric tunnel junction stack, a second dielectric layer disposed above the spacers and the ferroelectric tunnel junction stack, and a contact hole extending through the second dielectric layer and contacting a top surface of the top electrode layer, the top electrode layer being formed of a conductive metal oxide.

[0006] According to some embodiments of the present disclosure, a structure includes a conductive feature disposed in a first dielectric layer, an etch stop layer located above the conductive feature and the first dielectric layer, a bottom contact hole extending through the etch stop layer to contact the conductive feature, a bottom electrode layer contacting the bottom contact hole, a ferroelectric layer located above the bottom electrode layer, and a top electrode layer located on the ferroelectric layer, and a memory stack disposed in the etch stop layer and the bottom contact hole, wherein the top electrode layer is formed of a conductive material that allows radiation from a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source to penetrate the entire depth of the top electrode layer.

[0007] According to some embodiments of the present disclosure, a method includes providing a workpiece including a conductive feature disposed in a first dielectric layer; depositing an etch stop layer above the workpiece; forming a contact hole through the etch stop layer to contact the conductive feature; depositing a bottom electrode layer above the etch stop layer and the contact hole; depositing a ferroelectric layer above the bottom electrode layer; depositing a top electrode layer above the ferroelectric layer; after depositing the top electrode layer, performing a laser annealing process with a laser source to promote crystallization of the ferroelectric layer; and after the laser annealing process, patterning the bottom electrode layer, the ferroelectric layer, and the top electrode layer to form a memory stack, wherein the top electrode layer is formed of a conductive material that allows transmission of radiation from the laser source. [Brief description of the drawings]

[0008] Aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale, and in fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] [Figure 1] 1 is a flow chart illustrating an example method 100 for forming a device structure according to various aspects of the present disclosure. [Diagram 2] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Diagram 3] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 4] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Diagram 5] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 6] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 7] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 8] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 9] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 10] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 11] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 12] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 13] 2A-2C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 100 in FIG. 1 according to various aspects of the present disclosure. [Figure 14] 4 is a flow chart illustrating an example method 400 for forming a device structure according to various aspects of the present disclosure. [Figure 15] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 16] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 17] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 18] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 19]15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 20] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 21] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. [Figure 22] 15A-15C are fragmentary cross-sectional views of a workpiece undergoing steps of a method 400 in FIG. 14 according to various aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] TECHNICAL FIELD This disclosure relates generally to integrated circuit devices, and more particularly to interconnect structures used in integrated circuit devices.

[0011] In order to realize different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Hereinafter, specific examples of assemblies, arrangements, etc. will be described to simplify the present disclosure. Of course, these are merely examples and are not limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed so as to be in direct contact with each other, and may include an embodiment in which an additional feature is formed between the first feature and the second feature, allowing the first feature and the second feature to not be in direct contact with each other. In addition, the present disclosure may repeatedly refer to numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself represent a relationship between the various embodiments and / or arrangements discussed.

[0012] Spatially relative terms such as "below," "downward," "at the bottom," "on top," "above," and the like may also be used herein to facilitate describing the relationship of one element or feature to another element or feature as illustrated. In addition to the orientation as illustrated, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and similarly the spatially relative descriptive symbols used herein may be interpreted accordingly.

[0013] Also, when describing a number or range of numbers with "about," "approximately," and similar terms, the terms are intended to encompass the numbers within a reasonable range of error inherent in manufacturing as understood by one of ordinary skill in the art. For example, a number or range of numbers encompasses a reasonable range that includes the stated number, which range is based on known manufacturing tolerances for the manufacture of the characteristic features associated with the number, for example, within + / - 10% of the stated number. For example, a material layer having a thickness of "about 5 nm" may encompass a dimensional range of 4.25 nm to 5.75 nm, with manufacturing tolerances associated with the deposition of the material layer being + / - 15%, as known to those of ordinary skill in the art. Furthermore, the present disclosure may repeatedly refer to numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself limit the relationship between the various embodiments and / or configurations described.

[0014] The IC manufacturing process flow is typically divided into three types: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). FEOL processes typically include processes related to the fabrication of IC devices such as transistors. As examples, FEOL processes may include the formation of isolation features, channel features, gate features, and source and drain features (commonly referred to as source / drain features). MEOL processes typically include processes related to the fabrication of contacts to multi-gate devices such as fin-type field effect transistors (FinFETs) or gate-all-around (GAA) transistors (also referred to as multi-bridge-channel (MBC) type transistors or surrounding gate transistors (SGTs)). Examples of MEOL features include contacts to the gate structures and / or source / drain features of multi-gate transistors. BEOL processes typically include processes related to the fabrication of multilayer interconnect (MLI) features used to interconnect IC features in the FEOL, thus enabling IC device operation. To conserve real estate in the FEOL levels, devices with large transistors that do not require photolithographic accuracy levels may be moved to FEOL structures. As an example, ferroelectric-based memory devices, such as ferroelectric tunnel junction (FTJ) memory devices, may be fabricated in the BEOL levels.

[0015] Ferroelectric tunnel junction memory is a non-volatile memory that includes two electrodes that sandwich a ferroelectric tunnel barrier layer. Although ferroelectric tunnel junction memory and ferroelectric random access memory (FeRAM) share some similar properties, the two types of memory differ in many ways. In FeRAM, a thick ferroelectric film is sandwiched between two electrodes, and a remnant polarization is switched by applying an electric field between the two electrodes. However, capacitive reading of the remnant polarization can disrupt the polarization and require the information to be rewritten. Also, the read current in thick ferroelectric films tends to be low, making compaction or integration into BEOL structures a challenge. Compared to FeRAM, ferroelectric tunnel junction memory includes a thin ferroelectric layer (measured in nanometers) that allows for quantum mechanical tunneling. Quantum mechanical tunneling causes a tunnel resistance with a highly distinguishable on / off resistance, allowing for non-destructive resistive readout. Also, ferroelectric tunnel junction memory has a read current that allows for integration of the memory into BEOL structures.

[0016] It has been observed that sufficient heat treatment of the ferroelectric layer in ferroelectric tunnel junction memory is a prerequisite for achieving crystallization and good ferroelectric properties. In some prior art, the heat treatment of the ferroelectric layer needs to be performed carefully because excessive heat can damage FEOL structures such as gate structures. The temperature of the heat treatment is often kept below 400° C., which may result in insufficient crystallization of the ferroelectric layer.

[0017] The present disclosure provides a process and a ferroelectric tunnel junction memory structure to achieve crystallization of the ferroelectric layer without unintended damage to the FEOL structure. The ferroelectric tunnel junction memory of the present disclosure includes an optically transparent top electrode layer that allows radiation from a laser source to penetrate the top electrode layer during a laser annealing process. In the process according to the present disclosure, a bottom electrode layer, a ferroelectric layer, and an optically transparent top electrode layer are deposited above a workpiece, and laser annealing is performed. During the laser annealing, radiation from a laser source penetrates the optically transparent top electrode layer to locally heat the ferroelectric layer to a temperature of about 400° C. to about 1000° C. without the FEOL structure receiving excessive heat. At the same time, the optically transparent top electrode layer applies a stress to the ferroelectric layer such that the ferroelectric layer can exhibit ferroelectric crystalline phase crystallization. The ferroelectric tunnel junction memory structure and process provide improved crystallization of the ferroelectric layer with very low risk of damaging the FEOL structure or without damaging the FEOL structure.

[0018] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, FIGS. 1 and 14 are flow charts illustrating methods 100 and 400 of forming a device structure from a workpiece 200 according to various aspects of the present disclosure. The methods 100 and 400 are merely illustrative and are not intended to limit the present disclosure to those specifically shown in the methods 100 and 400. For further embodiments of the methods, further steps may be provided before, during and after the methods 100 or 400, and some steps described may be replaced, deleted or moved. For simplicity, not all steps are described in detail herein. The method 100 is described below in conjunction with FIGS. 2-13, which are fragmentary cross-sectional views of a workpiece 200 at different stages of manufacture according to various embodiments of the method 100. Similarly, method 400 is described below in conjunction with Figures 2-4 and 15-22, which are fragmentary cross-sectional views of workpiece 200 at different stages of manufacture according to various embodiments of method 400. Because workpiece 200 is manufactured as a device structure, workpiece 200 may be referred to as device structure 200 herein as the context requires. For the avoidance of doubt, the X-, Y- and Z-directions in the drawings are mutually perpendicular. Throughout this disclosure, like reference numerals represent like features unless expressly stated otherwise.

[0019] The device structure 200 shown in the drawings of the present disclosure is simplified and not all features of the device structure 200 are illustrated or described in detail. The device structure 200 shown in the drawings may be a part of an IC chip, a system on chip (SoC) or a part thereof that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide semiconductor (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable assemblies, or combinations thereof.

[0020] 1 and 2, the method 100 includes, at step 102, providing a workpiece 200. The workpiece 200 includes a substrate 202. In one embodiment, the substrate 202 includes silicon (Si). Additionally or alternatively, the substrate 202 may include another elemental semiconductor (e.g., germanium (Ge)), a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide), an alloy semiconductor (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP), and / or combinations thereof. Alternatively, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable method separation steps. The substrate 202 may include various doped regions (not shown) depending on the design requirements of the device structure 200. In some embodiments, the substrate 202 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant, such as boron (e.g., BF2), indium, other p-type dopants, or combinations thereof. In some embodiments, substrate 202 includes n-type doped regions (e.g., n-type wells) doped with n-type dopants, such as phosphorus (P), arsenic (As), other n-type dopants, or combinations thereof. In some embodiments, substrate 202 includes doped regions with a combination of p-type and n-type dopants. Various doped regions may be formed directly on and / or within substrate 202 to provide, for example, a p-well structure, an n-well structure, a dual well structure, a protruding structure, or combinations thereof.Ion implantation processes, diffusion processes and / or other suitable doping processes may be performed to form the various doped regions.

[0021] In the described embodiment, the workpiece 200 includes a device 20 fabricated on a substrate 202. The device 20 may be a planar transistor or a multi-gate transistor, such as a fin field effect transistor or a gate-all-around transistor. The gate-all-around transistor may include a channel region of various shapes, including nanowires, nanorods, or nanosheets, which may be collectively referred to as nanometric structures. The gate-all-around transistor may also be referred to as a multi-bridge channel transistor or a surrounding-gate-transistor (SGT). The device 20 representatively shown in FIG. 2 is a planar device, which includes a gate structure 206 disposed above a channel region of an active region 204, and source / drain regions 208. The active region 204 may be formed of a substrate 202, which may be a silicon (Si) substrate, or may be formed of an epitaxial layer formed on the substrate 202. In the latter case, the epitaxial layer may comprise germanium (Ge) or silicon germanium (SiGe). Although device 20 is shown in FIG. 2 and subsequent figures to be a planar device, it should be understood that it may also be a fin field effect transistor or a gate-all-around transistor.

[0022] Although not explicitly shown, the gate structure 206 includes an interfacial layer that interfaces with the fin structure, a gate dielectric layer overlying the interfacial layer, and a gate electrode layer overlying the gate dielectric layer. The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may be titanium dioxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicate (HfSiO4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), Ba Other high-k dielectric materials may be included, such as TiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicate (LaSiO), aluminum silicate (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0023] The gate electrode layer of the gate structure 206 may include a single layer or, alternatively, a multi-layer structure including a metal layer having a work function selected to enhance device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a combination of metal alloys or metal silicides, etc. By way of example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof.

[0024] The source / drain regions 208 may be doped regions or may be deposited by vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE) and / or other suitable processes. If the source / drain regions 208 are n-type, they may comprise silicon doped with an n-type dopant such as phosphorus (P) or arsenic (As). If the source / drain regions 208 are p-type, they may comprise silicon germanium (SiGe) doped with a p-type dopant such as boron (B) or boron difluoride (BF2). In some alternative embodiments not explicitly shown in the drawings, the source / drain regions 208 may comprise multiple layers. In one example, the source / drain regions 208 may include a lightly doped first epitaxial layer located above the source / drain regions of the fin structure, a heavily doped second epitaxial layer located above the lightly doped first epitaxial layer, and an overlying epitaxial layer disposed above the heavily doped second epitaxial layer. The first epitaxial layer has a lower dopant concentration or a lower germanium content (if germanium is present) than the second epitaxial layer to reduce lattice mismatch defects. The second epitaxial layer has a highest dopant concentration or a highest germanium content (if germanium is present) to reduce resistance and increase strain in the channel. The overlying epitaxial layer may have a lower dopant concentration and a lower germanium content (if germanium is present) than the second epitaxial layer to increase etch resistance.

[0025] Although not explicitly shown in FIG. 2, a plurality of active regions similar to active region 204 are formed above substrate 202. These active regions may be isolated from one another by isolation features. In some embodiments, the isolation features may be formed by etching grooves in substrate 202 or an epitaxial layer on substrate 202 by a dry etching process and filling the grooves with an insulator material by a chemical vapor deposition process, a flowable chemical vapor deposition (FCVD) process, or a spin-on glass process. A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and provide a flat surface. In the described embodiment, the isolation features are formed after the chemical mechanical polishing process. If device 20 is a multi-gate device including fin or fin-like structures, the insulator material may be etched back to form the isolation features and to cause the fin or fin-like structures to protrude above the isolation structures. In some embodiments, the isolation features may include a multi-layer structure, including a liner dielectric layer and a bulk dielectric layer. The isolation features may include silicon oxide, silicon oxynitride, boron silicate glass (BSG), or phosphosilicate glass (PSG). Although not explicitly shown in the drawings, if device 20 is a multi-gate device, workpiece 200 may also include a MEOL structure, which may include source / drain contacts or gate contact holes disposed in one or more interlayer dielectric layers (ILDs).The interlevel dielectric layer may include silicon oxide, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass (USG), doped silicate glass (e.g., borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG)), and / or other suitable dielectric materials. The source / drain contacts may include ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). The gate contact holes may include tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

[0026] In the embodiment shown in FIG. 2, the workpiece 200 further includes a portion of an interconnect structure 201. The interconnect structure 201 includes a first metal layer M1 through an nth metal layer M n The point includes a first metal layer M1 and an nth metal layer M n The further metal layers of the interconnect structure 201 are the nth metal layer M n In some embodiments, the interconnect structure may include about 9 to about 13 metal layers, and the nth metal layer M n The number n in may be greater than 2. The process of the present disclosure may be performed immediately after forming the device 20, but this may entail a higher risk of damaging the FEOL structure. That is, the first metal layer M1 and the nth metal layer M nThere may be 0 to 11 layers between. Each of the metal layers of the interconnect structure includes a plurality of vias and metal lines embedded in at least one intermetal dielectric layer (IMD). The vias and metal lines may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W) or aluminum (Al). In one embodiment, the vias and metal lines are formed of copper (Cu). The intermetal dielectric layer may have a similar composition to the interlevel dielectric layer. In the embodiment shown, the first metal layer M1 includes a first via hole 214 and a first metal line 216 disposed in the first via hole 214. The first via hole 214 and the first metal line 216 are both embedded or disposed in the first interlevel dielectric layer 212. Similarly, the nth metal layer M n includes an upper via 224 and an upper metal line 226 that are embedded or disposed within the nth interlevel dielectric layer 222. In the embodiment shown in FIG. 2, n is 3, and the first metal layer M1 and the nth metal layer M n Note that as used herein, the top metal line 226 represents the top metal line on which the memory stack is formed. n More metal layers are formed above.

[0027] 1 and 3, the method 100 includes depositing a first etch stop layer (ESL) 230 over the workpiece 200 at step 104. In some embodiments, the first etch stop layer 230 includes silicon carbide and may be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD). The first etch stop layer 230 may be used not only as an etch stop layer but also to prevent electromigration of metal in the upper metal line 226 when the upper metal line 226 is made of copper or a copper-containing material. In some embodiments, the first etch stop layer 230 may have a thickness of about 200 nm to about 350 nm. This thickness is not insignificant. If the thickness is less than 200 nm, the first etch stop layer 230 may not be able to sufficiently suppress electromigration in the upper metal line 226. If the thickness is greater than 350 nm, the first etch stop layer 230 will occupy too much thickness and prevent the entire process from being performed on metal layers with a small total thickness (e.g., the first three or first four metal layers from device 20).

[0028] 1 and 4, the method 100 includes, in step 106, forming an opening 232 through the first etch stop layer 230 to expose the top metal line 226. The opening 232 may be formed through the first etch stop layer 230 by a combination of photolithography and etching processes. For example, at least one hard mask is deposited above the first etch stop layer 230 by chemical vapor deposition, flowable chemical vapor deposition, or a suitable process. Then, a photoresist layer is deposited above the at least one hard mask layer by spin coating. The deposited photoresist layer may undergo a pre-exposure bake process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure bake process, and a development process to form a patterned photoresist. Then, the at least one hard mask layer is etched using the patterned photoresist as an etching mask to form a patterned hard mask. Subsequently, the first etch stop layer 230 is etched using the patterned hard mask as an etch mask to form an opening 232. The suitable etching process of step 106 may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process of step 106 may be a dry etching process (e.g., a reactive ion etching (RIE) process), which includes the use of an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), or a chlorine-containing gas (e.g., Cl2 and / or BCl3). As shown in FIG. 4, the opening 232 extends completely through the first etch stop layer 230 to expose the top surface of the upper metal line 226.

[0029] 1 and 5, the method 100 includes, at step 108, forming a contact hole 234 in the opening 232 to couple to the top metal line 226. In some embodiments, the contact hole 234 may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, the contact hole 234 is formed of titanium nitride (TiN) because titanium nitride tends to reduce copper electromigration in the top metal line 226 in the underlying layer. In one example of the process, the conductive material used for the contact hole 234 is first deposited by chemical vapor deposition or physical vapor deposition above the first etch stop layer 230 and the opening 232, and then a planarization process, such as a chemical mechanical polishing process, is performed to remove excess material above the first etch stop layer 230. In another embodiment, the contact hole 234 may be deposited by a bottom-up deposition method such as atomic layer deposition or metal organic chemical vapor deposition (MOCVD). In the latter example, the contact hole 234 may be selectively deposited on the conductive surface of the upper metal line 226 exposed by the opening 232.

[0030] 1 and 6, the method 100 includes depositing a bottom electrode layer 236 over the contact hole 234 and the first etch stop layer 230 in step 110. In some embodiments, the bottom electrode layer 236 includes tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), tungsten (W), platinum (Pt), ruthenium (Ru), iridium (Ir), or molybdenum (Mo). The bottom electrode layer 236 is blanket deposited over the top surface of the workpiece 200 (including the top surface of the first etch stop layer 230 and the contact hole 234) by physical vapor deposition or chemical vapor deposition. It should be noted that the bottom electrode layer 236 is not formed of a metal oxide that is opaque and semi-transparent or transparent because it does not serve to allow the transmission of laser radiation. In some examples, the bottom electrode layer 236 may have a thickness of about 10 nm to about 20 nm. This thickness range is not insignificant. If the thickness is less than 10 nm, the bottom electrode layer 236 may be poorly conductive due to the conduction mechanism at this thickness, and if the thickness is greater than 20 nm, a bottom electrode layer 236 formed of a low conductive material such as titanium nitride (TiN) may result in too much resistance.

[0031] 1 and 7, the method 100 includes, at step 112, depositing a ferroelectric layer 238 above the bottom electrode layer 236. The ferroelectric layer 238 may be a binary oxide, a ternary oxide, a ternary nitride, or a quaternary oxide that exhibits ferroelectric properties. The ferroelectric layer 238 may be a hafnium oxide, a hafnium silicate (HfSiO x ), hafnium zirconate (HfZrO x ), barium titanate (BaTiO3), lead titanate (PbTiO3), strontium titanate (SrTiO3), calcium manganite (CaMnO3), bismuth ferrite (BiFeO3), aluminum scandium nitride (AlScN), aluminum gallium nitride (AlGaN), aluminum yttrium nitride (AlYN), doped HfO2 (dopants are e.g. Si, Zr, Y, Al, Gd, Sr, La, Sc, Ge, etc.), lead zirconate titanate (PbZr x Tiy O z ;PZT), barium strontium titanate (BaSrTiO x ) or strontium bismuth tantalate (SrBi2Ta2O9; SBT). In one embodiment, the ferroelectric layer 238 includes zirconium doped hafnium oxide or hafnium zirconium oxide (HZO). As shown in FIG. 7, the ferroelectric layer 238 may be blanket deposited over the workpiece 200, including over the bottom electrode layer 236, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. It should be noted that the ferroelectric layer 238 does not have to exhibit ferroelectric properties when deposited in step 112, since the deposition method of the ferroelectric layer may cause the ferroelectric layer to not have sufficient crystallinity. In this respect, the ferroelectric layer 238 deposited in step 112 may be considered a ferroelectric precursor. As described above, the ferroelectric layer 238 is sufficiently thin to enable quantum mechanical tunneling. In some examples, the ferroelectric layer 238 may have a thickness of about 1 nm to about 10 nm. The thickness of the ferroelectric layer 238 is less than the thickness of the bottom electrode layer 236 .

[0032] 1 and 8, the method 100 includes depositing a top electrode layer 240 over the ferroelectric layer 238 at step 114. The top electrode layer 240 is formed of an optically transparent conductive material. In some embodiments, the top electrode layer 240 is formed of a conductive metal oxide, such as indium-tin oxide (ITO), zinc oxide (ZnO), fluorine doped tin oxide (FTO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), or the like. The top electrode layer 240 may be deposited by physical vapor deposition or a sol-gel process. In some embodiments, the deposited top electrode layer 240 may be annealed to improve its conductivity. In some examples, annealing the top electrode layer 240 may include using a carbon dioxide (CO2) laser source. According to the present disclosure, the top electrode layer 240 is formed of a material that allows the transmission of at least some of the laser source radiation. In some examples, the transmission of the top electrode layer 240 may be greater than 30%, otherwise defeating the purpose of having an optically transparent top electrode layer 240. That is, the top electrode layer 240 is semi-transparent or transparent to the radiation from the laser source. A laser source as used herein refers to a laser source used in laser annealing operations. Examples of laser sources include a helium-neon (He-Ne) laser source, a neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source, an argon-ion (Ar+) laser source, a continuous-wave (CW) argon laser source, a krypton-ion (Kr+) laser source, a gallium arsenide diode laser source, or a helium cadmium (He-Cd) laser source. Most of these example laser sources emit radiation in the visible spectrum, so the top electrode layer 240 may be considered to be semi-transparent or transparent to visible light. In some examples, the top electrode layer 240 may have a thickness between about 10 nm and about 20 nm.If the thickness is less than 10 nm, the top electrode layer 240 may be poorly conductive due to the conduction mechanism at this thickness. If the thickness is greater than 20 nm, the top electrode layer 240 formed of a poorly conductive metal oxide may result in too much resistance. Although not explicitly shown in the drawings, the operation of step 114 may include a low temperature annealing of the top electrode layer 240, thereby improving the optical transparency and electrical conductivity of this layer. In some examples, the low temperature annealing may include the use of an oven and an annealing temperature of 100° C. to about 200° C.

[0033] 1 and 9, the method 100 includes performing laser annealing 300 on the ferroelectric layer 238 in step 116. As described above, the as-deposited ferroelectric layer 238 may lack crystallinity and therefore may not exhibit ferroelectricity. In order to increase the crystallinity in the ferroelectric layer 238, the laser annealing 300 is performed in step 116. Although the laser annealing 300 is shown in FIG. 9 as irradiating the entire workpiece 200, the laser annealing 300 may include scanning or stepping over substantially the entire top surface of the top electrode layer 240. As in the general description of the operation of step 114 above, the top electrode layer 240 is semi-transparent or transparent to the laser source radiation from the laser annealing step (e.g., laser annealing 300 in FIG. 9). The radiation from the laser annealing 300 can still penetrate at least partially through the entire thickness of the top electrode layer 240 and effectively reach the ferroelectric layer 238. However, underlying layers (e.g., bottom electrode layer 236 or first etch stop layer 230) block the radiation from reaching the FEOL structures, etc., of device 20. That is, by having an optically transparent top electrode layer 240 above ferroelectric layer 238, laser annealing 300 can effectively anneal ferroelectric layer 238 to promote crystallization and ferroelectricity without significant risk of damaging the FEOL structures. In some embodiments, laser annealing 300 can include use of a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source, and can include an annealing temperature of about 400° C. to about 1000° C. This annealing temperature range is not insignificant. If the annealing temperature is lower than 400° C., the crystallization of the ferroelectric layer 238 is slow, and the laser annealing 300 may not achieve sufficient crystallization to ensure the ferroelectric property. If the annealing temperature is higher than 1000° C., the thermal energy may damage the upper metal line 226 or the upper through-hole 224.To illustrate the effect of laser annealing 300, ferroelectric layer 238 after annealing is relabeled as ferroelectric layer 2380. Ferroelectric layer 2380 and ferroelectric layer 238 share the same composition, but ferroelectric layer 2380 is more crystallized and exhibits higher ferroelectric properties.

[0034] It has been observed that the ferroelectric layer 238 does not form a ferroelectric phase when annealed without receiving strain from the top electrode layer 240. Therefore, it can be seen that the top electrode layer 240 of the present disclosure provides several functions: First, the top electrode layer 240 serves as the top electrode of the memory stack. To provide this function, the top electrode layer 240 is conductive. Second, the top electrode layer 240 applies a tensile stress to the ferroelectric layer 238 so that the ferroelectric layer 238 can exhibit a ferroelectric crystalline phase. In this respect, the top electrode layer 240 serves as a stress source or strain layer. Third, the top electrode layer 240 of the present disclosure is semi-transparent or transparent to the radiation of the laser source used for the laser annealing 300.

[0035] 1 and 10, the method 100 includes patterning the bottom electrode layer 236, the ferroelectric layer 2380, and the top electrode layer 240 to form the first memory stack 250 in step 118. After performing laser annealing 300 on the ferroelectric layer 238 through the top electrode layer 240 in step 116, a combination of photolithography and etching processes is performed to pattern the bottom electrode layer 236, the ferroelectric layer 2380, and the top electrode layer 240. In one example of the process, a hard mask layer 242 is blanket deposited above the top electrode layer 240 by chemical vapor deposition. The hard mask layer 242 may include silicon oxide, silicon nitride, or silicon oxynitride. It is noted that the composition of the hard mask layer 242 is different from the composition of the first etch stop layer 230. A photoresist layer is then deposited above the hard mask layer 242 by spin coating. The deposited photoresist layer may be subjected to a pre-exposure bake process, exposure to radiation reflected from or transmitted through a photomask, a post-exposure bake process, and a development process to form a patterned photoresist. The hard mask layer 242 is then etched using the patterned photoresist as an etch mask to form a patterned hard mask layer 242. The bottom electrode layer 236, the ferroelectric layer 2380, and the top electrode layer 240 are then etched using the patterned hard mask layer 242 as an etch mask to form the first memory stack 250. The suitable etching process of step 118 may be a dry etching process (e.g., a reactive ion etching process) including the use of an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. As shown in FIG. 10, the first memory stack 250 includes a bottom electrode layer 236, a ferroelectric layer 2380, a top electrode layer 240 and a patterned hard mask layer 242.The ferroelectric layer 2380 has a thickness that allows quantum mechanical tunneling, so that the first memory stack 250 is a ferroelectric tunnel junction stack or a ferroelectric tunnel junction memory device. The first memory stack 250 is disposed directly above the contact hole 234 such that the top surface of the contact hole 234 is physically coupled to the bottom surface of the bottom electrode layer 236. In the illustrated embodiments, the patterned hard mask layer 242 is left in place on the first memory stack 250. In these embodiments, the patterned hard mask layer 242 is left in place because removing the patterned hard mask layer 242 would damage the top electrode layer 240 and the patterned hard mask layer 242 does not substantially prevent any contact structures from being formed above the first memory stack 250.

[0036] 1, 11 and 12, the method 100 includes performing further processing in step 120. The further processing in step 120 may include forming spacers 244 (shown in FIG. 11) along sidewalls of the first memory stack 250, depositing a second etch stop layer 252 (shown in FIG. 12) above the first memory stack 250 and the spacers 244, depositing an (n+1)th interlayer dielectric layer 254 (shown in FIG. 12) above the second etch stop layer 252, and forming an (n+1)th through hole 256 and an (n+1)th metal line 258 (shown in FIG. 12) through the interlayer dielectric layer 254 and the second etch stop layer 252. The spacer 244 shown in FIG. 11 may be formed by conformally depositing a spacer material layer above the workpiece 200 (including above the first memory stack 250) and then anisotropically etching back the spacer material layer. As shown in FIG. 11, the spacer 244 is located only above a portion of the first etch stop layer 230 and exposes most of the first etch stop layer 230 after forming the spacer 244. In some embodiments, the spacer 244 may include silicon nitride. Then, referring to FIG. 12, a second etch stop layer 252 is conformally deposited above the first etch stop layer 230. The second etch stop layer 252 is formed of a different material than the first etch stop layer 230. In some embodiments, the second etch stop layer 252 includes silicon nitride. The choice of material for the second etch stop layer 252 is not unimportant. The second etch stop layer 252 can be an additional etch stop layer or protective layer other than the patterned hard mask layer 242, and can also be used to apply additional stress to the first memory stack 250 (especially the ferroelectric layer 2380). In one example of the process, the second etch stop layer 252 made of silicon nitride is conformally deposited above the first memory stack 250, and an annealing process is performed at an annealing temperature of about 350° C. to about 400° C. to introduce stress into the second etch stop layer 252.The second etch stop layer 252 applies additional stress to stabilize the ferroelectricity in the ferroelectric layer 2380. It is again noted that annealing by itself cannot guarantee the ferroelectricity of the ferroelectric layer 2380.

[0037] After depositing the second etch stop layer 252, a (n+1)th interlevel dielectric layer 254 is deposited above the workpiece 200. The interlevel dielectric layer 254 and the first interlevel dielectric layer 212 share the same composition, and for brevity, a detailed description of the interlevel dielectric layer 254 is omitted. Dual damascene may then be performed to form a (n+1)th through hole 256 and a (n+1)th metal line 258 through the interlevel dielectric layer 254 and the second etch stop layer 252, such that the (n+1)th through hole 256 is physically coupled to the top electrode layer 240. In terms of composition, the (n+1)th through hole 256 and the (n+1)th metal line 258 may be similar to the first through hole 214 and the first metal line 216, and for the sake of brevity, a detailed description of the (n+1)th through hole 256 and the (n+1)th metal line 258 will be omitted. It should be noted that since the through holes and the metal lines are formed by a dual damascene process, each of the through holes and the metal lines may be a continuous structure. The line steps in the drawings between the through holes and the metal lines covered thereon are for the sake of understanding only. Although not explicitly shown in the drawings, the (n+1)th metal layer M may be formed to complete the interconnect structure 201. n+1 More metal layers (e.g., M n+2 , M n+3 etc.) may be formed.

[0038] Reference is now made to FIG. 13, which illustrates an alternative embodiment in which an insulator layer 260 is deposited above the bottom electrode layer 236 before depositing the ferroelectric layer 238. The insulator layer 260 is used to create an imbalance on different sides of the ferroelectric layer 2380. As indicated by research, the introduction of a thin insulator layer on one side (e.g., the bottom side shown in FIG. 13) can make the on-resistance and off-resistance of the first memory stack 250 more distinguishable or detectable. That is, in some embodiments, the introduction of the insulator layer 260 can improve the signal-to-noise ratio (SNR) of the first memory stack 250. In some embodiments, the insulator layer 260 can include nickel oxide, hafnium oxide, zinc oxide, titanium oxide, silicon oxide, zirconium oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide, or copper oxide, and can be deposited by chemical vapor deposition or atomic layer deposition. Although zinc oxide has been mentioned as a candidate material for the top electrode layer 240 and the insulator layer 260, it should be noted that the zinc oxide used for the top electrode layer 240 and the zinc oxide used for the insulator layer 260 have different oxygen contents. The oxygen content of the zinc oxide used for the top electrode layer 240 is smaller than that of the insulator layer 260. To ensure that the insulator layer 260 can fulfill its role of improving the signal-to-noise ratio of the first memory stack 250, the composition of the insulator layer 260 is different from the composition of the ferroelectric layer 238. The insulator layer 260 may have a thickness of about 1 nm to about 10 nm. If the thickness is smaller than 1 nm, the insulator layer 260 does not improve the signal-to-noise ratio of the first memory stack 250. If the thickness is larger than 10 nm, the insulator layer 260 may result in too large a resistance. In the method 100 , the insulator layer 260 may be deposited in step 112 just before depositing the ferroelectric layer 238 .

[0039] 14 illustrates a method 400 in which a single contact hole is not formed to physically couple the bottom electrode layer to the top metal line 226. As will be apparent from the following description of method 400, some steps of method 400 are similar to corresponding steps of method 100. For example, the operations of step 402 may be similar to the operations of step 102, the operations of step 404 may be similar to the operations of step 104, the operations of step 406 may be similar to the operations of step 106, the operations of step 414 may be similar to the operations of step 116, the operations of step 416 may be similar to the operations of step 118, and the operations of step 418 may be similar to the operations of step 120. For the sake of brevity, the description of these similar steps in method 400 may be reduced or even omitted.

[0040] 14 and 2, method 400 includes, in step 402, providing a workpiece 200. The operations of step 402 are similar to those of step 102 of method 100, and therefore, for the sake of brevity, a detailed description of step 402 will be omitted.

[0041] 14 and 3, the method 400 includes depositing a first etch stop layer 230 over the workpiece 200 in step 404. The operations of step 404 are similar to those of step 104 of the method 100, and therefore a detailed description of step 404 will be omitted for brevity.

[0042] 14 and 4, the method 400 includes, in step 406, forming an opening 232 through the first etch stop layer 230 to expose the top metal line 226. Because the operations of step 406 are similar to those of step 106 of the method 100, a detailed description of step 406 will be omitted for the sake of brevity.

[0043] 14 and 15, the method 400 includes depositing a bottom electrode layer 266 over the opening 232 and the first etch stop layer 230 in step 408. The operation of step 408 distinguishes the method 400 from the method 100 because the bottom electrode layer 266 is deposited over the workpiece 200 when the contact hole 234 (shown in FIG. 5) has not been previously formed. As shown in FIG. 15, the bottom electrode layer 266 is conformally deposited over the first etch stop layer 230, the exposed top metal line 226, and the opening 232 to physically contact the exposed top surface of the top metal line 226. In some embodiments, the bottom electrode layer 266 includes tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), tungsten (W), platinum (Pt), ruthenium (Ru), iridium (Ir), or molybdenum (Mo). It should be noted that the bottom electrode layer 266 is not formed of a metal oxide that is opaque and semi-transparent or transparent, since it does not play a role in allowing the transmission of laser radiation. In some examples, the bottom electrode layer 266 may have a thickness of about 10 nm to about 20 nm. This thickness range is not insignificant. If the thickness is less than 10 nm, the bottom electrode layer 266 may be poorly conductive due to the conduction mechanism at this thickness. If the thickness is greater than 20 nm, a bottom electrode layer 266 formed of a low-conductivity material, such as titanium nitride (TiN), may result in too much resistance. Due to the conformality of the deposition of the bottom electrode layer 266, the bottom electrode layer 266 may include a groove or recess located directly above the opening 232.

[0044] 14 and 16, the method 400 includes, at step 410, depositing a ferroelectric layer 268 above the bottom electrode layer 266. The ferroelectric layer 268 may be a binary oxide, a ternary oxide, a ternary nitride, or a quaternary oxide that exhibits ferroelectric properties. The ferroelectric layer 268 may be a hafnium oxide, a hafnium silicate (HfSiO x ), hafnium zirconate (HfZrO x), barium titanate (BaTiO3), lead titanate (PbTiO3), strontium titanate (SrTiO3), calcium manganite (CaMnO3), bismuth ferrite (BiFeO3), aluminum scandium nitride (AlScN), aluminum gallium nitride (AlGaN), aluminum yttrium nitride (AlYN), doped HfO2 (dopants are e.g. Si, Zr, Y, Al, Gd, Sr, La, Sc, Ge, etc.), lead zirconate titanate (PbZr x Ti y O z ), barium strontium titanate (BaSrTiO x ) or strontium bismuth tantalate (SrBi2Ta2O9). In one embodiment, the ferroelectric layer 268 includes zirconium-doped hafnium oxide or hafnium zirconium oxide. As shown in FIG. 16, the ferroelectric layer 268 may be conformally deposited over the workpiece 200, including over the bottom electrode layer 266 and its recess, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. It should be noted that when deposited in step 410, the ferroelectric layer 268 may not exhibit ferroelectricity (or at least does not exhibit sufficient ferroelectricity) because the deposition method of the ferroelectric layer 268 does not cause the ferroelectric layer 268 to have sufficient crystallinity. In this respect, the ferroelectric layer 268 deposited in step 410 may be considered a ferroelectric precursor. As described above, the ferroelectric layer 268 is sufficiently thin to enable quantum mechanical tunneling. In some examples, the ferroelectric layer 268 may have a thickness of about 1 nm to about 10 nm. The thickness of the ferroelectric layer 268 is less than the thickness of the bottom electrode layer 266. Due to the conformality of the ferroelectric layer 268, the recesses or grooves in the bottom electrode layer 266 can also be transferred to the ferroelectric layer 268.

[0045] 14 and 17, the method 400 includes depositing a top electrode layer 270 above the ferroelectric layer 268 at step 412. The top electrode layer 270 is formed of an optically transparent conductive material. In some embodiments, the top electrode layer 270 is formed of a conductive metal oxide, such as indium tin oxide, zinc oxide, fluorine doped tin oxide, zinc gallium oxide, zinc aluminum oxide, antimony tin oxide, and the like. In accordance with the present disclosure, the top electrode layer 270 is formed of a material that allows at least a portion of the radiation of the laser source to pass through. In some examples, the transmittance of the top electrode layer 270 may be greater than 30%, otherwise defeating the purpose of having an optically transparent top electrode layer 270. That is, the top electrode layer 270 is semi-transparent or transparent to the radiation from the laser source. A laser source as used herein refers to a laser source used in laser annealing operations. Examples of laser sources include helium neon laser sources, neodymium doped yttrium aluminum garnet laser sources, argon ion laser sources, continuous wave argon laser sources, krypton ion laser sources, gallium arsenide diode laser sources, or helium cadmium laser sources. Most of these example laser sources emit radiation in the visible spectrum, so the top electrode layer 270 may be considered semi-transparent or transparent to visible light. In some examples, the top electrode layer 270 may have a thickness of about 10 nm to about 20 nm. If the thickness is less than 10 nm, the top electrode layer 270 may be poorly conductive due to the conduction mechanism at this thickness. If the thickness is greater than 20 nm, the top electrode layer 270 formed of a metal oxide with low conductivity may result in too much resistance. Although not explicitly shown in the drawings, the operation of step 412 may include performing a low temperature annealing on the top electrode layer 270 to improve the optical transparency and electrical conductivity of the top electrode layer 270. In some examples, the low temperature annealing may include the use of an oven and an annealing temperature of between 100° C. and about 200° C. The top electrode layer 270 may be conformally deposited above the ferroelectric layer 268 by physical vapor deposition or chemical vapor deposition.The conformality of the top electrode layer 270 allows the recesses or grooves in the ferroelectric layer 268 to be transferred to the top electrode layer 270 .

[0046] 14 and 18, the method 400 includes performing laser annealing 300 on the ferroelectric layer 268 in step 414. As described above, the as-deposited ferroelectric layer 268 may lack crystallinity and therefore may not exhibit ferroelectricity. To increase the crystallinity in the ferroelectric layer 268, the laser annealing 300 is performed in step 414. Although the laser annealing 300 is shown in FIG. 18 as a simultaneous irradiation of the entire workpiece 200, the laser annealing 300 may include scanning or stepping over substantially the entire top surface of the top electrode layer 270. As in the operation generally described for step 412 above, the top electrode layer 270 is semi-transparent or transparent to the laser source radiation from the laser annealing operation (e.g., laser annealing 300 in FIG. 18). The radiation from the laser annealing 300 can still penetrate at least partially through the entire thickness of the top electrode layer 270 and effectively reach the underlying ferroelectric layer 268. However, underlying layers (e.g., bottom electrode layer 266 or first etch stop layer 230) block the radiation from reaching the FEOL structures of device 20, etc. Thus, by having an optically transparent top electrode layer 270 above ferroelectric layer 268, laser annealing 300 can effectively anneal ferroelectric layer 268 to promote crystallization and ferroelectricity without significant risk of damaging the FEOL structures. In some embodiments, laser annealing 300 can include use of a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source, etc., and can include an annealing temperature of about 400° C. to about 1000° C. This range of annealing temperatures is not insignificant. If the annealing temperature is lower than 400° C., the crystallization of the ferroelectric layer 268 is slow, and the laser annealing 300 may not achieve sufficient crystallization of the ferroelectric layer 268 to ensure the ferroelectric properties.If the annealing temperature is higher than 1000° C., the thermal energy may damage the upper metal line 226 or the upper through-hole 224. To illustrate the effect of the laser annealing 300, the ferroelectric layer 268 after annealing is re-labeled as ferroelectric layer 2680. Although the ferroelectric layer 2680 and the ferroelectric layer 268 share the same composition, the ferroelectric layer 2680 is more crystallized and exhibits higher ferroelectricity.

[0047] It has been observed that the ferroelectric layer 268 does not form a ferroelectric phase when annealed without receiving strain from the top electrode layer 270. It has been found that the top electrode layer 270, like the top electrode layer 240 described above, provides several functions: First, the top electrode layer 270 serves as the top electrode of the memory stack. To provide this function, the top electrode layer 270 is conductive. Second, the top electrode layer 270 applies a tensile stress to the ferroelectric layer 268 so that the ferroelectric layer 268 can exhibit a ferroelectric crystalline phase. In this respect, the top electrode layer 270 serves as a stress source or strain layer. Third, the top electrode layer 270 of the present disclosure is semi-transparent or transparent to the radiation of the laser source used for the laser annealing 300.

[0048] 14 and 19, the method 400 includes patterning the bottom electrode layer 266, the ferroelectric layer 2680, and the top electrode layer 270 to form the second memory stack 280 in step 416. After performing laser annealing 300 on the ferroelectric layer 268 through the top electrode layer 270 in step 414, a combination of photolithography and etching processes is performed to pattern the bottom electrode layer 266, the ferroelectric layer 2680, and the top electrode layer 270. In one example of the process, a hard mask layer 272 is blanket deposited by chemical vapor deposition above the top electrode layer 270. The hard mask layer 272 may include silicon oxide, silicon nitride, or silicon oxynitride. As shown in FIG. 19, in some embodiments, a portion of the hard mask layer 272 may extend partially into the recess or groove in the top electrode layer 270. In some embodiments shown in FIG. 19, the top surface of the hard mask layer 272 may feature recesses or grooves. Note that the composition of the hard mask layer 272 is different from the composition of the first etch stop layer 230. A photoresist layer is then deposited above the hard mask layer 272 by spin coating. The deposited photoresist layer may undergo a pre-exposure bake process, exposure to radiation reflected from or transmitted through a photomask, a post-exposure bake process, and a development process to form a patterned photoresist. The hard mask layer 272 is then etched using the patterned photoresist as an etch mask to form the patterned hard mask layer 272. The bottom electrode layer 266, the ferroelectric layer 2680, and the top electrode layer 270 are then etched using the patterned hard mask layer 272 as an etch mask to form the second memory stack 280. A suitable etching process for step 416 may be a dry etching process (e.g., a reactive ion etching process) including the use of an oxygen-containing gas (e.g., O), a fluorine-containing gas (e.g., SF or NF), a chlorine-containing gas (e.g., Cl and / or BCl), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof.19, the second memory stack 280 includes a bottom electrode layer 266, a ferroelectric layer 2680, a top electrode layer 270, and a patterned hard mask layer 272. The ferroelectric layer 2680 has a thickness that allows for quantum mechanical tunneling, such that the second memory stack 280 is a ferroelectric tunnel junction stack or ferroelectric tunnel junction memory device. The second memory stack 280 is disposed directly above the exposed portions of the top metal lines 226 such that the exposed top surfaces of the top metal lines 226 are in physical contact with the bottom surface of the bottom electrode layer 266.

[0049] 14, 20, and 21, the method 400 includes performing further processing in step 418. These further processing in step 418 may include forming spacers 244 (shown in FIG. 20) along sidewalls of the second memory stack 280, depositing a second etch stop layer 252 (shown in FIG. 21) over the second memory stack 280 and the spacers 244, depositing an (n+1)th interlayer dielectric layer 254 (shown in FIG. 21) over the second etch stop layer 252, and forming an (n+1)th through hole 256 and an (n+1)th metal line 258 (shown in FIG. 21) through the interlayer dielectric layer 254 and the second etch stop layer 252. The spacer 244 shown in FIG. 20 may be formed by conformally depositing a spacer material layer above the workpiece 200 (including above the second memory stack 280) and then anisotropically etching back the spacer material layer. As shown in FIG. 20, the spacer 244 is located only above a portion of the first etch stop layer 230, and most of the first etch stop layer 230 is exposed after forming the spacer 244. In some embodiments, the spacer 244 may include silicon nitride. Then, referring to FIG. 21, a second etch stop layer 252 is conformally deposited above the first etch stop layer 230, the spacer 244, and the second memory stack 280. The second etch stop layer 252 is formed of a material different from the first etch stop layer 230. In some embodiments, the second etch stop layer 252 includes silicon nitride. The selection of such a material for the second etch stop layer 252 is not unimportant. The second etch stop layer 252 is used to apply additional stress to the second memory stack 280 (especially the ferroelectric layer 2680) in addition to being an additional etch stop layer or protective layer other than the patterned hard mask layer 272. In one example of the process, the second etch stop layer 252 made of silicon nitride is conformally deposited above the second memory stack 280, and an annealing process is performed at an annealing temperature of about 350° C. to about 400° C. to introduce stress into the second etch stop layer 252.The second etch stop layer 252 applies additional stress to stabilize the ferroelectricity in the ferroelectric layer 2680. It is again noted that annealing by itself cannot guarantee ferroelectricity in the ferroelectric layer 2680.

[0050] After depositing the second etch stop layer 252, a (n+1)th interlevel dielectric layer 254 is deposited above the workpiece 200. The interlevel dielectric layer 254 and the first interlevel dielectric layer 212 share the same composition, and for the sake of brevity, a detailed description of the interlevel dielectric layer 254 is omitted. Dual damascene may then be performed to form a (n+1)th through-hole 256 and a (n+1)th metal line 258 through the interlevel dielectric layer 254 and the second etch stop layer 252, with the (n+1)th through-hole 256 physically coupled to the top electrode layer 270. In the illustrated embodiment, the (n+1)th through-hole 256 also extends through the patterned hard mask layer 272 and partially through the top electrode layer 270, thereby removing any patterned hard mask layer 272 located vertically between the (n+1)th through-hole 256 and the top electrode layer 270. In terms of composition, the (n+1)th through hole 256 and the (n+1)th metal line 258 may be similar to the first through hole 214 and the first metal line 216, and for the sake of brevity, a detailed description of the (n+1)th through hole 256 and the (n+1)th metal line 258 is omitted. It should be noted that since the through holes and the metal lines are formed by a dual damascene process, each of the through holes and the metal lines may be continuous structures. The line steps between the through holes and the metal lines covered thereon in the drawings are shown for understanding only. Although not explicitly shown in the drawings, the (n+1)th metal layer M may be formed to complete the interconnect structure 201. n+1 More metal layers (e.g., M n+2 , M n+3 etc.) may be formed.

[0051] Reference is now made to FIG. 22, which illustrates an alternative embodiment in which an insulator layer 2600 is deposited above the bottom electrode layer 266 before depositing the ferroelectric layer 268. The insulator layer 2600 is used to create an imbalance on different sides of the ferroelectric layer 2680. As indicated by research, the introduction of a thin insulator layer on one side (e.g., the bottom side shown in FIG. 22) can make the on-resistance and off-resistance of the second memory stack 280 more distinguishable or detectable. That is, in some embodiments, the introduction of the insulator layer 2600 can improve the signal-to-noise ratio of the second memory stack 280. In some embodiments, the insulator layer 2600 can include nickel oxide, hafnium oxide, zinc oxide, titanium oxide, silicon oxide, zirconium oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide, or copper oxide, and can be deposited by chemical vapor deposition or atomic layer deposition. Although zinc oxide has been mentioned as a candidate material for the top electrode layer 270 and the insulator layer 2600, it should be noted that the zinc oxide used for the top electrode layer 270 and the zinc oxide used for the insulator layer 2600 have different oxygen contents. The oxygen content of the zinc oxide used for the top electrode layer 270 is smaller than that of the insulator layer 2600. To ensure that the insulator layer 2600 fulfills its role of improving the signal-to-noise ratio of the second memory stack 280, the composition of the insulator layer 2600 is different from the composition of the ferroelectric layer 268. The insulator layer 2600 may have a thickness of about 1 nm to about 10 nm. If the thickness is smaller than 1 nm, the insulator layer 2600 does not improve the signal-to-noise ratio of the second memory stack 280. If the thickness is larger than 10 nm, the insulator layer 2600 may result in too large a resistance. In the method 400 , just before depositing the ferroelectric layer 268 , the insulator layer 2600 may be deposited in step 410 .

[0052] In one exemplary embodiment, the present disclosure relates to a device structure including a conductive feature disposed in a first dielectric layer, a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer located above the bottom electrode layer, and a top electrode layer located on the ferroelectric layer, the device structure comprising a ferroelectric tunnel junction stack disposed above the conductive feature, a spacer disposed along a sidewall of the ferroelectric tunnel junction stack, a second dielectric layer disposed above the spacer and the ferroelectric tunnel junction stack, and a contact hole extending through the second dielectric layer and contacting a top surface of the top electrode layer, the top electrode layer being formed of a conductive metal oxide.

[0053] In some embodiments, the top electrode layer allows radiation from a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source to penetrate the entire depth of the top electrode layer. The top electrode layer comprises indium tin oxide, zinc oxide, fluorine doped tin oxide, zinc gallium oxide, zinc aluminum oxide, or tin antimony oxide. In some embodiments, the ferroelectric layer comprises hafnium oxide, hafnium silicate, hafnium zirconate, barium titanate, lead titanate, strontium titanate, calcium manganite, bismuth ferrite, aluminum scandium nitride, aluminum gallium nitride, aluminum yttrium nitride, lead zirconate titanate, barium strontium titanate, or strontium bismuth tantalate. In some embodiments, the composition of the top electrode layer is different from the composition of the bottom electrode layer. In some embodiments, the bottom electrode layer comprises tantalum nitride, titanium nitride, tantalum, tungsten, platinum, ruthenium, iridium, or molybdenum. In some embodiments, the device structure may further comprise an etch stop layer located above the conductive feature and the first dielectric layer. A portion of the bottom electrode layer extends completely through the etch stop layer. In some embodiments, the composition of the etch stop layer is different from the composition of the spacer. In some embodiments, the spacer comprises silicon nitride and the etch stop layer comprises silicon carbide.

[0054] In another exemplary aspect, the present disclosure relates to a structure comprising: a conductive feature disposed in a first dielectric layer, an etch stop layer located above the conductive feature and the first dielectric layer, a bottom contact hole extending through the etch stop layer to contact the conductive feature, a bottom electrode layer contacting the bottom contact hole, a ferroelectric layer located above the bottom electrode layer, and a top electrode layer located in the ferroelectric layer, and a memory stack disposed in the etch stop layer and the bottom contact hole, the top electrode layer being formed of a conductive material that allows radiation from a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source to penetrate the entire depth of the top electrode layer.

[0055] In some embodiments, the top electrode layer comprises indium tin oxide, zinc oxide, fluorine doped tin oxide, zinc gallium oxide, zinc aluminum oxide, or antimony tin oxide. In some embodiments, the composition of the bottom electrode layer is different from the composition of the top electrode layer. In some embodiments, the structure may further comprise an insulator layer sandwiched between the bottom electrode layer and the ferroelectric layer. The insulator layer comprises nickel oxide, titanium oxide, silicon oxide, zirconium oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide, or copper oxide. In some embodiments, the top electrode layer comprises a first thickness and the ferroelectric layer comprises a second thickness, the second thickness being less than the first thickness.

[0056] In yet another exemplary aspect, the present disclosure relates to a method, the method including providing a workpiece including a conductive feature disposed in a first dielectric layer; depositing an etch stop layer over the workpiece; forming a contact hole through the etch stop layer to contact the conductive feature; depositing a bottom electrode layer over the etch stop layer and the contact hole; depositing a ferroelectric layer over the bottom electrode layer; depositing a top electrode layer over the ferroelectric layer; after depositing the top electrode layer, performing a laser annealing process with a laser source to promote crystallization of the ferroelectric layer; and after the laser annealing process, patterning the bottom electrode layer, the ferroelectric layer, and the top electrode layer to form a memory stack, wherein the top electrode layer is formed of a conductive material that allows transmission of radiation from the laser source.

[0057] In some embodiments, the laser annealing process includes a temperature of about 400° C. to about 1000° C. In some embodiments, the laser source includes a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source. In some embodiments, the top electrode layer includes a conductive metal oxide. In some embodiments, the top electrode layer includes indium tin oxide, zinc oxide, fluorine doped tin oxide, gallium zinc oxide, aluminum zinc oxide, or antimony tin oxide. In some embodiments, the ferroelectric layer includes a first depth of about 1 nm to about 10 nm, and the top electrode layer includes a second depth of about 10 nm to about 20 nm.

[0058] The above outlines the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0059] 20 equipment 100, 400 ways 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 402, 404, 406, 408, 410, 412, 414, 416, 418 steps 200 Workpieces / equipment structure 201 Interconnect Structure 202 Substrate 204 Active area 206 Gate Structure 208 Source / Drain Region 212 First interlayer dielectric layer 214 First through hole 216 First Metal Wire 222 Interlayer dielectric layer 224 Upper through hole 226 Upper metal wire 230 First Etching Stop Layer 232 Aperture 234 Contact Hole 236, 266 lower electrode layer 238, 268, 2380, 2680 Ferroelectric layer 240 Upper electrode layer 242 Hard Mask Layer 244 Spacer 250 First Memory Stack 252 Second Etch Stop Layer 254 Interlayer Dielectric Layer 256 through hole 258 Metal Wire 260, 2600 Insulator layer 270 Upper electrode layer 272 Hard Mask Layer 280 Secondary Memory Stack 300 Laser Annealing M1 First metal layer M n nth metal layer M n+1 (n+1)th metal layer X, Y, Z directions

Claims

1. a metal line disposed within the first dielectric layer; an etch stop layer overlying the metal lines and the first dielectric layer; a ferroelectric tunnel junction stack disposed above the metal line, the ferroelectric tunnel junction stack comprising: a bottom electrode layer electrically coupled to the metal line, at least a portion of the bottom electrode layer being disposed on the etch stop layer; a ferroelectric layer disposed above the bottom electrode layer, the ferroelectric layer being in a crystalline phase, the ferroelectric layer crystallizing at an annealing temperature of 400° C. to 1000° C.; a top electrode layer disposed on the ferroelectric layer; and an insulator layer sandwiched between the bottom electrode layer and the ferroelectric layer, the insulator layer and the top electrode layer both comprising zinc oxide, the insulator layer having a different oxygen content than the zinc oxide in the top electrode layer and the zinc oxide in the insulator layer. spacers disposed along sidewalls of the ferroelectric tunnel junction stack; a second dielectric layer disposed above the spacer and the ferroelectric tunnel junction stack; a contact hole extending through the second dielectric layer and contacting a top surface of the upper electrode layer; Equipped with The device structure wherein the top electrode layer is formed from a conductive metal oxide.

2. 2. The device structure of claim 1, wherein the top electrode layer allows radiation from a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source to penetrate to an entire depth of the top electrode layer.

3. 3. A device structure according to claim 1 or 2, wherein the composition of the top electrode layer is different from the composition of the bottom electrode layer.

4. 3. The device structure of claim 1 or 2, wherein the remaining portion of the bottom electrode layer extends completely through the etch stop layer.

5. The device structure of claim 4 , wherein the composition of the etch stop layer is different from the composition of the spacer.

6. a metal line disposed within the first dielectric layer; an etch stop layer overlying the metal lines and the first dielectric layer; a bottom contact hole extending through the etch stop layer to contact the metal line; a bottom electrode layer contacting the bottom contact hole; a ferroelectric layer located above the bottom electrode layer, the ferroelectric layer being in a crystalline phase, the ferroelectric layer being crystallized at an annealing temperature of 400°C to 1000°C; a top electrode layer located on the ferroelectric layer; and an insulator layer sandwiched between the bottom electrode layer and the ferroelectric layer, the insulator layer and the top electrode layer both comprising zinc oxide, the zinc oxide in the top electrode layer having a different oxygen content from the zinc oxide in the insulator layer; and a memory stack disposed on the etch stop layer and the bottom contact hole; Equipped with The top electrode layer is formed of a conductive material that allows radiation from a helium neon laser source, a neodymium doped yttrium aluminum garnet laser source, an argon ion laser source, a continuous wave argon laser source, a krypton ion laser source, a gallium arsenide diode laser source, or a helium cadmium laser source to penetrate through the entire depth of the top electrode layer.

7. the top electrode layer comprises a first thickness; the ferroelectric layer includes a second thickness; 7. The structure of claim 6, wherein the second thickness is less than the first thickness.

8. providing a workpiece including a metal line disposed within a first dielectric layer; depositing an etch stop layer over the workpiece; forming a contact hole through the etch stop layer to contact the metal line; depositing a bottom electrode layer over the etch stop layer and the contact hole; depositing an insulator layer over the bottom electrode layer, the insulator layer and the top electrode layer both comprising zinc oxide, the zinc oxide in the top electrode layer having a different oxygen content than the zinc oxide in the insulator layer; depositing a ferroelectric layer over the bottom electrode layer and the insulator layer; depositing the top electrode layer above the ferroelectric layer; After depositing the top electrode layer, performing a laser annealing process by a laser source to promote crystallization of the ferroelectric layer, the laser annealing process comprising a temperature of 400° C. to 1000° C.; after the laser annealing process, patterning the bottom electrode layer, the ferroelectric layer and the top electrode layer to form a memory stack; Including, The method wherein the top electrode layer is formed of a conductive material that allows transmission of radiation from the laser source.

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