Photoelectric conversion device

Abstract

To provide a photoelectric conversion device that reduces the influence of a variation in potential of ground wiring to improve the accuracy of an output signal.SOLUTION: A photoelectric conversion device has a pixel array 10, a load circuit 32, a sample hold unit 42, and an AD conversion circuit 52, which are arranged in an element area R1. A first sample hold unit 44S acquires pixel signals output from pixels 12 through a column signal line 16 and holds the signals. A second sample hold unit 44N acquires reset signals output from the pixels 12 through the column signal line 16 and holds the signals. The second sample hold unit 44N supplies current based on the reset signals held therein to the first sample hold unit 44S. The first sample hold unit 44S outputs current based on the difference between the pixel signals and the reset signals to the AD conversion circuit 52. Ground wiring GL1 of the first sample hold unit 44S and ground wiring GL2 of the second sample hold unit 44N are made common to each other in a node N1.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device equipped with a sample-and-hold unit that holds signals output from pixels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] In the photoelectric conversion device as described in Patent Document 1, there is a demand for further improvement in accuracy.

[0005] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, an object of the present invention is to provide a photoelectric conversion device with improved accuracy. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a photoelectric conversion device having a pixel array in which a plurality of pixels, each of which generates a first signal based on incident light and a second signal based on a reset state, are arranged in a plurality of columns, and a column circuit arranged corresponding to each of the plurality of columns of the pixel array, wherein the column circuit has a first sample-and-hold unit that holds the first signal, a second sample-and-hold unit that holds the second signal, a delta-sigma type analog-to-digital conversion circuit that converts an analog signal based on outputs from the first sample-and-hold unit and the second sample-and-hold unit into a digital signal, a first potential line that supplies a drive potential to the first sample-and-hold unit, and a second potential line that supplies a drive potential to the second sample-and-hold unit, and the first potential line and the second potential line are shared in the photoelectric conversion device. a node at which the first potential line and the second potential line are common is provided corresponding to each of the plurality of column circuits. The present invention provides a photoelectric conversion device comprising:

[0007] According to another aspect of the present invention, a pixel array in which a plurality of pixels, each of which generates a first signal based on incident light and a second signal based on a reset state, are arranged in a plurality of columns; and column circuits arranged corresponding to each of the plurality of columns of the pixel array, the column circuits including a first sample-and-hold unit which holds the first signal, a second sample-and-hold unit which holds the second signal, a delta-sigma analog-to-digital conversion circuit which converts an analog signal based on outputs from the first sample-and-hold unit and the second sample-and-hold unit into a digital signal, a first potential line which supplies a drive potential to the first sample-and-hold unit, and a second potential line which supplies a drive potential to the second sample-and-hold unit, the first potential line and the second potential line being common in the photoelectric conversion device, and a node at which the first potential line and the second potential line are common is provided in common for a plurality of the column circuits. The present invention provides a photoelectric conversion device comprising:

[0008] According to another aspect of the present invention, a first sample-and-hold unit including a first inverting amplifier and a first source follower circuit connected in cascade and configured to hold the first signal; a second sample-and-hold unit including a second inverting amplifier and a second source follower circuit connected in cascade and configured to hold the second signal; a first potential line supplying a drive potential to at least one of the first inverting amplifier and the first source follower circuit; and a second potential line supplying a drive potential to at least one of the second inverting amplifier and the second source follower circuit, the first potential line and the second potential line being common in the photoelectric conversion device; and a node at which the first potential line and the second potential line are common is provided corresponding to each of the plurality of column circuits. The present invention provides a photoelectric conversion device comprising: According to another aspect of the present invention, there is provided a photoelectric conversion device having a pixel array in which a plurality of pixels, each of which generates a first signal based on incident light and a second signal based on a reset state, are arranged in a plurality of columns, and column circuits arranged corresponding to each of the plurality of columns of the pixel array, wherein the column circuit includes a first inverting amplifier and a first source follower circuit connected in cascade and has a first sample hold unit that holds the first signal, a second inverting amplifier and a second source follower circuit that are connected in cascade and have a second sample hold unit that holds the second signal, a first potential line that supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit, and a second potential line that supplies a drive potential to at least one of the second inverting amplifier and the second source follower circuit, the first potential line and the second potential line are common in the photoelectric conversion device, and a node at which the first potential line and the second potential line are common is provided in common for a plurality of the column circuits. Effect of the Invention

[0009] According to the present invention, a photoelectric conversion device with improved accuracy is provided. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Diagram 3] 4 is a timing chart illustrating a readout operation of a signal from a pixel according to the first embodiment. [Figure 4] FIG. 2 is a block diagram showing a circuit configuration and wiring connections for one column according to the first embodiment. [Diagram 5] 4 is a block diagram showing a configuration of a second sample-and-hold unit for a reset signal in the first embodiment. FIG. [Figure 6] 4 is a block diagram showing a configuration of a first sample-and-hold unit for pixel signals according to the first embodiment. FIG. [Figure 7] 2 is a block diagram showing a configuration of an AD conversion unit according to the first embodiment. FIG. [Figure 8] FIG. 11 is a block diagram showing a circuit configuration and wiring connections for one column according to a second embodiment. [Figure 9] FIG. 11 is a block diagram showing a circuit configuration and wiring connections for one column according to a third embodiment. [Figure 10] FIG. 13 is a block diagram showing a configuration of an AD conversion unit according to a third embodiment. [Figure 11] FIG. 13 is a block diagram showing a circuit configuration and wiring connections for one column according to a fourth embodiment. [Figure 12] FIG. 13 is a block diagram showing a circuit configuration and wiring connections for one column according to a fifth embodiment. [Figure 13] FIG. 13 is a block diagram showing a circuit configuration and wiring connections for one column according to a sixth embodiment. [Figure 14] FIG. 13 is a block diagram showing a configuration of an AD conversion unit according to a seventh embodiment. [Figure 15] FIG. 13 is a block diagram showing an arrangement of a sample-and-hold unit according to the eighth embodiment. [Figure 16] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a ninth embodiment. [Figure 17] FIG. 23 is a diagram illustrating an example of the configuration of an imaging system and a moving object according to a tenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same elements or corresponding elements in multiple drawings are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

[0012] [First embodiment] FIG. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device 100 according to the present embodiment. The photoelectric conversion device 100 includes a pixel array 10, a vertical scanning circuit 20, a load circuit section 30, a signal holding section 40, an analog-to-digital conversion section (AD conversion section) 50, a digital memory section 60, a horizontal scanning circuit 64, a digital signal processing section 70, an output section 80, and a control circuit 90. These circuits may be formed on one or more semiconductor substrates. Note that the photoelectric conversion device 100 of the present embodiment is an imaging device that acquires an image, but is not limited thereto. For example, the photoelectric conversion device may be a focus detection device, a distance measuring device, a TOF (Time-Of-Flight) camera, or the like.

[0013] The pixel array 10 includes a plurality of pixels 12 arranged in a plurality of rows and a plurality of columns. The vertical scanning circuit 20 is a scanning circuit that supplies control signals for controlling transistors included in the pixels 12 to be on (conductive state) or off (non-conductive state) via control signal lines 14 provided in each row of the pixels 12. The vertical scanning circuit 20 may be configured with a shift register or an address decoder. Here, the control signals supplied to each pixel 12 may include a plurality of types of control signals, and therefore the control signal lines 14 in each row may be configured as a set of a plurality of drive wirings. A column signal line 16 is provided in each column of the pixels 12, and signals from the pixels 12 are read out to the column signal line 16 for each column.

[0014] The load circuit section 30 has load circuits 32 corresponding to each column of the pixels 12. The load circuits 32 supply bias currents to the column signal lines 16 of the corresponding columns for reading out signals from the pixels 12. The signal holding section 40 has sample and hold sections 42 corresponding to each column of the pixels 12. The sample and hold sections 42 hold signals output from the pixels 12.

[0015] The AD conversion unit 50 has analog-to-digital conversion circuits (AD conversion circuits) 52 corresponding to each column of the pixels 12. The AD conversion circuits 52 convert an analog signal based on the signal held in the sample and hold unit 42 into a digital signal. The digital memory unit 60 has digital memories 62 corresponding to each column of the pixels 12. The digital memories 62 store the digital signals output from the AD conversion unit 50.

[0016] The horizontal scanning circuit 64 supplies a control signal for controlling the output of digital signals from the digital memory unit 60 to the digital signal processing unit 70 sequentially for each column. The horizontal scanning circuit 64 may be configured with a shift register or an address decoder. The digital signal processing unit 70 is a circuit that performs various signal processing on the input digital signal. The output unit 80 outputs the processed digital signal to the outside of the photoelectric conversion device 100. The control circuit 90 controls the operation timing of the vertical scanning circuit 20, the load circuit unit 30, the signal holding unit 40, the analog-to-digital conversion unit (AD conversion unit) 50, the digital memory unit 60, the horizontal scanning circuit 64, and the output unit 80, etc.

[0017] As described above, the load circuit 32, the sample and hold unit 42, the AD conversion circuit 52, and the digital memory 62 are arranged corresponding to each column of the pixel array 10. These circuits for reading out signals corresponding to each column of the pixel array 10 are sometimes called column circuits.

[0018] 2 is a circuit diagram of a pixel 12 according to this embodiment. The pixel 12 includes a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. These transistors may be configured as N-type MOS transistors having a gate electrode as a control electrode. Control signals PTX, PRES, and PSEL for controlling these transistors are input to the gates of the transfer transistor M1, the reset transistor M2, and the selection transistor M4 from the vertical scanning circuit 20 via a control signal line 14, respectively.

[0019] The photoelectric conversion unit PD is a photoelectric conversion element that generates charges according to incident light by photoelectric conversion and accumulates the charges. The photoelectric conversion unit PD may be composed of a photodiode formed in a semiconductor substrate. The anode of the photodiode constituting the photoelectric conversion unit PD is connected to a potential line having a ground potential GND, and the cathode is connected to the source of the transfer transistor M1.

[0020] The drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected to each other. This connection node is a so-called floating diffusion. When the transfer transistor M1 is turned on, it transfers the charge of the photoelectric conversion unit PD to the floating diffusion. The floating diffusion has a capacitance, and due to this capacitance, the potential of the floating diffusion changes according to the charge transferred from the photoelectric conversion unit PD.

[0021] The drain of the reset transistor M2 and the drain of the amplifying transistor M3 are connected to a potential line having a power supply potential VDD. The source of the amplifying transistor M3 is connected to the drain of the selecting transistor M4. The source of the selecting transistor M4 is connected to the column signal line 16. The amplifying transistor M3 forms a source follower circuit together with a current source in a load circuit 32 connected to the column signal line 16. This source follower circuit outputs a signal based on the voltage of the floating diffusion to the column signal line 16 via the selecting transistor M4. The reset transistor M2 resets the potential of the floating diffusion by being turned on.

[0022] Each pixel 12 may have a microlens and a color filter arranged on an optical path from incident light to the photoelectric conversion unit PD. The microlens focuses the incident light on the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0023] Fig. 3 is a timing chart for explaining the operation of reading out a signal from the pixel 12 according to this embodiment. Fig. 3 shows the timing of the control signals PSEL, PRES, and PTX output from the vertical scanning circuit 20 to one row of the pixels 12, and the output potential VOUT output from the pixel 12 to the column signal line 16 of the corresponding column.

[0024] At time T1, the control signal PSEL goes high, turning on the selection transistor M4, selecting the pixel 12 in the row, and outputting a signal based on the voltage of the floating diffusion to the column signal line 16.

[0025] At time T2, the control signal PRES goes high and then goes low. This operation temporarily turns on the reset transistor M2, and the potential of the floating diffusion is reset to a potential corresponding to the power supply potential VDD. As a result, the output potential VOUT becomes a potential based on the reset state of the pixel 12. This potential is held in the sample-and-hold unit 42 as a reset signal (second signal).

[0026] At time T3, the control signal PTX goes to high level and then goes to low level. This operation temporarily turns on the transfer transistor M1, and the charge accumulated in the photoelectric conversion unit PD is transferred to the floating diffusion. As a result, the output potential VOUT becomes a potential based on the charge accumulated in the photoelectric conversion unit PD in response to the incident light. This potential is held in the sample hold unit 42 as a pixel signal (first signal).

[0027] At time T4, the control signal PSEL goes to low level, which turns off the selection transistor M4 and deselects the pixels 12 in the row.

[0028] Fig. 4 is a block diagram showing the circuit configuration and wiring connections of one column according to this embodiment, in which the pixels 12 and some blocks of the column circuit corresponding to the pixels 12 described in Fig. 1 are shown in a form extracted for only one column.

[0029] 4 also shows an element region R1 of the photoelectric conversion device 100 in which the pixel array 10, column circuits, etc. are arranged, and a pad region R2 in which pads that are external terminals for supplying a driving potential from the outside to the photoelectric conversion device 100 are arranged. The element region R1 and the pad region R2 may be arranged in different regions on a semiconductor substrate. FIG. 4 also shows that the pixel array 10, the load circuit 32, the sample hold unit 42, and the AD conversion circuit 52 are arranged in the element region R1. FIG. 4 also shows that the pads P1, P2, P3, and P4 are arranged in the pad region R2. The pads P1, P2, P3, and P4 may be, for example, metal films to which mounting members such as bonding wires and bumps are connected.

[0030] In the following description, the pads P1, P2, P3, and P4 are assumed to be ground terminals for supplying a ground potential, but these pads may be power supply terminals for supplying a power supply potential or reference potential terminals for supplying a reference potential in each circuit. The ground potential, power supply potential, and reference potential are sometimes referred to as drive potentials as a more general term. In other words, the pads P1, P2, P3, and P4 may be external terminals for supplying drive potentials to each circuit of the photoelectric conversion device 100.

[0031] The pixel array 10 has a plurality of pixels 12, and the ground wiring of the pixels 12 is connected to a pad P1. The load circuit 32 has a current source 34 connected to the column signal line 16. The ground wiring of the current source 34 is connected to a pad P2.

[0032] The sample hold unit 42 has a first sample hold unit 44S, a second sample hold unit 44N, and a resistor R. The column signal line 16 is connected to the first sample hold unit 44S and the second sample hold unit 44N. The first sample hold unit 44S acquires and holds a pixel signal output from the pixel 12 via the column signal line 16. The second sample hold unit 44N acquires and holds a reset signal output from the pixel 12 via the column signal line 16.

[0033] The second sample hold unit 44N is connected to the first sample hold unit 44S via a signal line IL1, a resistor R, and a signal line IL2 in that order. This allows the second sample hold unit 44N to supply a current based on the held reset signal to the first sample hold unit 44S. The first sample hold unit 44S outputs a current based on the difference between the pixel signal and the reset signal to the AD conversion circuit 52 via a signal line IL3. This allows correction processing to be performed by correlated double sampling of the pixel signal and the reset signal.

[0034] The ground wiring GL1 (first potential line) of the first sample hold unit 44S and the ground wiring GL2 (second potential line) of the second sample hold unit 44N are shared at a node N1 outside the element region R1. The shared ground wiring is connected to a pad P3. The node N1 may be in the element region R1 or the pad region R2, and it is sufficient that the ground wiring is shared at least on the sample hold unit 42 side from the pad P3. The ground wiring GL3 (third potential line) of the AD conversion circuit 52 is connected to a pad P4.

[0035] 5 is a block diagram showing the configuration of a second sample-and-hold section 44N for a reset signal according to the present embodiment. The second sample-and-hold section 44N has a sample-and-hold circuit group 46N and an amplifier section 48N.

[0036] The sample and hold circuit group 46N includes N sample and hold circuits 462N1 to 462N n ~462N N(N is an integer of 2 or more, and n is an integer of 1 or more and less than N). The sample-and-hold circuit 462N1 has switches S11 and S21 and a capacitance C11. n is switch S1 n , S2 n and capacity C1 n In this way, the sample and hold circuits 462N1 to 462N N-1 Each of the sample and hold circuits 462N has two switches and one capacitance. N is switch S1 N and capacity C1 N It has.

[0037] The amplifier 48N includes an inverting amplifier 482N, a transistor M5, a current source 484N, and switches S3, S4, and S5. The transistor M5 is a P-type MOS transistor. The sample-and-hold circuit group 46N and the multiple switches included in the amplifier 48N are controlled to be turned on or off based on the control from the control circuit 90.

[0038] The column signal line 16 is connected to the switches S11 to S1 N The second terminal of the switch S11 is connected to a first terminal of the switch S21 and a first terminal of the capacitor C11. The second terminal of the switch S21 is connected to a second terminal of the switch S12, a first terminal of the switch S22, and a first terminal of the capacitor C12 included in the adjacent sample hold circuit 462N2. N-1 The switch S1 has a similar configuration. N The second terminal of the switch S2 N-1 The second terminal of the capacitor C1 N The capacitors C11 to C1 are connected to a first terminal of the capacitor C11 and a first terminal of the switch S4. N The second terminal of the switch S3 is connected to the input terminal of an inverting amplifier 482N and to a first terminal of a switch S3.

[0039] The output terminal of the inverting amplifier 482N is connected to the second terminal of the switch S3 and the first terminal of the switch S5. The second terminal of the switch S5 is connected to the gate of the transistor M5. The second terminal of the switch S4 is connected to the current source 484N and the source of the transistor M5. The power supply terminal of the current source 484N is connected to a potential line having a power supply potential VDD. The connection node of the second terminal of the switch S4, the current source 484N, and the source of the transistor M5 forms the output terminal of the second sample-and-hold unit 44N and is connected to the signal line IL1. The ground terminal of the inverting amplifier 482N and the drain of the transistor M5 are connected to the ground wiring GL2.

[0040] In this manner, the amplifier 48N forms an amplifier circuit in which an inverting amplifier 482N (second inverting amplifier) ​​and a source follower circuit (second source follower circuit) constituted by a current source 484N and a transistor M5 are connected in series. N A current according to the voltage held in the capacitor can be output to the signal line IL1.

[0041] 6 is a block diagram showing the configuration of a first sample-and-hold unit 44S for pixel signals according to the present embodiment. The first sample-and-hold unit 44S has a sample-and-hold circuit group 46S and an amplifier unit 48S.

[0042] The sample-and-hold circuit group 46S includes N sample-and-hold circuits 462S1 to 462S n ~462S N The sample-and-hold circuit 462S1 includes switches S61 and S71 and a capacitor C21. n Switch S6 n , S7 n and capacity C2 n In this manner, the sample and hold circuits 462S1 to 462S N-1 The sample-and-hold circuit 462S has two switches and one capacitor. N Switch S6 N and capacity C2N The connections of the circuits in the sample-and-hold circuit group 46S are similar to those in the sample-and-hold circuit group 46N, and therefore will not be described.

[0043] The amplifier 48S includes an inverting amplifier 482S, a transistor M6, a current source 484S, and switches S8, S9, and S10. The transistor M6 is a P-type MOS transistor. The sample-and-hold circuit group 46S and the multiple switches included in the amplifier 48S are controlled to be turned on or off based on the control from the control circuit 90.

[0044] The connections of the inverting amplifier 482S, the transistor M6, the current source 484S, and the switches S8, S9, and S10 are generally similar to those of the amplifier 48N. Therefore, the following will describe the differences from the amplifier 48N.

[0045] A connection node between the second terminal of the switch S9, the current source 484S, and the source of the transistor M6 is connected to a signal line IL2. A current is input to this node from the second sample-and-hold unit 44N. A ground terminal of the inverting amplifier 482S is connected to the ground wiring GL1. A drain of the transistor M6 serves as an output terminal of the first sample-and-hold unit 44S and is connected to a signal line IL3.

[0046] The amplifier 48S is an amplifier circuit in which an inverting amplifier 482S (first inverting amplifier) ​​and a source follower circuit (first source follower circuit) constituted by a current source 484S and a transistor M6 are connected in series. N and a current input from signal line IL2.

[0047] 3 to 6, an outline of the operation of the sample-and-hold unit 42 will be described. During the output period of the reset signal from time T2 to time T3 in FIG. N , S3, S6 n+1 ~S6N During this period, the other switches are in the off state. After that, the switches S11 to S1 N , S3, S6 n+1 ~S6 N , S8 is turned off. By these operations, the capacitances C11 to C1 N , C2 n+1 ~C2 N A voltage based on the reset signal is held in the

[0048] After that, during the pixel signal output period from time T3 to time T4 in FIG. N―1 , S4, S5, S61~S6 n During this period, the other switches are in the off state. N are connected in parallel, and the second sample hold unit 44N includes capacitances C11 to C1 N Then, the switches S61 to S66 are turned on to output a current to the signal line IL1 in accordance with the voltage held in the n , S8 is turned off. By these operations, the capacitors C21 to C2 n A voltage based on a pixel signal is held in the pixel.

[0049] Then, switches S21 to S2 N―1 , S4, S5, S71~S7 N―1 , S9, and S10 are turned on. The other switches are turned off. N are connected in parallel, and the first sample-and-hold unit 44S includes capacitances C21 to C2 N and a current input from signal line IL2 is output to signal line IL3.

[0050] By the above operation, a current signal that has been subjected to correction processing by correlated double sampling of the pixel signal and the reset signal can be output to the signal line IL3. n The pixel signals stored in the Nn capacitors C2n+1 ~C2 N The reset signal held in the pixel signal is weighted and averaged according to the number of capacitors. This attenuates the voltage difference between the reset signal and the pixel signal by a factor of n / N. This makes it possible to expand the voltage range of the input signal in the column circuit.

[0051] FIG. 7 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. The AD conversion circuit 52 exemplified in this embodiment is a delta-sigma type AD conversion circuit, but is not limited thereto. For example, the AD conversion circuit 52 may be an AD conversion circuit of a type that compares a ramp signal with an input voltage and measures the time until the magnitude relationship is inverted by a counter. The AD conversion circuit 52 may also be a successive approximation type AD conversion circuit that obtains a digital value close to the input voltage by repeatedly comparing the output voltage of the DA conversion circuit with the input voltage. Note that, although a 1-bit AD conversion circuit is exemplified in this embodiment, the number of bits is not limited thereto, and in reality, AD conversion with a number of bits greater than this may be performed.

[0052] The AD conversion circuit 52 includes digital-to-analog conversion circuits (DA conversion circuits) 54a and 54b, capacitances Ca and Cb, a voltage-to-current conversion unit 56, a quantizer 58, a decimation filter DF, and buffers B1 and B2. As described above, the AD conversion circuit 52 receives the current signal processed by correlated double sampling from the sample-and-hold unit 42 via the signal line IL3.

[0053] The signal line IL3 is connected to the output terminal of the DA conversion circuit 54a, the first terminal of the capacitance Ca, and the input terminal of the voltage-current conversion unit 56. The output terminal of the voltage-current conversion unit 56 is connected to the output terminal of the DA conversion circuit 54b, the first terminal of the capacitance Cb, and the input terminal of the quantizer 58. The output terminal of the quantizer 58 is connected to the input terminal of the decimation filter DF and the input terminal of the buffer B1. The output terminal of the buffer B1 is connected to the input terminal of the DA conversion circuit 54b and the input terminal of the buffer B2. The output terminal of the buffer B2 is connected to the input terminal of the DA conversion circuit 54a. The ground terminals of the DA conversion circuits 54a and 54b, the second terminals of the capacitances Ca and Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3. The output terminal of the decimation filter DF is the output terminal of the AD conversion circuit 52.

[0054] Charge is accumulated in the capacitance Ca according to the amount of current flowing through the signal line IL3 and the passage of time. The voltage-current converter 56 outputs a current signal according to the potential of the first terminal of the capacitance Ca from the output terminal. In this way, the capacitance Ca functions as an integrator.

[0055] Charge is accumulated in the capacitance Cb according to the amount of current output from the voltage-current converter 56 and the passage of time. In this way, the capacitance Cb and the voltage-current converter 56 also function as an integrator. The quantizer 58 may be a comparison circuit. The quantizer 58 compares the potential of the first terminal of the capacitance Cb with a predetermined threshold value, and outputs a 1-bit digital signal indicating the comparison result. In this way, the quantizer 58 performs 1-bit analog-to-digital conversion. The quantizer 58 performs oversampling at a frequency higher than a desired sampling frequency.

[0056] The digital signal output from the quantizer 58 is input to the buffer B1. This digital signal is fed back to the DA conversion circuits 54a and 54b via the buffers B1 and B2. The DA conversion circuits 54a and 54b include a current source, a switch, and the like. The DA conversion circuit 54a performs digital-to-analog conversion to pass a current corresponding to the input digital signal, thereby extracting a charge corresponding to the digital signal from the first terminal of the capacitance Ca and passing it to the ground wiring GL3. Similarly, the DA conversion circuit 54b extracts a charge of an amount corresponding to the input digital signal from the first terminal of the capacitance Cb and passes it to the ground wiring GL3. In this way, the digital signal output from the quantizer 58 is fed back to the integrator or the input side of the quantizer 58. This feedback loop operates to reduce quantization errors in the low-frequency range.

[0057] 7, the AD conversion circuit 52 of this embodiment is likely to have a circuit arrangement that extends in one direction, and therefore the feedback wiring may be long. The provision of the buffers B1 and B2 reduces the effects of voltage drop and the like caused by the long feedback wiring. However, if the effects of the feedback wiring are tolerable, the buffers B1 and B2 do not need to be provided.

[0058] The decimation filter DF performs processing to lower the sampling frequency by thinning out the signal output from the quantizer 58. This reduces noise in the high frequency range.

[0059] As described above, the AD conversion circuit 52 of this embodiment employs a delta-sigma type suitable for achieving high accuracy and high resolution, thereby making it possible to output a highly accurate digital signal.

[0060] In this embodiment, the effect of sharing the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N as shown in Fig. 4 will be described. The potential of the ground wiring may fluctuate due to the operation of the circuit in the photoelectric conversion device 100, the influence of external noise, etc. This potential fluctuation may be a factor that reduces the accuracy of the output signal.

[0061] In this embodiment, the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N are shared. Therefore, the influence of fluctuations in the ground potential is superimposed on the first sample-and-hold unit 44S and the second sample-and-hold unit 44N to the same extent. Here, the reset signal held in the second sample-and-hold unit 44N is a signal used for correlated double sampling with the pixel signal held in the first sample-and-hold unit 44S. Therefore, the influence of noise caused by fluctuations in the potential of the ground wiring on the second sample-and-hold unit 44N and the first sample-and-hold unit 44S is reduced by performing correlated double sampling. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0062] [Second embodiment] The photoelectric conversion device 100 of this embodiment is a modified example of the configuration of the first embodiment in which the position where the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N are shared is changed. Since other elements are similar to those of the first embodiment, a description thereof will be omitted.

[0063] Fig. 8 is a block diagram showing the circuit configuration and wiring connections of one column according to this embodiment. As shown in Fig. 8, the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N are shared at a node N2 in the sample-and-hold unit 42. Although Fig. 8 shows only one column, the node N2 where the ground wiring is shared can be provided for each column circuit.

[0064] In this embodiment, unlike the first embodiment, the ground wiring is not shared outside the element region R1, but a sharing node N2 is provided for each column. Since the ground wiring is shared for each unit of correlated double sampling, the effect of noise reduction can be further improved.

[0065] In the configuration of the first embodiment, the ground wiring is shared at node N1, which is closer to pad P3. Also, node N1 can be provided in common for a plurality of column circuits. In this configuration, it is possible to reduce the common impedance caused by the wiring between node N1 and pad P3. Therefore, depending on the design, the configuration of the first embodiment may be able to reduce noise more effectively. The configuration of the first embodiment and the configuration of the second embodiment can be appropriately selected in consideration of conditions such as circuit design and layout.

[0066] [Third embodiment] The photoelectric conversion device 100 of this embodiment is a modified example of the first embodiment in which the configuration of the ground wiring of the AD conversion circuit 52 is changed. Since other elements are similar to those of the first embodiment, a description thereof will be omitted.

[0067] 9 is a block diagram showing the circuit configuration and wiring connections of one column according to this embodiment. As shown in Fig. 9, a ground wiring GL4 (fourth potential line) of a part of the AD conversion circuit 52 is shared with the ground wiring GL1 and the ground wiring GL2 at the node N3.

[0068] Fig. 10 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. As shown in Fig. 10, the ground terminal of the DA conversion circuit 54a is connected to the ground wiring GL4. The ground terminal of the DA conversion circuit 54b, the second terminals of the capacitors Ca and Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3.

[0069] In this embodiment, the ground wiring GL3 connected to the part performing the AD conversion operation such as the quantizer 58 in the AD conversion circuit 52 is separated from the ground wiring GL4 of the DA conversion circuit 54a arranged on the input side of the AD conversion circuit 52. This can reduce kickback, which is an effect of potential fluctuations caused by the AD conversion operation on the input side node. In addition, the ground wiring GL3 is also separated from the grounds of the first sample hold unit 44S and the second sample hold unit 44N, so that kickback to the first sample hold unit 44S and the second sample hold unit 44N is also reduced. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0070] Also in this embodiment, as in the first embodiment, the ground wiring GL1 and the ground wiring GL2 are shared at the node N3, which can reduce the effect of noise on the first sample-and-hold unit 44S and the second sample-and-hold unit 44N for the same reason as in the first embodiment.

[0071] [Fourth embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the positions at which the ground wirings GL1, GL2, and GL4 are shared are changed from the configuration of the third embodiment. Since the other elements are similar to those of the third embodiment, a description thereof will be omitted.

[0072] Fig. 11 is a block diagram showing the circuit configuration and wiring connections of one column according to this embodiment. As shown in Fig. 11, the ground wiring GL1, the ground wiring GL2, and the ground wiring GL4 are shared at a node N4 in the sample-and-hold unit 42. Although Fig. 11 shows only one column, the node N4 where the ground wiring is shared can be provided for each column circuit.

[0073] In this embodiment, a common node N4 is provided for each column, instead of commonizing the ground wiring outside the element region R1 as in the third embodiment. Since the ground wiring is commonized for each unit of correlated double sampling and AD conversion, the effect of noise reduction can be further improved.

[0074] In the configuration of the third embodiment, the ground wiring is shared at node N3, which is closer to pad P3. Also, node N3 can be provided in common for a plurality of column circuits. In this configuration, it is possible to reduce the common impedance caused by the wiring between node N3 and pad P3. Therefore, depending on the design, the configuration of the third embodiment may be able to reduce noise more effectively. The configuration of the third embodiment and the configuration of the fourth embodiment can be appropriately selected in consideration of conditions such as circuit design and layout.

[0075] [Fifth embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the configuration of the ground wiring GL1 of the first sample-and-hold unit 44S and the arrangement of the pads are changed from the configuration of the third embodiment. Since the other elements are the same as those of the third embodiment, the description will be omitted.

[0076] 12 is a block diagram showing the circuit configuration and wiring connections of one column according to this embodiment. As shown in FIG. 12, the ground wiring GL4 of a part of the AD conversion circuit 52 is shared with the ground wiring GL2 of the second sample hold unit 44N at a node N5. The node N5 is connected to a pad P3. The ground wiring GL1 of the first sample hold unit 44S is not connected to the node N5 but is connected to a pad P5.

[0077] In the present embodiment, as in the third embodiment, the ground wiring GL3 and the ground wiring GL4 are separated, and therefore, the kickback is reduced, resulting in a reduction in noise. Therefore, according to the present embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0078] 12, the ground wiring GL4 is shared with the ground wiring GL2 at the node N5, and the ground wiring GL1 is separated from them. However, the ground wiring GL4 may be shared with the ground wiring GL1, and the ground wiring GL2 may be separated from them.

[0079] [Sixth embodiment] The photoelectric conversion device 100 of this embodiment is a modified example in which the position where the ground wirings GL2 and GL4 are shared is changed from the configuration of the fifth embodiment. Since the other elements are similar to those of the fifth embodiment, the description will be omitted.

[0080] Fig. 13 is a block diagram showing the circuit configuration and wiring connections of one column according to this embodiment. As shown in Fig. 13, the ground wiring GL2 and the ground wiring GL4 are shared at a node N6 in the sample-and-hold unit 42. Although only one column is shown in Fig. 13, the node N6 where the ground wiring is shared can be provided for each column circuit.

[0081] In this embodiment, unlike the fifth embodiment, the ground wiring is not shared outside the element region R1, but a sharing node N6 is provided for each column. Since the ground wiring is shared for each unit of AD conversion, the effect of noise reduction can be further improved.

[0082] In the configuration of the fifth embodiment, the ground wiring is shared at node N5, which is closer to pad P3. Also, node N5 can be provided in common for a plurality of column circuits. In this configuration, it is possible to reduce the common impedance caused by the wiring between node N5 and pad P3. Therefore, depending on the design, the configuration of the fifth embodiment may be able to reduce noise more effectively. The configuration of the fifth embodiment and the configuration of the sixth embodiment can be appropriately selected in consideration of the conditions such as the circuit design and layout.

[0083] 13, the ground wiring GL4 is shared with the ground wiring GL2 at the node N6, and the ground wiring GL1 is separated from them. However, the ground wiring GL4 may be shared with the ground wiring GL1, and the ground wiring GL2 may be separated from them.

[0084] [Seventh embodiment] The photoelectric conversion device 100 of this embodiment is a modified example of any one of the configurations of the third to sixth embodiments, in which the configuration of the ground wiring in the AD conversion circuit 52 is changed. Since the other elements are similar to those of the third to sixth embodiments, the description thereof will be omitted.

[0085] Fig. 14 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. As shown in Fig. 14, the ground terminal of the DA conversion circuit 54a and the second terminal of the capacitance Ca are connected to the ground wiring GL4. The ground terminal of the DA conversion circuit 54b, the second terminal of the capacitance Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3.

[0086] In this embodiment, the ground wiring GL3 connected to the part performing the AD conversion operation such as the quantizer 58 in the AD conversion circuit 52 is separated from the ground wiring GL4 of the DA conversion circuit 54a and the second terminal of the capacitor Ca arranged on the input side of the AD conversion circuit 52. This can reduce kickback, which is an effect of potential fluctuations caused by the AD conversion operation on the input side node. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0087] As a method of separating the ground wirings GL3 and GL4 in the AD conversion circuit 52, two examples are shown in FIG. 10 and FIG. 14, but the method is not limited thereto. For example, the ground wiring may be separated at a node between the ground terminal of the voltage-current conversion unit 56 and the ground terminal of the DA conversion circuit 54b. Also, the ground wiring may be separated at a node between the ground terminal of the DA conversion circuit 54b and the second terminal of the capacitance Cb. Also, the ground wiring may be separated at a node between the second terminal of the capacitance Cb and the ground terminal of the quantizer 58. In this way, if at least the ground terminal of the quantizer 58 and the ground terminal of the element in the previous stage are separated, the effect of reducing kickback can be obtained.

[0088] [Eighth embodiment] The photoelectric conversion device 100 of this embodiment is a more specific arrangement of the sample-and-hold unit 42 described in the first embodiment. The configuration of the sample-and-hold unit 42 described in this embodiment is applicable to any of the first to seventh embodiments, and a description of the parts that overlap with the first to seventh embodiments will be omitted.

[0089] 15 is a block diagram showing the arrangement of the sample-and-hold section 42 according to the eighth embodiment. N , amplifier 48N, sample hold circuits 462S1 to 462S N 15, the arrangement of the sample-and-hold circuits 462N1 to 462N2 and the amplifier 48S is shown. The connection relationships of the various parts are similar to those shown in FIGS. 5 and 6, and therefore will not be described. As shown in FIG. 15, the column signal lines 16 and the signal lines IL1, IL2, and IL3 extend in a first direction (the vertical direction in FIG. 15). As shown in FIG. 15, the sample-and-hold circuits 462N1 to 462N N , amplifier 48N, sample hold circuits 462S1 to 462S N and the blocks of amplifier 48S also extend in the first direction in this order. By arranging the circuits and signal lines in parallel in this manner, these elements can be laid out efficiently.

[0090] [Ninth embodiment] An imaging system according to a ninth embodiment of the present invention will be described with reference to Fig. 16. Fig. 16 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0091] The photoelectric conversion device 100 described in the first to eighth embodiments above can be applied to various photoelectric conversion systems. An example of a photoelectric conversion system is an imaging system. Examples of imaging systems to which the photoelectric conversion device 100 can be applied include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and a photoelectric conversion device are also included in imaging systems. FIG. 16 illustrates a block diagram of a digital still camera as an example of these.

[0092] 16 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to eighth embodiments, and converts the optical image formed by the lens 202 into image data.

[0093] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data.

[0094] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the imaging system 200, or may be removable.

[0095] Furthermore, the imaging system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0096] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0097] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to eighth embodiments is applied.

[0098] [Tenth embodiment] An imaging system and a moving object according to a tenth embodiment of the present invention will be described with reference to Fig. 17. Fig. 17 is a diagram showing the configuration of an imaging system and a moving object according to this embodiment.

[0099] FIG. 17(a) shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to eighth embodiments described above. The imaging system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0100] The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0101] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 17(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). A vehicle information acquisition device 320 sends instructions to the imaging system 300 or imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0102] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies, but also to devices that use object recognition widely, such as intelligent transport systems (ITS).

[0103] [Modified embodiment] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention.

[0104] Furthermore, the imaging systems shown in the above-mentioned ninth and tenth embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 16 and 17.

[0105] In the above-mentioned embodiment, two types of examples are shown: an example in which a node to which a ground wiring is shared is provided corresponding to each column circuit, and an example in which a node is provided in common for a plurality of column circuits, but the present invention is not limited to these. For example, if any two columns among the plurality of columns are the first column and the second column, the ground wiring of the first column may be shared with the ground wiring of the second column. Here, the first column and the second column may be adjacent columns, or may be non-adjacent columns. Examples of non-adjacent columns include a case in which the first column and the second column are both even-numbered columns, or a case in which the first column and the second column are both even-numbered columns. As another example, the first column and the second column may be columns in which color filters of the same color are arranged in the pixels 12. As yet another example, in a configuration in which the column circuits extend both vertically from the pixel array 10, the first column and the second column may be columns arranged in different vertical directions.

[0106] In the above-mentioned embodiments, various examples are given in which the ground wiring that supplies the ground potential is shared or separated, but the present invention is not limited to this. For example, in the same manner as the above-mentioned ground wiring, the power supply wiring that supplies the power supply potential may be shared or separated, and the reference potential wiring that supplies the reference potential may be shared or separated. The same effect can be obtained in these examples. The ground wiring, the power supply wiring, and the reference potential wiring are sometimes more generally called potential lines.

[0107] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0108] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0109] 10 Pixel Array 12 pixels 44S 1st sample hold section 44N Second sample and hold section 52 AD conversion circuit 100 Photoelectric conversion device GL1, GL2, GL3 Ground wiring

Claims

1. a pixel array including a plurality of pixels arranged in a plurality of columns, each pixel generating a first signal based on incident light and a second signal based on a reset state; a column circuit arranged corresponding to each of a plurality of columns of the pixel array; A photoelectric conversion device having The column circuit includes: a first sample-and-hold unit that holds the first signal; a second sample-and-hold unit that holds the second signal; a delta-sigma analog-to-digital conversion circuit that converts an analog signal based on outputs from the first sample-and-hold unit and the second sample-and-hold unit into a digital signal; a first potential line that supplies a drive potential to the first sample hold unit; a second potential line that supplies a drive potential to the second sample hold unit; having the first potential line and the second potential line are shared in the photoelectric conversion device, A node at which the first potential line and the second potential line are common is provided corresponding to each of the plurality of column circuits. A photoelectric conversion device comprising:

2. A pixel array including a plurality of pixels arranged in a plurality of columns, each of the pixels generating a first signal based on incident light and a second signal based on a reset state; a column circuit arranged corresponding to each of a plurality of columns of the pixel array; A photoelectric conversion device having The column circuit includes: a first sample-and-hold unit that holds the first signal; a second sample-and-hold unit that holds the second signal; a delta-sigma analog-to-digital conversion circuit that converts an analog signal based on outputs from the first sample-and-hold unit and the second sample-and-hold unit into a digital signal; a first potential line that supplies a drive potential to the first sample hold unit; a second potential line that supplies a drive potential to the second sample hold unit; having the first potential line and the second potential line are shared in the photoelectric conversion device, A node at which the first potential line and the second potential line are common to a plurality of the column circuits. A photoelectric conversion device comprising:

3. the first sample-and-hold unit includes a first inverting amplifier and a first source follower circuit connected in series; the second sample-and-hold unit includes a second inverting amplifier and a second source follower circuit connected in cascade; the first potential line supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit; the second potential line supplies a drive potential to at least one of the second inverting amplifier and the second source follower circuit; 3. The photoelectric conversion device according to claim 1 or 2.

4. The analog signal is a signal based on a difference between the first signal and the second signal.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

5. a pixel array including a plurality of pixels arranged in a plurality of columns, each pixel generating a first signal based on incident light and a second signal based on a reset state; a column circuit arranged corresponding to each of a plurality of columns of the pixel array; A photoelectric conversion device having The column circuit includes: a first sample-and-hold unit including a first inverting amplifier and a first source follower circuit connected in cascade and configured to hold the first signal; a second sample-and-hold unit including a second inverting amplifier and a second source follower circuit connected in cascade and configured to hold the second signal; a first potential line that supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit; a second potential line that supplies a drive potential to at least one of the second inverting amplifier and the second source follower circuit; having the first potential line and the second potential line are shared in the photoelectric conversion device, A node at which the first potential line and the second potential line are common is provided corresponding to each of the plurality of column circuits. A photoelectric conversion device comprising:

6. A pixel array including a plurality of pixels arranged in a plurality of columns, each pixel generating a first signal based on incident light and a second signal based on a reset state; a column circuit arranged corresponding to each of a plurality of columns of the pixel array; A photoelectric conversion device having The column circuit includes: a first sample-and-hold unit including a first inverting amplifier and a first source follower circuit connected in cascade and configured to hold the first signal; a second sample-and-hold unit including a second inverting amplifier and a second source follower circuit connected in cascade and configured to hold the second signal; a first potential line that supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit; a second potential line that supplies a drive potential to at least one of the second inverting amplifier and the second source follower circuit; having the first potential line and the second potential line are shared in the photoelectric conversion device, A node at which the first potential line and the second potential line are common to a plurality of the column circuits. A photoelectric conversion device comprising:

7. a common external terminal for supplying a common driving potential to the first potential line and the second potential line; 7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

8. The first potential line and the second potential line included in the column circuit of a first column of the plurality of columns are common to the first potential line and the second potential line included in the column circuit of a second column of the plurality of columns.

8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

9. The driving potential is any one of a power supply potential, a ground potential, and a reference potential.

9. The photoelectric conversion device according to claim 1,

10. The photoelectric conversion device according to claim 1 , A signal processing means for processing a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

11. A mobile object, The photoelectric conversion device according to claim 1 , a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; A control means for controlling the moving object based on the distance information; A moving object comprising:

Images