Method for providing an auxiliary electrode and device including an auxiliary electrode - Patent application

Abstract

To provide a method for providing a suitable auxiliary electrode, and a device including an auxiliary electrode.SOLUTION: An opto-electronic device includes: (i) a substrate having a surface; (ii) a first electrode disposed over the surface; (iii) a semiconducting layer disposed over at least a portion of the first electrode; (iv) a second electrode disposed over the semiconducting layer; (v) a nucleation inhibiting coating disposed over at least a portion of the second electrode; (vi) a patterning structure disposed over the surface, the patterning structure providing a shadowed region between the patterning structure and the second electrode; (vii) an auxiliary electrode disposed over the surface; and (viii) a conductive coating disposed in the shadowed region, the conductive coating electrically connecting the auxiliary electrode and the second electrode.SELECTED DRAWING: Figure 18

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 62 / 668,134, filed May 7, 2018, and U.S. Provisional Application No. 62 / 729,889, filed September 11, 2018, the contents of which are incorporated herein by reference in their entirety.

[0002] The following generally relates to a method for providing an auxiliary electrode for an optoelectronic device. Specifically, this method relates to selectively depositing a conductive material on a surface to form a conductive structure of the device.

Background Art

[0003] An organic light - emitting diode (OLED) typically includes several layers of organic materials inserted between conductive thin - film electrodes, at least one of the organic layers being an electroluminescent layer. When a voltage is applied to the electrodes, holes and electrons are injected from the anode and cathode, respectively. The holes and electrons injected by the electrodes move through the organic layers and reach the electroluminescent layer. When holes and electrons are in proximity, they are attracted to each other by Coulomb forces. Subsequently, the holes and electrons may combine to form a bound state called an exciton. The exciton may decay by a radiative recombination process that emits a photon. Alternatively, the exciton may decay by a non - radiative recombination process that does not emit a photon. It should be noted that, as used herein, the internal quantum efficiency (IQE) is understood to be the ratio of all electron - hole pairs generated in a device that decay by a radiative recombination process.

[0004] The radiative recombination process can occur as fluorescence or phosphorescence processes depending on the spin state of the electron-hole pair (i.e., exciton). Specifically, the exciton formed by the electron-hole pair may be characterized as having a singlet or triplet spin state. Generally, fluorescence is generated by the radiative decay of singlet excitons, and phosphorescence is generated by the radiative decay of triplet excitons.

[0005] More recently, other emission mechanisms of OLEDs have been proposed and investigated, which include thermally activated delayed fluorescence (TADF). Briefly, TADF emission is generated by converting triplet excitons to singlet excitons through an inverse intersystem crossing process under the assistance of thermal energy, followed by the radiative decay of the singlet excitons.

[0006] The external quantum efficiency (EQE) of an OLED device may refer to the ratio of the charge carriers provided to the OLED device to the number of photons emitted by the device. For example, when the EQE is 100%, it indicates that one photon is emitted for each electron injected into the device. Naturally, the EQE of the device is generally substantially lower than the IQE of the device. The difference between EQE and IQE may generally be attributed to a number of factors, such as the absorption and reflection of light caused by various components of the device.

[0007] OLED devices can generally be classified as either "bottom-emitting" devices or "top-emitting" devices, depending on the relative direction in which light is emitted from the device. In bottom-emitting devices, the light generated as a result of the radiative recombination process is emitted in the direction towards the base substrate of the device, while in top-emitting devices, the light is emitted in the direction away from the base substrate. Accordingly, the electrode proximal to the base substrate is generally fabricated to be light-transmissive (e.g., substantially transparent or translucent) in bottom-emitting devices, while in top-emitting devices, the electrode distal to the base substrate is generally fabricated to be light-transmissive to reduce light attenuation. Depending on the specific device structure, either the anode or the cathode may function as the transmissive electrode in both top-emitting and bottom-emitting devices.

[0008] The OLED device may also be a double-sided emitting device configured to emit light in both directions with respect to the base substrate. For example, the double-sided emitting device may include a transmissive anode and a transmissive cathode, such that the light from each pixel is emitted in both directions. In another example, the double-sided emitting display device may include a first set of pixels configured to emit light in one direction and a second set of pixels configured to emit light in the other direction, such that a single electrode from each pixel is transmissive.

[0009] In addition to the above device configurations, transparent or semi-transparent OLED devices can also be implemented, which include a transparent portion through which external light can pass through the device. For example, in a transparent OLED display device, the transparent portion may be provided in the non-emitting region between adjacent pixels. In another example, a transparent OLED illumination panel may be formed by providing a plurality of transparent regions between the emitting regions of the panel. The transparent or semi-transparent OLED device may be a bottom-emitting, top-emitting, or double-sided emitting device.

[0010] Either the cathode or the anode can be selected as the transparent electrode, but a typical top-emitting device includes a light-transmissive cathode. Materials commonly used to form the transmissive cathode include transparent conductive oxides (TCOs) such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), as well as thin films formed by depositing thin layers of various metal alloys having a composition in the range of about 1:9 to about 9:1 by volume, such as silver (Ag), aluminum (Al), or magnesium silver (Mg:Ag) alloys and ytterbium silver (Yb:Ag) alloys. Multilayer cathodes including two or more TCOs and / or metal films can also be used.

[0011] Particularly in the case of thin films, a relatively thin layer thickness of up to about several tens of nanometers contributes to improved transparency and favorable optical properties (e.g., reduction of the microcavity effect) for use in OLEDs. However, reducing the thickness of the transparent electrode increases its sheet resistance. An electrode with a high sheet resistance is generally not desirable for use in OLEDs because it causes a large current resistance (IR) drop during device operation, which adversely affects the performance and efficiency of the OLED. The IR drop can be compensated to some extent by increasing the power level, but increasing the power level of one pixel also increases the voltage supplied to other components to maintain proper device operation, which is not preferable.

[0012] To reduce the power specifications of top-emitting OLED devices, solutions have been proposed to form a busbar structure or an auxiliary electrode in the device. For example, such an auxiliary electrode may be formed by depositing a conductive coating that electrically communicates with the transparent electrode of the OLED device. Such an auxiliary electrode enables more effectively carrying current to various regions of the device by reducing the sheet resistance of the transparent electrode and the associated IR drop.

[0013] Since the auxiliary electrode is typically provided on top of an OLED stack including an anode, one or more organic layers, and a cathode, patterning of the auxiliary electrode has conventionally been achieved using a shadow mask with a mask aperture and selectively depositing a conductive coating through it, for example, by physical vapor deposition (PVD) processing. However, since the mask is typically a metal mask, it tends to warp during high-temperature deposition processing, thereby distorting the mask aperture and the resulting deposition pattern. Moreover, since the conductive coating adheres to the mask and obscures the features of the mask, the mask typically deteriorates by continuous deposition. As a result, such masks must be cleaned using time-consuming and costly processes or disposed of once the mask is considered ineffective for manufacturing the desired pattern, thereby making such processes very expensive and complex. Therefore, shadow mask processing may not be commercially viable for mass production of OLED devices. Moreover, the aspect ratio of the features that can be manufactured using shadow mask processing is typically limited by the shielding effect and the mechanical (e.g., tensile) strength of the metal mask, which is because large metal masks typically stretch during the deposition process of the shadow mask.

[0014] Another issue when patterning a conductive coating on a surface through a shadow mask is that while a single mask can be used to achieve a particular pattern, not all patterns are possible. Since each part of the mask is physically supported, not all patterns are possible in a single processing step. For example, when the pattern specifies isolated features, it is usually not possible to achieve the desired pattern using a single mask processing step. In addition, the masks used to manufacture repeating structures (e.g., busbar structures or auxiliary electrodes) that span the entire device surface include a large number of perforations or apertures formed in the mask. However, forming a large number of apertures in the mask can compromise the structural integrity of the mask, thereby causing significant warping or deformation of the mask during processing and distorting the pattern of the deposition structure.

[0015] In addition to the above, when a common electrode having a substantially uniform thickness is provided as an upper emission cathode in an OLED display device, it is not easy to finely adjust the optical performance of the device according to the emission spectra associated with each sub-pixel. In a normal OLED display device, red, green, and blue sub-pixels are provided to form the pixels of the display device. The upper emission electrode used in such an OLED display device is usually a common electrode covering a plurality of pixels. For example, such a common electrode may be a relatively thin conductive layer having a substantially uniform thickness over the entire device. Efforts have been made to adjust the optical microcavity effect associated with the color of each sub-pixel by varying the thickness of the organic layers disposed within different sub-pixels, but such a method may not be able to sufficiently adjust the degree of the optical microcavity effect in at least some cases. In addition, such a method may be difficult to implement in the manufacturing environment of an OLED display device. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0016] According to some embodiments, an optoelectronic device includes: (i) a substrate having a surface; (ii) a first electrode disposed on the surface; (iii) a semiconductor layer disposed on at least a portion of the first electrode; (iv) a second electrode disposed on the semiconductor layer; (v) a nucleation suppression coating disposed on at least a portion of the second electrode; (vi) a patterning structure disposed on the surface, the patterning structure providing a shielding region between the patterning structure and the second electrode; (vii) an auxiliary electrode disposed on the surface; and (viii) a conductive coating disposed in the shielding region, the conductive coating electrically connecting the auxiliary electrode and the second electrode.

[0017] According to some embodiments, an optoelectronic device includes a non-radiative region and a radiative region disposed adjacent to the non-radiative region. The radiative region includes a first electrode and a second electrode, and a semiconductor layer disposed between the first electrode and the second electrode. The non-radiative region includes an auxiliary electrode and a patterning structure disposed to overlap the auxiliary electrode and laterally extending to provide a shielding region, and a conductive coating disposed in the shielding region and electrically connecting the auxiliary electrode and the second electrode.

[0018] According to some embodiments, a method for manufacturing an optoelectronic device includes: (i) providing a substrate having a surface, the substrate including a plurality of thin film transistors, a first electrode disposed on the surface and electrically communicating with at least one of the thin film transistors, a pixel defining layer disposed on the surface and covering the periphery of the first electrode, an auxiliary electrode disposed on the surface, and a patterning structure disposed to overlap the auxiliary electrode and laterally extending to provide a shielding region; (ii) depositing a semiconductor layer on the first electrode; (iii) depositing a second electrode on the semiconductor layer; (iv) depositing a nucleation suppression coating on the second electrode; and (v) treating the nucleation suppression coating and the shielding region to deposit a conductive coating in the shielding region while leaving at least a portion of the nucleation suppression coating substantially uncovered by the conductive coating.

[0019] According to some embodiments, a method for manufacturing an optoelectronic device includes: (i) providing a substrate having a surface, the substrate including at least one thin film transistor, a first electrode disposed on the surface and in electrical communication with the at least one thin film transistor, an auxiliary electrode disposed on the surface, and a bank structure disposed on the surface and defining a via region that exposes the auxiliary electrode; (ii) depositing a semiconductor layer on the first electrode; (iii) depositing a second electrode on the semiconductor layer; (iv) depositing a nucleation suppression coating on the second electrode; and (v) treating the nucleation suppression coating and the via region to deposit a conductive coating in the via region while leaving at least a portion of the nucleation suppression coating substantially uncovered by the conductive coating.

[0020] According to some embodiments, an optoelectronic device includes: (i) a first electrode and a second electrode; (ii) a semiconductor layer disposed between the first electrode and the second electrode; (iii) a nucleation suppression coating disposed on at least a portion of the second electrode; (iv) an auxiliary electrode having sidewalls; and (v) a conductive coating disposed adjacent to the sidewalls and in electrical connection with the auxiliary electrode and the second electrode. This specification also provides, for example, the following items. (Item 1) An optoelectronic device, comprising a substrate having a surface; a first electrode disposed on the surface; a semiconductor layer disposed on at least a portion of the first electrode; a second electrode disposed on the semiconductor layer; a nucleation suppression coating disposed on at least a portion of the second electrode; a patterning structure disposed on the surface, the patterning structure providing a shielding region between the patterning structure and the second electrode; an auxiliary electrode disposed on the surface; A conductive coating disposed in the shielding region, the conductive coating electrically connecting the auxiliary electrode and the second electrode, and an optoelectronic device comprising the same. (Item 2) The optoelectronic device according to item 1, further comprising a nucleation promoting coating, wherein the nucleation promoting coating is disposed between the surface and the conductive coating. (Item 3) The optoelectronic device according to item 2, wherein the nucleation promoting coating is disposed in contact with the conductive coating. (Item 4) The optoelectronic device according to any one of items 1 to 3, further comprising a pixel defining layer, wherein the pixel defining layer is disposed on the surface. (Item 5) The optoelectronic device according to item 4, wherein the pixel defining layer covers the periphery of the first electrode. (Item 6) The optoelectronic device according to item 4 or 5, wherein the auxiliary electrode is disposed on the pixel defining layer. (Item 7) The optoelectronic device according to any one of items 1 to 5, wherein the auxiliary electrode is disposed on the surface. (Item 8) The optoelectronic device according to any one of items 1 to 7, wherein the patterning structure is disposed on the auxiliary electrode. (Item 9) The optoelectronic device according to any one of items 1 to 7, wherein the auxiliary electrode is disposed in the shielding region. (Item 10) The optoelectronic device according to any one of items 1 to 9, wherein the conductive coating and the auxiliary electrode are integrally formed with each other. (Item 11) The optoelectronic device according to any one of items 1 to 10, wherein the shielding region substantially does not contain the nucleation suppressing coating. (Item 12) The photoelectric device according to any one of items 1 to 11, wherein the patterning structure includes a base portion and an upper portion, the base portion is disposed proximal to the surface, and the upper portion is disposed distal to the surface. (Item 13) The photoelectric device according to item 12, wherein the upper portion extends laterally outward from the base portion, thereby providing the shielding region. (Item 14) The photoelectric device according to item 12 or 13, wherein a side wall extends between the base portion and the upper portion, and the side wall is substantially linear, tapered, or curved. (Item 15) The photoelectric device according to any one of items 1 to 14, wherein the substrate further includes a thin film transistor that is in electrical communication with the first electrode. (Item 16) The photoelectric device according to any one of items 1 to 15, wherein the semiconductor layer includes a light emitting layer. (Item 17) The photoelectric device according to item 16, wherein the semiconductor layer further includes at least one of a hole injection layer, an electron blocking layer, a hole transport layer, an electron transport layer, a hole blocking layer, or an electron injection layer. (Item 18) The photoelectric device according to any one of items 1 to 17, wherein the conductive coating includes magnesium. (Item 19) A photoelectric device, comprising a non-light emitting region and a light emitting region disposed adjacent to the non-light emitting region, wherein the light emitting region includes a first electrode and a second electrode, and a semiconductor layer disposed between the first electrode and the second electrode, wherein the non-light emitting region includes an auxiliary electrode, and a patterning structure disposed so as to overlap the auxiliary electrode, the patterning structure extending laterally so as to provide a shielding region. A photoelectronic device comprising: a conductive coating disposed in the shielding region, the conductive coating electrically connecting the auxiliary electrode and the second electrode. (Item 20) The photoelectronic device according to item 19, further comprising a nucleation suppression coating disposed on the second electrode in the emission region. (Item 21) The photoelectronic device according to item 20, wherein the shielding region substantially does not include the nucleation suppression coating. (Item 22) The photoelectronic device according to any one of items 19 to 21, wherein the patterning structure is disposed on the auxiliary electrode. (Item 23) The photoelectronic device according to any one of items 19 to 22, wherein the non-emission region further comprises a pixel defining layer. (Item 24) The photoelectronic device according to item 23, wherein the auxiliary electrode is disposed on the pixel defining layer. (Item 25) The photoelectronic device according to any one of items 19 to 24, wherein the patterning structure comprises a laterally extending portion, and the laterally extending portion provides the shielding region. (Item 26) A method for manufacturing a photoelectronic device, comprising: (i) providing a substrate having a surface, the substrate comprising: a plurality of thin film transistors, a first electrode disposed on the surface, the first electrode being electrically connected to at least one of the thin film transistors, a pixel defining layer disposed on the surface and covering the periphery of the first electrode, an auxiliary electrode disposed on the surface, and a patterning structure disposed to overlap the auxiliary electrode, the patterning structure laterally extending to provide a shielding region; (ii) depositing a semiconductor layer on the first electrode; (iii) depositing a second electrode on the semiconductor layer; (iv) depositing a nucleation suppression coating on the second electrode; (v) treating the nucleation suppression coating and the shielding region to deposit a conductive coating on the shielding region, wherein at least a portion of the nucleation suppression coating remains substantially uncovered by the conductive coating, a method comprising. (Item 27) The method according to item 26, wherein depositing the conductive coating is performed using an open mask or without a mask. (Item 28) The method according to item 26 or 27, wherein depositing the nucleation suppression coating is performed using an open mask or without a mask. (Item 29) The method according to any one of items 26 to 28, wherein treating the nucleation suppression coating and the shielding region in (v) includes exposing the nucleation suppression coating and the shielding region to the evaporation flux of the material forming the conductive coating. (Item 30) The method according to item 29, wherein at least a portion of the evaporation flux is not collimated. (Item 31) The method according to item 29 or 30, wherein at least a portion of the evaporation flux is incident on the shielding surface of the shielding region at a non-normal incident angle. (Item 32) The method according to any one of items 29 to 31, wherein treating the nucleation suppression coating and the shielding region in (v) includes displacing the substrate during processing. (Item 33) The method according to item 32, wherein the substrate undergoes at least one of angular displacement, lateral displacement, or vertical displacement. (Item 34) The evaporation flux is generated by a point evaporation source, a line evaporation source, or a surface evaporation source, and is the method according to any one of items 29 to 33. (Item 35) In (v), processing the nucleation suppression coating and the shielding region includes rotating the substrate around a rotation axis, and the rotation axis is substantially normal to the surface of the substrate, and is the method according to item 32 or 33. (Item 36) The evaporation flux is generated by a point evaporation source, an array of point evaporation sources, or a surface evaporation source, and is the method according to item 35. (Item 37) When depositing the conductive coating, the second electrode and the auxiliary electrode are electrically connected to each other by the conductive coating, and is the method according to any one of items 26 to 36. (Item 38) The auxiliary electrode is disposed between the surface and the patterning structure, and is the method according to any one of items 26 to 37. (Item 39) The auxiliary electrode is disposed between the pixel defining layer and the patterning structure, and is the method according to any one of items 26 to 37. (Item 40) A method for manufacturing an optoelectronic device, (i) providing a substrate having a surface, the substrate comprising at least one thin film transistor, a first electrode disposed on the surface, the first electrode being in electrical communication with the at least one thin film transistor, an auxiliary electrode disposed on the surface, and providing a bank structure disposed on the surface and defining a through hole region exposing the auxiliary electrode, (ii) depositing a semiconductor layer on the first electrode; (iii) depositing a second electrode on the semiconductor layer; (iv) depositing a nucleation suppression coating on the second electrode; (v) treating the nucleation suppression coating and the via region to deposit a conductive coating on the via region, while leaving at least a portion of the nucleation suppression coating substantially uncovered by the conductive coating, a method. (Item 41) The method according to item 40, wherein the second electrode and the auxiliary electrode are electrically connected by the conductive coating. (Item 42) The method according to item 40 or 41, wherein at least a portion of the bank structure is disposed laterally between the first electrode and the auxiliary electrode. (Item 43) The method according to any one of items 40 to 42, wherein the via region is defined by vias extending substantially vertically. (Item 44) The method according to item 43, wherein the via is defined by the bank structure. (Item 45) The method according to item 43, further comprising another bank structure disposed on the surface, wherein the via is defined by a gap between the bank structure and the another bank structure. (Item 46) The method according to any one of items 40 to 45, wherein at least a portion of the semiconductor layer is deposited by printing. (Item 47) The method according to any one of items 40 to 46, wherein the nucleation suppression coating is deposited at a non-normal angle of incidence. (Item 48) The method according to any one of items 40 to 47, wherein the via region substantially does not contain the nucleation suppression coating. (Item 49) An optoelectronic device, a first electrode and a second electrode, a semiconductor layer disposed between the first electrode and the second electrode, a nucleation suppression coating disposed on at least a portion of the second electrode, An auxiliary electrode having sidewalls, a conductive coating disposed adjacent to the sidewalls and electrically connected to the auxiliary electrode and the second electrode, and a photoelectronic device comprising the same. (Item 50) The photoelectronic device according to item 49, wherein the auxiliary electrode includes an upper portion and a base portion, and the sidewalls extend between the upper portion and the base portion. (Item 51) The photoelectronic device according to item 49 or 50, wherein the sidewalls of the auxiliary electrode substantially do not include the nucleation suppression coating. (Item 52) The photoelectronic device according to any one of items 49 to 51, wherein the sidewalls extend substantially vertically. (Item 53) The photoelectronic device according to any one of items 49 to 52, wherein the auxiliary electrode defines a step edge. (Item 54) The photoelectronic device according to any one of items 49 to 51, wherein the sidewalls define an overhang. (Item 55) The photoelectronic device according to item 54, wherein the sidewalls include substantially linear, tapered, or curved portions. (Item 56) The photoelectronic device according to item 54 or 55, wherein the overhang forms a shielding region. (Item 57) The photoelectronic device according to item 56, wherein the shielding region is substantially exposed from the nucleation suppression coating. (Item 58) The photoelectronic device according to item 56 or 57, wherein the conductive coating is disposed in the shielding region. (Item 59) The photoelectronic device according to any one of items 49, 50, 51, 54, and 55, wherein the auxiliary electrode includes a lower portion and an upper portion. (Item 60) The optoelectronic device according to item 59, wherein the lower portion is concave with respect to the upper portion. (Item 61) The optoelectronic device according to item 59 or 60, wherein the lower portion comprises a material different from that of the upper portion. (Item 62) The optoelectronic device according to any one of items 49 to 61, wherein the conductive coating is in contact with at least one of the auxiliary electrode or the second electrode. (Item 63) The optoelectronic device according to any one of items 49 to 61, further comprising an intermediate layer disposed between the conductive coating and the auxiliary electrode or between the conductive coating and the second electrode. (Item 64) The optoelectronic device according to any one of items 49 to 63, further comprising a pixel defining layer, wherein the auxiliary electrode is disposed on the pixel defining layer. (Item 65) The optoelectronic device according to any one of items 49 to 63, wherein the auxiliary electrode and the first electrode are disposed in the same plane. (Item 66) The optoelectronic device according to any one of items 49 to 65, wherein the conductive coating extends laterally and overlaps the second electrode. (Item 67) The optoelectronic device according to any one of items 49 to 66, further comprising a non-radiating region, wherein the auxiliary electrode is disposed in the non-radiating region of the optoelectronic device. (Item 68) The optoelectronic device according to any one of items 49 to 67, further comprising a plurality of radiating regions, wherein the auxiliary electrode is disposed between the plurality of radiating regions. (Item 69) The optoelectronic device according to any one of items 49 to 67, further comprising a plurality of radiating regions, wherein the plurality of radiating regions are substantially exposed from the conductive coating. (Item 70) The core generation suppression coating is disposed in the plurality of radiation regions, and the optoelectronic device according to item 69.

Brief Description of the Drawings

[0021] Here, several embodiments will be described as examples with reference to the accompanying drawings.

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8-1

Figure 8-2

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15-1

Figure 15-2

Figure 16

Figure 17A

Figure 17B

Figure 18

Figure 19-1

Figure 19-2

Figure 19-3

Figure 20-1

Figure 20-2

Figure 21

Figure 22

DETAILED DESCRIPTION OF THE INVENTION

[0023] It will be understood that, for the sake of simplicity and clarity of the drawings, reference numerals may be repeated between the drawings in order to indicate corresponding or similar elements where appropriate. In addition, numerous specific details are set forth in order to provide a complete understanding of the exemplary embodiments described herein. However, it will be understood by those skilled in the art that the exemplary embodiments described herein may be practiced without some of these specific details. In other instances, specific methods, procedures, and components have not been described in detail so as not to obscure the exemplary embodiments described herein.

[0024] In one aspect according to some embodiments, a method for manufacturing an optoelectronic device is provided. In some embodiments, this method is carried out in the context of a method for manufacturing an active matrix OLED device. In some embodiments, this method includes providing a substrate having a surface. In some embodiments, the substrate includes one or more thin film transistors, a first electrode disposed on the surface, a pixel defining layer disposed on the surface, an auxiliary electrode disposed on the surface, and a patterning structure disposed so as to overlap the auxiliary electrode. The first electrode is in electrical communication with at least one thin film transistor. In some embodiments, the pixel defining layer covers an edge or periphery of the first electrode. In some embodiments, the patterning structure extends laterally to provide a shielding region. This method includes depositing a semiconductor layer on the first electrode. In some embodiments, the semiconductor layer includes an emissive layer. Also, this method includes depositing a second electrode on the semiconductor layer. In some embodiments, the first electrode is an anode and the second electrode is a cathode. Also, this method includes depositing a nucleation suppression coating on the second electrode. Also, this method includes treating the nucleation suppression coating and the shielding region to deposit a conductive coating on the shielding region. In some embodiments, at least a portion of the nucleation suppression coating remains substantially uncovered by the conductive coating. In some embodiments, depositing the conductive coating is performed using an open mask or without a mask. In some embodiments, depositing the nucleation suppression coating is performed using an open mask or without a mask. In some embodiments, treating the nucleation suppression coating and the shielding region includes exposing the nucleation suppression coating and the shielding region to an evaporation flux of a material for forming the conductive coating. In some embodiments, at least a portion of the evaporation flux is not collimated. In some embodiments, at least a portion of the evaporation flux impinges on a shielding surface of the shielding region at a non-normal angle of incidence.In some embodiments, processing the nucleation suppression coating and the shielding region includes displacing the substrate during processing. In some embodiments, the substrate undergoes angular displacement, lateral displacement, and / or vertical displacement. In some embodiments, the evaporation flux is generated by a point evaporation source, a line evaporation source, or an area evaporation source. In some embodiments, processing the nucleation suppression coating and the shielding region includes rotating the substrate about an axis of rotation that is substantially normal to the surface of the substrate. In some embodiments, the evaporation flux is generated by a point evaporation source, an array of point evaporation sources, or an area evaporation source. In some embodiments, when depositing the conductive coating, the second electrode and the auxiliary electrode are electrically connected to each other by the conductive coating. In some embodiments, the material of the conductive coating includes magnesium.

[0025] As used herein, the term "nucleation suppression" is used to refer to a coating or layer of material that has a surface presenting a relatively low affinity for the deposition of a conductive material, and as a result, suppresses the deposition of the conductive coating material onto the surface, while the term "nucleation promotion" is used to refer to a coating or layer of material that has a surface presenting a relatively high affinity for the deposition of a conductive material, and as a result, promotes the deposition of the conductive material onto the surface. One measure of the nucleation suppression or nucleation promotion characteristics of a surface is the initial adhesion probability of the surface to a conductive material such as magnesium. For example, a nucleation suppression coating for magnesium can refer to a coating that has a surface presenting a relatively low initial adhesion probability to magnesium vapor, and as a result, suppresses the deposition of magnesium onto the surface, and a nucleation promotion coating for magnesium can refer to a coating that has a surface presenting a relatively high initial adhesion probability to magnesium vapor, and as a result, promotes the deposition of magnesium onto the surface. As used herein, the terms "adhesion probability" and "adhesion coefficient" may be used interchangeably. Another measure of the nucleation suppression or nucleation promotion characteristics of a surface is the initial deposition rate or initial film growth rate of a conductive material such as magnesium on that surface relative to the initial deposition rate or initial film growth rate of the conductive material on another (reference) surface, where both surfaces are exposed to or made to expose an evaporation flux of the conductive coating material.

[0026] As used herein, the terms "evaporation" and "sublimation" are used interchangeably and generally refer to a deposition process that converts a source material to vapor (e.g., by heating) and deposits it, for example, in a solid state onto a target surface.

[0027] As used herein, a surface (or a particular area of a surface) that is "substantially free" of a material or "substantially uncovered" by a material refers to a surface (or a particular area of a surface) on which the material is substantially absent. Specifically, with respect to a conductive coating, one measure of the amount of conductive material on a surface is light transmittance, because conductive materials such as metals containing magnesium attenuate and / or absorb light. Thus, in the visible portion of the electromagnetic spectrum, a surface can be considered to be substantially free of conductive material if the light transmittance exceeds 90%, exceeds 92%, exceeds 95%, or exceeds 98%. Another measure of the amount of material on a surface is the coverage of the surface by the material. For example, if the coverage by the material is 10% or less, 8% or less, 5% or less, 3% or less, or 1% or less, the surface can be considered to be substantially free of that material. The coverage of the surface can be evaluated using imaging techniques, i.e., using a transmission electron microscope, an atomic force microscope, or a scanning electron microscope, etc.

[0028] Figures 1 to 5 are a series of schematic diagrams showing the process for manufacturing an optoelectronic device according to an embodiment. In Figure 1, the substrate 100 is shown as having a surface 105. The substrate 100 includes one or more thin film transistors (TFTs) 200. For example, such a TFT may be formed by depositing and patterning a series of thin films when manufacturing the substrate 100. The surface 105 of the substrate 100 provides a first electrode 300. For example, the first electrode 300 may be an anode. The first electrode 300 is in electrical communication with the TFT 200. A pixel defining layer (PDL) 401 is also provided on the surface 105, such that the pixel defining layer 401 covers the surface 105 and the edges or periphery of the first electrode 300. The pixel defining layer 401 defines an opening that exposes the surface of the anode 300. The opening defined by the pixel defining layer 401 generally corresponds to the emission region of the device. For example, the device may include a plurality of openings defined by the pixel defining layer 401, and each opening may correspond to a sub-pixel region of the device. In the illustrated embodiment, an auxiliary electrode 501 is formed on the pixel defining layer 401. For example, the auxiliary electrode 501 may include a conductive material such as a metal. Examples of such conductive materials include copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag). In some embodiments, the auxiliary electrode 501 includes two or more conductive materials. For example, the auxiliary electrode 501 may be formed by a multi-layer metal structure such as that formed by Mo / Al / Mo. The auxiliary electrode 501 may be formed directly on top of the pixel defining layer 401, such as on the upper plane of the pixel defining layer 401. A patterning structure 601 is also provided. In the illustrated embodiment, the patterning structure 601 is disposed or arranged on top of the pixel defining layer 401, such that at least a portion of the patterning structure 601 overlaps the auxiliary electrode 501. The patterning structure 601 extends laterally to form a lateral extension 605. The lateral extension 605 may be configured to vertically offset the base portion 612 of the patterning structure 601 from the upper portion 615 to provide a shielding region 421.Specifically, in the illustrated embodiment, the shielding region 421 corresponds to a part or region of the surface of the pixel defining layer 401, where it overlaps with the laterally extending portion 605 of the patterning structure 601.

[0029] FIG. 2 shows depositing the semiconductor layer 701. As shown, the semiconductor layer 701 may be deposited on the exposed surface of the first electrode 300. In some embodiments where the optoelectronic device is an OLED, the semiconductor layer 701 includes one or more organic semiconductor layers. For example, the semiconductor layer 701 may include an emissive layer. In some embodiments, the semiconductor layer 701 includes a hole injection layer, an electron blocking layer, a hole transport layer, an emissive layer, an electron transport layer, a hole blocking layer, an electron injection layer, and any combination of the above. In some embodiments, the semiconductor layer 701 may form a "tandem" structure including a plurality of emissive layers. In such a structure, the semiconductor layer 701 may include one or more charge generation layers (CGLs). In some embodiments, the semiconductor layer 701 is deposited using a thermal evaporation process. In some embodiments, a shadow mask is used with such a thermal evaporation process to selectively deposit the semiconductor layer 701.

[0030] FIG. 3 shows the deposition of the second electrode 801 on the semiconductor layer 701. For example, the second electrode 801 may be a cathode. The second electrode 801 may comprise various materials used to form a light-transmissive conductive layer or coating. For example, the second electrode 801 may include a transparent conductive oxide (TCO), a metal or non-metal thin film, and any combination thereof. The second electrode 801 may further comprise two or more layers or coatings. For example, such layers or coatings may be separate layers or coatings disposed on top of each other. The second electrode 801 may comprise various materials including, for example, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), other oxides containing indium and / or zinc, magnesium (Mg), aluminum (Al), ytterbium (Yb), silver (Ag), zinc (Zn), cadmium (Cd), and any combination thereof, and alloys containing any of the above materials. For example, the second electrode 801 may comprise an Mg:Ag alloy, an Mg:Yb alloy, or a combination thereof. In the case of an Mg:Ag alloy or an Mg:Yb alloy, the alloy composition may be in the range of about 1:9 to about 9:1 by volume. In other examples, the second electrode 801 may comprise a Yb / Ag bilayer coating. For example, such a bilayer coating may be formed by depositing a ytterbium coating followed by a silver coating. The thickness of the silver coating may be greater than the thickness of the ytterbium coating, or vice versa. In yet another example, the second electrode 801 is a multilayer cathode comprising one or more metal layers and one or more oxide layers. In yet another example, the second electrode 801 may comprise fullerene and magnesium. For example, such a coating may be formed by depositing a fullerene coating followed by a magnesium coating. In another example, fullerene may be dispersed in a magnesium coating to form a fullerene-containing magnesium alloy coating.Examples of such coatings are further described in U.S. Patent Application Publication No. US2015 / 0287846 (published October 8, 2015) and PCT Application No. PCT / IB2017 / 054970 (filed August 15, 2017) (published February 22, 2018 as WO2018 / 033860). In some embodiments, depositing the second electrode 801 is performed using an open mask or without a mask. For example, the second electrode 801 may be deposited by exposing the exposed upper surfaces of the pixel defining layer 401, the semiconductor layer 701, and the patterning structure 601 to the evaporation flux of the material for forming the second electrode 801. In such embodiments, the remaining second electrode 811 is formed on the patterning structure 601. As shown, the remaining second electrode 811 is generally physically separated and separately formed from the second electrode 801 due to the presence of the patterning structure 601. Generally, the remaining second electrode 811 is formed in the non-radiative region of the device, and the second electrode 801 is formed in the radiative region of the device. In some embodiments, the remaining second electrode 811 is electrically insulated or disconnected from the second electrode 801. In some embodiments, the remaining second electrode 811 is electrically connected to the second electrode 801 and / or the auxiliary electrode 501. For example, the remaining second electrode 811 may be connected to the second electrode 801 and / or the auxiliary electrode 501 at or near the edge or periphery of the device. The remaining second electrode 811 is generally substantially compositionally identical to the second electrode 801. In the illustrated embodiment, the shielding region 421 does not substantially include or is not covered by the second electrode 801 or the remaining second electrode 811. Specifically, during the deposition of the second electrode 801 and the remaining second electrode 811, the shielding region 421 is masked by the patterning structure 601, such that the evaporation flux of the material for forming the second electrode 801 and the remaining second electrode 811 is suppressed from incident on a portion of the surface of the pixel defining layer 401 corresponding to the shielding region 421, thereby suppressing the deposition of the electrode. For example, the lateral extension 605 of the patterning structure 601 may be used to provide a shielding region 421 where such deposition is suppressed.In some embodiments, at least a portion of the evaporation flux of the material for forming the second electrode 801 impinges on the shielding region 421, such that the second electrode 801 covers at least a portion of the shielding region 421. In some further embodiments, the surface of the laterally extending portion 605 of the patterning structure 601 is covered by the second electrode 801.

[0031] FIG. 4 shows the deposition of the nucleation suppression coating 901 onto the second electrode 801. In some embodiments, the deposition of the nucleation suppression coating 901 is performed using an open mask or without a mask. For example, the nucleation suppression coating 901 may be deposited by exposing the exposed upper surfaces of the second electrode 801 and the remaining second electrode 811 to the evaporation flux of the material for forming the nucleation suppression coating 901. In such embodiments, the remaining nucleation suppression coating 911 is formed on the patterning structure 601. As shown, the remaining nucleation suppression coating 911 may be formed on and in contact with the upper portion of the remaining second electrode 811. The remaining nucleation suppression coating 911 is generally physically separated and separately formed from the nucleation suppression coating 901 due to the presence of the patterning structure 601. Generally, the remaining nucleation suppression coating 911 is formed in the non-radiative region of the device, and the nucleation suppression coating 901 is formed in the radiative region of the device. In some embodiments, the remaining nucleation suppression coating 911 is substantially compositionally identical to the nucleation suppression coating 901. As shown in FIG. 4, the shielding region 421 is substantially free of or not covered by the nucleation suppression coating 901 or the remaining nucleation suppression coating 911. Specifically, during the deposition of the nucleation suppression coating 901 and the remaining nucleation suppression coating 911, the shielding region 421 is masked by the patterning structure 601, such that the evaporation flux of the material for forming the nucleation suppression coating 901 and the remaining nucleation suppression coating 911 is suppressed from incident on a portion of the surface of the pixel definition layer 401 corresponding to the shielding region 421, thereby suppressing the deposition of the nucleation suppression material thereon. For example, the lateral extension 605 of the patterning structure 601 may be used to provide the shielding region 421 where such deposition is suppressed.

[0032] FIG. 5 shows the deposition of the conductive coating 1010. In some embodiments, the deposition is performed by treating the nucleation suppression coating 901 and the shielding region 421 to deposit the conductive coating 1010 on the shielding region 421, but at least a portion of the nucleation suppression coating 901 remains substantially uncovered by the conductive coating 1010. In the illustrated embodiment, the exposed surfaces of the nucleation suppression coating 901 and the remaining nucleation suppression coating 911, as well as the surface of the pixel defining layer 401 corresponding to the shielding region 421, are exposed to the evaporation flux 1005 of the material for forming the conductive coating 1010. For example, a conductive coating source (not shown) may be used to direct the evaporated conductive material towards the surface of the nucleation suppression coating 901, the surface of the remaining nucleation suppression coating 911, and a portion of the surface of the pixel defining layer 401 corresponding to the shielding region 421, such that the evaporated conductive material impinges on these surfaces. However, since the surfaces of the nucleation suppression coating 901 and the remaining nucleation suppression coating 911 exhibit a relatively low initial adhesion coefficient compared to the surface of the pixel defining layer 401, the conductive coating 1010 selectively deposits on the shielding region 421 where the nucleation suppression coating 901 and the remaining nucleation suppression coating 911 are absent. In some embodiments, the deposition of the conductive coating 1010 is performed using an open mask or without a mask. In some embodiments, at least a portion of the evaporation flux 1005 is directed at an off-normal angle with respect to the surface of the pixel defining layer 401 corresponding to the shielding region 421. For example, at least a portion of the evaporation flux 1005 may impinge on the surface of the pixel defining layer 401 at an incident angle of less than 90°. For example, the incident angle is less than about 85°, less than about 80°, less than about 75°, less than about 70°, less than about 60°, or less than about 50°. The shielding region 421 may be exposed to the evaporation flux 1005 by directing the evaporation flux 1005 such that it includes a portion that impinges on the surface at an off-normal angle.Specifically, the possibility that such an evaporation flux 1005 is suppressed from incident on the surface in the shielding region 421 due to the presence of the patterning structure is reduced by the evaporation flux 1005 including a portion induced at an incident angle in a non-normal direction. For example, the evaporation flux 1005 is at an incident angle θ. i It may contain a portion incident on the shielding region 421 at θ i which is the angle θ in the tangential direction of a part of the patterning structure 601 extending between the base portion 612 and the upper portion 615 p or more. For example, the portion extending between the base portion 612 and the upper portion 615 may or may not be substantially linear as will be described later. In some embodiments, at least a portion of the evaporation flux 1005 is not collimated. In some embodiments, the device 1100 is displaced during processing. For example, the device 1100 including the substrate 100 is displaced while being exposed to the evaporation flux 1005. In some embodiments, the device 1100 and the substrate 100 undergo angular displacement, lateral displacement, and / or vertical displacement. The evaporation flux 1005 may be generated by a point evaporation source, a line evaporation source, or a surface evaporation source. In some embodiments, processing the nucleation suppression coating 901 and the shielding region 1010 includes rotating the device 1100 including the substrate 100 around the rotation axis 520. For example, the rotation axis 520 shown in FIG. 5 may be oriented substantially normal to the surface 105 or the plane of the substrate 100. As shown in the figure, the conductive coating 1010 is formed such that the conductive coating 1010 is in direct physical contact with both the auxiliary electrode 501 and the second electrode 801. In some embodiments, the second electrode 801 and the auxiliary electrode 501 are electrically connected to each other by the conductive coating 1010. In some embodiments, the material of the conductive coating 1010 includes magnesium.

[0033] FIG. 6 shows an optoelectronic device 1100 of one embodiment manufactured according to the process described above. The device 1100 includes a radiative region 1201 disposed adjacent to a non-radiative region 1204. In some embodiments, the radiative region 1201 corresponds to a sub-pixel region of the device 1100. The radiative region 1201 includes a first electrode 300, a second electrode 801, and a semiconductor layer 701 disposed between the first electrode 300 and the second electrode 801. The non-radiative region 1204 includes an auxiliary electrode 501 and a patterning structure 601 disposed to overlap the auxiliary electrode 501. The patterning structure 601 extends laterally to provide a shielding region 421. In the illustrated embodiment, the shielding region 421 corresponds to a region above the surface of the pixel defining layer 401, and that region overlaps the lateral extension of the patterning structure 601. The non-radiative region 1204 further includes a conductive coating 1010 disposed on the shielding region 421. The conductive coating 1010 electrically connects the auxiliary electrode 501 and the second electrode 801. The nucleation suppression coating 901 is disposed on the radiative region 1201 and the non-radiative region 1204. The nucleation suppression coating 901 is disposed on the surface of the second electrode 801. In some embodiments, the surface of the patterning structure 601 is covered with the remaining second electrode 811 and the remaining nucleation suppression coating 911. The shielding region 421 does not substantially include or is not covered by the nucleation suppression coating 901, and the conductive coating 1010 can be deposited thereon.

[0034] FIG. 7 shows a optoelectronic device 1101 according to an embodiment in which an auxiliary electrode 501 is disposed on a surface 105 of a substrate 100. In the illustrated embodiment, the device 1101 includes a radiation region 1201 disposed adjacent to a non-radiation region 1204. The radiation region 1201 includes a first electrode 300 disposed on the surface 105 of the substrate 100, a semiconductor layer 701 disposed on the first electrode 300, and a second electrode 801 disposed on the semiconductor layer 701. The non-radiation region 1204 includes an auxiliary electrode 501 formed on the surface 105 of the substrate 100 and a patterning structure 601 disposed so as to overlap the auxiliary electrode 501. The patterning structure 601 extends laterally so as to provide a shielding region 421. In the illustrated embodiment, the shielding region 421 corresponds to a region on the surface 105 of the surface 100, and that region overlaps with the lateral extension of the patterning structure 601. The non-radiation region 1204 further includes a conductive coating 1010 disposed in the shielding region 421. The conductive coating 1010 electrically connects the auxiliary electrode 501 and the second electrode 801. A nucleation suppression coating 901 is disposed in the radiation region 1201 and the non-radiation region 1204. The nucleation suppression coating 901 is disposed on the surface of the second electrode 801. In some embodiments, the surface of the patterning structure 601 is covered with the remaining second electrode 811 and the remaining nucleation suppression coating 911. A part of the surface 105 corresponding to the shielding region 421 substantially does not contain or is not covered by the nucleation suppression coating 901, and the conductive coating 1010 can be deposited thereon.

[0035] FIGS. 8A-8F show patterning structures 601 and auxiliary electrodes 501 according to various embodiments. Corresponding features in the various embodiments of FIGS. 8A-8F are labeled with the same reference numerals, but different subscripts such as a, b, c, d, e, etc. are given to show the different embodiments.

[0036] In FIG. 8A, the patterning structure 601a includes a base portion 612a, an upper portion 615a, and sidewalls 601a extending between the base portion 612a and the upper portion 615a. The upper portion 615a extends laterally from the base portion 601, and as a result, a laterally extending portion 605a of the patterning structure 601a is formed. The laterally extending portion 605a forms a shielding region 421a on the surface 515 on which the patterning structure 601a is disposed. For example, the surface 515 may be the surface of a pixel defining layer or the surface of a substrate. In the illustrated embodiment, the sidewalls 601a are shown as including curved surfaces. Specifically, concave sidewalls 601a are shown. The auxiliary electrode 501 is disposed in an overlapping relationship with the patterning structure 601a. In the illustrated embodiment, the shielding region 421a does not substantially include or cover the auxiliary electrode 501, and as a result, the surface 515 is exposed.

[0037] In FIG. 8B, an embodiment is shown in which the auxiliary electrode 501 extends laterally and overlaps a laterally extending portion 605b of the patterning structure 601b. In such an embodiment, a part of the auxiliary electrode 501 is provided in the shielding region 421b of the surface 515. Therefore, a conductive coating (not shown) may be deposited on the surface of the auxiliary electrode 501 in the shielding region 421b.

[0038] In FIG. 8C, the patterning structure 601c includes a base portion 612c, an upper portion 615c, and sidewalls 601c extending between the base portion 612c and the upper portion 615c. The laterally extending portion 605c is formed between the base portion 612c and the upper portion 615c of the patterning structure 601c. The laterally extending portion 605c forms a shielding region 421c on the surface 515 where the patterning structure 601c is disposed. For example, the surface 515 may be the surface of the pixel defining layer or the surface of the substrate. In the illustrated embodiment, the sidewalls 601c are shown to include curved surfaces. Specifically, the sidewall 601a includes both concave and convex portions. The auxiliary electrode 501 is disposed in an overlapping relationship with the patterning structure 601c. In the illustrated embodiment, the shielding region 421a does not substantially include or is not covered by the auxiliary electrode 501, and as a result, the surface 515 is exposed.

[0039] In FIG. 8D, an embodiment is shown in which the auxiliary electrode 501 extends laterally and overlaps the laterally extending portion 605d of the patterning structure 601d. In such an embodiment, a portion of the auxiliary electrode 501 is provided in the shielding region 421d of the surface 515. Accordingly, a conductive coating (not shown) may be deposited on the surface of the auxiliary electrode 501 in the shielding region 421d. Optionally, the conductive coating 501 may extend beyond the shielding region 421b, and as a result, a portion of the auxiliary electrode 501 is not covered or masked by the patterning structure 601d.

[0040] In FIG. 8E, the patterning structure 601e includes a base portion 612e, an upper portion 615e, and sidewalls 601e extending between the base portion 612e and the upper portion 615e. The upper portion 615e extends laterally from the base portion 601, and as a result, a laterally extending portion 605e of the patterning structure 601e is formed. In the illustrated embodiment, the sidewalls 601e and the laterally extending portions 605e are provided on at least two sides of the patterning structure 601e. Each laterally extending portion 605e forms a shielding region 421e on the surface 515 on which the patterning structure 601e is disposed. For example, the surface 515 may be the surface of a pixel defining layer or the surface of a substrate. In the illustrated embodiment, the sidewall 601a is shown to include a linear or straight surface. The auxiliary electrode 501 is disposed in an overlapping relationship with the patterning structure 601e. In the illustrated embodiment, each shielding region 421e formed by the laterally extending portion 605e substantially does not include or is not covered by the auxiliary electrode 501, and as a result, the surface 515 is exposed.

[0041] In FIG. 8F, an embodiment is shown in which the auxiliary electrode 501 extends laterally and overlaps each of the laterally extending portions 605e of the patterning structure 601b. In such an embodiment, a portion of the auxiliary electrode 501 is provided in each shielding region 421f of the surface 515. Accordingly, a conductive coating (not shown) may be deposited on the surface of the auxiliary electrode 501 in the shielding region 421f and be in electrical contact with the auxiliary electrode 501 on at least two sides.

[0042] Naturally, the sidewalls 601e, 601f shown in FIGS. 8E and 8F respectively may include curved portions such as those shown in FIGS. 8A - 8E. In some embodiments, the sidewalls are symmetric. In some embodiments, the sidewalls are asymmetric, and as a result, different sidewalls are provided on one side and the other side.

[0043] FIG. 9 shows a optoelectronic device 1102 according to an embodiment in which an auxiliary electrode is integrally formed on a conductive coating 1012 and disposed on the surface of a pixel defining layer 401. In the illustrated embodiment, the device 1102 includes a light emitting region 1201 disposed adjacent to a non-light emitting region 1204. The light emitting region 1201 includes a first electrode 300 disposed on a surface 105 of a substrate 100, a semiconductor layer 701 disposed on the first electrode 300, and a second electrode 801 disposed on the semiconductor layer 701. The non-light emitting region 1204 includes a pixel defining layer 401 and a patterning structure 601 disposed on the surface of the pixel defining layer 401. The patterning structure 601 extends laterally to provide a shielding region 421. In the illustrated embodiment, the shielding region 421 corresponds to a region on the surface of the pixel defining layer 410 that overlaps with the lateral extension of the patterning structure 601. The non-light emitting region 1204 further includes a conductive coating 1012 disposed in the shielding region 421. In the illustrated embodiment, at least a portion of the conductive coating 1012 is formed to function as an auxiliary electrode. The conductive coating 1012 is electrically connected to the second electrode 801 and reduces the sheet resistance of the second electrode 801. A nucleation inhibition coating 901 is disposed on the light emitting region 1201 and the non-light emitting region 1204. The nucleation inhibition coating 901 is disposed on the surface of the second electrode 801. In some embodiments, the surface of the patterning structure 601 is covered with the remaining second electrode 811 and the remaining nucleation inhibition coating 911. A portion of the surface of the pixel defining layer 401 corresponding to the shielding region 421 is substantially free of or not covered by the nucleation inhibition coating 901, and the conductive coating 1012 can be deposited thereon.

[0044] FIG. 10 shows a photoelectronic device 1103 according to an embodiment in which an auxiliary electrode is integrally formed with a conductive coating 1012 and disposed on a surface 105 of a substrate 100. In the illustrated embodiment, the device 1103 includes a radiation region 1201 disposed adjacent to a non-radiation region 1204. The radiation region 1201 includes a first electrode 300 disposed on the surface 105 of the substrate 100, a semiconductor layer 701 disposed on the first electrode 300, and a second electrode 801 disposed on the semiconductor layer 701. The non-radiation region 1204 includes a pixel defining layer 401 and a patterning structure 601 disposed on the surface 105 of the substrate 100. The patterning structure 601 extends laterally to provide a shielding region 421. In the illustrated embodiment, the shielding region 421 corresponds to a region on the surface of the pixel defining layer 410, and that region overlaps with the lateral extension of the patterning structure 601. The non-radiation region 1204 further includes a conductive coating 1012 disposed in the shielding region 421. In the illustrated embodiment, at least a portion of the conductive coating 1012 is formed to function as an auxiliary electrode. The conductive coating 1012 is electrically connected to the second electrode 801 and reduces the sheet resistance of the second electrode 801. A nucleation suppression coating 901 is disposed on the radiation region 1201 and the non-radiation region 1204. The nucleation suppression coating 901 is disposed on the surface of the second electrode 801. In some embodiments, the surface of the patterning structure 601 is covered with the remaining second electrode 811 and the remaining nucleation suppression coating 911. A portion of the surface 105 corresponding to the shielding region 421 is substantially free of or not covered by the nucleation suppression coating 901, and the conductive coating 1012 can be deposited thereon.

[0045] In some embodiments, a nucleation promoting coating is provided. FIG. 11 shows an embodiment in which device 1104 includes a nucleation promoting coating 1022 disposed on the surface of pixel defining layer 401 and under conductive coating 1010. The nucleation promoting coating 1022 may be deposited before the deposition of nucleation inhibiting coating 901 and / or second electrode 801. For example, the nucleation promoting coating 1022 may be formed after providing the pixel defining layer 401 on the surface 105 of substrate 100 and before depositing semiconductor layer 701. In the illustrated embodiment, the nucleation promoting coating 1022 is provided in the region of the surface of the pixel defining layer 401 corresponding to the shielding region 421. The nucleation promoting coating 1022 is disposed so as to be in direct contact with the surfaces of pixel defining layer 401 and conductive coating 1010. In some embodiments, the nucleation promoting coating 1022 may be provided by a portion of semiconductor layer 701. For example, the material for forming the electron injection layer of semiconductor layer 701 may be deposited using an open mask deposition process, resulting in the deposition of such material in both the emission region 1201 and non-emission region 1204 of device 1104. For example, referring to FIG. 11, a portion of semiconductor layer 701 (e.g., the electron injection layer) may be deposited to cover the surface of pixel defining layer 401 in shielding region 421. Examples of such materials for forming the electron injection layer include, but are not limited to, alkali metals, alkaline earth metals, fluorides of alkaline earth metals, fullerenes, and mixtures of two or more of the foregoing. Examples of such materials include lithium (Li), ytterbium (Yb), ytterbium fluoride (YbF 3 ), magnesium fluoride (MgF 2) and include, but are not limited to, cesium fluoride (CsF). In other embodiments, the nucleation promoting coating 1022 may be provided by the second electrode 801 or a part thereof. For example, the second electrode 801 may extend laterally to cover the surface of the pixel defining layer 401 in the shielding region 421. For example, the second electrode 801 may, in some cases, include two or more layers or materials. For example, the second electrode 801 may include a lower second electrode layer and an upper second electrode layer, and the upper second electrode layer is disposed on top of the lower second electrode layer. For example, the lower second electrode layer may include oxides such as ITO, IZO, and ZnO, and the upper second electrode layer may include metals such as Ag, Mg, Yb, Mg:Ag, Yb / Ag, other alkali and alkaline earth metals, and combinations thereof. In a further example, the lower second electrode layer may extend laterally to cover the shielding region 421, and as a result, the lower second electrode layer forms the nucleation promoting coating 1022.

[0046] In some embodiments, the surface of the pixel defining layer 401 may be treated to form a nucleation promoting coating. FIG. 12 shows an embodiment in which the device 1105 includes a pixel defining layer 401 having a nucleation promoting coating 1022 provided on its surface. Specifically, in the embodiment of FIG. 12, the surface of the pixel defining layer 1022 including the region corresponding to the shielding region 421 and the region outside the shielding region 421 is provided with the nucleation promoting coating 1022. For example, the nucleation promoting coating 1022 may be provided before forming the auxiliary electrode 501 and the patterning structure 601. For example, the nucleation promoting coating 1022 may be provided after forming the pixel defining layer 401 and before forming the auxiliary electrode 501 and the patterning structure 601. In some embodiments, the nucleation promoting coating 1022 is formed by treating the surface of the pixel defining layer 401. In some embodiments, the surface of the pixel defining layer is treated chemically and / or physically. For example, the surface of the pixel defining layer 401 may be treated by exposing the surface to plasma treatment, UV treatment, and / or UV-ozone treatment. Without wishing to be bound by a particular theory, such treatment is assumed to chemically and / or physically modify the surface of the pixel defining layer 401 and modify its properties. For example, the treatment of the pixel defining layer 401 results in an increase in the concentration of C-O or C-OH bonds on the surface, an increase in the surface roughness, and / or an increase in the concentration of certain particles and / or functional groups such as halogen, nitrogen-containing functional groups, and / or oxygen-containing functional groups, thereby functioning as the nucleation promoting coating 1022. Although the nucleation promoting coating 1022 is shown as being provided only on the surface of the pixel defining layer 401, in some embodiments, the pixel defining layer 401 may be formed using a material for forming the nucleation promoting coating 1022, whereby it will be understood that the entire pixel defining layer 401 may function as the nucleation promoting coating.

[0047] FIG. 13 shows an embodiment of a device 1106 in which the nucleation promoting coating 1022 is provided on both the radiation region 1201 and the non-radiation region 1204. In the illustrated embodiment, the nucleation promoting coating 1022 is deposited after depositing the second electrode 801 and before depositing the nucleation suppressing coating 901. In such an embodiment, the nucleation promoting coating 1022 is disposed between the second electrode 801 and the nucleation suppressing coating 901, and the nucleation promoting coating 1022 may be in direct contact with the second electrode 801 and the nucleation suppressing coating 901. In this way, during the deposition of the conductive coating 1010, the surface of the radiation region 1201 is covered by the nucleation suppressing coating 901, thereby suppressing the deposition of the conductive coating 1010 in the radiation region 1201. In the illustrated embodiment, the nucleation promoting coating 1010 is also provided on the surface of the pixel defining layer 401 corresponding to the shielding region 421. For example, an evaporation source for depositing the nucleation promoting material may be used to direct the evaporated nucleation promoting material toward the radiation region 1201 and the non-radiation region 1204, including the surface of the pixel defining layer 401 corresponding to the shielding region 421, such that the evaporated nucleation promoting material impinges on such surfaces. In some embodiments, the deposition of the nucleation promoting coating 1022 is performed using an open mask or without a mask. In some embodiments, at least a portion of the evaporation flux is directed at an angle non-normal to the surface of the pixel defining layer 401 corresponding to the shielding region 421. For example, at least a portion of the evaporation flux may impinge on the surface of the pixel defining layer 401 at an angle of incidence less than 90° with respect to the surface of the pixel defining layer 401. For example, the angle of incidence is less than about 85°, less than about 80°, less than about 75°, less than about 70°, less than about 60°, or less than about 50°. By directing the evaporation flux including the portion that impinges on the surface at a non-normal angle, the shielding region 421 may be exposed to the evaporation flux. Specifically, the possibility that such an evaporation flux is prevented from colliding with the surface in the shielding region 421 due to the presence of the patterning structure is reduced for the evaporation flux including the portion directed at a non-normal angle of incidence.In some embodiments, at least a portion of the evaporation flux is not collimated. In some embodiments, device 1106 is displaced during processing. For example, device 1106 including substrate 100 is displaced while being exposed to the evaporation flux. In some embodiments, device 1106 and substrate 100 undergo angular displacement, lateral displacement, and / or vertical displacement. In some embodiments, device 1106 including substrate 100 is rotated about an axis of rotation. For example, the axis of rotation may be oriented substantially normal to surface 105 or the plane of substrate 100. During deposition of nucleation promoting coating 1022, the remaining nucleation promoting coating 1032 may be formed on top of patterning structure 601. In particular, such remaining nucleation promoting coating 1032 is formed in embodiments where an open mask is used or the nucleation promoting coating material is deposited without a mask. As shown, the remaining nucleation promoting coating 1032 is disposed between the remaining second electrode 811 and the remaining nucleation suppressing coating 911.

[0048] FIG. 14 shows an embodiment of device 1107 in which auxiliary electrode 501 is formed on surface 105 of substrate 100 and nucleation promoting coating 1022 is provided between surface 105 and conductive coating 1010 in shielding region 421. The various descriptions of nucleation promoting coating 1022 described in connection with the embodiments of FIGS. 11, 12, and 13 may be applicable to the embodiment of FIG. 14. For example, nucleation promoting coating 1022 may be formed by depositing a nucleation promoting material on a portion of surface 105 corresponding to shielding region 421, or by treating at least a portion of surface 105 to modify its properties. In some embodiments, surface 105 is chemically and / or physically treated. For example, surface 105 may be treated by exposing the surface to plasma treatment, UV treatment, and / or UV-ozone treatment. In some embodiments, nucleation promoting coating 1022 covers non-radiative region 1204. In some embodiments, nucleation promoting coating 1022 covers both radiative region 1201 and non-radiative region 1204.

[0049] Figures 15A - 15F are schematic views of the conductive coating 1010 deposited on the shielding region 421 according to various embodiments. In the illustrated embodiments, the conductive coating 1010 is deposited on a shielding region 421 disposed laterally on the surface 515 between the auxiliary electrode 501 and the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901. As described above, the second electrode 801 is generally disposed on top of the semiconductor layer 701, and the nucleation suppression coating 901 is disposed on top of the second electrode 801. In each of the embodiments of Figures 15A - 15E, the conductive coating 1010 is in direct physical and electrical contact with the auxiliary electrode 501.

[0050] In Figure 15A, the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901 are shown as extending laterally to the boundary of the shielding region 421. In such an embodiment, the edge of the conductive coating 1010 is in direct contact with the edge of the second electrode 801 at the boundary of the shielding region 421. Moreover, the edge of the conductive coating 1010 is in direct contact with the edges of the semiconductor layer 701 and the nucleation suppression coating 901 at the boundary of the shielding region 421.

[0051] In Figure 15B, the semiconductor layer 701 is shown as extending laterally to the boundary of the shielding region 421. The corresponding edges of the second electrode 801 and the nucleation suppression coating 901 are shown as being recessed from the boundary of the shielding region 421. In such an embodiment, the conductive coating 1010 extends away from the auxiliary electrode 501 beyond the shielding region 421, such that the edge of the conductive coating 1010 is in direct contact with the edge of the second electrode 801 at a position outside of the shielding region 421 (e.g., a position recessed from the boundary of the shielding region 421).

[0052] In FIG. 15C, the edge of the semiconductor layer 701 is shown as being recessed from the boundary of the shielding region 421, and such an edge of the semiconductor layer 701 is covered by the second electrode 801. The edges of the second electrode 801 and the nucleation suppression coating are shown as extending to the boundary of the shielding region 421, and as a result, the edge of the conductive coating 1010 is in direct contact with the edge of the second electrode 801 at such a boundary.

[0053] In FIG. 15D, the edges of the semiconductor layer 701 and the second electrode 801 are recessed from the boundary of the shielding region 421. The edge of the semiconductor layer is covered by the second electrode 801, and the edge of the second layer 801 is covered by the nucleation suppression coating 901. In such an embodiment, the edge of the conductive coating 1010 may be in direct contact with the edge of the nucleation suppression coating 901 at the boundary of the shielding region 421.

[0054] In FIG. 15E, the semiconductor layer 701 is shown as extending to the boundary of the shielding region 421. The second electrode 801 is disposed on the semiconductor layer 701 and extends beyond the boundary of the shielding region 421 towards the auxiliary electrode 501, and as a result, the second electrode 801 covers at least a part of the shielding region 421. For example, the second electrode 801 may substantially cover a part of the surface 515 corresponding to the shielding region 801. In other examples, the second electrode 801 may selectively cover a part of the shielding region 801, and as a result, the second electrode 801 is not in direct physical contact with the auxiliary electrode 501. The nucleation suppression coating 901 is provided on the second electrode 801, and is configured such that the surface of the second electrode 801 corresponding to the shielding region 421 does not substantially contain or is exposed from the nucleation suppression coating 901. In this way, the conductive coating 1010 may be deposited on the second electrode 801 in the shielding region 421 and be in direct physical and electrical contact with the auxiliary electrode 501 and the second electrode 801.

[0055] In FIG. 15F, an embodiment is shown in which the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901 are arranged in the same manner as in the embodiment of FIG. 15E, except that the second electrode 801 further extends to cover at least a part of the auxiliary electrode 501. For example, the second electrode 801 may cover the surface 515 in the shielding region 421 and the surface of the auxiliary electrode 501, and as a result, the second electrode is disposed at the interface between the auxiliary electrode 501 and the conductive coating 1010. In such an embodiment, the auxiliary electrode 501 and the conductive coating 1010 are not in direct physical contact, but the auxiliary electrode 501, the conductive coating 1010, and the second electrode 801 may still be in electrical contact with each other.

[0056] In some embodiments, it may be particularly desirable to deposit the remaining nucleation suppression coating 911 on top of the patterning structure 601, such that depositing the conductive coating 1010 on top of the patterning structure 601 is substantially suppressed. For example, in some cases where a conductive coating material is deposited on top of the patterning structure 601, such a coating grows laterally beyond the edge of the top 615 of the patterning structure 601, thereby suppressing the deposition of the conductive coating material in the shielding region 421. Thus, in some embodiments, the top surface of the patterning structure 601 is substantially free of or exposed from the conductive coating.

[0057] In some embodiments, the second electrode 801 and the conductive coating 1010 may not be in direct contact (e.g., the second electrode 801 and the conductive coating 1010 may be physically separated from each other by other layers and / or coatings), and yet, the second electrode 801 and the conductive coating 1010 are electrically connected to enable current to flow between them, thereby reducing the effective sheet resistance of the second electrode 801. For example, referring to the embodiment of FIG. 15D, the thickness of the nucleation suppression coating 901 is thin enough that current can flow or tunnel through it with little substantial impedance. Alternatively or additionally, the nucleation suppression coating 901 is formed using a conductive material and can electrically connect the conductive coating 1010 to the second electrode 801.

[0058] In particular, in an AMOLED device having a pixel defining layer or a bank structure with a relatively high aspect ratio (e.g., the relative ratio of height to width), it is difficult to electrically connect a common electrode to an auxiliary electrode formed on the surface of a substrate using a relative method.

[0059] In one aspect, a method for manufacturing an optoelectronic device is provided, the method including providing a substrate having a substrate surface. The substrate includes at least one thin film transistor. A first electrode and an auxiliary electrode are disposed on the substrate surface. The first electrode is in electrical communication with at least one thin film transistor. A bank structure is disposed on the surface, and the bank structure defines a via region for exposing the auxiliary electrode. For example, the surface of the auxiliary electrode may be exposed in the via region. The method includes depositing a semiconductor layer on the first electrode, depositing a second electrode on the semiconductor layer, depositing a nucleation suppression coating on the second electrode, and treating the nucleation suppression coating and the via region to deposit a conductive coating on the via region, with at least a portion of the nucleation suppression coating remaining substantially uncovered by the conductive coating. When depositing the conductive coating, the second electrode and the auxiliary electrode are electrically connected by the conductive coating. In some embodiments, the via is defined by the bank structure. In some embodiments, the via region is defined by a via extending substantially vertically. In some embodiments, the via extends substantially vertically through a portion of the bank structure. In some embodiments, another bank structure is disposed on the surface, and the via is defined by a gap formed between this bank structure and the other bank structure. For example, the other bank structure may be disposed laterally spaced from this bank structure. In some embodiments, at least a portion of the bank structure is disposed laterally between the first electrode and the auxiliary electrode. In some embodiments, at least a portion of the semiconductor layer is deposited by printing. In some embodiments, the nucleation suppression coating is deposited at a non-normal angle of incidence. The via region is substantially free of the nucleation suppression coating.

[0060] FIG. 16 shows a device 1108 manufactured in accordance with one embodiment in which the device 1108 includes one or more bank structures 425a, 425b, 425c. In the illustrated embodiment, the device 1108 includes a radiation region 1201 disposed adjacent to a non-radiation region 1204. The radiation region 1201 includes a first electrode 300 disposed on a surface 105 of a substrate 100, a semiconductor layer 701 disposed on the first electrode 300, and a second electrode 801 disposed on the semiconductor layer 701. For example, at least a portion of the semiconductor layer 701 may be deposited by a printing technique such as inkjet printing. The non-radiation region 1204 includes one or more bank structures 425a, 425b, 425c. The one or more bank structures 425a, 425b, 425c generally define a particular structure, such as a well structure, which may be filled with a material forming the semiconductor layer 701. An auxiliary electrode 501 is provided on the surface 105 of the substrate 100. In the illustrated embodiment, the auxiliary electrode 501 is disposed in the non-radiation region 1204 and in a via region 448 defined between the bank structure 425b and the bank structure 425c. In some embodiments, the bank structures 425b and 425c may be physically cut or insulated such that a via 450 is defined between the bank structure 425b and an adjacent bank structure 425c. In such embodiments, the via region 448 corresponds to an area defined by the walls of the bank structures 425b, 425c forming the via 450. In some embodiments, the bank structures 425b and 425c may be formed as an integral or continuous structure. In such embodiments, the via 450 may extend through the bank structures 425b, 425c and define the via region 448. For example, the via 450 may extend substantially perpendicular to the surface of the auxiliary electrode 501. The non-radiation region 1204 further includes a conductive coating 1010 disposed in the via region 448. In the illustrated embodiment, the conductive coating 1010 is disposed inside the via 450 and is in electrical contact with the auxiliary electrode 501 and the second electrode 801. In some embodiments, the conductive coating 1010 is in direct physical contact with the auxiliary electrode 448 and / or the second electrode 801.The nucleation inhibition coating 901 is disposed in the radiation region 1201 and the non-radiation region 1204. The nucleation inhibition coating 901 is disposed on the surface of the second electrode 801. The through-hole region 448 does not substantially contain or is not covered by the nucleation inhibition coating 901, and the conductive coating 1010 can be deposited thereon. In some embodiments, the nucleation inhibition coating 901 is deposited by evaporating a nucleation inhibition coating material to generate an evaporation flux and exposing the surface of the second electrode 801 to the evaporation flux to deposit the nucleation inhibition coating 901 thereon. In order to reduce the possibility of the evaporation flux of the nucleation inhibition coating material incident on the through-hole region 448, the evaporation flux of the nucleation inhibition coating material may be induced to an off-normal incident angle. Specifically, by providing the bank structures 425b, 425c having a relatively high aspect ratio, the evaporation flux induced as an off-normal incident angle is less likely to reach the surface of the auxiliary electrode 501 disposed in the through-hole region 448 formed by the bank structures 425b, 425c. Therefore, the deposition of the nucleation inhibition coating 901 on the surfaces of the through-hole region 448 and the auxiliary electrode 501 is reduced. In some embodiments, the nucleation inhibition coating 901 may be deposited by selectively printing a material for forming the nucleation inhibition coating 901 on the surface of the second electrode 801. For example, various printing techniques such as inkjet printing may be used to deposit the nucleation inhibition coating 901.

[0061] It will be understood that the features described in various embodiments are applicable to and may be combined with other features described in other embodiments. For example, referring to the embodiment of FIG. 16, the device 1108 may further include, for example, a nucleation promotion coating on the surfaces of the bank structures 425b, 425c.

[0062] In one aspect, an optoelectronic device is provided. The optoelectronic device includes a first electrode and a second electrode, a semiconductor layer disposed between the first electrode and the second electrode, a nucleation suppression coating disposed on at least a portion of the second electrode, an auxiliary electrode having sidewalls, and a conductive coating disposed adjacent to the sidewalls and electrically connected to the auxiliary electrode and the second electrode.

[0063] FIG. 17A shows an optoelectronic device 1109 according to one embodiment. The device 1109 includes a substrate 100 that includes one or more TFTs 200. A first electrode 300 is formed on a surface 105 of the substrate 100 such that the first electrode 300 is in electronic communication with the TFTs 200. Next, a pixel definition layer 401 is provided on the surface 105 of the substrate 100 such that the PDL 401 defines an opening through which the surface of the first electrode 300 is exposed. Each opening defined by the PDL 401 generally corresponds to an emission region 1201 of the device 1109. In the illustrated embodiment, the auxiliary electrode 503 is shown as being provided on the PDL 401. For example, the auxiliary electrode 503 may be disposed on the surface of the PDL 401 such that the auxiliary electrode 503 is in physical contact with the PDL 401. For example, the surface of the PDL 401 on which the auxiliary electrode 503 is provided may be electrically insulating. The device 1109 further includes a semiconductor layer 701 disposed on the first electrode 300 and a second electrode 801 disposed on the semiconductor layer 701. Next, a nucleation suppression coating 901 is disposed on at least a portion of the second electrode 801. In some embodiments, at least a portion of the second electrode 801 corresponding to the emission region 1201 is covered by the nucleation suppression coating 901. In some further embodiments, a portion of the second electrode 801 corresponding to the non-emission region 1204 is also covered by the nucleation suppression coating 901. The conductive coating 1010 is disposed adjacent to the auxiliary electrode 503 and electrically connects the auxiliary electrode 1010 and the second electrode 801.

[0064] FIG. 17B shows details of the device 1109 in the vicinity of the auxiliary electrode 503. In the illustrated embodiment, the auxiliary electrode 503 includes an upper portion 513, a base portion 512, and sidewalls 517 extending between the upper portion 513 and the base portion 512. The base portion 512 may form the auxiliary electrode 503 that is recessed with respect to the upper portion 513 and defines an overhang portion. In other words, the upper portion 513 may extend laterally and block an area of the underlying surface that extends beyond the area covered by the base portion 512. In this way, the sidewalls 517 extending between the upper portion 513 and the base portion 512 form an overhang profile. For example, the angle θ of the tangential direction of the sidewall 517 with respect to the normal direction of the underlying surface AIt may be about 10° or more, about 20° or more, about 30° or more, about 40° or more, about 45° or more, about 50° or more, about 55° or more, or about 60° or more. In some embodiments, due to the overhang profile of the auxiliary electrode 503, a shielding region 521 is formed adjacent to the auxiliary electrode 503. As a result, in some embodiments, the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901 may be prevented from depositing in the shielding region 521. In such embodiments, the shielding region 521 is substantially free of or substantially exposed from the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901. For example, particularly in embodiments where the deposition of materials for forming the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901 is performed using an open mask or without a mask, such materials may be deposited on the auxiliary electrode 503. For example, as shown in FIGS. 17A and 17B, the remaining semiconductor layer 711, the remaining second electrode 811, and the remaining nucleation suppression coating 911 may be sequentially deposited on the upper surface of the auxiliary electrode 503. The conductive coating 1010 is selectively deposited on the shielding region 521 according to the process detailed above. In the illustrated embodiment, the conductive coating 1010 is disposed so as to be in direct physical contact with the sidewall 517 of the auxiliary electrode 503. In some embodiments, the conductive coating 1010 may be disposed so as to be in direct physical contact with the surface of the PDL401. The conductive coating 1010 may be brought into contact with the second electrode 801 to establish electrical contact therewith.

[0065] FIG. 18 shows another embodiment of a optoelectronic device 1110 in which an auxiliary electrode 503 is disposed directly on a surface 105 of a substrate 100. Specifically, device 1110 includes a substrate 100 that includes one or more TFTs 200. Substrate 100 defines a surface 105 on which a first electrode 300 and an auxiliary electrode 503 are disposed. In some embodiments, the first electrode 300 and the auxiliary electrode 503 are formed using the same material. This can be advantageous in some cases to simplify the deposition and patterning processes for forming the first electrode 300 and the auxiliary electrode 503. For example, the surface 105 may be provided with an electrically insulating material so that the first electrode 300 and the auxiliary electrode 503 are electrically insulated from each other. Next, a PDL 401 is provided to cover a portion of the first electrode 300 and define a radiation region 1201. Next, a semiconductor layer 701, a second electrode 801, and a nucleation suppression coating 901 are sequentially deposited on the radiation region 1201 and the non-radiation region 1204. However, due to the overhang profile of the auxiliary electrode 503, the deposition of the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901 is substantially suppressed in a shielding region 521 formed adjacent to the auxiliary electrode 503. In the illustrated embodiment, the shielding region 521 is disposed in a portion of the device 1110 between the auxiliary electrode 503 and the PDL 401. For example, the auxiliary electrode 503 and the PDL 401 may be laterally spaced from each other, and the shielding region 521 may be disposed on the surface 105 of the substrate 100 between a base portion 521 of the auxiliary electrode 503 and an edge 421 of the PDL 401. A conductive coating 1010 is selectively deposited on the shielding region 521 according to the process described above to electrically contact the auxiliary electrode 503 and the second electrode 801.

[0066] FIGS. 19A-19J show side cross-sectional views of a portion of a device including an auxiliary electrode 503 and a conductive coating 1010 according to various embodiments.

[0067] In FIG. 19A, a semiconductor layer 701 extends laterally within a shielding region 521, and an embodiment is shown in which the shielding region 521 substantially does not include or is exposed from a second electrode 801 and a nucleation suppression coating 901. In the illustrated embodiment, a conductive coating 1010 is deposited on the semiconductor layer 701 in the shielding region 521. For example, the conductive coating 1010 may be deposited directly on and in contact with sidewalls 517 of the semiconductor layer 701 and / or the auxiliary electrode 503. Also, the conductive coating 1010 contacts the second electrode 801 and electrically connects the auxiliary electrode 503 to the second electrode 801. The remaining semiconductor layer 711, the remaining second electrode 811, and the remaining nucleation suppression coating 911 are sequentially deposited on top of the auxiliary electrode 503.

[0068] In FIG. 19B, both the semiconductor layer 701 and the second electrode 801 extend laterally within a shielding region 521, and an embodiment is shown in which the shielding region 521 substantially does not include or is exposed from a nucleation suppression coating 901. In the illustrated embodiment, a conductive coating 1010 is deposited on the second electrode 801 in the shielding region 521. For example, the conductive coating 1010 may be deposited directly on and in contact with sidewalls 517 of the second electrode 801 and / or the auxiliary electrode 503. In this way, the conductive coating 1010 electrically connects the auxiliary electrode 503 to the second electrode 801.

[0069] In FIG. 19C, both the semiconductor layer 701 and the second electrode 801 extend laterally within the shielding region 521, but an embodiment is shown where the shielding region 521 substantially does not contain or is exposed from the nucleation suppression coating 901. In the illustrated embodiment, the conductive coating 1010 is deposited on the second electrode 801, extends laterally away from the auxiliary electrode 503, and overlaps a portion of the nucleation suppression coating 901. For example, the conductive coating 1010 may include a portion that overlaps the nucleation suppression coating 901 by lateral growth of the conductive coating 1010. In some embodiments, the conductive coating 1010 extends laterally beyond the shielding region 521. In some further embodiments, the conductive coating 1010 is disposed in a non-radiative region of the device, and the radiative region of the device substantially does not contain or is exposed from the conductive coating 1010.

[0070] In FIG. 19D, an embodiment is shown in which the semiconductor layer 701, the second electrode 801, and the nucleation suppression coating 901 all extend laterally within the shielding region 521. For example, the thickness of the nucleation suppression coating 901 may be tapered, such that the thickness of the nucleation suppression coating 901 in the shielding region 521 is less than the thickness of the nucleation suppression coating 901 outside the shielding region 521. Similarly, in some examples, the thicknesses of the semiconductor layer 701 and the second electrode 801 in the shielding region 521 may be tapered, such that they are less than their respective thicknesses outside the shielding region 521. In the embodiment shown, the conductive coating 1010 may be deposited on the sidewall 517 of the auxiliary electrode 503 and brought into contact with the nucleation suppression coating 901. FIG. 19E shows an embodiment in which the thickness of the nucleation suppression coating 901 is substantially uniform. FIG. 19F shows an embodiment in which the conductive coating 1010 extends laterally away from the auxiliary electrode 503 and covers a portion of the device outside the shielding region 521. In the embodiments of FIGS. 19D, 19E, and 19F, the thickness of the nucleation suppression coating 901 may be sufficiently thin to establish electrical contact between the conductive coating 1010 and the second electrode 801, which is the substrate of the nucleation suppression coating 901. For example, the thickness of the nucleation suppression coating 901 may be about 15 nm or less, about 10 nm or less, about 8 nm or less, or about 5 nm or less.

[0071] FIG. 19G shows an embodiment in which the semiconductor layer 701 is disposed on the shielding region 521 and the sidewall 517 of the auxiliary electrode 503. For example, the semiconductor layer 701 may be disposed continuously to cover the shielding region 521, the sidewall 517, and the upper surface of the auxiliary electrode 503. In another example, the semiconductor layer 701 may be formed as a separate discontinuous coating on such a surface. In some embodiments, the thickness of the semiconductor layer 701 disposed on the sidewall 517 is thinner than the thickness of the semiconductor layer 701 disposed in other portions of the device, for example, in a region outside the shielding region 521. The second electrode 801 and the nucleation suppression coating 901 are shown to be deposited on the semiconductor layer 701 in a region outside the shielding region 521. However, in some embodiments, the second electrode 801 and / or the nucleation suppression coating 901 may extend laterally towards the auxiliary electrode 503 to cover the shielding region 521. The conductive coating 1010 is deposited on the shielding region 521 on the semiconductor layer 701. For example, the conductive coating 1010 may be in direct physical contact with a part of the semiconductor layer 701 disposed on the shielding region 521 and the sidewall 517. In such embodiments, for example, a part of the semiconductor layer 701 disposed on the sidewall 517 may be thin enough to establish an electrical connection between the auxiliary electrode 503 and the conductive coating 1010.

[0072] In FIG. 19H, an embodiment is shown in which the auxiliary electrode 503 defines a step edge. In the illustrated embodiment, the sidewall 517 of the auxiliary electrode 503 is substantially vertical. Thus, in such an embodiment, no shielding region is formed due to the presence of the auxiliary electrode 503. In some embodiments, the sidewall 517 of the auxiliary electrode is substantially free of or exposed from the nucleation inhibition coating 901, such that the conductive coating 1010 is deposited thereon. Then, the conductive coating 1010 may be formed to extend laterally away from the auxiliary electrode 503 and overlap the second electrode 801. The nucleation inhibition coating 901 is shown to be disposed between the conductive coating 1010 and the second electrode 801, but nevertheless, the nucleation inhibition coating 901 may be configured to establish an electrical connection between the conductive coating 1010 and the second electrode 801.

[0073] In FIG. 19I, an embodiment is shown in which the shielding region 521 is substantially free of or exposed from the semiconductor layer 521 and the nucleation inhibition coating 901. The second electrode 801 extends laterally and covers at least a portion of the shielding region 521. In such an embodiment, the conductive coating 1010 is disposed on top of the second electrode 801 in the shielding region 521, such that it is in direct physical and electrical contact with both the auxiliary electrode 503 and the second electrode 801.

[0074] In FIG. 19J, an embodiment is shown in which the second electrode 801 is configured to cover the shielding region 521 and at least a portion of the auxiliary electrode 503. In the illustrated embodiment, the second electrode 801 substantially covers the sidewall 517 of the auxiliary electrode 503 and the remaining semiconductor layer 711 disposed on the upper surface of the auxiliary electrode 503. In such a configuration, for example, the second electrode 801 is provided as a continuous or single monolithic structure, and thus, no remaining second electrode may be present. The conductive coating 1010 is disposed on the second electrode 801 in the shielding region 521.

[0075] Figures 20A to 20I show the auxiliary electrode 503 according to various embodiments in which the auxiliary electrode 503 includes a lower portion 531 and an upper portion 533.

[0076] In FIGS. 20A and 20B, the lower portion 531 includes a tapered profile such that the width of the base portion of the lower portion 531 is narrower. The lower portion 531 defines a linearly tapered side wall, and the upper portion 533 is shown to have a substantially vertical side wall. Both the lower portion 531 and the upper portion 533 define the auxiliary electrode 503 that defines an overhang and provides a shielding region. In the embodiment shown in FIG. 20A, the thickness of the lower portion 531 exceeds the thickness of the upper portion 533. In another embodiment according to FIG. 20B, the thickness of the upper portion 533 exceeds the thickness of the lower portion 531. In yet another embodiment, the thicknesses of the upper portion 533 and the lower portion 531 are substantially the same.

[0077] In FIGS. 20C and 20D, the lower portion 531 includes a tapered profile defined by a concave side wall. The upper portion 533 is shown to have a substantially vertical side wall. Both the lower portion 531 and the upper portion 533 define the auxiliary electrode 503 that defines an overhang and provides a shielding region. In the embodiment shown in FIG. 20C, the thickness of the lower portion 531 exceeds the thickness of the upper portion 533. In another embodiment according to FIG. 20D, the thickness of the upper portion 533 exceeds the thickness of the lower portion 531. In yet another embodiment, the thicknesses of the upper portion 533 and the lower portion 531 are substantially the same.

[0078] In FIG. 20E, both the lower portion 531 and the upper portion 533 include substantially vertical side walls. The width of the lower portion 531 is shown to be narrower than the width of the upper portion 533, and as a result, both the lower portion 531 and the upper portion 533 define the auxiliary electrode 503 that defines an overhang.

[0079] In FIG. 20F, the lower portion 531 includes a portion having a curved sidewall and a portion having a sidewall substantially perpendicular thereto. The upper portion 533 having a width wider than that of the lower portion 531 is disposed above the lower portion 531. In this way, the auxiliary electrode 503 defining the overhanging profile is formed.

[0080] FIG. 20G shows an embodiment in which the lower portion 531 includes a tapered portion and a recess. In this way, a recess is formed by the auxiliary electrode 503 to provide a shielding region.

[0081] In FIG. 20H, both the upper portion 533 and the lower portion 531 linearly define a tapered profile. For example, the inclination of the lower portion 531 may be steeper than that of the upper portion 533, and as a result, the base portion of the auxiliary electrode 503 is narrower than the upper portion.

[0082] In FIG. 20I, the upper portion 533 linearly defines a tapered profile, and the lower portion 531 defines a concave profile.

[0083] In some embodiments, the lower portion 531 and the upper portion 533 comprise different materials. For example, the lower portion 531 may comprise a first material and the upper portion 533 may comprise a second material. Examples of the first material and the second material include, but are not limited to, metals, alloys, metal alloys, oxides (including conductive oxides), and combinations thereof. Examples of such materials include ITO, ZnO, IZO, Ag, Cu, Mo, Al, Ti, and combinations thereof including examples such as Mo / Al / Mo and Ag / ITO. In some examples, the auxiliary electrode 503 may include additional portions and / or materials. In some embodiments, the auxiliary electrode 503 is formed using a conductive material(s). In some embodiments, the auxiliary electrode 503 includes a dielectric material, a semiconductor material, and / or an insulating material. For example, the lower portion 531 may include a conductive material such as a metal, an alloy, a metal alloy, and a conductive oxide, and the upper portion 533 may include a dielectric material, a semiconductor material, and / or an insulating material.

[0084] In some embodiments, the material for forming the lower portion 531 may have an etching rate different from that of the material for forming the upper portion 533. For example, when the lower portion 531 and the upper portion 533 are subjected to an etching process, the etching rate of the lower portion 531 may exceed the etching rate of the upper portion 533. In this way, the auxiliary electrode 503 defining the overhang profile may be formed.

[0085] In some embodiments, the lower portion 531 and the upper portion 533 are formed integrally or continuously with each other to provide a single monolithic structure. In such embodiments, for example, the lower portion 531 and the upper portion 533 may be formed using the same material.

[0086] In the various embodiments described above, the auxiliary electrode 503 is shown to have a substantially symmetric profile. In other embodiments, the auxiliary electrode 503 may have an asymmetric profile. For example, the auxiliary electrode 503 may define an overhang profile along one sidewall and not along the other sidewall.

[0087] The semiconductor layer 701 is shown to be disposed in both the emission area 1201 and the non-emission area 1204 in some embodiments, but it will be understood that in other embodiments, the semiconductor layer 701 may be selectively deposited in the emission area 1201.

[0088] In some embodiments, it may be particularly desirable to deposit the remaining nucleation suppression coating 911 on the upper surface of the auxiliary electrode 911, such that deposition of the conductive coating 1010 on the upper portion of the auxiliary electrode 911 is substantially suppressed. For example, in some cases where a conductive coating material is deposited on the upper portion of the auxiliary electrode 911, such a coating may grow laterally beyond the edge of the upper portion 513 of the auxiliary electrode 911, thereby suppressing deposition of the conductive coating material in the shielding region 521 and / or on the sidewall 517. Accordingly, in some embodiments, the upper surface of the auxiliary electrode 911 is substantially free of or exposed from the conductive coating.

[0089] In some embodiments, the thickness or height of the auxiliary electrode 503 exceeds the thickness of the semiconductor layer 701. For example, the thickness of the auxiliary electrode 503 may be about 200 nm or more, about 250 nm or more, about 300 nm or more, about 350 nm or more, about 500 nm or more, about 600 nm or more, about 750 nm or more, about 800 nm or more, or about 1 μm or more. For example, the thickness of the auxiliary electrode 503 may be about 1.1 times or more, about 1.3 times or more, about 1.5 times or more, about 1.6 times or more, about 2 times or more, about 3 times or more, about 5 times or more, or about 10 times or more the thickness of the semiconductor layer 701. By providing the auxiliary electrode 503 having a thickness exceeding the thickness of the semiconductor layer 701, the possibility that the sidewall 517 of the auxiliary electrode 503 does not substantially contain or is exposed from the nucleation suppression coating 901 increases.

[0090] In some embodiments, the second electrode or a portion thereof is provided in a shielding region. Referring to FIG. 21 here, an embodiment is shown in which the second electrode 801 is disposed in a shielding region 421 provided in the non-radiating region 1204 of the device 2101. In the illustrated embodiment, the second electrode 801 is formed as an integral or continuous structure spanning the radiating region 1201 and the non-radiating region 1204. For example, the second electrode 801 may be disposed on the surface 617 of the laterally extending portion of the patterning structure 601 for providing the shielding region 421, as well as on the upper surface 619 of the patterning structure 601. In this way, for example, the second electrode 801 may substantially cover the patterning structure 601. When the conductive coating 1010 is deposited following the nucleation suppression coating 901, the conductive coating 1010 is deposited on and in electrical contact with the upper portion of the second electrode 801. In some embodiments, the thickness of the second electrode 801 in the radiating region 1201 exceeds the thickness of the second electrode 801 in the shielding region 421. For example, during the deposition of the second electrode 801, at least a portion of the evaporation flux for forming the second electrode 801 may be suppressed from incident on a portion of the surface 105 corresponding to the shielding region 421 due to the presence of the patterning structure 601. In another example, the second electrode 801 may include a lower portion and an upper portion, and only one of the lower portion and the upper portion of the second electrode 801 may be deposited in the shielding region 421, but both portions may be deposited in the radiating region 1201, thereby creating a difference in the thickness of the second electrode 801. As shown in the embodiment of FIG. 21, at least a portion of the auxiliary electrode 501 may be covered by the second electrode 801, and thereby, the auxiliary electrode 501 and the second electrode 801 may be in electrical contact with each other. However, in some cases, it may be desirable to provide a conductive coating 1010 in the shielding region 421, for example, to reduce the contact resistance between the auxiliary electrode 501 and the conductive coating 1010. For example, providing the conductive coating 1010 in such a configuration may, in some cases, also enhance the reliability of the electrical contact. For example, the second electrode 801 in the embodiment of FIG. 21 may include a transparent conductive oxide.Examples of such transparent conductive oxides include, but are not limited to, ITO, IZO, and ZnO.

[0091] Figure 22 shows an embodiment of device 2201 with transparent conductive coatings 951 provided on the emission region 1201 and non - emission region 1204 of device 2201. For example, device 2201 may be manufactured substantially the same as device 1101 in the embodiment of FIG. 7 up to the step of depositing conductive coating 1010. Referring again to FIG. 22, after depositing conductive coating 1010, transparent conductive coating 951 is deposited using an open mask or without a mask. For example, transparent conductive coating 951 may be deposited using a physical vapor deposition process such as sputtering, which may direct at least a portion of the evaporation flux of the material used to form transparent conductive coating 951 onto the surfaces of the shielding region 421 and the patterning structure 601. Thus, in the embodiment shown in FIG. 22, transparent conductive coating 951 is provided as a continuous or single monolithic structure covering the emission region 1201 and non - emission region 1204 of device 2201. For example, transparent conductive coating 951 may be in physical and electrical direct contact with auxiliary electrode 501 and conductive coating 1010. In some embodiments, transparent conductive coating 951 may be in direct physical and electrical contact with a portion of the second electrode 801. In the emission region 1201, transparent conductive coating 951 is disposed on the nucleation suppression coating 901. In such embodiments, it will be understood that the material for forming transparent conductive coating 951 is different from the material for forming conductive coating 1010, and as a result, the deposition of transparent conductive coating 951 on the nucleation suppression coating 901 is not substantially inhibited. For example, transparent conductive coating 951 may include a transparent conductive oxide. Examples of such transparent conductive oxides include, but are not limited to, ITO, IZO, and ZnO. In some cases, providing such a transparent conductive coating 951 is particularly advantageous for improving the reliability of electrical contact, flattening the surface of device 2201, and facilitating encapsulation and / or light output coupling.

[0092] In connection with the embodiments of devices 2101 and 2201 respectively, embodiments showing the presence of the second electrode 801 and the presence of the transparent conductive coating 951 in the shielding region 421 have been described, but it will also be understood that such features may be similarly applied to other embodiments of the devices described herein.

[0093] In some embodiments, the device is configured such that the optical path of the light emitted by the device substantially does not contain or omits the presence of a conductive oxide material. For example, in the emission region 1201, the presence of the conductive oxide material may be omitted from all layers and coatings on the semiconductor layer 701. For example, the conductive oxide material may be omitted from the second electrode 801, the nucleation suppression coating 901, and any additional layers or coatings that may be deposited thereon. In some cases, it may be desirable to omit the presence of the conductive oxide material to reduce any absorption and / or reflection of the light emitted by the device. For example, conductive oxide materials such as ITO and IZO may absorb light in the blue region of the visible spectrum, especially when deposited with a sufficient thickness. This generally reduces the efficiency and performance of the device and is undesirable.

[0094] In some embodiments, the optoelectronic device further includes a capping layer or an output coupling layer. For example, the capping layer or the output coupling layer may be provided directly on the surface of the second electrode 801 or on the surface of the nucleation suppression coating 901. In particular, such a capping layer or output coupling layer may be provided in the emission region(s). In some embodiments, the nucleation suppression coating 901 may function as or form a part of the capping layer or the output coupling layer.

[0095] In some embodiments, the optoelectronic device further includes a encapsulation layer. Examples of such encapsulation layers include, but are not limited to, glass caps, barrier films, barrier adhesives, and thin film capsules. For example, the encapsulation layer may be disposed on the second electrode 801 and the nucleation suppression coating 901. In some embodiments, the optoelectronic device further includes additional optical and / or structural layers, coatings, and components. Examples of these include, but are not limited to, polarizing plates, color filters, anti-reflection coatings, anti-glare coatings, cover glasses, and optically clear adhesives (OCA).

[0096] In some embodiments, the auxiliary electrodes 501, 503, the conductive coating 1010, and the patterning structure 601 may be selectively provided in specific region(s) of the display panel. For example, any of the above features may be provided at or near one or more edges of the display panel to electrically connect one or more elements on the front surface (e.g., the second electrode) to one or more members on the back surface. In some embodiments, the auxiliary electrodes 501, 503, the conductive coating 1010, and the patterning structure 601 may be omitted from specific region(s) of the display panel. For example, such features may be omitted from a portion of the display panel except at or near one or more edges of the panel when a relatively high pixel density is desired. In such cases, it may still be desirable to provide any of the above features along one or more edges of the display panel, for example, to supply and distribute current to the cathode from auxiliary electrodes located at one or more edges. For example, such an implementation may be particularly desirable for reducing the bezel of the display panel.

[0097] In some embodiments, the sheet resistance of the conductive coating is less than or equal to the sheet resistance of the second electrode.

[0098] As used herein, the terms "overlapping" or "overlapped" are understood to refer to two or more layers and / or structures arranged so as to intersect a line drawn perpendicular to the underlying surface, and two or more layers and / or structures are disposed on the underlying surface.

[0099] In some embodiments, the remaining second electrode and the remaining nucleation suppression coating are removed and / or not deposited, and thus the surface of the patterning structure remains exposed.

[0100] While not wishing to be bound by any particular theory, it is assumed that providing the nucleation promoting coating 1022 may facilitate the deposition of the conductive coating 1010 on a particular surface. In some embodiments, the nucleation promoting coating includes fullerenes. In some embodiments, the nucleation promoting coating includes a metal. As used herein, the term "fullerene" refers to a material that includes carbon molecules. Examples of fullerene molecules include carbon cage molecules that include a three-dimensional backbone of a plurality of carbon atoms, which form a closed shell and may be spherical or hemispherical in shape. Fullerene molecules can be designated as C n where n is an integer corresponding to the number of carbon atoms included in the carbon backbone of the fullerene molecule. Examples of fullerene molecules include C n where n ranges from 50 to 250 such as C 60 C 70 C 72 C 74 C 76 C 78 C 80 C 82 and C 84 Additional examples of fullerene molecules include tube-shaped or cylindrical carbon molecules such as single-walled carbon nanotubes and multi-walled carbon nanotubes.

[0101] Materials suitable for use in forming a nucleation-inhibiting coating are characterized by presenting or having an initial adhesion probability of a conductive coating material of about 0.3 (i.e., 30%) or less or less than, or about 0.2 or less or less than, or about 0.1 or less or less than, or about 0.05 or less or less than, more specifically, about 0.03 or less or less than, about 0.02 or less or less than, about 0.01 or less or less than, about 0.08 or less or less than, about 0.005 or less or less than, about 0.003 or less or less than, about 0.001 or less or less than, about 0.0008 or less or less than, about 0.0005 or less or less than, or about 0.0001 or less or less than.

[0102] In some embodiments, materials suitable for use in forming a nucleation suppression coating are characterized as presenting or having an initial adhesion probability of a conductive coating material of from about 0.03 to about 0.0001, from about 0.03 to about 0.0003, from about 0.03 to about 0.0005, from about 0.03 to about 0.0008, from about 0.03 to about 0.001, from about 0.03 to about 0.005, from about 0.03 to about 0.008, or from about 0.03 to about 0.01. In some embodiments, materials suitable for use in forming a nucleation suppression coating are characterized as presenting or having an initial adhesion probability of a conductive coating material of from about 0.02 to 0.0001, from about 0.02 to 0.0003, from about 0.02 to 0.0005, from about 0.02 to 0.0008, from about 0.02 to 0.001, from about 0.02 to 0.005, from about 0.02 to 0.008, or from about 0.02 to 0.01. In some embodiments, materials suitable for use in forming a nucleation suppression coating are characterized as presenting or having an initial adhesion probability of a conductive coating material of from about 0.01 to about 0.0001, from about 0.01 to about 0.0003, from about 0.01 to about 0.0005, from about 0.01 to about 0.0008, from about 0.01 to about 0.001, from about 0.01 to about 0.005, or from about 0.01 to about 0.008. In some embodiments, materials suitable for use in forming a nucleation suppression coating are characterized as presenting or having an initial adhesion probability of a conductive coating material of from about 0.008 to about 0.0001, from about 0.008 to about 0.0003, from about 0.008 to about 0.0005, from about 0.008 to about 0.0008, from about 0.008 to about 0.001, or from about 0.008 to about 0.005. In some embodiments, materials suitable for use in forming a nucleation suppression coating are characterized as presenting or having an initial adhesion probability of a conductive coating material of from about 0.005 to about 0.0001, from about 0.005 to about 0.0003, from about 0.005 to about 0.0005, from about 0.005 to about 0.0008, or from about 0.005 to about 0.001.

[0103] Materials suitable for use in forming nucleation promoting coatings are characterized as presenting or having an initial adhesion probability of at least about 0.4 (i.e., 40%), at least about 0.5 (i.e., 50%), at least about 0.6 (i.e., 60%), at least about 0.7, at least about 0.75, at least about 0.8, at least about 0.9, at least about 0.93, at least about 0.95, at least about 0.98, or at least about 0.99 of a conductive coating material. Examples of suitable materials for forming nucleation promoting coatings include, but are not limited to, metals (including alkali metals, alkaline earth metals, transition metals, post-transition metals), metal fluorides, metal oxides, fullerenes, and mixtures of two or more of the foregoing. Examples of such materials include Ca, Ag, Mg, Yb, ITO, IZO, ZnO, ytterbium fluoride (YbF 3 ), magnesium fluoride (MgF 2 ), and cesium fluoride (CsF), among others.

[0104] Substrate 100 on which various coatings are deposited may include one or more additional organic and / or inorganic layers not specifically shown or described in the above embodiments. Substrate 100 may further include other electronic components such as one or more transistors and resistors and capacitors, which may be included in active matrix or passive matrix OLED devices. For example, substrate 100 may include one or more top-gate thin film transistors (TFTs), one or more bottom-gate TFTs, and / or other TFT structures. The TFT may be an n-type TFT or a p-type TFT. Examples of TFT structures include amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), and low temperature polycrystalline silicon (LTPS), among others.

[0105] The substrate 100 may include a base substrate that supports the additional organic and / or inorganic layers identified above. For example, the base substrate may be a flexible or rigid substrate. The base substrate may include, for example, silicon, glass, metal, polymer (e.g., polyimide), sapphire, or other materials suitable for use as a base substrate.

[0106] In another embodiment where the device is an electroluminescent quantum dot device, the electroluminescent layer generally includes quantum dots and emits light when current is supplied.

[0107] It will also be understood that an open mask used for the deposition of any of the various layers or coatings, including a conductive coating, a nucleation suppression coating, and a nucleation promotion coating, may "mask" or prevent the deposition of material onto a specific region of the substrate. However, unlike a fine metal mask (FMM) used to form relatively small features with feature sizes on the order of tens of microns or less, the feature sizes of an open mask generally correspond to the size of the OLED device being manufactured. For example, the open mask may mask the edges of the display device during manufacturing, such that the open mask will have an aperture that generally corresponds to the size of the display device (e.g., approximately 1 inch for a microdisplay device, approximately 4 - 6 inches for a mobile display device, approximately 8 - 17 inches for a laptop or tablet display device, etc.). For example, the feature sizes of the open mask may be on the order of about 1 cm or greater. Thus, the apertures formed in the open mask are typically sized to encompass a plurality of emission regions or pixels that together form the display device.

[0108] In some embodiments of the device, the first electrode 300 has been described as being the anode and the second electrode 801 as being the cathode, but it will be understood that in other embodiments, the first electrode 300 may be the cathode and the second electrode 801 may be the anode.

[0109] In some embodiments, the nucleation suppression coating 901 may function as an optical coating. For example, the nucleation suppression coating 901 may modify the properties or characteristics of the light emitted from the emission region 1201 of the device. In some embodiments, the nucleation suppression coating 901 may exhibit a certain degree of haze and scatter light. For example, the nucleation suppression coating 901 may comprise a crystalline material for scattering the light transmitted through the nucleation suppression coating 901. Such light scattering may be useful, for example, for increasing the external coupling of the light from the device. In some embodiments, the nucleation suppression coating 901 is first deposited as a substantially amorphous (e.g., substantially amorphous) coating. After depositing the conductive coating 1010, the nucleation suppression coating 901 may be crystallized to function as an optical coating.

[0110] The pixel defining layer 401 is generally shown as having a linearly sloped surface and forming a "bank" for defining the emission area 1201, but it will be understood that the shape, aspect ratio, thickness, width, and configuration of the pixel defining layer 401 may be different in other embodiments. For example, the pixel defining layer 401 may be formed with steeper or gentler sloped portions. In other examples, the pixel defining layer 401 may be configured as a substantially vertically extending structure covering one or more edges of the first electrode 300. For example, the pixel defining layer 401 may be configured to deposit a semiconductor layer via solution processing techniques (e.g., by printing including inkjet printing).

[0111] It will be understood that in the various embodiments described herein, the use of the open mask may be omitted as needed. Specifically, the open mask deposition process described herein may alternatively be performed without using a mask such that the entire target surface is exposed.

[0112] Unless otherwise clearly indicated in the context, it should be understood that features, components, and / or elements described in the singular may be provided in the plural and vice versa. For example, various embodiments of a device have been described as including radiation regions and non-radiation regions, but it should be understood that such a device may further include additional radiation regions and non-radiation regions. For example, a device may include a plurality of radiation regions. The plurality of radiation regions may further include radiation regions configured to emit light corresponding to red, blue, green, white, and / or any other color. The device may also include a plurality of thin film transistors and a plurality of first electrodes. In such embodiments, each of the plurality of first electrodes may be electrically connected to at least one of the plurality of thin film transistors.

[0113] At least some of the above embodiments are described with reference to various layers or coatings including a nucleation promoting coating, a nucleation inhibiting coating, and a conductive coating formed using an evaporation process. Of course, the evaporation process is a type of PVD process, in which one or more source materials are evaporated or sublimated in a low-pressure (such as vacuum) environment, and the reverse sublimation of the one or more evaporated source materials is used to deposit them on a target surface. It will be understood that various different evaporation sources may be used to heat the source material, and thus the source material may be heated in various ways. For example, the source material may be heated by an electric filament, an electron beam, induction heating, or resistance heating. In addition, such layers or coatings may be deposited and / or patterned using other suitable processes including photolithography, printing, OVPD, LITI patterning, and combinations thereof. These processes may be used in combination with a shadow mask to achieve various patterns.

[0114] Although specific processes have been described for evaporation to deposit the nucleation promoting material, the nucleation inhibiting material, and the second electrode, it will be understood that various other processes may be used to deposit these materials. For example, the deposition may be carried out using other PVD processes (including sputtering), CVD processes (including plasma enhanced chemical vapor deposition (PECVD)), or other suitable processes for depositing such materials. In some embodiments, magnesium is deposited by heating a magnesium source material using a resistive heater. In other embodiments, the magnesium source material may be mounted in a heated crucible, a heated boat, a Knudsen cell (e.g., an effusion evaporation source), or any other type of evaporation source.

[0115] The deposition source material used to deposit the conductive coating may be a mixture or a compound. In some embodiments, at least one component of the mixture or compound is not deposited on the substrate during deposition (or, for example, is deposited in a relatively small amount with respect to magnesium). In some embodiments, the source material may be a copper-magnesium (Cu-Mg) mixture or a Cu-Mg compound. In some embodiments, the source material of the magnesium deposition source includes magnesium and a material having a lower vapor pressure than magnesium, such as Cu. In other embodiments, the source material of the magnesium deposition source is substantially pure magnesium. Specifically, substantially pure magnesium can exhibit substantially the same properties (e.g., the initial adhesion probability on the nucleation suppression coating and the nucleation promotion coating) as pure magnesium (magnesium with a purity of 99.99% or more). For example, the initial adhesion probability of substantially pure magnesium on the nucleation suppression coating may be within ±10% or ±5% of the initial adhesion probability of 99.99% pure magnesium on the nucleation suppression coating. The purity of magnesium may be about 95% or more, about 98% or more, about 99% or more, or about 99.9% or more. The deposition source material used to deposit the conductive coating may include other metals instead of magnesium or in combination with magnesium. For example, the source material may include a high vapor pressure material such as ytterbium (Yb), cadmium (Cd), zinc (Zn), or any combination thereof.

[0116] As used herein, the terms "substantially", "substantial", "about", and "approximate" are used to represent and account for minor variations. When used with an event or situation, these terms may refer to the case where the event or situation occurs exactly, as well as the case where the event or situation occurs approximately. For example, when used with a numerical value, these terms may refer to a range of variation of ±10% or less of that numerical value, such as ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less. For example, if a first numerical value is within a range of variation of ±10% or less, such as ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less of a second numerical value, the first numerical value can be considered to be substantially the same as, or approximately the same as, the second numerical value.

[0117] In the description of some embodiments, a component provided "on (or over)" another component, or a component "covering" or "covers" another component can include the case where the former component is directly on the latter component (e.g., in physical contact), as well as the case where one or more intervening components are located between the former component and the latter component.

[0118] Additionally, amounts, ratios, and other numerical values may be presented herein in a range format. It should also be understood that such range formats are used for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly specified as the limits of the range, but also all individual numerical values or sub-ranges subsumed within that range as if each numerical value and sub-range were explicitly specified.

[0119] Although the present disclosure has been described with reference to specific embodiments, various modifications will be apparent to those skilled in the art. Any examples provided herein are included only for the purpose of illustrating particular aspects of the present disclosure and are in no way intended to limit the present disclosure. For example, the various features described with respect to specific embodiments or examples herein may be combined with features of other embodiments or examples. Any drawings provided herein are for the purpose of illustrating particular aspects of the present disclosure only and need not be drawn to scale and are in no way intended to limit the present disclosure. The claims appended hereto should not be limited by the specific embodiments described in the above description, but should be given the full scope consistent with the present disclosure as a whole. The disclosure of all documents described herein is incorporated herein by reference in its entirety.

Claims

1. 1. A photoelectric element having a plurality of layers, a nucleation inhibiting coating (NIC) disposed on a first portion of a side of the element; a feature disposed on a layer surface of a layer of the plurality of layers, the feature configured to shield a shielding region on the layer surface at a second portion of the side of the element, the feature comprising a laterally extending portion overlapping the shielding region, the shielding region being substantially devoid of the NIC; a conductive coating comprising a conductive coating material; at least a portion of a surface of the NIC is substantially devoid of the conductive coating; At least a portion of the conductive coating is disposed in the shielded region.

2. The optoelectronic device of claim 1 , wherein the shielding region is covered by the feature during deposition of the NIC to inhibit deposition of the NIC.

3. The photoelectric element is a light-emitting element, and the photoelectric element further comprises an emission region in the first portion, the emission region being: A first electrode; A second electrode; and at least one semiconductor layer disposed between the first electrode and the second electrode; The optoelectronic device of claim 1 , wherein the second electrode is disposed between the at least one semiconductor layer and the NIC, and the conductive coating is electrically coupled to the second electrode.

4. The optoelectronic device of claim 3 , wherein at least a portion of the NIC is disposed between the second electrode and the conductive coating.

5. 4. The optoelectronic device of claim 3, further comprising a pixel definition layer (PDL) covering an edge of the first electrode, the PDL defining an opening through which the first electrode is exposed and corresponding to an emissive area of ​​the device.

6. The photovoltaic device of claim 5 further comprising a third electrode spaced apart from the second electrode.

7. The photovoltaic device of claim 6 , wherein the third electrode is electrically coupled to the second electrode through the conductive coating.

8. The optoelectronic device of claim 7 , wherein the feature is a patterned structure.

9. 9. The optoelectronic device of claim 8, wherein the patterning structure comprises a base and a top portion, the top portion extending laterally outward from the base portion, thereby blocking the blocking region.

10. 10. The photovoltaic device of claim 9, wherein a sidewall extends between the base and the top, the sidewall being at least one of substantially straight, tapered, and curved.

11. The photovoltaic device of claim 8 , wherein at least a portion of the third electrode is disposed in the shielded region.

12. The photoelectric device of claim 8 , wherein the third electrode is disposed below the patterning structure.

13. The photovoltaic device of claim 8 , wherein the third electrode is integrally formed with the conductive coating.

14. The optoelectronic device of claim 8 , wherein the patterning structure is disposed on a surface of the PDL.

15. The optoelectronic device of claim 14 , wherein the third electrode is disposed on a surface of the PDL.

16. The optoelectronic device of claim 7 , wherein the feature is the third electrode.

17. 17. The optoelectronic device of claim 16, wherein the third electrode has at least one sidewall, the conductive coating being disposed adjacent to the sidewall.

18. The optoelectronic device of claim 3 further comprising a non-emissive region comprising said shielding region and said conductive coating.

19. The photoelectric element according to claim 6 , wherein the third electrode is an auxiliary electrode.

20. The photovoltaic device of claim 1 , wherein the conductive coating material comprises magnesium.

Images