Solid-state imaging device and electronic device

Abstract

A solid-state imaging device according to an embodiment of the present disclosure includes a mode switching unit that, in a first mode, electrically connects a first signal path to a photoelectric conversion unit and electrically disconnects a second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit. At least the photoelectric conversion unit is formed on a first substrate out of a first substrate and a second substrate stacked on each other, and at least a second amplification transistor is formed on the second substrate.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device and an electronic device. [Background technology]

[0002] Solid-state imaging devices are used in electronic devices such as digital still cameras, video cameras, and portable terminal devices with imaging functions. Examples of solid-state imaging devices include complementary metal-oxide semiconductor (CMOS) image sensors that read out charges accumulated in photodiodes, which are photoelectric conversion elements, via metal-oxide semiconductor (MOS) transistors.

[0003] In a CMOS image sensor, high sensitivity is desirable so that an imaging signal can be acquired even under low illumination conditions. Furthermore, to increase the dynamic range, it is desirable for the photodiode to be less prone to saturation. However, there is a trade-off between high sensitivity and photodiode saturation resistance, making it difficult to increase the dynamic range while maintaining high sensitivity. Therefore, for example, Patent Document 1 discloses providing a small-capacity floating diffusion and a large-capacity floating diffusion, connecting the small-capacity floating diffusion to the photodiode under low illumination conditions and connecting the large-capacity floating diffusion under high illumination conditions. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-134396 Summary of the Invention

[0005] However, when the invention described in Patent Document 1 is applied to high-definition applications, it is difficult to secure enough space to provide two floating diffusions. Therefore, it is desirable to provide a solid-state imaging device that can achieve both high sensitivity and a wide dynamic range even in high-definition applications, and an electronic device equipped with the same.

[0006] A solid-state imaging device according to a first aspect of the present disclosure includes a photoelectric conversion unit, a first signal path including a first floating diffusion and a first amplification transistor, a second floating diffusion and a , the size of which is larger than the size of the first amplifying transistor and a second signal path including a second amplifying transistor. The solid-state imaging device further includes a mode switching unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit. The solid-state imaging device further includes a first substrate and a second substrate. The first substrate has at least the photoelectric conversion unit formed thereon, which is comprised of the photoelectric conversion unit, first floating diffusion, first amplifying transistor, second floating diffusion, second amplifying transistor, and mode switching unit. The second substrate is stacked on the first substrate. The second substrate has at least the second amplifying transistor formed thereon, which is comprised of the photoelectric conversion unit, first floating diffusion, first amplifying transistor, second floating diffusion, second amplifying transistor, and mode switching unit.

[0007] An electronic device according to a first aspect of the present disclosure includes a solid-state imaging device that outputs pixel signals according to incident light, and a signal processing circuit that processes the pixel signals. The solid-state imaging device provided in the electronic device has a configuration similar to that of the solid-state imaging device according to the first aspect of the present disclosure.

[0008] A solid-state imaging device according to a second aspect of the present disclosure includes a photoelectric conversion unit, a first signal path including a first floating diffusion and a first amplification transistor, a second floating diffusion and a , the size of which is larger than the size of the first amplifying transistor and a second signal path including a second amplifying transistor. The solid-state imaging device further includes a mode switching unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit. The solid-state imaging device further includes a first substrate, a second substrate, and a third substrate. The first substrate has a photoelectric conversion unit and a first floating diffusion formed thereon. The second substrate is stacked on the first substrate. The second substrate has a first amplifying transistor, a second floating diffusion, and a mode switching unit formed thereon. The third substrate is stacked on the second substrate. The third substrate has a second amplifying transistor formed thereon.

[0009] An electronic device according to a second aspect of the present disclosure includes a solid-state imaging device that outputs pixel signals in response to incident light, and a signal processing circuit that processes the pixel signals. The solid-state imaging device provided in the electronic device has a configuration similar to that of the solid-state imaging device according to the second aspect of the present disclosure.

[0010] In a solid-state imaging device and an electronic device according to a first aspect of the present disclosure, and a solid-state imaging device and an electronic device according to a second aspect of the present disclosure, the amplification transistor to be used is selected according to the mode. This makes it possible to expand the dynamic range while maintaining high sensitivity. Furthermore, in a solid-state imaging device and an electronic device according to a first aspect of the present disclosure, and a solid-state imaging device and an electronic device according to a second aspect of the present disclosure, at least the amplification transistor is formed on a substrate separate from the substrate on which the photoelectric conversion unit is formed. This makes it possible to ensure sufficient space for providing a floating diffusion and an amplification transistor, even in a high-resolution solid-state imaging device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating an example of a schematic configuration of a solid-state imaging device according to an embodiment of the present disclosure. [Figure 2] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 3] 2 is a diagram illustrating an example of a cross-sectional configuration of the solid-state imaging device of FIG. 1 in the vertical direction. [Figure 4] 2 is a diagram illustrating an example of a cross-sectional configuration of the solid-state imaging device of FIG. 1 in the horizontal direction. [Figure 5] 2 is a diagram illustrating an example of a cross-sectional configuration of the solid-state imaging device of FIG. 1 in the horizontal direction. [Figure 6] 6 is a diagram illustrating an example of a configuration when the cross-sectional configuration of FIG. 4 and the cross-sectional configuration of FIG. 5 are superimposed on each other. [Figure 7] 1. FIG. 4 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device of FIG. [Figure 8A] 2A to 2C are diagrams illustrating an example of a method for manufacturing the solid-state imaging device of FIG. [Figure 8B] FIG. 8B is a diagram illustrating the manufacturing process following FIG. 8A. [Figure 8C] FIG. 8C is a diagram illustrating the manufacturing process following FIG. 8B. [Figure 8D] FIG. 8D is a diagram illustrating the manufacturing process following FIG. 8C. [Figure 8E] FIG. 8D is a diagram illustrating the manufacturing process following FIG. 8D. [Figure 8F] FIG. 8C is a diagram illustrating the manufacturing process following FIG. 8E. [Figure 8G] FIG. 8C is a diagram illustrating the manufacturing process following FIG. 8F. [Figure 9] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. FIG. [Figure 10] FIG. 5 is a diagram illustrating a modified example of the cross-sectional configuration of FIG. [Figure 11] FIG. 6 is a diagram illustrating a modified example of the cross-sectional configuration of FIG. [Figure 12] FIG. 8 is a diagram illustrating a modified example of the cross-sectional configuration of FIG. [Figure 13]2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. FIG. [Figure 14] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. FIG. [Figure 15] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. FIG. [Figure 16] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. FIG. [Figure 17] 2 is a diagram illustrating a modified example of the sensor pixel and the readout circuit of FIG. 1. FIG. [Figure 18] 1. FIG. 4 is a diagram illustrating a modification of the vertical cross-sectional configuration of the solid-state imaging device of FIG. [Figure 19] 1. FIG. 4 is a diagram illustrating a modification of the vertical cross-sectional configuration of the solid-state imaging device of FIG. [Figure 20] FIG. 10 is a diagram illustrating a modified example of a connection between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 21] 16 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device having the configuration of FIG. 15. FIG. [Figure 22] 16 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device having the configuration of FIG. 15. FIG. [Figure 23] 10A and 10B are diagrams illustrating a modification of the vertical cross-sectional configuration of the solid-state imaging device according to the above embodiment and the modification thereof. [Figure 24] FIG. 24 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device having the configurations of FIGS. 15, 21, 22, and 23. [Figure 25] FIG. 24 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device having the configurations of FIGS. 15, 21, 22, and 23. [Figure 26] 26 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device having the configurations of FIGS. 15, 21, 22, and 23 to 25. FIG. [Figure 27] FIG. 27 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging device having the configurations of FIGS. 15, 21, 22, and 23 to 26. [Figure 28]FIG. 10 is a diagram illustrating an example of a circuit configuration of an imaging device including a solid-state imaging device according to the above embodiment and its modified example. [Figure 29] FIG. 29 is a diagram illustrating an example in which the solid-state imaging device of FIG. 28 is configured by stacking three substrates. [Figure 30] 10 is a diagram illustrating an example in which a logic circuit is formed separately on a substrate on which sensor pixels are provided and a substrate on which a readout circuit is provided. FIG. [Figure 31] FIG. 10 is a diagram showing an example in which a logic circuit is formed on a third substrate. [Figure 32] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including a solid-state imaging device according to the above embodiment and its modified example. [Figure 33] 33 is a diagram illustrating an example of an imaging procedure in the imaging system of FIG. 32. [Figure 34] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 35] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 36] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 37] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment (Solid-state imaging device)...FIGS. 1 to 8G 2. Modifications (solid-state imaging device)...FIGS. 9 to 31 3. Application example (imaging system)...Fig. 32, Fig. 33 4. Application Examples Application examples for mobile devices: Figures 34 and 35 Application example to endoscopic surgery system...Figures 36 and 37

[0013] <1. Embodiment> [composition] A solid-state imaging device 1 according to an embodiment of the present disclosure will be described. The solid-state imaging device 1 is, for example, a back-illuminated image sensor formed of a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like. The solid-state imaging device 1 captures an image by receiving light from a subject, photoelectrically converting the light, and generating an image signal. The solid-state imaging device 1 outputs a pixel signal corresponding to the incident light.

[0014] A back-illuminated image sensor is an image sensor configured such that a photoelectric conversion unit such as a photodiode that receives light from a subject and converts the light into an electrical signal is provided between a light-receiving surface where light from a subject is incident and a wiring layer where wiring such as transistors that drive each pixel is provided. Note that the present disclosure is not limited to application to CMOS image sensors.

[0015] 1 illustrates an example of a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present disclosure. The solid-state imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The solid-state imaging device 1 is an imaging device with a three-dimensional structure formed by bonding together the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0016] The first substrate 10 has a pixel region 13 in which a plurality of sensor pixels 12 that perform photoelectric conversion are arranged in a matrix. The pixel region 13 is formed on a semiconductor substrate 11. The second substrate 20 has a plurality of readout circuits 22 that output pixel signals based on the charges output from the sensor pixels 12. The plurality of readout circuits 22 are formed on the semiconductor substrate 21, and, for example, one readout circuit 22 is assigned to each sensor pixel 12. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a logic circuit 32 that processes pixel signals. The logic circuit 32 is formed on the semiconductor substrate 31. The logic circuit 32 has, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout for each sensor pixel 12 to the outside.

[0017] The vertical drive circuit 33, for example, sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts signal levels of the pixel signals by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0018] 2 shows an example of the circuit configuration of the sensor pixel 12 and the readout circuit 22. The following describes a case where one readout circuit 22 is assigned to one sensor pixel 12, as shown in FIG.

[0019] Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TRG electrically connected to the photodiode PD, and two floating diffusions FD1 and FD2 that temporarily hold the charge output from the photodiode PD via the transfer transistor TRG. The photodiode PD corresponds to a specific example of a "photoelectric conversion unit" in the present disclosure. The floating diffusion FD1 corresponds to a specific example of a "first floating diffusion" in the present disclosure. The floating diffusion FD2 corresponds to a specific example of a "second floating diffusion" in the present disclosure.

[0020] The photodiode PD performs photoelectric conversion to generate an electric charge according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TRG, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground GND). The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD1, and the gate of the transfer transistor TRG is electrically connected to the pixel drive line 23. The transfer transistor TR G is, for example, an NMOS (Metal Oxide Semiconductor) transistor.

[0021] Each sensor pixel 12 further includes, for example, a switching transistor FDG that switches between two floating diffusions FD1 and FD2. The switching transistor FDG corresponds to a specific example of a "mode switching unit" in the present disclosure. The switching transistor FDG is, for example, an NMOS transistor. The source of the switching transistor FDG is the floating diffusion FD1, which is electrically connected to the drain of the transfer transistor TRG. The drain of the switching transistor FDG is the floating diffusion FD2, which is electrically connected to the source of the reset transistor RST, which will be described later.

[0022] The read circuit 22 includes, for example, a reset transistor RST, two amplification transistors AMP1 and AMP2, and two selection transistors SEL1 and SEL2. 2 The amplifier transistor AMP1 corresponds to a specific example of a "first amplifier transistor" in the present disclosure. The amplifier transistor AMP2 corresponds to a specific example of a "second amplifier transistor" in the present disclosure. The reset transistor RST, the amplifier transistors AMP1 and AMP2, and the select transistors SEL1 and SEL2 are, for example, NMOS transistors.

[0023] The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD2, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drains of the two amplifier transistors AMP1 and AMP2. The gate of the reset transistor RST is electrically connected to a pixel drive line 23 (see FIG. 1). The source of the amplifier transistor AMP1 is electrically connected to the drain of the select transistor SEL1, and the gate of the amplifier transistor AMP1 is electrically connected to the floating diffusion FD1. The source of the select transistor SEL1 (the output terminal of the readout circuit 22) is electrically connected to a vertical signal line 24, and the gate of the select transistor SEL1 is electrically connected to the pixel drive line 23 (see FIG. 1). The source of the amplifier transistor AMP2 is electrically connected to the drain of the select transistor SEL2, and the gate of the amplifier transistor AMP2 is electrically connected to the floating diffusion FD2. The source of the select transistor SEL2 (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the select transistor SEL2 is electrically connected to the pixel drive line 23 (see FIG. 1).

[0024] The readout circuit 22 has a signal path P1 including a floating diffusion FD1 and an amplifier transistor AMP1, and a signal path P2 including a floating diffusion FD2 and an amplifier transistor AMP2. The signal path P1 corresponds to a specific example of a "first signal path" in the present disclosure. The signal path P2 corresponds to a specific example of a "second signal path" in the present disclosure. One end of each of the signal paths P1 and P2 is electrically connected to the vertical signal line 24, the other end of the signal path P1 is electrically connected to the floating diffusion FD1, and the other end of the signal path P2 is electrically connected to the floating diffusion FD2. Therefore, when the switching transistor FDG is on, the signal paths P1 and P2 are connected in parallel to each other. Furthermore, regardless of whether the switching transistor FDG is on or off, the signal path P1 is electrically connected to the transfer transistor TRG. One signal path P2 is electrically connected to the transfer transistor TRG when the switching transistor FDG is on, but is electrically isolated from the transfer transistor TRG when the switching transistor FDG is off. In other words, when the switching transistor FDG is off, no current flows through the signal path P2.

[0025] When the transfer transistor TRG is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD1 or the floating diffusion FD2. The gate (transfer gate TG) of the transfer transistor TRG extends from the upper surface of the semiconductor substrate 11 through the well layer 42 to a depth reaching the PD 41, for example, as shown in FIG.

[0026] The reset transistor RST resets the potentials of the floating diffusions FD1 and FD2 to a predetermined potential. When the reset transistor RST is turned on, the potentials of the floating diffusions FD1 and FD2 are reset to the potential of the power supply line VDD. The selection transistors SEL1 and SEL2 control the output timing of pixel signals from the readout circuit 22.

[0027] The amplifier transistor AMP1 generates a pixel signal having a voltage corresponding to the level of the charge held in the floating diffusion FD1. The amplifier transistor AMP2 generates a pixel signal having a voltage corresponding to the level of the charge held in the floating diffusion FD2. The amplifier transistors AMP1 and AMP2 form a source-follower amplifier and output a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the select transistor SEL1 is turned on, the amplifier transistor AMP1 amplifies the potential of the floating diffusion FD1 and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. When the select transistor SEL2 is turned on, the amplifier transistor AMP2 amplifies the potential of the floating diffusion FD2 and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24.

[0028] The switching transistor FDG is used to change the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD1 (FD capacitance C) is large, the V when converted to voltage by the amplifier transistor will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusion FD1 cannot fully absorb the charge from the photodiode PD. Furthermore, the FD capacitance C must be large so that the V when converted to voltage by the amplifier transistor does not become too large (in other words, to reduce it). Given these factors, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor FDG on and off, the FD capacitance C can be varied, allowing the conversion efficiency to be changed.

[0029] The switching transistor FDG switches the FD capacitance C between a high-sensitivity, low-illuminance mode (first mode) and a low-sensitivity, high-illuminance mode (second mode). Specifically, the switching transistor FDG is turned off in the first mode, making the FD capacitance C relatively small, and turned on in the second mode, making the FD capacitance C relatively large. The switching transistor FDG, reset transistor RST, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2 are, for example, NMOS transistors. Under the control of the vertical drive circuit 33, the switching transistor FDG electrically connects the signal path P1 to the photodiode PD and electrically disconnects the signal path P2 from the photodiode PD in the first mode, and electrically connects both the signal path P1 and the signal path P2 to the photodiode PD in the second mode. Specifically, the switching transistor FDG is turned off in the first mode and turned on in the second mode.

[0030] 3 shows an example of a vertical cross-sectional configuration of the solid-state imaging device 1. FIG. 3 illustrates the cross-sectional configuration of a portion of the solid-state imaging device 1 that faces the sensor pixels 12. The solid-state imaging device 1 is configured by stacking a first substrate 10, a second substrate 20, and a third substrate 30 in this order, and further includes a color filter 40 and a light-receiving lens 50 on the back surface side of the first substrate 10. For example, one color filter 40 and one light-receiving lens 50 are provided for each sensor pixel 12. In other words, the solid-state imaging device 1 is a back-illuminated imaging device.

[0031] The first substrate 10 is formed by laminating an insulating layer 46 on a semiconductor substrate 11. The first substrate 10 has the insulating layer 46 as part of an interlayer insulating film 51. The insulating layer 46 is provided in the gap between the semiconductor substrate 11 and the semiconductor substrate 21. The semiconductor substrate 11 is formed of a silicon substrate. The semiconductor substrate 11 has a p-well layer 42, for example, on a part of its upper surface and in the vicinity thereof, and has a PD 41 of a different conductivity type from the p-well layer 42 in the other region (a region deeper than the p-well layer 42). The conductivity type of the p-well layer 42 is, for example, p-type. The conductivity type of the PD 41 is a different conductivity type from the p-well layer 42, for example, n-type. The semiconductor substrate 11 has floating diffusions FD1 and FD2 of a different conductivity type from the p-well layer 42 in the p-well layer 42.

[0032] The first substrate 10 has a photodiode PD, a transfer transistor TRG, a switching transistor FDG, and floating diffusions FD1 and FD2 for each sensor pixel 12. The first substrate 10 has a photodiode PD, a transfer transistor TRG, a switching transistor FDG, and floating diffusions FD1 and FD2 on the upper surface of a semiconductor substrate 11. G , a switching transistor FDG, and floating diffusions FD1 and FD2 are provided. The first substrate 10 has an element isolation portion 43 that isolates each sensor pixel 12. The element isolation portion 43 is formed extending in the normal direction (thickness direction) of the semiconductor substrate 11. The element isolation portion 43 is provided between two adjacent sensor pixels 12. The element isolation portion 43 electrically isolates the adjacent sensor pixels 12 from each other. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates, for example, the semiconductor substrate 11.

[0033] The first substrate 10 further includes, for example, a p-well layer 44 on the side of the element isolation portion 43 and in contact with the surface on the photodiode PD side. The conductivity type of the p-well layer 44 is different from that of the photodiode PD, for example, p-type. The first substrate 10 further includes, for example, a fixed charge film 45 in contact with the back surface of the semiconductor substrate 11. The fixed charge film 45 has a negative fixed charge to suppress the generation of dark current due to interface states on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. The electric field induced by the fixed charge film 45 forms a hole accumulation layer at the interface on the light-receiving surface side of the semiconductor substrate 11. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed charge film 45, and is provided at a position facing the sensor pixel 12 across the fixed charge film 45. The light receiving lens 50 is provided, for example, in contact with the color filter 40, and is provided at a position facing the sensor pixel 12 across the color filter 40 and the fixed charge film 45.

[0034] The second substrate 20 is configured by laminating an insulating layer 52 on a semiconductor substrate 21. The second substrate 20 has the insulating layer 52 as part of an interlayer insulating film 51. The insulating layer 52 is provided in the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is configured as a silicon substrate. The second substrate 20 has, for example, one readout circuit 22 for each sensor pixel 12. The second substrate 20 is configured such that the readout circuit 22 is provided on the upper surface of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the upper surface side of the semiconductor substrate 21. In other words, the second substrate 20 is bonded to the first substrate 10 face-to-back. The second substrate 20 further has an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The second substrate 20 has the insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided so as to cover the side surfaces of the through wiring 54 described below.

[0035] The stacked body made up of the first substrate 10 and the second substrate 20 has an interlayer insulating film 51 and a plurality of through-wires 54 provided in the interlayer insulating film 51. The plurality of through-wires 54 extend in the normal direction of the semiconductor substrate 21 and are provided so as to penetrate the interlayer insulating film 51 at a location including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the plurality of through-wires 54. For example, two through-wires 54 are electrically connected to floating diffusions FD1 and FD2 and a connection wire 55, which will be described later.

[0036] The second substrate 20 has, for example, a plurality of connection portions 59 electrically connected to the readout circuit 22 and the semiconductor substrate 21 within the insulating layer 52. The second substrate 20 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 provided within the insulating layer 57. The wiring layer 56 further has, for example, a plurality of connection wires 55 within the insulating layer 57. The plurality of connection wires 55 are electrically connected to the readout circuit 22 and to through wires 54 electrically connected to the floating diffusions FD1 and FD2. For example, the floating diffusion FD1 and the gate of the amplification transistor AMP1 are electrically connected by the connection wires 55 and the through wires 54. Furthermore, for example, the floating diffusion FD2 and the gate of the amplification transistor AMP2 are electrically connected by the connection wires 55 and the through wires 54.

[0037] The wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is made of, for example, Cu (copper). Each pad electrode 58 is exposed on the upper surface of the wiring layer 56. Each pad electrode 58 is used for electrically connecting the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 are provided, for example, one for each pixel driving line 23 and vertical signal line 24.

[0038] The third substrate 30 is configured, for example, by laminating an interlayer insulating film 61 on a semiconductor substrate 31. The third substrate 30 is bonded face-to-face to the second substrate 20. Therefore, when describing the internal configuration of the third substrate 30, the up-down direction is reversed from the up-down direction in the drawings. The semiconductor substrate 31 is configured as a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided on the upper surface of the semiconductor substrate 31. The third substrate 30 further includes, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the upper surface of the wiring layer 62. Each pad electrode 64 is used to electrically connect the second substrate 20 and the third substrate 30 and to bond the second substrate 20 and the third substrate 30 together. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58 and 64 together. That is, the gate (transfer gate TG) of the transfer transistor TRG is electrically connected to the logic circuit 32 via, for example, the through wiring 54, the connection wiring 55, the connection portion 59, and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 with the upper surface of the semiconductor substrate 31 facing the upper surface of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0039] The first substrate 10 and the second substrate 20 are electrically connected to each other by through-hole wiring 54. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding pad electrodes 58, 64. The width of the through-hole wiring 54 is narrower than the width of the bonding portion between the pad electrodes 58, 64. That is, the cross-sectional area of ​​the through-hole wiring 54 is smaller than the cross-sectional area of ​​the bonding portion between the pad electrodes 58, 64. Therefore, the through-hole wiring 54 does not hinder the high integration of the sensor pixels 12 in the first substrate 10. Furthermore, because the readout circuit 22 is formed on the second substrate 20 and the logic circuit 32 is formed on the third substrate 30, the structure for electrically connecting the second substrate 20 and the third substrate 30 to each other can be formed with lower density than the structure for electrically connecting the first substrate 10 and the second substrate 20 to each other. Therefore, bonding pad electrodes 58, 64 can be used as the structure for electrically connecting the second substrate 20 and the third substrate 30 to each other.

[0040] 4 and 5 show an example of a horizontal cross-sectional configuration of the solid-state imaging device 1. FIG. 4 shows an example of the top surface configuration of the semiconductor substrate 11, and FIG. 5 shows an example of the top surface configuration of the semiconductor substrate 21. FIG. 6 shows an example of a configuration in which the configuration shown in FIG. 4 and the configuration shown in FIG. 5 are superimposed on each other. A transfer transistor TRG, a switching transistor FDG, and floating diffusions FD1 and FD2 are provided on the top surface of the semiconductor substrate 11. That is, the transfer transistor TRG, the switching transistor FDG, and the floating diffusions FD1 and FD2 are provided on the first substrate 10. Meanwhile, for example, a reset transistor RST, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2 are provided on the top surface of the semiconductor substrate 21. That is, the reset transistor RST, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2 are provided on the second substrate 20.

[0041] In this case, for example, when the configuration shown in Fig. 4 and the configuration shown in Fig. 5 are superimposed on each other, as shown in Fig. 6, an overlapping region α exists. This shows that the solid-state imaging device 1 is smaller by the overlapping region α than when the transfer transistor TRG, switching transistor FDG and floating diffusions FD1 and FD2, reset transistor RST, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2 are provided on a common substrate.

[0042] The L lengths b1 and b2 of the amplifier transistors AMP1 and AMP2 are, for example, equal to each other. Meanwhile, the W lengths of the amplifier transistors AMP1 and AMP2 are, for example, such that the W length a2 of the amplifier transistor AMP2 is greater than the W length a1 of the amplifier transistor AMP1. The W length a2 of the amplifier transistor AMP2 is, for example, two or three times the W length a1 of the amplifier transistor AMP1. When the switching transistor FDG is turned on, the W length of the amplifier transistors serving as the readout circuit 22 is the sum of the W length a1 of the amplifier transistor AMP1 and the W length a2 of the amplifier transistor AMP2. Therefore, by switching the switching transistor FDG on and off, the W length of the amplifier transistors serving as the readout circuit 22 can be increased, for example, three or four times.

[0043] 7, a plurality of amplifier transistors AMP2 may be provided for the readout circuit 22. In this case, the width a2 of each amplifier transistor AMP2 may be equal to the width a1 of the amplifier transistor AMP1, or may be greater than the width a1 of the amplifier transistor AMP1.

[0044] [Manufacturing method] Next, a description will be given of a method for manufacturing the solid-state imaging device 1. Figures 8A to 8G show an example of a manufacturing process for the solid-state imaging device 1.

[0045] First, a p-well layer 42, an element isolation portion 43, and a p-well layer 44 are formed on the semiconductor substrate 11. Next, a photodiode PD, a transfer transistor TRG, a switching transistor FDG, and floating diffusions FD1 and FD2 are formed on the semiconductor substrate 11 (FIG. 8A). This forms the sensor pixels 12 on the semiconductor substrate 11. At this time, it is preferable not to use a material with low heat resistance, such as CoSi2 or NiSi formed by a salicide process, as the electrode material for the sensor pixels 12. Rather, it is preferable to use a material with high heat resistance as the electrode material for the sensor pixels 12. An example of a material with high heat resistance is polysilicon. Thereafter, an insulating layer 46 is formed on the semiconductor substrate 11 (FIG. 8A). In this manner, the first substrate 10 is formed.

[0046] Next, the semiconductor substrate 21 is bonded onto the first substrate 10 (insulating layer 46) (FIG. 8B). At this time, the semiconductor substrate 21 is thinned as necessary. At this time, the thickness of the semiconductor substrate 21 is set to a film thickness necessary for forming the readout circuit 22. The thickness of the semiconductor substrate 21 is generally about several hundred nm. However, depending on the concept of the readout circuit 22, an FD (Fully Depletion) type is also possible, and in that case, the thickness of the semiconductor substrate 21 is set to several n The range can be from a few microns to several microns.

[0047] Next, an insulating layer 53 is formed in the same layer as the semiconductor substrate 21 (FIG. 8C). The insulating layer 53 is formed, for example, in a location facing the floating diffusions FD1 and FD2. For example, slits are formed in the semiconductor substrate 21 penetrating the semiconductor substrate 21 to separate the semiconductor substrate 21 into multiple blocks. Then, the insulating layer 53 is formed to fill the slits. Then, a readout circuit 22 including amplification transistors AMP1 and AMP2 and selection transistors SEL1 and SEL2 is formed in each block of the semiconductor substrate 21 (FIG. 8D). At this time, if a metal material with high heat resistance is used as the electrode material of the sensor pixels 12, the gate insulating film of the readout circuit 22 can be formed by thermal oxidation. Furthermore, the electrodes of each transistor included in the readout circuit 22 may be configured to include silicide. The readout circuit 22 is formed after the sensor pixels 12 are formed. Therefore, silicide with low heat resistance can be used on the surfaces of impurity diffusion regions in contact with the source and drain electrodes of each transistor included in the readout circuit 22.

[0048] Next, an insulating layer 52 is formed on the semiconductor substrate 21. In this manner, an interlayer insulating film 51 consisting of insulating layers 46, 52, and 53 is formed. Subsequently, through holes 51A, 51B, 51C, and 51D are formed in the interlayer insulating film 51 (FIG. 8E). Specifically, through holes 51C and 51D are formed through the insulating layer 52 in locations of the insulating layer 52, which is part of the interlayer insulating film 51, facing the readout circuit 22 (e.g., the amplification transistors AMP1 and AMP2). Furthermore, through holes 51A and 51B are formed through the interlayer insulating film 51 in locations of the interlayer insulating film 51 facing the floating diffusions FD1 and FD2 (i.e., locations facing the insulating layer 53).

[0049] Next, a conductive material is filled into the through holes 51A, 51B, 51C, and 51D to form through wirings 54 in the through holes 51A and 51B, and to form connection portions 59 in the through holes 51C and 51D (FIG. 8F). Furthermore, connection wirings 55 that electrically connect the through wirings 54 and the connection portions 59 to each other are formed on the insulating layer 52 (FIG. 8F). Thereafter, a wiring layer 56 including pad electrodes 58 is formed on the insulating layer 52. In this manner, the second substrate 20 is formed.

[0050] Next, the second substrate 20 is bonded to the third substrate 30 on which the logic circuit 32 and the wiring layer 62 are formed, with the upper surface of the semiconductor substrate 21 facing the upper surface of the semiconductor substrate 31 (FIG. 8G). At this time, the pad electrodes 58 of the second substrate 20 and the pad electrodes 64 of the third substrate 30 are joined to each other, thereby electrically connecting the second substrate 20 and the third substrate 30 to each other. In this manner, the solid-state imaging device 1 is manufactured.

[0051] [effect] Next, the effects of the solid-state imaging device 1 according to this embodiment will be described.

[0052] For CMOS image sensors, high sensitivity is desirable so that imaging signals can be acquired even under low illumination conditions. Furthermore, to increase the dynamic range, it is desirable for the photodiode to be less prone to saturation. However, there is a trade-off between high sensitivity and photodiode saturation, making it difficult to expand the dynamic range while maintaining high sensitivity. Therefore, for example, Patent Document 1 discloses providing a small-capacity floating diffusion and a large-capacity floating diffusion, connecting the small-capacity floating diffusion to the photodiode under low illumination conditions and connecting the large-capacity floating diffusion under high illumination conditions. However, when the invention described in Patent Document 1 is applied to high-resolution applications, it is difficult to secure sufficient space for two floating diffusions.

[0053] On the other hand, in this embodiment, the amplifier transistors AMP1 and AMP2 to be used are selected depending on the mode. This makes it possible to expand the dynamic range while maintaining high sensitivity. Furthermore, in this embodiment, at least the amplifier transistors AMP1 and AMP2 are formed on a second substrate 20 separate from the first substrate 10 on which the photodiode PD is formed. Specifically, the photodiode PD, transfer transistor TRG, floating diffusions FD1 and FD2, and switching transistor FDG are formed on the first substrate 10, while the reset transistor RST, amplifier transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2 are formed on the second substrate 20. This makes it possible to ensure sufficient space for providing the floating diffusions FD1 and FD2 and amplifier transistors AMP1 and AMP2, even when the solid-state imaging device 1 has high resolution. As a result, high sensitivity and a wide dynamic range can be achieved simultaneously, even in high-resolution applications.

[0054] Furthermore, in this embodiment, when the electrodes of each transistor included in the readout circuit 22 are configured to contain silicide, the parasitic resistance of each transistor included in the readout circuit 22 can be reduced, resulting in reduced noise.

[0055] In this embodiment, the vertical drive circuit 33 may change the drive current in accordance with the size of the amplification transistors AMP1 and AMP2, which are converted by switching using the switching transistor FDG, under the control of the system control circuit 36. In this case, it is possible to prevent a decrease in the drive current per unit amplification transistor, and to suppress deterioration of noise characteristics.

[0056] <2. Modifications> Modifications of the solid-state imaging device 1 according to the above embodiment will be described below.

[0057] [[Variation A]] FIG. 9 shows a modified circuit configuration of the sensor pixels 12 and readout circuit 22 of the solid-state imaging device 1 according to the above embodiment. In this modified example, the photodiode PD, transfer transistor TRG, floating diffusions FD1 and FD2, switching transistor FDG, amplifier transistor AMP1, and select transistor SEL1 are formed on the first substrate 10. Meanwhile, the reset transistor RST, amplifier transistor AMP2, and select transistor SEL2 are formed on the second substrate 20. Even in this case, as in the above embodiment, it is possible to ensure sufficient space for providing the floating diffusions FD1 and FD2 and amplifier transistors AMP1 and AMP2. As a result, high sensitivity and a wide dynamic range can be achieved even in high-resolution applications.

[0058] FIG. 10 shows an example of the top surface configuration of the semiconductor substrate 11 in the solid-state imaging device 1 having the configuration shown in FIG. 9. FIGS. 11 and 12 show an example of the top surface configuration of the semiconductor substrate 21 in the solid-state imaging device 1 having the configuration shown in FIG. 9. In this modification, the photodiode PD, transfer transistor TRG, floating diffusions FD1 and FD2, switching transistor FDG, amplifier transistor AMP1, and select transistor SEL1 can be accommodated in a small area, for example, as shown in FIG. 10. Similarly, the reset transistor RST, amplifier transistor AMP2, and select transistor SEL2 can be accommodated in a small area, for example, as shown in FIGS. 11 and 12. In this way, when the occupied area is reduced, the solid-state imaging device 1 can be miniaturized.

[0059] [[Variation B]] FIG. 13 illustrates a modified circuit configuration of the sensor pixels 12 and the readout circuit 22 of the solid-state imaging device 1 according to the embodiment. In this modification, two sensor pixels 12 (12A, 12B) share one readout circuit 22. Here, "shared" refers to the outputs of the two sensor pixels 12 (12A, 12B) being input to the common readout circuit 22. In this case, one readout circuit 22 is formed in a region of the semiconductor substrate 21 facing the two sensor pixels 12. Therefore, compared with the embodiment, the formation area of ​​one readout circuit 22 can be doubled, making it possible to secure sufficient space for providing floating diffusions FD1 and FD2 and amplification transistors AMP1 and AMP2. As a result, high sensitivity and a wide dynamic range can be achieved even in high-resolution applications.

[0060] [[Variation C]] 14 shows a modified example of the circuit configuration of the sensor pixels 12 and readout circuit 22 of the solid-state imaging device 1 according to the above-described modification B. In this modification, the photodiodes PD and transfer transistors TRG are formed on the first substrate 10. Meanwhile, the floating diffusions FD1 and FD2, two switching transistors FDG, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2 are formed on the second substrate 20. Even in this case, as with the above-described modification B, it is possible to ensure sufficient space for providing the floating diffusions FD1 and FD2 and the amplification transistors AMP1 and AMP2. As a result, high sensitivity and a wide dynamic range can be achieved simultaneously, even in high-resolution applications.

[0061] [[Variation D]] FIG. 15 shows a modified circuit configuration of the sensor pixels 12 and the readout circuit 22 of the solid-state imaging device 1 according to the above-described modification B. In this modification, four sensor pixels 12 (12A, 12B, 12C, and 12D) share one readout circuit 22. In this configuration, one readout circuit 22 is formed in a region of the second substrate 20 facing the four sensor pixels 12. Therefore, compared with the above-described embodiment, the formation area of ​​one readout circuit 22 can be expanded four times, thereby ensuring sufficient space for providing floating diffusions FD1 and FD2 and amplification transistors AMP1 and AMP2. As a result, high sensitivity and a wide dynamic range can be achieved even in high-resolution applications.

[0062] [[Variation E]] FIG. 16 shows a modified circuit configuration of the sensor pixels 12 and the readout circuit 22 of the solid-state imaging device 1 according to the above-described modification C. In this modification, four sensor pixels 12 (12A, 12B, 12C, and 12D) share one readout circuit 22. In this configuration, one readout circuit 22 is formed in a region of the second substrate 20 facing the four sensor pixels 12. Therefore, compared with the above-described embodiment, the formation area of ​​one readout circuit 22 can be expanded four times, thereby ensuring sufficient space for providing floating diffusions FD1 and FD2 and amplification transistors AMP1 and AMP2. As a result, high sensitivity and a wide dynamic range can be achieved even in high-resolution applications.

[0063] [[Variation F]] 17 shows a modified circuit configuration of the sensor pixel 12 and readout circuit 22 of the solid-state imaging device 1 according to the above embodiment. In this modified example, a switching transistor FDGa having the same configuration as the switching transistor FDG is provided in the location where the switching transistor FDG was provided, and a switching transistor FDGb is provided in the middle of the wiring connecting the floating diffusion FD1 and the gate of the amplification transistor AMP1. The switching transistors FDGa and FDGb are, for example, NMOS transistors.

[0064] In this modification, the FD capacitance C is switched between a high-sensitivity, low-illuminance mode (first mode) and a low-sensitivity, high-illuminance mode (second mode). Specifically, under the control of the system control circuit 36, the vertical drive circuit 33 electrically connects the signal path P1 to the photodiode PD and electrically disconnects the signal path P2 from the photodiode PD in the first mode. Under the control of the system control circuit 36, the vertical drive circuit 33 electrically connects both the signal path P1 and the signal path P2 to the photodiode PD in the second mode. For example, in the first mode, the vertical drive circuit 33 turns the switching transistor FDGa off and the switching transistor FDGb on. Furthermore, for example, in the second mode, the vertical drive circuit 33 turns the switching transistor FDGa on and the switching transistor FDGb on. By doing so, similar to the above embodiment, high sensitivity and a wide dynamic range can be achieved even in high-resolution applications.

[0065] In this modification, two sensor pixels 12 may share one readout circuit 22. Also, in this modification, four sensor pixels 12 may share one readout circuit 22. In this case, similar to the above modifications B to E, it is possible to achieve both high sensitivity and a wide dynamic range even in high-resolution applications.

[0066] [[Variation G]] 18 shows a modified example of the cross-sectional configuration of a solid-state imaging device 1 according to the above-described embodiment and the modified example. In this modified example, two photodiodes PD are provided for one light-receiving lens 50, and these two photodiodes PD are separated from each other by an element isolation portion 43. Hereinafter, the two photodiodes PD provided corresponding to one light-receiving lens 50 will be referred to as photodiodes PDa and PDb.

[0067] In this modification, one floating diffusion FD1 is provided for each of the photodiodes PDa and PDb. Meanwhile, one switching transistor FDG is assigned to each of the photodiodes PDa and PDb. Therefore, the floating diffusion FD1 provided for the photodiode PDa and the floating diffusion FD1 provided for the photodiode PDb are electrically connected by a connection wiring 49 provided in the insulating layer 46.

[0068] In this modification, the first substrate 10 is formed with photodiodes PDa and PDb, two transfer transistors TRG, two floating diffusions FD1, one floating diffusion FD2, a switching transistor FDG, an amplifier transistor AMP1, and a selection transistor SEL1. Meanwhile, the second substrate 20 is formed with a reset transistor RST, an amplifier transistor AMP2, and a selection transistor SEL2. Even in this case, as in the above embodiment, it is possible to ensure sufficient space for providing the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, high sensitivity and a wide dynamic range can be achieved simultaneously, even in high-resolution applications.

[0069] [[Variation H]] 19 shows a modified cross-sectional configuration of the solid-state imaging device 1 according to the above-described modification G. In this modification, one floating diffusion FD1 is provided for each of the photodiodes PDa and PDb. Meanwhile, one switching transistor FDG is assigned to each of the photodiodes PDa and PDb. Therefore, the floating diffusion FD1 provided for the photodiode PDa and the floating diffusion FD1 provided for the photodiode PDb are electrically connected by a connection wiring 55 provided in the insulating layer 52. The floating diffusion FD1 provided for the photodiode PDa and the floating diffusion FD1 provided for the photodiode PDb are connected to the switching transistor FDG and the gate of the amplification transistor AMP1 via the connection wiring 55 and the through-wire 54.

[0070] In this modification, the second substrate 20 has two semiconductor substrates 21 and 26. The semiconductor substrate 26 is stacked on the semiconductor substrate 21 via an interlayer insulating film 51 (insulating layer 52). The semiconductor substrate 26 is provided between the interlayer insulating film 51 (insulating layer 52) and an insulating layer 57. The semiconductor substrate 26 has an opening, and a part of the insulating layer 57 (hereinafter referred to as "insulating layer 28") is provided in the opening. A through-wire 54 penetrates the insulating layer 28. The through-wire 54 penetrating the insulating layer 28 electrically connects the floating diffusion FD2 and the gate of the amplification transistor AMP2 to each other via a connection wire 55 and another through-wire 54.

[0071] In this modification, the photodiodes PDa and PDb and the two floating diffusions FD1 are formed on the first substrate 10, the amplifier transistor AMP1, the floating diffusion FD2 and the switching transistor FDG are formed on the semiconductor substrate 21 of the second substrate 20, and the amplifier transistor AMP2 is formed on the semiconductor substrate 26 of the second substrate 20. Even in this case, as in the above embodiment, it is possible to ensure sufficient space for providing the floating diffusions FD1 and FD2 and the amplifier transistors AMP1 and AMP2. As a result, it is possible to achieve both high sensitivity and a wide dynamic range even in high-definition applications.

[0072] In this modification, the electrodes of the transistors formed on the semiconductor substrates 21 and 26 may be configured to contain silicide. In this case, the transistors formed on the semiconductor substrates 21 and 26 are formed after the sensor pixels 12 are formed. Therefore, silicide, which has low heat resistance, can be used on the surfaces of the impurity diffusion regions in contact with the source and drain electrodes of the transistors included in the readout circuit 22.

[0073] [[Variation I]] 20 shows an example of a connection between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. In the above embodiment and its modifications, when a plurality of readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), one of the plurality of vertical signal lines 24 may be assigned to each readout circuit 22. For example, as shown in FIG. 20, when four readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), one of the four vertical signal lines 24 may be assigned to each readout circuit 22.

[0074] [Variation J] 21 and 22 illustrate a modified horizontal cross-sectional configuration of the solid-state imaging device 1 having the configuration of FIG. 15 . The upper diagrams of FIGS. 21 and 22 illustrate an example of a cross-sectional configuration of the first substrate 10 in the solid-state imaging device 1 having the configuration of Modification D. The upper diagrams of FIGS. 21 and 22 illustrate an example of a cross-sectional configuration of a portion of the first substrate 10 in the solid-state imaging device 1 having the configuration of Modification D, corresponding to cross section Sec1 in FIG. 3 . Note that in the upper cross-sectional views of FIGS. 21 and 22 , a diagram illustrating an example of the surface configuration of the semiconductor substrate 11 is superimposed, and the insulating layer 46 is omitted. The lower diagrams of FIGS. 21 and 22 illustrate an example of a cross-sectional configuration of the second substrate 20 in the solid-state imaging device 1 having the configuration of Modification D. The lower diagrams of FIGS. 21 and 22 illustrate an example of a cross-sectional configuration of a portion of the second substrate 20 in the solid-state imaging device 1 having the configuration of Modification D, corresponding to cross section Sec2 in FIG. 3 . 21 and 22, diagrams showing example surface configurations of the semiconductor substrate 21 and the insulating layer 53 are superimposed, and the insulating layer 52 is omitted. Fig. 21 illustrates a configuration in which two sets of four 2x2 sensor pixels 12 are arranged in the second direction H. Fig. 22 illustrates a configuration in which four sets of four 2x2 sensor pixels 12 are arranged in the first direction V and the second direction H.

[0075] The stacked body made up of the first substrate 10 and the second substrate 20 has through-hole wires 67 and 68 provided in the interlayer insulating film 51. The stacked body has one through-hole wire 67 and one through-hole wire 68 for each sensor pixel 12. The through-hole wires 67 and 68 each extend in a normal direction to the semiconductor substrate 21 and penetrate a portion of the interlayer insulating film 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-hole wires 67 and 68. Specifically, the through-hole wire 67 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and wiring in the second substrate 20. The through-hole wire 68 is electrically connected to the transfer gate TG and the pixel drive line 23. As shown in FIGS. 21 and 22, the plurality of through-hole wires 54, the plurality of through-hole wires 68, and the plurality of through-hole wires 67 are arranged in a strip shape in the first direction V (the vertical direction in FIG. 21, the horizontal direction in FIG. 22) within the plane of the first substrate 10. 21 and 22 illustrate an example in which the plurality of through wirings 54, the plurality of through wirings 68, and the plurality of through wirings 67 are arranged in two columns in the first direction V. The first direction V is parallel to one of two arrangement directions (e.g., the row direction and the column direction) of the plurality of sensor pixels 12 arranged in a matrix. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG are arranged to surround the four floating diffusions FD, and for example, the four transfer gates TG form a circular ring shape.

[0076] The insulating layer 53 is composed of multiple blocks extending in a first direction V. The semiconductor substrate 21 is composed of multiple island-shaped blocks 21A extending in the first direction V and arranged side by side in a second direction H perpendicular to the first direction V, with the insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, multiple sets of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is composed of, for example, an amplification transistor AMP in the block 21A adjacent to the left of the insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 21A adjacent to the right of the insulating layer 53.

[0077] [Variation K] 23 shows a modified vertical cross-sectional configuration of a solid-state imaging device 1 according to the above-described embodiment and its modified examples. In this modified example, the second substrate 20 and the third substrate 30 are electrically connected in a region of the first substrate 10 facing the peripheral region 14. The peripheral region 14 corresponds to the frame region of the first substrate 10 and is provided on the periphery of the pixel region 13. In this modified example, the second substrate 20 has a plurality of pad electrodes 58 in a region facing the peripheral region 14, and the third substrate 30 has a plurality of pad electrodes 64 in a region facing the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14.

[0078] As described above, in this modification, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14. This reduces the risk of hindering miniaturization of the area per pixel compared to when the pad electrodes 58, 64 are bonded to each other in the region facing the pixel region 13. Therefore, it is possible to provide a solid-state imaging device 1 with a three-layer structure that does not hinder miniaturization of the area per pixel, while maintaining the same chip size as before.

[0079] [Variation L] 24 and 25 illustrate a modified horizontal cross-sectional configuration of the solid-state imaging device 1 according to Modifications D, J, and K. The upper diagrams in FIGS. 24 and 25 illustrate a modified cross-sectional configuration of the first substrate 10 in the solid-state imaging device 1 having the configurations of Modifications D, J, and K. The upper diagrams in FIGS. 24 and 25 illustrate a cross-sectional configuration of a portion of the first substrate 10 in the solid-state imaging device 1 having the configurations of Modifications D, J, and K, corresponding to cross-section Sec1 in FIG. 3. Note that in the upper diagrams in FIGS. 24 and 25, a diagram illustrating an example of the surface configuration of the semiconductor substrate 11 is superimposed, and the insulating layer 46 is omitted. The lower diagrams in FIGS. 24 and 25 illustrate a modified cross-sectional configuration of the second substrate 20 in the solid-state imaging device 1 having the configurations of Modifications D, J, and K. The lower diagrams in FIGS. 24 and 25 illustrate a cross-sectional configuration of a portion of the second substrate 20 in the solid-state imaging device 1 having the configurations of Modifications D, J, and K, corresponding to cross-section Sec2 in FIG. 3. In the cross-sectional views at the bottom of FIGS. 24 and 25, diagrams showing examples of the surface configurations of semiconductor substrate 21 and insulating layer 53 are superimposed, and insulating layer 52 is omitted.

[0080] As shown in FIGS. 24 and 25, the plurality of through wirings 54, the plurality of through wirings 68, and the plurality of through wirings 67 (the plurality of dots arranged in a matrix in the figures) are arranged in a strip shape in the first direction V (the left-right direction in FIGS. 24 and 25) within the plane of the first substrate 10. Note that FIGS. 24 and 25 illustrate an example in which the plurality of through wirings 54, the plurality of through wirings 68, and the plurality of through wirings 67 are arranged in two rows in the first direction V. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusions FD, and for example, the four transfer gates TG form a ring shape.

[0081] The insulating layer 53 is composed of a plurality of blocks extending in a first direction V. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V and arranged side by side in a second direction H perpendicular to the first direction V, with the insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is, for example, not arranged directly opposite the four sensor pixels 12 but arranged offset in the second direction H.

[0082] 24, one readout circuit 22 shared by four sensor pixels 12 is configured by a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area of ​​the second substrate 20 that is shifted in the second direction H from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured by, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0083] In FIG. 25 , one readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and a switching One readout circuit 22 shared by four sensor pixels 12 is configured by, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and switching It is composed of transistors FDG.

[0084] In this modification, the single readout circuit 22 shared by the four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed offset in the second direction H from a position directly opposite the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured using a common impurity region. As a result, the size of the readout circuit 22 can be reduced, or the size of other parts within the readout circuit 22 can be increased.

[0085] [Variation M] FIG. 26 illustrates a modified horizontal cross-sectional configuration of a solid-state imaging device 1 according to Modifications D, J, K, and L. The upper diagram of FIG. 26 illustrates an example of a cross-sectional configuration of a first substrate 10 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, and L. The upper diagram of FIG. 26 illustrates an example of a cross-sectional configuration of a portion of the first substrate 10 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, and L, corresponding to cross-section Sec1 in FIG. 3. Note that in the upper cross-sectional view of FIG. 26, a diagram illustrating an example of the surface configuration of a semiconductor substrate 11 is superimposed, and the insulating layer 46 is omitted. The lower diagram of FIG. 26 illustrates an example of a cross-sectional configuration of a second substrate 20 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, and L. The lower diagram of FIG. 26 illustrates an example of a cross-sectional configuration of a portion of the second substrate 20 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, and L, corresponding to cross-section Sec2 in FIG. 3. 26, a diagram showing an example of the surface configuration of the semiconductor substrate 21 and the insulating layer 53 is superimposed, and the insulating layer 52 is omitted. In FIG. 26, a configuration in which two sets of four sensor pixels 12, each of which is 2×2, are arranged in the second direction H is illustrated.

[0086] In this modification, the semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of reset transistor RST, amplification transistor AMP, and selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and degradation of image quality due to reduced resolution and color mixing on a reproduced image can be suppressed.

[0087] [Variation N] FIG. 27 illustrates a modified horizontal cross-sectional configuration of a solid-state imaging device 1 according to Modifications D, J, K, L, and M. The upper diagram of FIG. 27 illustrates an example of a cross-sectional configuration of a first substrate 10 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, L, and M. The upper diagram of FIG. 27 illustrates an example of a cross-sectional configuration of a portion of the first substrate 10 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, L, and M, corresponding to cross-section Sec1 in FIG. 3. Note that in the upper cross-sectional view of FIG. 27, a diagram illustrating an example of the surface configuration of a semiconductor substrate 11 is superimposed, and the insulating layer 46 is omitted. The lower diagram of FIG. 27 illustrates an example of a cross-sectional configuration of a second substrate 20 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, L, and M. The lower diagram of FIG. 27 illustrates an example of a cross-sectional configuration of a portion of the second substrate 20 in a solid-state imaging device 1 having the configuration of Modifications D, J, K, L, and M, corresponding to cross-section Sec2 in FIG. 3. 27, a diagram showing an example of the surface configuration of the semiconductor substrate 21 and the insulating layer 53 is superimposed, and the insulating layer 52 is omitted. In FIG. 27, a configuration in which two sets of four sensor pixels 12, each of which is 2×2, are arranged in the second direction H is illustrated.

[0088] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed offset in the first direction V. Furthermore, in this modification, similar to modification F, the semiconductor substrate 21 is configured with a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A includes, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this modification, a plurality of through wires 67 and a plurality of through wires 54 are also arranged in the second direction H. Specifically, the plurality of through wires 67 are disposed between four through wires 54 sharing a certain readout circuit 22 and four through wires 54 sharing another readout circuit 22 adjacent to the readout circuit 22 in the second direction H. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through wires 67, thereby suppressing image quality degradation due to reduced resolution and color mixing in a reproduced image.

[0089] [Variation O] 28 shows an example of the circuit configuration of the solid-state imaging device 1 according to the above embodiment and its modification. The solid-state imaging device 1 according to this modification is a CMOS image sensor equipped with a column-parallel ADC.

[0090] As shown in Figure 28, the solid-state imaging device 1 of this modified example is configured to have a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion element, are arranged two-dimensionally in a matrix, as well as a vertical driving circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal driving circuit 35, a horizontal output line 37, and a system control circuit 36.

[0091] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0092] The vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0093] Although not shown here, the sensor pixel 12 may include, for example, a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to a floating diffusion FD. G Although not shown here, the readout circuit 22 may have a three-transistor configuration including a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0094] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and pixel drive lines 23 are wired for each row of this m-row by n-column pixel arrangement, and vertical signal lines 24 are wired for each column. One end of each of the pixel drive lines 23 is connected to an output terminal of a vertical drive circuit 33 corresponding to each row. The vertical drive circuit 33 is configured with a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the pixel drive lines 23.

[0095] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24, and converts the analog signals output from each sensor pixel 12 in the pixel region 13 for each column into digital signals and outputs them.

[0096] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as means for generating a reference voltage Vref having a so-called ramp waveform, the level of which changes in a sloping manner as time passes. However, the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0097] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK given from the system control circuit 36 ​​under the control of a control signal CS1 given from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column signal processing circuit 34.

[0098] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to an operation mode between a normal frame rate mode using a progressive scan method in which information from all of the sensor pixels 12 is read out, and a high-speed frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased by N times, for example, twice, compared to the normal frame rate mode. This operation mode switching is performed under control of control signals CS2 and CS3 provided by the system control circuit 36. An external system controller (not shown) also provides the system control circuit 36 ​​with instruction information for switching between the normal frame rate mode and the high-speed frame rate mode.

[0099] The ADCs 34-1 to 34-m all have the same configuration, and the following description will be given taking the ADC 34-m as an example. The ADC 34-m includes a comparator 34A, a counting means such as an up / down counter (denoted as U / DCNT in the drawing) 34B, a transfer switch 34C, and a memory device 34D.

[0100] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with the reference voltage Vref of a ramp waveform supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco becomes an “L” level.

[0101] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 given from the system control circuit 36, a clock CK is supplied from the system control circuit 36 ​​to the DAC. 3 8A and counts down or up in synchronization with the clock CK, thereby measuring the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation.

[0102] Specifically, in the normal frame rate mode, when reading out a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0103] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, the comparison time for the first readout is measured by counting down from the previous count result during the first readout operation, and the comparison time for the second readout is measured by counting up during the second readout operation.

[0104] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 36, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0105] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the count results of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0106] In this way, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line 24 are converted into N-bit digital signals by the operations of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m and stored in the memory device 34D.

[0107] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of this horizontal drive circuit 35, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are read out in order to a horizontal output line 37 and output via the horizontal output line 37 as imaging data.

[0108] Although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits other than the above components that perform various signal processing on the imaging data output via the horizontal output line 37.

[0109] In the solid-state imaging device 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37 can be controlled independently.

[0110] [Variation P] FIG. 29 illustrates an example in which the solid-state imaging device 1 of FIG. 28 is configured by stacking three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). In this modification, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. A readout circuit region 15 including a plurality of readout circuits 22 is formed in the center of the second substrate 20, and the vertical drive circuit 33 is formed around the readout circuit region 15. A column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed on the third substrate 30. This prevents the chip size from increasing or the area per pixel from being reduced, as in the above-described embodiment and its modifications, due to the structure electrically connecting the substrates. As a result, a three-layer solid-state imaging device 1 can be provided that maintains the same chip size as before and does not hinder the area per pixel from being reduced. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0111] [Variation Q] FIG. 30 illustrates a modified cross-sectional configuration of the solid-state imaging device 1 according to the above-described embodiment and its modified examples. In the above-described embodiment and its modified examples, the third substrate 30 may be omitted, and the logic circuit 32 provided on the third substrate 30 may be formed separately on the first substrate 10 and the second substrate 20, as shown in FIG. 30. In this case, the circuit 32A of the logic circuit 32 provided on the first substrate 10 includes a transistor having a gate structure in which a high-dielectric-constant film made of a material (e.g., high-k) that can withstand high-temperature processes and a metal gate electrode are stacked. Meanwhile, in the circuit 32B provided on the second substrate 20, a low-resistance region 27 made of silicide, such as CoSi2 or NiSi, is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode using a salicide (self-aligned silicide) process. The low-resistance region 27 made of silicide is formed of a compound of the semiconductor substrate material and a metal. This allows a high-temperature process, such as thermal oxidation, to be used when forming the sensor pixels 12. Furthermore, in the circuit 32B of the logic circuit 32 provided on the second substrate 20 side, if low-resistance regions 27 made of silicide are provided on the surfaces of the impurity diffusion regions in contact with the source electrode and the drain electrode, the contact resistance can be reduced, and as a result, the operation speed of the logic circuit 32 can be increased.

[0112] FIG. 31 illustrates a modified cross-sectional configuration of the solid-state imaging device 1 according to the above-described embodiment and its modifications. In the logic circuit 32 provided on the third substrate 30 according to the above-described embodiment and its modifications, low-resistance regions 39 made of silicide, such as CoSi2 or NiSi, may be formed on the surface of the impurity diffusion region in contact with the source and drain electrodes using a salicide (self-aligned silicide) process. This allows a high-temperature process, such as thermal oxidation, to be used when forming the sensor pixels 12. Furthermore, if the low-resistance regions 39 made of silicide are formed on the surface of the impurity diffusion region in contact with the source and drain electrodes in the logic circuit 32, contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be increased.

[0113] In the above-described embodiments and their modifications, the conductivity types may be reversed. For example, in the description of the above-described embodiments and their modifications, p-type may be read as n-type, and n-type may be read as p-type. Even in this case, the same effects as those of the above-described embodiments and their modifications can be obtained.

[0114] <3. Application Examples> FIG. 32 shows an example of a schematic configuration of an imaging system 2 including a solid-state imaging device 1 according to the above embodiment and its modifications.

[0115] The imaging system 2 is, for example, an electronic device such as a solid-state imaging device such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 2 includes, for example, the solid-state imaging device 1 according to the above-described embodiment and its modifications, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the solid-state imaging device 1 according to the above-described embodiment and its modifications, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus line 147.

[0116] The solid-state imaging device 1 according to the above-described embodiments and modifications outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes signals (image data) output from the solid-state imaging device 1 according to the above-described embodiments and modifications. The frame memory 142 temporarily stores the image data processed by the DSP circuit 141 in units of frames. The display unit 143 is, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel. The imaging system 2 includes a panel-type display device such as a display panel, which displays moving images or still images captured by the solid-state imaging device 1 according to each of the above-described embodiments and their modifications. The storage unit 144 records image data of moving images or still images captured by the solid-state imaging device 1 according to each of the above-described embodiments and their modifications in a storage medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation commands for various functions of the imaging system 2 in accordance with operations by a user. The power supply unit 146 appropriately supplies various types of power to these power sources as operating power for the solid-state imaging device 1, DSP circuit 141, frame memory 142, display unit 143, storage unit 144, and operation unit 145 according to each of the above-described embodiments and their modifications.

[0117] Next, the imaging procedure in the imaging system 2 will be described.

[0118] 33 shows an example of a flowchart of the imaging operation in the imaging system 2. The user operates the operation unit 145 to instruct the start of imaging (step S101). Then, the operation unit 145 transmits an imaging command to the solid-state imaging device 1 (step S102). Upon receiving the imaging command, the solid-state imaging device 1 (specifically, the system control circuit 36) performs imaging in a predetermined imaging method (step S103).

[0119] The solid-state imaging device 1 outputs image data obtained by imaging to the DSP circuit 141. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the solid-state imaging device 1 (step S104). The DSP circuit 141 stores the image data that has undergone the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage unit 144 (step S105). In this manner, imaging is performed in the imaging system 2.

[0120] In this application example, the solid-state imaging device 1 according to each of the above-described embodiments and their modified examples is applied to an imaging system 2. This allows the solid-state imaging device 1 to be made smaller or have higher resolution, and therefore a small or high-resolution imaging system 2 can be provided.

[0121] <4. Application Examples> [Application example 1] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0122] FIG. 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0123] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 34, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0124] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0125] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0126] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0127] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0128] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0129] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0130] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0131] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0132] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 34, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0133] FIG. 35 is a diagram showing an example of the installation position of the imaging unit 12031.

[0134] In FIG. 35, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0135] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0136] 35 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0137] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0138] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0139] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0140] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0141] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the solid-state imaging device 1 according to the above-described embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a high-resolution captured image with little noise, thereby enabling high-precision control using the captured image in the mobile object control system.

[0142] [Application example 2] FIG. 36 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0143] 36 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0144] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0145] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0146] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0147] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0148] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0149] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0150] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0151] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0152] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0153] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0154] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0155] FIG. 37 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0156] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0157] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0158] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0159] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0160] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0161] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0162] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0163] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0164] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0165] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0166] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0167] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0168] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0169] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0170] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0171] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0172] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0173] The present disclosure has been described above by way of embodiments, their modifications, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0174] The present disclosure can also be configured as follows. (1) a photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor; a mode switching unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit; a first substrate on which at least the photoelectric conversion unit is formed, among the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, the second amplification transistor, and the mode switching unit; a second substrate stacked on the first substrate, the second substrate including at least the second amplification transistor formed thereon among the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, the second amplification transistor, and the mode switching unit; Equipped with Solid-state imaging device. (2) the photoelectric conversion unit, the first floating diffusion, the second floating diffusion, and the mode switching unit are formed on the first substrate; The first amplifying transistor and the second amplifying transistor are formed on the second substrate. The solid-state imaging device according to (1). (3) the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, and the mode switching unit are formed on the first substrate; The second amplification transistor is formed on the second substrate. The solid-state imaging device according to (1). (4) the photoelectric conversion unit is formed on the first substrate, The first floating diffusion, the first amplifying transistor, the second floating diffusion, the second amplifying transistor, and the mode switching switch unit are formed on the second substrate. The solid-state imaging device according to (1). (5) The electrodes of the transistors formed on the second substrate are configured to contain silicide. The solid-state imaging device according to any one of (1) to (4). (6) The mode selector switch further includes a drive circuit that changes the drive current according to the size of the transistor. The solid-state imaging device according to any one of (1) to (5). (7) a photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor; a mode switching unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit; a first substrate on which the photoelectric conversion section and the first floating diffusion are formed; a second substrate stacked on the first substrate and having the first amplification transistor, the second floating diffusion, and the mode switching unit formed thereon; a third substrate stacked on the second substrate and having the second amplification transistor formed thereon; and Equipped with Solid-state imaging device. (8) The electrodes of the transistors formed on the second substrate and the third substrate contain silicide. (7) A solid-state imaging device according to (7). (9) a solid-state imaging device that outputs pixel signals according to incident light; a signal processing circuit that processes the pixel signals; Equipped with the solid-state imaging device, a photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor; a mode switching unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit; a first substrate on which at least the photoelectric conversion unit is formed, among the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, the second amplification transistor, and the mode switching unit; a second substrate stacked on the first substrate, the second substrate including at least the second amplification transistor formed thereon among the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, the second amplification transistor, and the mode switching unit; have electronic equipment. (10) a solid-state imaging device that outputs pixel signals according to incident light; a signal processing circuit that processes the pixel signals; Equipped with the solid-state imaging device, a photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor; a mode switching unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit; a first substrate on which the photoelectric conversion section and the first floating diffusion are formed; a second substrate stacked on the first substrate and having the first amplification transistor, the second floating diffusion, and the mode switching unit formed thereon; a third substrate stacked on the second substrate and having the second amplification transistor formed thereon; and have electronic equipment.

[0175] According to a solid-state imaging device and an electronic device according to a first aspect of the present disclosure, and a solid-state imaging device and an electronic device according to a second aspect of the present disclosure, the amplification transistor to be used is selected according to the mode, and at least the amplification transistor is formed on a substrate separate from the substrate on which the photoelectric conversion unit is formed, so that it is possible to achieve both high sensitivity and a wide dynamic range even in high-definition applications. Note that the effects of the present technology are not necessarily limited to the effects described herein and may be any of the effects described in this specification.

[0176] This application claims priority based on Japanese Patent Application No. 2018-213147, filed on November 13, 2018, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0177] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor having a size larger than that of the first amplifying transistor; a mode changeover switch unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit; a first substrate on which the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, and the mode changeover switch unit are formed; a second substrate laminated on the first substrate and having the second amplifying transistor formed thereon; Equipped with Solid-state imaging device.

2. The electrodes of the transistors formed on the second substrate are configured to include silicide. The solid-state imaging device according to claim 1 .

3. The mode changeover switch unit further includes a drive circuit that changes a drive current according to the size of a transistor. The solid-state imaging device according to claim 1 .

4. a solid-state imaging device that outputs pixel signals in response to incident light; a signal processing circuit for processing the pixel signal; Equipped with The solid-state imaging device includes: A photoelectric conversion unit; a first signal path including a first floating diffusion and a first amplifying transistor; a second signal path including a second floating diffusion and a second amplifying transistor having a size larger than that of the first amplifying transistor; a mode changeover switch unit that, in a first mode, electrically connects the first signal path to the photoelectric conversion unit and electrically disconnects the second signal path from the photoelectric conversion unit, and, in a second mode, electrically connects both the first signal path and the second signal path to the photoelectric conversion unit; a first substrate on which the photoelectric conversion unit, the first floating diffusion, the first amplification transistor, the second floating diffusion, and the mode changeover switch unit are formed; a second substrate laminated on the first substrate and having the second amplifying transistor formed thereon; Equipped with electronic equipment.

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