Image Sensor

Abstract

To provide an image sensor in which an image quality was improved.SOLUTION: An image sensor includes: first to fourth pixels (hereinbelow, a PX) of a first direction arrangement; fifth to eighth PXs of a second direction arrangement and first direction arrangement crossed to a first direction from the first to fourth PXs; ninth to twelfth PXs of the second direction arrangement and first direction arrangement from the fifth to eighth PXs; thirteenth to sixteenth PXs of the second direction arrangement and first direction arrangement from the ninth to twelfth PXs; a first analog-digital converter (ADC) connected to the first, third, fifth ... fifteenth PXs; and a second ADC connected to the second, fourth, sixth ... sixteenth PXs. Each of the first to sixteenth PXs outputs first to sixteenth PX signals, and the first ADC outputs a first binning signal by performing a binning on the basis of the first, third, ninth, and eleventh PXs, and outputs a second binning signal by performing a binning on the basis of the fifth and fifteenth PX signals. The second ADC outputs a third binning signal by performing the binning on the basis of the sixth, eighth, fourteenth, and sixteenth PX signals, and outputs a fourth binning signal by performing a binning on the basis of the second, fourth, tenth, and twelfth PX signals.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to image sensors with improved image quality. [Background technology]

[0002] An image sensing device is a semiconductor device that converts optical information into an electrical signal. Such image sensing devices include a charge coupled device (CCD) image sensing device and a complementary metal-oxide semiconductor (CMOS) image sensing device.

[0003] CMOS image sensors are abbreviated as CIS (CMOS image sensor). The CIS comprises a plurality of pixels arranged two-dimensionally. Each pixel may include, for example, a photodiode (PD). The photodiode serves to convert incident light into an electrical signal. In recent years, with the development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in a variety of fields, including digital cameras, camcorders, smartphones, game devices, security cameras, medical micro cameras, and robots, making it necessary to develop image sensors with improved image quality. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-183527 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor with improved image quality. [Means for solving the problem]

[0006] The image sensor according to the present invention, which has been made to achieve the above object, includes a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in a first direction, a fifth pixel, a sixth pixel, a seventh pixel, and an eighth pixel arranged in a second direction intersecting the first direction from the first to fourth pixels and arranged in the first direction, a ninth pixel, a tenth pixel, an eleventh pixel, and a twelfth pixel arranged in the second direction from the fifth to eighth pixels and arranged in the first direction, a thirteenth pixel, a fourteenth pixel, a fifteenth pixel, and a sixteenth pixel arranged in the second direction from the ninth to twelfth pixels and arranged in the first direction, a first analog-to-digital converter connected to the first pixel, the third pixel, the fifth pixel, the seventh pixel, the ninth pixel, the eleventh pixel, the thirteenth pixel, and the fifteenth pixel, and a second pixel, a fourth pixel, a sixth pixel, and an eighth pixel, which are arranged in the second direction from the fifth to eighth pixels and arranged in the first direction. the first to 16th pixels output 1st to 16th pixel signals, respectively; the first analog-to-digital converter performs binning based on the first pixel signal, the third pixel signal, the ninth pixel signal, and the eleventh pixel signal to output a first binning signal, performs binning based on the fifth pixel signal and the fifteenth pixel signal to output a second binning signal, the second analog-to-digital converter performs binning based on the sixth pixel signal, the eighth pixel signal, the fourteenth pixel signal, and the 16th pixel signal to output a third binning signal, and performs binning based on the second pixel signal, the fourth pixel signal, the tenth pixel signal, and the twelfth pixel signal to output a fourth binning signal.

[0007] In order to achieve the above object, an image sensor according to the present invention includes a first pixel array that outputs a plurality of first white pixel values, a plurality of first green pixel values, a plurality of first red pixel values, and a plurality of first blue pixel values, a second pixel array that outputs a plurality of second white pixel values, a plurality of second green pixel values, a plurality of second red pixel values, and a plurality of second blue pixel values, and a binning module connected to the first pixel array and the second pixel array, the binning module performing binning based on the first white pixel values ​​to generate first white binned pixel values. , binning is performed based on the first green pixel value to generate a first green binned pixel value, binning is performed based on the first red pixel value to generate a first red binned pixel value, binning is performed based on the second white pixel value to generate a second white binned pixel value, binning is performed based on the second green pixel value to generate a second green binned pixel value, binning is performed based on the second blue pixel value to generate a second blue binned pixel value, no binning is performed based on the first blue pixel value, and no binning is performed based on the second red pixel value.

[0008] In addition, an image sensor according to the present invention, which has been made to achieve the above-mentioned object, includes a first array of pixels having a color pattern formed in an "n x m" array and including at least one first color pixel, a second color pixel, and a third color pixel; a second array of pixels adjacent to the first pixel array and having the same color pattern as the first pixel array formed in an "n x m" array and including at least one first color pixel, a second color pixel, and a third color pixel; and a binning module, wherein the binning module is configured to bin the first color pixels of the first array, the first color pixels of the second array, the second color pixels of the first array, and the third color pixels of the second array for an image to be sensed, not to bin the third color pixels of the first array, and not to bin the second color pixels of the second array.

[0009] To achieve the objectives, an image sensing method according to some embodiments of the present invention includes generating a plurality of first white pixel values, a plurality of first green pixel values, a plurality of first red pixel values, and a plurality of first blue pixel values, generating a plurality of second white pixel values, a plurality of second green pixel values, a plurality of second red pixel values, and a plurality of second blue pixel values, performing binning based on the first white pixel values ​​to generate first white binned pixel values, performing binning based on the first green pixel values ​​to generate first green binned pixel values, performing binning based on the first red pixel values ​​to generate first red binned pixel values, performing binning based on the second white pixel values ​​to generate second white binned pixel values, performing binning based on the second green pixel values ​​to generate second green binned pixel values, and performing binning based on the second blue pixel values ​​to generate second blue binned pixel values, and may not perform binning based on the second blue pixel values ​​and may not perform binning based on the second red pixel values. Effect of the Invention

[0010] According to the image sensor of the present invention, a second image signal is generated by performing binning based on a first image signal output from a pixel array having an RGBW pattern. At this time, the second image signal can be generated using a relatively simple binning method, thereby achieving an effect of generating a binned image signal in a relatively simple manner while improving image quality. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensing device according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a perspective view showing a conceptual layout of an image sensor according to an embodiment of the present invention. [Diagram 3] 1 is a top view for illustrating an outline of a pixel array of an image sensor according to an embodiment of the present invention; [Figure 4] 4 is a diagram illustrating a first image signal output from the pixel array of FIG. 3. FIG. [Diagram 5] 1 is a schematic circuit diagram of an image sensor according to an embodiment of the present invention; [Figure 6] 11 is a flowchart illustrating a binning operation on a first image signal. [Figure 7] 4 is a diagram for explaining generation of a second image signal by performing binning on a first image signal. FIG. [Figure 8] 4 is a diagram for explaining generation of a second image signal by performing binning on a first image signal. FIG. [Figure 9] 4 is a diagram for explaining generation of a second image signal by performing binning on a first image signal. FIG. [Figure 10] 4 is a diagram for explaining generation of a second image signal by performing binning on a first image signal. FIG. [Figure 11]4 is a diagram for explaining generation of a second image signal by performing binning on a first image signal. FIG. [Figure 12] 1 is a flowchart illustrating a binning mode of the image sensor. [Figure 13] FIG. 11 is a schematic circuit diagram for explaining the operation of the image sensor when not in the binning mode. [Figure 14] 1 is a schematic circuit diagram of an image sensor according to an embodiment of the present invention; [Figure 15] FIG. 2 is a block diagram showing a schematic configuration of a first image signal processor according to an embodiment of the present invention. [Figure 16] 16 is a flowchart for explaining the operation of the phase correction module of FIG. 15. [Figure 17] FIG. 11 is a diagram for explaining a phase correction method. [Figure 18] FIG. 11 is a diagram for explaining a phase correction method. [Figure 19] FIG. 2 is a diagram for explaining a first image signal having a high frequency. [Figure 20] 16 is a flowchart for explaining the operation of the false color reduction module of FIG. 15. [Figure 21] FIG. 11 is a diagram for explaining a false color reduction method. [Figure 22] FIG. 11 is a diagram for explaining a false color reduction method. [Diagram 23] 4 is a diagram illustrating a third image signal output from a first image signal processor according to an embodiment of the present invention; FIG. [Figure 24] FIG. 2 is a block diagram showing a schematic configuration of a second image signal processor according to an embodiment of the present invention. [Diagram 25] 1 is a top view for illustrating an outline of a pixel array of an image sensor according to an embodiment of the present invention; [Figure 26] FIG. 26 is a diagram for explaining a first quad image signal generated from FIG. 25. [Figure 27] FIG. 26 is a circuit diagram of the image sensor of FIG. 25. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Next, a specific example of an embodiment of an image sensor according to the present invention will be described with reference to the drawings.

[0013] FIG. 1 is a block diagram showing a schematic configuration of an image sensing device according to an embodiment of the present invention. Referring to FIG. 1, the image sensing device 1 includes an image sensor 100 and a second image signal processor 900 . The image sensor 100 senses an image of a sensing target using light and generates a first image signal IMGS1.

[0014] In one embodiment, the generated first image signal IMGS1 is, for example, a digital signal, although embodiments according to the inventive concept are not limited thereto. The first image signal IMGS1 is provided to a readout circuit 150, a buffer 170, and a latch 180 where it is binned. Therefore, the first image signal IMGS1 is output as a second image signal IMGS2 through the binning operation. The image sensor 100 performs analog binning on the first image signal IMGS1. The first image signal processor 400 performs correction on the second image signal IMGS2 and outputs a third image signal IMGS3. The third image signal IMGS3 is provided to a second image signal processor 900 for processing. The second image signal processor 900 processes or manipulates the received third image signal IMGS3 so that it can be easily displayed.

[0015] In one embodiment, the second image signal processor 900 performs digital binning on the third image signal IMGS3 output from the image sensor 100. At this time, the third image signal IMGS3 output from the image sensor 100 is a third image signal IMGS3 on which analog binning has already been performed. In one embodiment, the image sensor 100 and the second image signal processor 900 are disposed separately from each other as shown. For example, the image sensor 100 is mounted on a first chip, and the second image signal processor 900 is mounted on a second chip, and they communicate with each other via a predetermined interface. However, the embodiment is not limited thereto, and the image sensor 100 and the second image signal processor 900 can also be implemented as one package, for example, a multi-chip package (MCP).

[0016] The image sensor 100 includes a control register block 110, a timing generator 120, a row driver 130, a pixel array PA, a readout circuit 150, a ramp signal generator 160, a buffer 170, a latch 180, and a first image signal processor 400. The control register block 110 provides overall control over the operation of the image sensor 100 . In particular, the control register block 110 transmits direct operating signals to the timing generator 120 , the ramp signal generator 160 and the buffer 170 . In one embodiment, the control register block 110 controls the image sensor 100 to perform a binning operation on the first image signal IMGS1. The timing generator 120 generates signals that serve as a reference for the operation timing of various components of the image sensor 100 . The operation timing reference signal generated by the timing generator 120 is transmitted to the row driver 130, the readout circuit 150, the ramp signal generator 160, and the like.

[0017] The ramp signal generator 160 generates and transmits a ramp signal used by the readout circuit 150 . For example, the readout circuit 150 may include a correlated double sampler CDS, a comparator, etc., while the ramp signal generator 160 generates and transmits a ramp signal used by the correlated double sampler CDS, the comparator, etc. The buffer 170 temporarily stores the first image signal IMGS1 or the second image signal IMSG2. That is, the buffer 170 stores the generated second image signal IMGS2 in the binning mode, and stores the generated first image signal IMGS1 in the non-binning mode. In addition, the latch 180 latches the first image signal IMGS1 or the second image signal IMGS2 buffered in the buffer 170 and outputs it. Buffer 170 and latch 180 may include memory such as DRAM or SRAM.

[0018] The pixel array PA senses an external image. The pixel array PA includes a plurality of pixels (or unit pixels). The row driver 130 selectively activates rows of the pixel array PA. The readout circuit 150 samples the pixel signal provided from the pixel array PA, compares it with the ramp signal, and then converts the analog image signal (data) into a digital image signal (data) based on the comparison result. That is, the readout circuit 150 converts the first image signal IMGS1 from the pixel array PA into a digital image signal. In one embodiment, the readout circuit 150 outputs the second image signal IMGS2 by performing binning on the first image signal IMGS1.

[0019] The first image signal processor 400 receives the second image signal IMSG2 from the latch 180 . The first image signal processor 400 is disposed separately from the second image signal processor 900 . For example, the first image signal processor 400 is disposed in the image sensing device 1, whereas the second image signal processor 900 is implemented by an application processor, etc. The first image signal processor 400 performs correction on the second image signal IMGS2 to generate a third image signal IMGS3.

[0020] FIG. 2 is a perspective view showing a conceptual layout of an image sensor according to an embodiment of the present invention. Referring to FIG. 2, the image sensor 100 of this embodiment includes an upper chip 200 and a lower chip 300 that are stacked together. A plurality of pixels are arranged in a two-dimensional array structure on the upper chip 200 . That is, the upper chip 200 includes a pixel array PA. The lower chip 300 includes a logic area LC and a memory area. The lower chip 300 is disposed below the upper chip 200 and is electrically connected to the upper chip 200 . The lower chip 300 allows pixel signals transmitted from the upper chip 200 to be transmitted to a logic region LC of the lower chip 300 .

[0021] Logic elements are arranged in the logic region LC of the lower chip 300. The logic element includes circuitry for processing pixel signals from the pixels. For example, the logic elements include the control register block 110, the timing generator 120, the row driver 130, the read-out circuit 150, the ramp signal generator 160, the first image signal processor 400, etc. of FIG. Furthermore, memory elements are arranged on the lower chip 300 . For example, the buffer 170 and the latch 180 are located on the lower chip 300 .

[0022] FIG. 3 is a top view illustrating a schematic pixel array of an image sensor according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating a first image signal output from the pixel array of FIG. Referring to FIG. 3, a pixel array PA is disposed on the top surface of the image sensor 100. In detail, the pixel array PA is disposed on the upper surface of the upper chip 200 of the image sensor 100 . The pixel array PA includes a plurality of microlenses ML and a plurality of photodiodes PD. The pixel array PA includes a plurality of pixels regularly arranged in a first direction X and a second direction Y. Here, a microlens ML is disposed above each pixel, and a photodiode PD is disposed within each pixel. When light passes through the microlens ML and enters the photodiode PD, the photodiode PD converts the light into an electrical signal and outputs it.

[0023] Referring to FIG. 4, the first image signal IMGS1 output from the pixel array PA of FIG. 3 includes the first to eighth white pixel values ​​(W1a to W8a), the first to fourth green pixel values ​​(G1a to G4a), the first and second red pixel values ​​(R1a and R2a), and the first and second blue pixel values ​​(B1a and B2a). In addition, the first image signal IMGS1 includes the first to eighth white pixel values ​​(W1b to W8b), the first to fourth green pixel values ​​(G1b to G4b), the first and second red pixel values ​​(R1b and R2b), the first and second blue pixel values ​​(B1b and B2b), the first to eighth white pixel values ​​(W1c to W8c), the first to fourth green pixel values ​​(G1c to G4c), the first and second red pixel values ​​(R1c and R2c), the first and second blue pixel values ​​(B1c and B2c), the first to eighth white pixel values ​​(W1d to W8d), the first to fourth green pixel values ​​(G1d to G4d), the first and second red pixel values ​​(R1d and R2d), and the first and second blue pixel values ​​(B1d and B2d).

[0024] That is, the pixel array PA is configured in a pattern including 8 white pixels, 4 green pixels, 2 red pixels and 2 blue pixels. The green, red, and blue pixels are arranged so as to be surrounded by the white pixels, and the white pixels are arranged so as to be surrounded by the green, red, and blue pixels. Here, the pixel array PA is arranged in an RGBW pattern. In this embodiment, the first image signal IMGS1 will be described using the first to eighth white pixel values ​​(W1a to W8a), the first to fourth green pixel values ​​(G1a to G4a), the first and second red pixel values ​​(R1a and R2a), and the first and second blue pixel values ​​(B1a and B2a); however, the description of this embodiment can also be applied to other pixel values.

[0025] The first white pixel value W1a, the first green pixel value G1a, the second white pixel value W2a, and the second green pixel value G2a are sequentially arranged in a first direction X. The first red pixel value R1a, the third white pixel value W3a, the first blue pixel value B1a, and the fourth white pixel value W4a are disposed in a direction opposite to the second direction Y from the first white pixel value W1a, the first green pixel value G1a, the second white pixel value W2a, and the second green pixel value G2a. In addition, the first red pixel value R1a, the third white pixel value W3a, the first blue pixel value B1a, and the fourth white pixel value W4a are sequentially arranged in the first direction X.

[0026] The fifth white pixel value W5a, the third green pixel value G3a, the sixth white pixel value W6a, and the fourth green pixel value G4a are disposed in a direction opposite to the second direction Y from the first red pixel value R1a, the third white pixel value W3a, the first blue pixel value B1a, and the fourth white pixel value W4a. The fifth white pixel value W5a, the third green pixel value G3a, the sixth white pixel value W6a, and the fourth green pixel value G4a are sequentially arranged in the first direction X.

[0027] The second blue pixel value B2a, the seventh white pixel value W7a, the second red pixel value R2a, and the eighth white pixel value W8a are disposed in the opposite direction to the second direction Y from the fifth white pixel value W5a, the third green pixel value G3a, the sixth white pixel value W6a, and the fourth green pixel value G4a. The second blue pixel value B2a, the seventh white pixel value W7a, the second red pixel value R2a, and the eighth white pixel value W8a are sequentially arranged in the first direction X. Here, the array of pixel values ​​corresponds to an array of pixels corresponding to each pixel value.

[0028] In one embodiment, the first blue pixel value B1a and the second blue pixel value B2a are disposed in a fourth direction W. Here, the fourth direction W forms an acute angle with the first direction X and also forms an acute angle with the second direction Y. For example, the fourth direction W forms an angle of 45 degrees with the first direction X and forms an angle of 45 degrees with the second direction Y. That is, the fourth direction W corresponds to the diagonal direction. The first blue pixel value B1a and the second blue pixel value B2a are disposed in a fourth direction W with a third green pixel value G3a therebetween. In one embodiment, the first red pixel value R1a and the second red pixel value R2a are disposed in a direction intersecting with the fourth direction W. The third green pixel value G3a is located between the first red pixel value R1a and the second red pixel value R2a.

[0029] FIG. 5 is a schematic circuit diagram of an image sensor according to an embodiment of the present invention. Referring to FIG. 5, the first to sixteenth pixels (PX1 to PX16) are regularly arranged. Here, the first to sixteenth pixels (PX1 to PX16) output and correspond to the first to eighth white pixel values ​​(W1a to W8a), the first to fourth green pixel values ​​(G1a to G4a), the first and second red pixel values ​​(R1a and R2a), and the first and second blue pixel values ​​(B1a and B2a) of the first image signal IMGS1 in Figure 4.

[0030] The first to fourth pixels (PX1 to PX4) are arranged in the first direction X, and the fifth to eighth pixels (PX5 to PX8) are disposed in the direction opposite to the second direction Y from the first to fourth pixels (PX1 to PX4) and are arranged in the first direction X. The ninth to twelfth pixels (PX9 to PX12) are arranged in the direction opposite to the second direction Y from the fifth to eighth pixels (PX5 to PX8), and are arranged in the first direction X. The thirteenth to sixteenth pixels (PX13 to PX16) are arranged in the direction opposite to the second direction Y from the ninth to twelfth pixels (PX9 to PX12), and are arranged in the first direction X.

[0031] A plurality of row lines (ROW1a to ROW1d, ROW2a to ROW2d, ROW3a to ROW3d, ROW4a to ROW4d) are arranged extending in a first direction X, and a plurality of column lines (COL1 to COL4) are arranged extending in a second direction Y. The row lines (ROW1a to ROW1d, ROW2a to ROW2d, ROW3a to ROW3d, ROW4a to ROW4d) and the column lines (COL1 to COL4) are all connected to the 1st to 16th pixels (PX1 to PX16) at their intersecting positions.

[0032] The first pixel PX1 includes a first white photodiode PDW1, a first row line ROW1a, and a first transfer transistor TTG1 connected to a first column line COL1. The second pixel PX2 includes a first green photodiode PDG1, a first row line ROW1b, and a second transfer transistor TTG2 connected to the second column line COL2. The third pixel PX3 includes a second white photodiode PDW2, a first row line ROW1c, and a third transfer transistor TTG3 connected to the third column line COL3. The fourth pixel PX4 includes a second green photodiode PDG2, a first row line ROW1d, and a fourth transfer transistor TTG4 connected to a fourth column line COL4.

[0033] The thirteenth pixel PX13 includes a second blue photodiode PDB2, a fourth row line ROW4a, and a thirteenth transfer transistor TTG13 connected to the first column line COL1. The fourteenth pixel PX14 includes a seventh white photodiode PDW7, a fourth row line ROW4b, and a fourteenth transfer transistor TTG14 connected to the second column line COL2. The fifteenth pixel PX15 includes a second red photodiode PDR2, a fourth row line ROW4c, and a fifteenth transfer transistor TTG15 connected to the third column line COL3. The sixteenth pixel PX16 includes an eighth white photodiode PDW8, a fourth row line ROW4d, and a sixteenth transfer transistor TTG16 connected to the fourth column line COL4.

[0034] The image sensor 100 includes a binning module BM that includes a switch circuit 151 , an analog-to-digital converter 152 , a buffer 170 , and a latch 180 . Here, the binning module BM is controlled by a control register block 110 . The switch circuit 151 is connected to the first to fourth column lines (COL1 to COL4) and receives a first image signal IMGS1 via the first to fourth column lines (COL1 to COL4). Moreover, the switch circuit 151 is connected to first to fourth analog-to-digital converters (ADC) (152a to 152d). The switch circuit 151 selectively connects the first to fourth column lines (COL1 to COL4) to the first to fourth analog-to-digital converters (152a to 152d). This causes binning to be performed on the first image signal IMGS1.

[0035] The first pixel PX1, the fifth pixel PX5, the ninth pixel PX9, and the thirteenth pixel PX13 are connected to the first column line COL1, and provide the first white pixel value W1a, the first red pixel value R1a, the fifth white pixel value W5a, and the second blue pixel value B2a to the switch circuit 151. The second pixel PX2, the sixth pixel PX6, the tenth pixel PX10, and the fourteenth pixel PX14 are connected to the second column line COL2, and provide the first green pixel value G1a, the third white pixel value W3a, the third green pixel value G3a, and the seventh white pixel value W7a to the switch circuit 151. The third pixel PX3, the seventh pixel PX7, the eleventh pixel PX11, and the fifteenth pixel PX15 are connected to the third column line COL3, and provide the second white pixel value W2a, the first blue pixel value B1a, the sixth white pixel value W6a, and the second red pixel value R2a to the switch circuit 151. The fourth pixel PX4, the eighth pixel PX8, the twelfth pixel PX12, and the sixteenth pixel PX16 are connected to the fourth column line COL4, and provide the second green pixel value G2a, the fourth white pixel value W4a, the fourth green pixel value G4a, and the eighth white pixel value W8a to the switch circuit 151.

[0036] The switch circuit 151 bins pixel values ​​by connecting the first to fourth column lines (COL1 to COL4) to one of the first to fourth analog-to-digital converters (152a to 152d). An analog-to-digital converter 152 converts the received pixel values ​​into a digital signal. The analog-to-digital converter 152 also performs binning on the received pixel values. The buffer 170 buffers the binned pixel values, and the latch 180 latches the buffered binned pixel values ​​to output a second image signal IMGS2.

[0037] Hereinafter, the binning operation on the first image signal IMGS1 will be described with reference to FIGS. FIG. 6 is a flowchart for explaining the binning operation on the first image signal, and FIGS. 7 to 11 are diagrams for explaining the generation of the second image signal by performing binning on the first image signal.

[0038] 5 and 6, the first to sixteenth pixels (PX1 to PX16) output a first image signal IMGS1 (step S400). The first to eighth white pixel values ​​(W1a to W8a), the first to fourth green pixel values ​​(G1a to G4a), the first and second red pixel values ​​(R1a and R2a), and the first and second blue pixel values ​​(B1a and B2a) included in the first image signal IMGS1 are transmitted to a binning module BM. 5 to 7, the image sensor 100 generates white binned pixel values ​​by performing binning based on white pixel values ​​(step S401).

[0039] The image sensor 100 generates a first white binned pixel value W1a' by performing binning based on the first white pixel value W1a, the second white pixel value W2a, the fifth white pixel value W5a, and the sixth white pixel value W6a included in the first image signal IMGS1. For example, the first white binned pixel value W1a' corresponds to the sum or average of the first white pixel value W1a, the second white pixel value W2a, the fifth white pixel value W5a, and the sixth white pixel value W6a. At this time, the switch circuit 151 connects the first column line COL1 to the first analog-to-digital converter 152a and the third column line COL3 to the third analog-to-digital converter 152c, and the analog-to-digital converter 152 performs binning to generate a first white binned pixel value W1a'.

[0040] The image sensor 100 generates a second white binned pixel value W2a' by performing binning based on the third white pixel value W3a, the fourth white pixel value W4a, the seventh white pixel value W7a, and the eighth white pixel value W8a included in the first image signal IMGS1. For example, the second white binned pixel value W2a' corresponds to the sum or average of the third white pixel value W3a, the fourth white pixel value W4a, the seventh white pixel value W7a, and the eighth white pixel value W8a. At this time, the switch circuit 151 connects the second column line COL2 to the second analog-to-digital converter 152b and the fourth column line COL4 to the fourth analog-to-digital converter 152d, and the analog-to-digital converter 152 performs binning to generate a second white binned pixel value W2a'.

[0041] 5, 6 and 8, the image sensor 100 generates green binned pixel values ​​by performing binning based on the green pixel values ​​(step S402). The image sensor 100 generates a first green binned pixel value G1a' by performing binning based on the first to fourth green pixel values ​​(G1a to G4a) included in the first image signal IMGS1. For example, the first green binned pixel value G1a' corresponds to the sum or average of the first to fourth green pixel values ​​(G1a to G4a). At this time, the switch circuit 151 connects the second column line COL2 to the second analog-to-digital converter 152b and the fourth column line COL4 to the fourth analog-to-digital converter 152d, and the analog-to-digital converter 152 performs binning to generate a first green binned pixel value G1a'.

[0042] 5, 6, and 9, the image sensor 100 generates red binned pixel values ​​by performing binning based on the red pixel values ​​(step S403). The image sensor 100 generates a first red binned pixel value R1a' by performing binning based on the first and second red pixel values ​​(R1a and R2a) included in the first image signal IMGS1. For example, a first red binned pixel value R1a' corresponds to the sum or average of the first and second red pixel values ​​(R1a and R2a). At this time, the switch circuit 151 connects the first column line COL1 to the first analog-to-digital converter 152a and the third column line COL3 to the third analog-to-digital converter 152c, and the analog-to-digital converter 152 performs binning to generate a first red binned pixel value R1a'.

[0043] 5, 6, and 10, the image sensor 100 generates blue binned pixel values ​​by performing binning based on the blue pixel values ​​(step S404). The image sensor 100 generates a first blue binned pixel value B1b' by performing binning based on the first and second blue pixel values ​​(B1b and B2b) included in the first image signal IMGS1. For example, a first blue binned pixel value B1b' corresponds to the sum or average of the first and second blue pixel values ​​(B1b and B2b). At this time, the switch circuit 151 connects the first column line COL1 to the first analog-to-digital converter 152a and the third column line COL3 to the third analog-to-digital converter 152c, and the analog-to-digital converter 152 performs binning to generate a first blue binned pixel value B1b'.

[0044] Referring to FIG. 11, the image sensor 100 generates a second image signal IMGS2 by performing binning based on a first image signal IMGS1. At this time, the second image signal IMGS2 includes first and second white binned pixel values ​​(W1a' and W2a'), a first green binned pixel value G1a', and a first red binned pixel value R1a'. At this time, the image sensor 100 does not perform binning based on the first blue pixel value B1a and the second blue pixel value B2a. That is, information on the first blue pixel value B1a and the second blue pixel value B2a is not included in the second image signal IMGS2.

[0045] In addition, the second image signal IMGS2 includes first and second white binning pixel values ​​(W1b' and W2b'), a first green binning pixel value G1b' and a first blue binning pixel value B1b', first and second white binning pixel values ​​(W1c' and W2c'), a first green binning pixel value G1c' and a first blue binning pixel value B1c', first and second white binning pixel values ​​(W1d' and W2d'), a first green binning pixel value G1d' and a first red binning pixel value R1d'. The image sensor 100 does not perform binning based on the first red pixel value R1b and the second red pixel value R2b, does not perform binning based on the first red pixel value R1c and the second red pixel value R2c, and does not perform binning based on the first blue pixel value B1d and the second blue pixel value B2d.

[0046] That is, the second image signal IMGS2 does not include information on the first red pixel value R1b, the second red pixel value R2b, the first red pixel value R1c, the second red pixel value R2c, the first blue pixel value B1d, and the second blue pixel value B2d. In summary, the image sensor 100 generates a second image signal IMGS2 by performing binning on a first image signal IMGS1 output from a pixel array PA having an RGBW pattern. In this case, the second image signal IMGS2 is generated using a relatively simple binning method. Thus, an image sensor 100 can be provided that generates a binned image signal in a relatively simple manner while improving image quality.

[0047] FIG. 12 is a flow chart for explaining the binning mode of the image sensor, and FIG. 13 is a schematic circuit diagram for explaining the operation of the image sensor when not in the binning mode.

[0048] Referring to FIG. 12, the image sensor 100 determines whether or not it is in the binning mode (step S410). If the determination corresponds to the binning mode ("Y" es in step S410), the image sensor 100 outputs the second image signal IMGS2 by performing binning based on the first image signal IMGS1 (step S412). That is, the image sensor 100 generates the second image signal IMGS2 including the binned pixel values ​​as described with reference to FIGS. If it is determined that the binning mode is not applicable ("No" in step S410), the image sensor 100 outputs the first image signal IMGS1 (step S411).

[0049] 13, when the mode does not correspond to the binning mode, the switch circuit 151 connects the first to fourth column lines (COL1 to COL4) to the first to fourth analog-digital converters (152a to 152d), respectively. At this time, the binning module BM does not perform binning on the first image signal IMGS1. In this case, the binning module BM therefore outputs a first image signal IMGS1. That is, depending on whether the binning mode is selected or not, the binning module BM outputs at least one of a first image signal IMGS1 and a second image signal IMGS2.

[0050] FIG. 14 is a schematic circuit diagram of an image sensor according to an embodiment of the present invention. 14, the image sensor 100 includes a binning module BM′, which includes a first analog-to-digital converter 152 e, a second analog-to-digital converter 152 f, a buffer 170, and a latch 180.

[0051] The first analog-to-digital converter 152e is connected to the first column line COL1 and the third column line COL3, and the second analog-to-digital converter 152f is connected to the second column line COL2 and the fourth column line COL4. That is, the first analog-to-digital converter 152e is connected to the first pixel PX1, the third pixel PX3, the fifth pixel PX5, the seventh pixel PX7, the ninth pixel PX9, the eleventh pixel PX11, the thirteenth pixel PX13, and the fifteenth pixel PX15 via the first and third column lines (COL1 and COL3). The second analog-to-digital converter 152f is connected to the second pixel PX2, the fourth pixel PX4, the sixth pixel PX6, the eighth pixel PX8, the tenth pixel PX10, the twelfth pixel PX12, the fourteenth pixel PX14, and the sixteenth pixel PX16 via the second and fourth column lines (COL2 and COL4). The first analog-to-digital converter 152e receives pixel values ​​from each pixel and performs binning, and the second analog-to-digital converter 152f receives pixel values ​​from each pixel and performs binning.

[0052] FIG. 15 is a block diagram showing a schematic configuration of a first image signal processor according to an embodiment of the present invention, FIG. 16 is a flowchart for explaining the operation of the phase correction module of FIG. 15, and FIG. 17 and FIG. 18 are diagrams for explaining a phase correction method. Referring to FIG. 15, the first image signal processor 400 includes a phase correction module 410 , a false color reduction module 420 , and an adder 430 .

[0053] The first image signal processor 400 performs correction on the second image signal IMGS2 to generate and output a third image signal IMGS3. However, the embodiment of the present invention is not limited thereto, and the second image signal processor 900 generates a third image signal IMGS3 by performing correction on the second image signal IMGS2. That is, the second image processor 900 included in the application processor can also perform correction on the second image signal IMGS2. The phase correction module 410 performs phase correction on the second image signal IMGS2 to generate a second image signal IMGS2'.

[0054] 16 and 17, the phase correction module 410 generates a white interpolated pixel value by performing interpolation based on the white binning pixel value (step S420). In addition, the phase correction module 410 generates a green interpolated pixel value by performing interpolation based on the green binning pixel value (step S421).

[0055] The second image signal IMGS2' differs from the second image signal IMGS2 in that it includes a first white interpolated pixel value W1a", a second white interpolated pixel value W2a", a first green interpolated pixel value G1a", a first white interpolated pixel value W1b", a second white interpolated pixel value W2b", a first green interpolated pixel value G1b", a first white interpolated pixel value W1c", a second white interpolated pixel value W2c", a first green interpolated pixel value G1c", a first white interpolated pixel value W1d", a second white interpolated pixel value W2d", and a first green interpolated pixel value G1d".

[0056] For example, the phase correction module 410 generates a plurality of white interpolated pixel values ​​by performing interpolation based on a plurality of white binned pixel values. For example, the second white interpolated pixel value W2a" is generated by interpolating based on the first white binning pixel value W1a', the first white binning pixel value W1b', the second white binning pixel value W2b', the first white binning pixel value W1c', the second white binning pixel value W2c', the first white binning pixel value W1d', and the second white binning pixel value W2d'. The phase correction module 410 also generates a plurality of green interpolated pixel values ​​by performing interpolation based on the plurality of green binned pixel values.

[0057] Here, the plurality of white-interpolated pixel values ​​and the plurality of green-interpolated pixel values ​​correspond to the second image signal IMGS2 and other positions. Therefore, the spacing between pixel values ​​is changed uniformly. As shown in FIG. 18, jagging artifacts are prevented, thereby improving image quality. At this time, the first and second red binned pixel values ​​(R1a' and R2d') and the first and second blue binned pixel values ​​(B1b' and B2c') are not changed.

[0058] FIG. 19 is a diagram for explaining a first image signal having a high frequency. 19, the first image signal IMGS1 includes high frequency components in the fourth direction W. That is, the first image signal IMGS1 includes edge components in the diagonal direction. For example, the pixel values ​​in the fourth direction W are repeated as "1" and "0" at regular intervals. Therefore, the first image signal IMGS1 has high frequency components and includes edge components.

[0059] The first green binned pixel value G1a' corresponds to the average of the "0" and "1" values, where the binning module BM corresponds to a low pass filter. That is, diagonal high frequency components are removed from the first green binned pixel value G1a'. However, the first red binned pixel value R1a' corresponds to "0". That is, diagonal high frequency components are not removed from the first red binned pixel value R1a', the second red binned pixel value R2d', the first blue binned pixel value B1b', and the second blue binned pixel value B2c', which may result in false colors.

[0060] FIG. 20 is a flowchart for explaining the operation of the false color reduction module of FIG. 15, and FIGS. 21 and 22 are diagrams for explaining a false color reduction method.

[0061] 15 and 20, the false color reduction module 420 detects high frequency components in the fourth direction W from the first image signal IMGS1 (step S430). Here, the false color reduction module 420 detects high frequency components in the diagonal direction using the first image signal IMGS1, not the second image signal IMGS2. If no high frequency components in the fourth direction W are detected from the first image signal IMGS1 ("N" in step S430), no false color reduction correction is performed. If high frequency components in the fourth direction W are detected from the first image signal IMGS1 ("Y" es in step S430), the false color reduction module 420 compensates the red binning pixel values ​​based on the green binning pixel values ​​(step S431) and compensates the blue binning pixel values ​​based on the green binning pixel values ​​(step S432).

[0062] Referring to FIG. 21, the second image signal IMGS2″ includes a first red corrected pixel value R1a″, a first red corrected pixel value R1d′”, a first blue corrected pixel value B1b′”, and a first blue corrected pixel value B1c′”. The false color reduction module 420 corrects the false color of the first red binned pixel value R1a' using components of the first plurality of green binned pixel values ​​(G1a', G1b', G1c', G1d').

[0063] For example, when a high frequency component is detected in the fourth direction W, the components of the first green binning pixel value G1a' and the first green binning pixel value G1d' arranged in the fourth direction W are subtracted from the first red binning pixel value R1a'. In addition, the components of the first green binning pixel value G1b' and the first green binning pixel value G1c' that are not disposed in the fourth direction W from the first red binning pixel value R1a' are added. This generates a first red corrected pixel value R1a''' in which the false color of the first red binned pixel value R1a' is corrected. The first red corrected pixel value R1d''', the first blue corrected pixel value B1b''', and the first blue corrected pixel value B1c''' may also be generated in a similar manner. According to the correction method, false colors are corrected when high frequency components exist in the fourth direction W as shown in FIG.

[0064] FIG. 23 is a diagram illustrating a third image signal output from a first image signal processor according to an embodiment of the present invention. 15 and 23, an adder 430 adds a second image signal IMGS2'' to a second image signal IMGS2'. That is, the first red binned pixel values ​​(R1a' and R1d') and the first blue binned pixel values ​​(B1b' and B1c') of the second image signal IMGS2' are replaced with first red compensated pixel values ​​(R1a''' and R1d'''') and first blue compensated pixel values ​​(B1b''' and B1c'''). Thereby, the adder 430 outputs the third image signal IMGS3 with improved image quality.

[0065] FIG. 24 is a block diagram showing a schematic configuration of a second image signal processor according to an embodiment of the present invention. Referring to FIG. 24, an image signal processor 400' includes a phase correction module 410 and a false color reduction module 420 connected in series. After the phase correction is performed on the second image signal IMGS2 by the phase correction module 410, the false color reduction correction is performed by the false color reduction module 420. As a result, the third image signal IMGS3' is output.

[0066] Hereinafter, an image sensor 100' according to another embodiment of the present invention will be described with reference to FIGS. FIG. 25 is a top view for illustrating an outline of a pixel array of an image sensor according to an embodiment of the present invention, FIG. 26 is a diagram for illustrating a first quad image signal generated from FIG. 25, and FIG. 27 is a schematic circuit diagram of the image sensor of FIG. 25. For convenience of explanation, parts that overlap with the contents explained using FIGS. 1 to 24 will be explained briefly or omitted.

[0067] Referring to FIG. 25, an image sensor 100' includes multiple pixel groups. A pixel group of the plurality of pixel groups includes a plurality of pixels. For example, one pixel group includes four pixels. In this embodiment, the first white pixel group includes first to fourth white photodiodes (PDW1 to PDW4). The first white pixel group overlaps one microlens ML'. That is, the light transmitted through the microlens ML' is converted into electric signals by the first to fourth white photodiodes (PDW1 to PDW4). For example, the image sensor 100' includes a pixel array PA' corresponding to a quadra cell. However, the embodiment of the present invention is not limited thereto, and the image sensor 100' may correspond to a nona cell.

[0068] 25 and 26, a pixel array PA' outputs a first quad image signal IMGSQ1. The first quad image signal IMGSQ1 includes first to eighth white pixel values ​​(W1a to W8a), first to fourth green pixel values ​​(G1a to G4a), first and second red pixel values ​​(R1a and R2a), and first and second blue pixel values ​​(B1a and B2a). Here, one pixel value corresponds to a pixel value that is binned and output from one pixel group.

[0069] Referring to FIG. 27, the first to fourth white photodiodes PDW1 to PDW4 are connected to the first row lines ROW1a and ROW1b, the second row lines ROW2a and ROW2b, and the first column line COL1. The first and second white photodiodes (PDW1 and PDW2) are arranged in a first direction, and the third and fourth white photodiodes (PDW3 and PDW4) are arranged in the first direction. The electrical signals output from the first to fourth white photodiodes (PDW1 to PDW4) correspond to a first white pixel value W1a that is generated by binning the electrical signals output from each of the first to fourth white photodiodes (PDW1 to PDW4). Here, the first white pixel value W1a corresponds to an analog signal and is converted into a digital signal by the analog-to-digital converter 152.

[0070] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0071] 1. Image sensing device 100 Image Sensor 110 Control Register Block 120 Timing Generator 130 Row driver 150 Readout circuit 151 Switch Circuit 152 Analog-to-Digital Converter 152a, 152e first analog-to-digital converter 152b, 152f second analog-to-digital converter 152c 3rd Analog-to-Digital Converter 152d 4th analog-to-digital converter 160 Ramp Signal Generator 170 buffers 180 Latch 200 Top Tip 300 Lower Tip 400, 400' First image signal processor 410 Phase Correction Module 420 False Color Reduction Module 430 Adder 900 Second Image Signal Processor PA Pixel Array

Claims

1. a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in a first direction; a fifth pixel, a sixth pixel, a seventh pixel, and an eighth pixel arranged in a second direction intersecting the first direction from the first to fourth pixels, and aligned in the first direction; a ninth pixel, a tenth pixel, an eleventh pixel, and a twelfth pixel arranged in the first direction from the fifth pixel to the eighth pixel in the second direction; a thirteenth pixel, a fourteenth pixel, a fifteenth pixel, and a sixteenth pixel disposed in the second direction from the ninth to twelfth pixels and arranged in the first direction; a first analog-to-digital converter coupled to the first pixel, the third pixel, the fifth pixel, the seventh pixel, the ninth pixel, the eleventh pixel, the thirteenth pixel, and the fifteenth pixel; a second analog-to-digital converter coupled to the second pixel, the fourth pixel, the sixth pixel, the eighth pixel, the tenth pixel, the twelfth pixel, the fourteenth pixel, and the sixteenth pixel; the first to sixteenth pixels output first to sixteenth pixel signals, respectively; the first analog-to-digital converter performs binning based on the first pixel signal, the third pixel signal, the ninth pixel signal, and the eleventh pixel signal to output a first binned signal; performing binning based on the fifth pixel signal and the fifteenth pixel signal to output a second binned signal; the second analog-to-digital converter performs binning based on the sixth pixel signal, the eighth pixel signal, the fourteenth pixel signal, and the sixteenth pixel signal to output a third binned signal; 13. The image sensor according to claim 12, wherein the image sensor performs binning on the second pixel signal, the fourth pixel signal, the tenth pixel signal, and the twelfth pixel signal to output a fourth binning signal.

2. the first, third, sixth, eighth, ninth, eleventh, fourteenth, and sixteenth pixels include a white color filter; The image sensor of claim 1 , wherein the second, fourth, tenth, and twelfth pixels include a green color filter.

3. the fifth and fifteenth pixels include a red color filter; The image sensor of claim 2 , wherein the seventh and thirteenth pixels include a blue color filter.

4. the fifth and fifteenth pixels include a blue color filter; The image sensor of claim 2 , wherein the seventh and thirteenth pixels include a red color filter.

5. The image sensor of claim 1 , wherein the first and second analog-to-digital converters do not perform binning based on the seventh pixel signal and the thirteenth pixel signal.

6. 17th to 20th pixels arranged in the first direction from the fourth pixel, and aligned in the first direction; 21st to 24th pixels arranged in the second direction from the 17th to 20th pixels and arranged in the first direction; 25th to 28th pixels arranged in the second direction from the 21st to 24th pixels and arranged in the first direction; 29th to 32nd pixels arranged in the second direction from the 25th to 28th pixels and arranged in the first direction; a third analog-to-digital converter connected to the 17th pixel, the 19th pixel, the 21st pixel, the 23rd pixel, the 25th pixel, the 27th pixel, the 29th pixel, and the 31st pixel; a fourth analog-to-digital converter coupled to the 18th pixel, the 20th pixel, the 22nd pixel, the 24th pixel, the 26th pixel, the 28th pixel, the 30th pixel, and the 32nd pixel; the 17th to 32nd pixels output 17th to 32nd pixel signals, respectively; the third analog-to-digital converter performs binning based on the 17th pixel signal, the 19th pixel signal, the 25th pixel signal, and the 27th pixel signal to output a fifth binned signal; performing binning based on the 23rd pixel signal and the 29th pixel signal to output a sixth binning signal; the fourth analog-to-digital converter performs binning based on the 22nd pixel signal, the 24th pixel signal, the 30th pixel signal, and the 32nd pixel signal to output a seventh binning signal; 2. The image sensor of claim 1, further comprising: a binning step for binning an eighth binned signal based on the 18th pixel signal, the 20th pixel signal, the 26th pixel signal, and the 28th pixel signal;

7. The image sensor of claim 6 , wherein the third and fourth analog-to-digital converters do not perform binning based on the second and third pixel signals.

8. The image sensor of claim 7 , wherein the first and second analog-to-digital converters do not perform binning based on the seventh pixel signal and the thirteenth pixel signal, respectively.

9. the first to sixteenth pixels are disposed on a first substrate; The image sensor of claim 1 , wherein the first and second analog-to-digital converters are disposed on a second substrate below the first substrate.

10. an image signal processor for performing correction on an image signal including the first to fourth binning signals; 2. The image sensor of claim 1, wherein the image signal processor generates a first interpolated binning signal, a third interpolated binning signal, and a fourth interpolated binning signal by performing interpolation on the first binning signal, the third binning signal, and the fourth binning signal.

11. The image sensor of claim 10 , wherein the image signal processor does not perform interpolation on the second binned signal.

12. 11. The image sensor of claim 10, wherein the image signal processor corrects the second binning signal using a component of the fourth binning signal.

13. a first pixel array outputting a plurality of first white pixel values, a plurality of first green pixel values, a plurality of first red pixel values, and a plurality of first blue pixel values; a second pixel array outputting a plurality of second white pixel values, a plurality of second green pixel values, a plurality of second red pixel values, and a plurality of second blue pixel values; a binning module coupled to the first pixel array and the second pixel array; the binning module performs binning based on the first white pixel value to generate a first white binned pixel value; performing binning based on the first green pixel value to generate a first green binned pixel value; performing binning based on the first red pixel value to generate a first red binned pixel value; performing binning based on the second white pixel value to generate a second white binned pixel value; performing binning based on the second green pixel value to generate a second green binned pixel value; performing binning based on the second blue pixel value to generate a second blue binned pixel value; no binning is performed based on the first blue pixel value; The image sensor further comprises: an image sensor that does not perform binning based on the second red pixel value.

14. the second pixel array is disposed in a first direction from the first pixel array; The image sensor of claim 13 , wherein the binning module is disposed in a second direction intersecting the first direction from the first and second pixel arrays.

15. a third pixel array arranged in the second direction from the first pixel array, the third pixel array outputting a plurality of third white pixel values, a plurality of third green pixel values, a plurality of third red pixel values, and a plurality of third blue pixel values; the binning module performs binning based on the third white pixel value to generate a third white binned pixel value; performing binning based on the third green pixel value to generate a third green binned pixel value; performing binning based on the third blue pixel value to generate a third blue binned pixel value; 15. The image sensor of claim 14, wherein no binning is performed based on the third red pixel value.

16. receiving the first and second white binned pixel values, the first and second green binned pixel values, the first red binned pixel value, and the second blue binned pixel value; generating first and second white interpolated pixel values ​​by performing an interpolation on the white binned pixel values ​​including the first and second white binned pixel values; 14. The image sensor of claim 13, further comprising an image signal processor that generates first and second green interpolated pixel values ​​by performing interpolation on green binned pixel values ​​including the first and second green binned pixel values.

17. 17. The image sensor of claim 16, wherein the image signal processor does not perform interpolation on the first red binned pixel values ​​and the second blue binned pixel values.

18. when high frequency components are detected from the first and second white pixel values, the first and second green pixel values, the first and second red pixel values, and the first and second blue pixel values, correcting the first red binned pixel value using the first and second green binned pixel values; 17. The image sensor of claim 16, wherein the second blue binned pixel value is corrected using the first and second green binned pixel values.

19. a first array of pixels having a color pattern formed in an "n x m" array, the first array including at least one first color pixel, a second color pixel, and a third color pixel; a second array of pixels adjacent to the first pixel array and having the same color pattern as the first pixel array formed in an "n x m" array, the second array of pixels including at least one first color pixel, a second color pixel, and a third color pixel; a binning module, the binning module performs binning on the first color pixels of the first array, the first color pixels of the second array, the second color pixels of the first array, and the third color pixels of the second array for a sensed image; no binning is performed on the third color pixels of the first array; an image sensor configured to perform no binning on the second color pixels of the second array;

20. 20. The image sensor of claim 19, wherein the first array and the second array each include more first color pixels than second color pixels and more first color pixels than third color pixels.

Images