Nitride Semiconductor Device

Abstract

This nitride semiconductor device comprises: an electron transit layer; an electron supply layer which is formed on the electron transit layer; a gate layer which is formed on the electron supply layer and contains an Al1-xGaxN material (wherein 0 < X < 1) that contains a first impurity; a gate electrode which is formed on the gate layer so as to form a Schottky junction with the gate layer; and a source electrode and a drain electrode, which are electrically connected to the electron supply layer. Since the gate withstand voltage is able to be improved due to this configuration, the present invention is able to provide a nitride semiconductor device that has high reliability.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] For example, Patent Document 1 discloses a HEMT including a support substrate, a buffer layer on the support substrate, an electron traveling layer on the buffer layer, an electron supply layer on the electron traveling layer, a gate recess formed in the electron supply layer and reaching the electron traveling layer, an insulating film formed on the wall surface of the gate recess and on the electron supply layer, a gate electrode embedded on the insulating film, and a source electrode and a drain electrode formed to be in ohmic contact with the electron supply layer and electrically connected to a two-dimensional electron gas layer through the electron supply layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Means for Solving the Problems

[0004] A nitride semiconductor device according to an embodiment of the present disclosure includes an electron traveling layer, an electron supply layer formed on the electron traveling layer, a gate layer formed on the electron supply layer and containing an Al 1-x Ga x N (0 < X < 1) - based material containing a first impurity, a gate electrode formed on the gate layer and Schottky - junctioned to the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0006] <Embodiments of the Present Disclosure> First, embodiments of the present disclosure will be listed and described.

[0007] A nitride semiconductor device according to an embodiment of the present disclosure includes an electron traveling layer, an electron supply layer formed on the electron traveling layer, and a gate layer formed on the electron supply layer and containing an Al 1-x Ga x N (0 <X <1) -based material, a gate electrode formed on the gate layer and Schottky-junctioned to the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer.

[0008] A nitride semiconductor device according to an embodiment of the present disclosure includes an electron traveling layer, an electron supply layer formed on the electron traveling layer, and Al formed on the electron supply layer and containing a first impurity. 1-x Ga x It may include a gate layer including an N (0 < X < 1) - based semi - insulating material, a gate electrode formed on the gate layer and Schottky - junctioned to the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer.

[0009] According to the nitride semiconductor device according to an embodiment of the present disclosure, the gate breakdown voltage can be improved, so that a highly reliable nitride semiconductor device can be provided. Further, since the gate electrode is Schottky - junctioned to the gate layer, the gate leakage current can also be reduced.

[0010] In the nitride semiconductor device according to an embodiment of the present disclosure, the gate electrode may include at least one of TiN, Ti, Al, W, Mo, and TaN.

[0011] In the nitride semiconductor device according to an embodiment of the present disclosure, the first impurity may include at least one of Mg and Zn.

[0012] In the nitride semiconductor device according to an embodiment of the present disclosure, the gate layer has a thickness of 60 nm or more and a concentration of the first impurity of 3×10 18 cm -3 or more.

[0013] In the nitride semiconductor device according to an embodiment of the present disclosure, the gate layer may have a thickness of 100 nm or more.

[0014] In the nitride semiconductor device according to an embodiment of the present disclosure, the electron traveling layer includes a GaN - based material, the electron supply layer includes an Al 1-x Ga x N (0 < X < 1) - based material, and the gate layer may have an Al composition ratio smaller than the Al composition ratio of the electron supply layer.

[0015] In a nitride semiconductor device according to an embodiment of the present disclosure, the gate layer includes a first portion having a relatively small Al composition ratio and a second portion formed on the opposite side of the electron supply layer with respect to the first portion and having a relatively larger Al composition ratio than the first portion, and an average Al composition ratio of the first portion and the second portion may be smaller than the Al composition ratio of the electron supply layer.

[0016] In a nitride semiconductor device according to an embodiment of the present disclosure, the Al composition ratio of the gate layer may increase linearly or stepwise from the electron supply layer toward the gate electrode.

[0017] A nitride semiconductor device according to an embodiment of the present disclosure may include a mesa structure portion that continuously straddles the gate layer and the gate electrode and has a wall surface inclined with respect to the surface of the electron supply layer.

[0018] In a nitride semiconductor device according to an embodiment of the present disclosure, the gate electrode may have a thickness smaller than that of the gate layer.

[0019] In a nitride semiconductor device according to an embodiment of the present disclosure, the gate electrode may be formed in an inner region of the gate layer such that a step is formed between a side surface of the gate layer and a side surface of the gate electrode.

[0020] In a nitride semiconductor device according to an embodiment of the present disclosure, the gate electrode may have a thickness larger than that of the gate layer. <Detailed Description of Embodiments of the Present Disclosure> Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. ≪Planar Structure of Nitride Semiconductor Device 1≫ FIG. 1 is a schematic plan view of a nitride semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is a schematic plan view showing an internal structure of the nitride semiconductor device 1 of FIG. 1. The nitride semiconductor device 1 may be a chip formed in a rectangular shape in plan view. In this embodiment, the nitride semiconductor device 1 is formed in a square shape in plan view, and has, for example, a first side 11, a second side 12, a third side 13, and a fourth side 14 that are continuous in a clockwise direction.

[0021] The lengths L1 of the first side 11 and the third side 13 of the nitride semiconductor device 1 are, for example, 0.5 mm to 10 mm, and the lengths L2 of the second side 12 and the fourth side 14 may be, for example, 0.5 mm to 10 mm.

[0022] An active region 2 is formed at a substantially central portion on the nitride semiconductor device 1. As shown in FIG. 2, the active region 2 has a structure in which a set of a gate electrode 3, a source electrode 4, and a drain electrode 5 arranged so as to sandwich the gate electrode 3 from both sides is taken as one unit, and the units are arranged in parallel with each other.

[0023] More specifically, the source electrode 4 and the drain electrode 5 extend in the X direction. The gate electrode 3 includes a plurality of electrode portions 6 extending in the X direction in parallel with each other, and two base portions 7 connecting the corresponding ends of these plurality of electrode portions 6.

[0024] In the example of FIG. 2, the source electrode 4 (S), the electrode portion 6 (G) of the gate electrode 3, and the drain electrode 5 (D) are periodically arranged in the order of DGSGDGS in the Y direction. Thereby, an element structure is configured by sandwiching the electrode portion 6 (G) of the gate electrode 3 between the source electrode 4 (S) and the drain electrode 5 (D). The region on the surface of the semiconductor stack structure 28 (described later) includes the active region 2 including the element structure and a non-active region 8 other than the active region 2. In FIG. 2, reference numeral 9 indicates an element isolation line that is a boundary line between the active region 2 and the non-active region 8. The base portion 7 of the gate electrode 3 connects the corresponding ends of the plurality of electrode portions 6 in the non-active region 8.

[0025] In this embodiment, the active region 2 has a rectangular shape in plan view that is elongated in the direction along the first side 11 and the third side 13, and has a length approximately equal to the length L1 of the first side 11.

[0026] As electrodes drawn from the source electrode 4, gate electrode 3, and drain electrode 5 of each unit of the active region 2, a source electrode film 10, a gate electrode film 15, and a drain electrode film 16 are arranged. As the source electrode film 10, gate electrode film 15, and drain electrode film 16, for example, a metal film such as an Al film can be applied. Note that the source electrode film 10, gate electrode film 15, and drain electrode film 16 may be referred to as a source metal, a gate metal, and a drain metal, respectively, based on the constituent materials, or may simply be referred to as a source electrode, a gate electrode, and a drain electrode based on the functional aspect.

[0027] The source electrode film 10 is arranged on the first side 11 side with respect to the active region 2. In this embodiment, the source electrode film 10 is formed in a rectangular shape in plan view having a width narrower than that of the active region 2.

[0028] In the region on the nitride semiconductor device 1, a region 17 composed of a step formed by the difference in width between the active region 2 and the source electrode film 10 is formed. As shown in FIG. 1, the region 17 may be formed at the intersection of the first side 11 and the second side 12 of the nitride semiconductor device 1.

[0029] The gate electrode film 15 is arranged in the region 17 formed by the step between the active region 2 and the source electrode film 10 (in this embodiment, the intersection of the first side 11 and the second side 12 of the nitride semiconductor device 1), and is formed in a square shape in plan view.

[0030] The drain electrode film 16 is arranged between the active region 2 and the third side 13 of the nitride semiconductor device 1, and is formed in a rectangular shape in plan view having a width approximately equal to the length L1 of the first side 11. That is, the drain electrode film 16 may be formed in a rectangular shape elongated in the direction along the first side 11 and the third side 13.

[0031] Then, the source electrode film 10, the gate electrode film 15, and the drain electrode film 16 are covered with the surface insulating film 18. As the surface insulating film 18, for example, SiN or the like can be applied. Openings 22, 23, and 24 are formed in the surface insulating film 18 to expose a part of the source electrode film 10, the gate electrode film 15, and the drain electrode film 16 as the source pad 19, the gate pad 20, and the drain pad 21, respectively.

[0032] The source pad 19 is formed, for example, in a substantially elliptical shape along the first side 11 in the vicinity of the first side 11 of the nitride semiconductor device 1. As shown in FIG. 1, the substantially elliptical source pad 19 may have a shape including a pair of straight lines facing each other along the first side 11 and in a direction intersecting the first side 11, and a semi-circle connecting the ends of the pair of sides.

[0033] The gate pad 20 is arranged along the first side 11 of the nitride semiconductor device 1 with a space from the source pad 19. That is, the source pad 19 and the gate pad 20 may be arranged side by side along the first side 11 of the nitride semiconductor device 1. Also, the shape of the gate pad 20 may be a substantially elliptical shape along the first side 11, similar to the source pad 19.

[0034] The drain pad 21 is formed, for example, in a substantially elliptical shape along the third side 13 in the vicinity of the third side 13 of the nitride semiconductor device 1. As shown in FIG. 1, the substantially elliptical drain pad 21 may have a shape including a pair of straight lines facing each other along the third side 13 and in a direction intersecting the third side 13, and a semi-circle connecting the ends of the pair of sides. In this embodiment, the length of the pair of straight lines may be approximately equal to the length L1 of the first side 11 of the nitride semiconductor device 1. In this case, the drain pad 21 may face both the source pad 19 and the gate pad 20 in the direction intersecting the first side 11.

[0035] Note that, regarding the shapes, arrangements, numbers, etc. of the source pad 19, gate pad 20, and drain pad 21, the above example is merely an example, and it may be appropriately changed according to the design. ≪Cross-sectional structure of nitride semiconductor device 1≫ FIG. 3 is a diagram showing the III-III cross-section of FIG. 2. FIG. 4 is an enlarged view of the main part of the portion surrounded by the two-dot chain line IV in FIG. 3. FIG. 5 is a diagram for explaining variations of the gate structure in FIG. 4.

[0036] The nitride semiconductor device 1 includes a substrate 27 having a first surface 25 and a second surface 26 on the opposite side of the first surface 25, and a semiconductor laminate structure 28 formed on the first surface 25 of the substrate 27.

[0037] As the substrate 27, for example, an insulating substrate such as a sapphire substrate, a semiconductor substrate such as an Si substrate, an SiC substrate, or a GaN substrate can be applied. In this embodiment, the substrate 27 is an Si substrate. Also, the thickness of the substrate 27 may be, for example, 400 μm to 1000 μm. Note that the first surface 25 and the second surface 26 of the substrate 27 may be referred to as the front surface and the back surface of the substrate 27, respectively. Also, the second surface 26 of the substrate 27 may be an exposed surface on which no structures such as electrodes or semiconductor laminate structures are formed.

[0038] The semiconductor laminate structure 28 is a laminate structure composed of a plurality of semiconductor layers having different compositions. In this embodiment, the semiconductor laminate structure 28 includes a buffer layer 29, an electron traveling layer 30, and an electron supply layer 31 in order from the side closer to the first surface 25 of the substrate 27. These layers 29 to 31 may be formed by epitaxially growing raw materials on the first surface 25 of the substrate 27.

[0039] The buffer layer 29 is not particularly limited as long as it can relax the lattice mismatch of the electron transport layer 30 with respect to the substrate 27. The buffer layer 29 may be, for example, a multilayer buffer layer formed by laminating a plurality of nitride semiconductor layers. In this embodiment, the buffer layer 29 includes a first buffer layer 32 made of an AlN layer in contact with the first surface 25 of the substrate 27, and a second buffer layer 33 made of an AlGaN layer laminated on the first buffer layer 32. The thickness of the first buffer layer 32 may be, for example, about 50 nm to 500 nm. The thickness of the second buffer layer 33 may be, for example, larger than that of the first buffer layer 32 and about 50 nm to 2000 nm. The buffer layer 29 may be a single layer of AlN or a single layer of AlGaN.

[0040] As the electron transport layer 30, for example, an undoped nitride semiconductor can be applied. Specifically, it may be a layer made of an undoped Al 1-x Ga x N (0 < X ≦ 1) - based material. The undoped nitride semiconductor layer means, for example, a semiconductor layer formed without intentionally doping impurities during the crystal growth process of the electron transport layer 30. In addition to Al, Ga, and N constituting the electron transport layer 30, several other elements may be unintentionally mixed in.

[0041] Further, the thickness of the electron transport layer 30 may be, for example, 0.3 μm or less and 0.01 μm or more. Since the two - dimensional electron gas 34 described later is formed in the electron transport layer 30 and the channel of the nitride semiconductor device 1 is formed in this layer, it may also be referred to as the channel layer.

[0042] As the electron supply layer 31, for example, Al with an Al composition ratio different from that of the electron transport layer 30 1-x Ga xA layer made of an N(0≦X<1) - based material can be applied. For example, the electron transport layer 30 may be a GaN layer and the electron supply layer 31 may be an AlGaN layer. Also, the thickness of the electron supply layer 31 may be, for example, 5 nm to 100 nm if the electron supply layer 31 is AlGaN, or 1 nm to 5 nm if the electron supply layer 31 is AlN. Note that the electron supply layer 31 may also be referred to as a barrier layer.

[0043] As described above, the electron transport layer 30 and the electron supply layer 31 are made of nitride semiconductors with different Al composition ratios, and a lattice mismatch occurs between them. Then, due to the polarization caused by this lattice mismatch, a two - dimensional electron gas 34 caused by the polarization spreads at a position close to the interface between the electron transport layer 30 and the electron supply layer 31 (for example, at a position about several Å from the interface).

[0044] On the semiconductor stack structure 28, a gate layer 35 is formed, and a gate electrode 3 is formed on this gate layer 35.

[0045] The gate layer 35 is selectively formed on a part of the surface 37 of the electron supply layer 31. The gate layer 35 is made of an Al 1-x Ga x N(0<X<1) - based material. In this embodiment, the gate layer 35 contains at least one of Mg and Zn as an impurity, which is an example of the first impurity of the present disclosure. The Al 1-x Ga x N(0<X<1) - based material may be a semi - insulating material. A semi - insulating material means that when forming the gate layer 35, without performing an annealing process for activating the above - mentioned impurities while epitaxially growing the Al 1-x Ga x N(0<X<1) - based material, the impurities are in an inactive state, and it can be defined as an Al 1-x Ga x N(0<X<1) - based material.

[0046] Also, as shown in FIG. 4, the thickness T of the gate layer 35 1is, for example, 60 nm or more, preferably 60 nm to 165 nm, and more preferably 100 nm to 165 nm. Further, the impurity concentration of the gate layer 35 (when both Mg and Zn are contained, the total concentration of both) is, for example, 3×10 18 cm -3 or more, preferably 3×10 18 cm -3 to 5×10 20 cm -3 may be sufficient.

[0047] In the nitride semiconductor device 1, the positive polarization charges generated near the heterointerface between the electron transport layer 30 in the electron supply layer 31 and the gate layer 35 are canceled by the spontaneous polarization generated in the gate layer 35. As a result, the two-dimensional electron gas 34 selectively disappears in the region directly under the gate electrode 3. Thereby, the two-dimensional electron gas 34 is divided into distribution regions with the region directly under the gate electrode 3 as a boundary, and the normally-off operation of the nitride semiconductor device 1 is achieved.

[0048] The gate electrode 3 is Schottky-junctioned to the gate layer 35. The material of the gate electrode 3 is not particularly limited as long as it can be Schottky-junctioned to the gate layer 35. For example, for the gate layer 35 made of an AlGaN-based material, the gate electrode 3 may be at least one of TiN, Ti, Al, W, Mo, and TaN.

[0049] Further, as shown in FIG. 4, the thickness T 2 of the gate electrode 3 is smaller than the thickness T 1 of the gate layer 35, and is, for example, 100 nm or more, and preferably may be 50 nm to 150 nm.

[0050] Also, in this embodiment, as shown in FIG. 4, the stacked structure of the gate layer 35 and the gate electrode 3 forms a mesa structure portion 36. This mesa structure portion 36 extends in a stripe shape with a space between them as shown by the gate electrode 3 (electrode portion 6) in FIG. 2, and may be referred to as a ridge structure.

[0051] The mesa structure portion 36 has a wall surface 38 inclined with respect to the surface 37 of the electron supply layer 31. The wall surface 38 continuously extends across the gate layer 35 and the gate electrode 3. In other words, the side surface 39 of the gate layer 35 and the side surface 40 of the gate electrode 3 are continuously connected without a step so as to form a single flat surface, thereby forming the wall surface 38. Accordingly, as shown in FIG. 4, the mesa structure portion 36 may have a substantially isosceles trapezoidal shape in a cross-sectional view, with the upper surface 41 of the gate electrode 3 as the upper base and the lower surface 42 of the gate layer 35 as the lower base.

[0052] An insulating layer 43 is formed on the semiconductor stack structure 28 so as to cover the gate electrode 3. As the insulating layer 43, for example, SiO 2 etc. can be applied. Also, the thickness of the insulating layer 43 may be, for example, 50 nm to 300 nm.

[0053] Source contact holes 44 and drain contact holes 45 for exposing the electron supply layer 31 are formed in the insulating layer 43. Source electrodes 4 and drain electrodes 5 are respectively formed in the source contact holes 44 and the drain contact holes 45.

[0054] The source electrode 4 makes an ohmic contact with the electron supply layer 31. The source electrode 4 may have, for example, a lower layer (for example, a Ti layer) that makes an ohmic contact with the electron supply layer 31 and an upper layer (for example, an Al layer) laminated on the lower layer. Also, the source electrode 4 has an extension portion 46 that extends from the source contact hole 44 toward the drain electrode 5. The extension portion 46 is formed so as to cover the gate electrode 3 and has an end portion 47 between the gate electrode 3 and the drain electrode 5 in the direction along the surface 37 of the electron supply layer 31.

[0055] The drain electrode 5 makes an ohmic contact with the electron supply layer 31. The drain electrode 5 may have, for example, a lower layer (for example, a Ti layer) that makes an ohmic contact with the electron supply layer 31 and an upper layer (for example, an Al layer) laminated on the lower layer. <<Variations of the Gate Structure>> Next, variations of the gate structure formed by the gate layer 35 and the gate electrode 3 will be described with reference to FIG. 5.

[0056] In FIG. 4, the gate structure formed a mesa structure portion 36 having a wall surface 38 that continuously straddles the gate layer 35 and the gate electrode 3. In contrast, the mesa structure portion 48 formed by the gate layer 35 and the gate electrode 3 in FIG. 5 has a wall surface 50 having a step 49 at the boundary between the gate layer 35 and the gate electrode 3. More specifically, the side surface 40 of the gate electrode 3 is formed at a position away from the side surface 39 of the gate layer 35 and inside the gate layer 35. As a result, the gate electrode 3 is formed in the inner region of the gate layer 35.

[0057] Also, the side surface 39 of the gate layer 35 and the side surface 40 of the gate electrode 3 are each inclined with respect to the surface 37 of the electron supply layer 31. Further, the side surface 40 of the gate electrode 3 may include a flat surface 51 inclined with respect to the surface 37 of the electron supply layer 31 and a curved surface 52 that is continuous with the flat surface 51 and bulges into the inner region of the gate layer 35. For example, the lower side surface 40 of the gate electrode 3 may be the curved surface 52. The curved surface 52 may be continuous with the side surface 39 of the gate layer 35.

[0058] Also, in the mesa structure portion 48, the thickness T of the gate electrode 3 2 may be greater than the thickness T of the gate layer 35. 1 In this case, the thickness T of the gate layer 35 1 is 50 nm to 150 nm, and the thickness T of the gate electrode 3 2 may be 100 nm to 300 nm. ≪Al composition ratio of gate layer 35≫ Next, with reference to FIGS. 6 to 8, the Al composition ratio of the gate layer 35 will be described in detail. FIG. 6 is a diagram for comparing the Al composition ratios of the electron supply layer 31 and the gate layer 35.

[0059] As described above, the electron supply layer 31 is made of an Al 1-x Ga x N (0 ≦ X < 1) - based material, and the gate layer 35 is Al 1-xGa x It may be made of an AlGaN (0 < X < 1) - based material. Therefore, even when the electron supply layer 31 is made of an AlGaN (0 < X < 1) - based material, both the electron supply layer 31 and the gate layer 35 may be AlGaN layers. 1-x Ga x When the electron supply layer 31 is made of an AlGaN (0 < X < 1) - based material, both the electron supply layer 31 and the gate layer 35 may be AlGaN layers.

[0060] In this case, it is preferable that the gate layer 35 has an Al composition ratio (average Al composition ratio X4 described later) smaller than the Al composition ratio X1 of the electron supply layer 31. For example, when the Al composition ratio X1 of the AlGaN electron supply layer 31 is 15% to 30%, the Al composition ratio X4 of the AlGaN gate layer 35 may be 5% to 10%. Thereby, the generation of cracks in the gate layer 35 can be suppressed, and the flow of gate leakage current can be prevented.

[0061] The electron supply layer 31 grown from the underlying GaN layer (electron traveling layer 30) with a lattice constant close to that of GaN has a lattice constant close to that of GaN on its surface 37 although it is an AlGaN layer. Therefore, by reducing the Al composition ratio of the gate layer 35 and making the crystal structure of the gate layer 35 closer to the crystal structure of GaN, the lattice constant difference between the gate layer 35 and the electron supply layer 31 can be reduced. As a result, the strain caused by the lattice constant difference can be reduced, so that the probability of crack generation in the gate layer 35 can be reduced.

[0062] Also, in this embodiment, as shown in FIG. 6, the gate layer 35 includes a first portion 53 having a relatively small Al composition ratio X2 and a second portion 54 formed on the side opposite to the electron supply layer 31 with respect to the first portion 53 and having a relatively larger Al composition ratio X3 than the first portion 53. In this case, the average Al composition ratio ((X2 + X3) / 2) of the first portion 53 and the second portion 54 may be smaller than the Al composition ratio X1 of the electron supply layer 31. Also, the thickness of the first portion 53 may be smaller than the thickness of the second portion 54. For example, the thickness of the first portion 53 may be 5 nm to 30 nm, and the thickness of the second portion 54 may be 50 nm to 120 nm.

[0063] By making the Al composition ratio X2 of the first portion 53 closer to the electron supply layer 31 smaller than the Al composition ratio X3 of the second portion 54, the Schottky characteristics of the gate electrode 3 with respect to the gate layer 35 can be stabilized. Further, the gate layer 35 can be stably formed in a ridge structure. For example, when selectively etching the gate layer 35, the etching is stopped based on the change in the etching rate. By forming the first portion 53, since the etching rates of the first portion 53 and the electron supply layer 31 are significantly different, more accurate etching stop becomes possible.

[0064] The first portion 53 and the second portion 54 of the gate layer 35 can be formed, for example, by changing the supply amount of an aluminum source gas (for example, trimethylaluminum (TMAl)) supplied to the chamber of the epitaxial growth apparatus during the epitaxial growth of the gate layer 35. Therefore, a clear boundary does not necessarily have to be formed between the first portion 53 and the second portion 54 of the gate layer 35. For example, in FIG. 6, the boundary portion 55 between the first portion 53 and the second portion 54 of the gate layer 35 is shown by a straight dashed line, but in reality, it does not have to be a clear straight line. For example, when performing a composition analysis in the thickness direction of the gate layer 35, a certain thickness portion where the Al composition ratio is increasing or decreasing may be defined as a vague boundary portion.

[0065] Next, the distribution of the Al composition ratio in the gate layer 35 will be described in more detail with reference to FIGS. 6, 7, and 8. FIGS. 7 and 8 are diagrams for explaining the distribution of the Al composition ratio of the gate layer 35. Note that FIG. 7 shows a case where the gate layer 35 has, in order from the side of the electron supply layer 31, a first portion 56, a second portion 57, a third portion 58, and a fourth portion 59 as portions having different Al composition ratios from each other. That is, the gate layer 35 does not have to be limited to two portions as shown in FIG. 6, but may have three portions, four portions, or more portions as portions having different Al composition ratios from each other.

[0066] In FIGS. 6 and 7, the distribution of the Al composition ratio of the gate layer 35 increases stepwise from the electron supply layer 31 toward the gate electrode 3. The stepwise increase may mean that, for example, when the composition analysis in the thickness direction of the gate layer 35 is performed, a plurality of portions having an Al composition ratio within a certain range are formed. For example, in FIG. 6, a first portion 53 having an Al composition ratio of 0% to 3% and a second portion 54 having an Al composition ratio of 5% to 15% are formed, and when these Al composition ratios are graphed, a step with a certain width may be provided.

[0067] On the other hand, in FIG. 8, the distribution of the Al composition ratio of the gate layer 35 increases linearly from the electron supply layer 31 toward the gate electrode 3 as shown by the distribution curve 60. The linear increase may mean that, for example, when the composition analysis in the thickness direction of the gate layer 35 is performed, the Al composition ratio continuously increases from the electron supply layer 31 toward the gate electrode 3. In FIG. 8, for comparison, the distribution of the stepwise changing Al composition ratio in FIG. 7 is shown by a broken line. ≪Operation and Effect of Nitride Semiconductor Device 1≫ Next, the operation and effect of the nitride semiconductor device 1 according to this embodiment will be described.

[0068] According to the aforementioned nitride semiconductor device 1, since the gate layer 35 is made of an Al 1-x Ga x N (0 <X <1) - based material containing at least one of Mg and Zn, the gate breakdown voltage can be improved. Further, since the gate electrode 3 is Schottky - bonded to the gate layer 35, the gate leakage current can also be reduced. As a result, a highly reliable nitride semiconductor device 1 can be provided.

[0069] The improvement of the gate breakdown voltage by the AlGaN gate layer 35 is shown in FIGS. 9 and 10. FIG. 9 is a diagram showing the relationship between the gate voltage and the breakdown time (tBD) of Sample 1 and Sample 2. FIG. 10 is a diagram showing the relationship between the electric field strength and the breakdown time (tBD) of Sample 1 and Sample 2.

[0070] More specifically, a TDDB (Time Dependent Dielectric Breakdown) test was conducted on a HEMT having gate layers 35 of AlGaN (Mg-doped) and GaN (Mg-doped) respectively, and it was compared which of the AlGaN gate layer 35 (sample 1) and the GaN gate layer 35 (sample 2) breaks down in a short time. The thickness of the gate layer 35 was 80 nm, the Al composition ratio was 8%, and the concentration of Mg was 5×10 19 cm -3 as specified.

[0071] As shown in FIG. 9, in sample 2, as the gate voltage Vg is increased to 7.5 V, 8.5 V, and 9.5 V, the time tBD until the gate layer 35 breaks down becomes shorter. On the other hand, in sample 1, similar to sample 2, the time tBD becomes shorter as the gate voltage Vg increases, but it can be seen that at any gate voltage Vg, the time tBD until breakdown is longer than that of sample 2.

[0072] Further, FIG. 10 shows the X-axis (horizontal axis) of the graph in FIG. 9 represented by the electric field strength of the gate layer 35. According to FIG. 10, the electric field strength of the gate layer 35 of sample 1 is shifted to the higher electric field strength side compared to the electric field strength of the gate layer 35 of sample 2, and it can be seen that the breakdown voltage of the gate layer 35 of sample 1 is superior. For example, when a gate voltage Vg = 7.5 V is applied, the electric field strength of sample 2 is about 7.2×10 5 V / cm, while the electric field strength of sample 1 is about 7.8×10 5 V / cm.

[0073] As described above, the embodiments of the present disclosure have been explained, but the present disclosure can also be implemented in other forms, and various design changes can be made within the scope of the matters described in the claims.

[0074] This application corresponds to Japanese Patent Application No. 2020-076664 filed with the Japan Patent Office on April 23, 2020, and the entire disclosure of this application is incorporated herein by reference.

Description of Symbols

[0075] 1: Nitride semiconductor device 3: Gate electrode 4: Source electrode 5: Drain electrode 6: Electrode portion 7: Base portion 10: Source electrode film 15: Gate electrode film 16: Drain electrode film 28: Semiconductor laminate structure 30: Electron traveling layer 31: Electron supply layer 35: Gate layer 36: Mesa structure portion 37: (Electron supply layer) surface 38: (Mesa structure portion) wall surface 39: (Gate layer) side surface 40: (Gate electrode) side surface 48: Mesa structure portion 49: Step 50: (Mesa structure portion) wall surface 51: (Gate electrode) flat surface 52: (Gate electrode) curved surface 53: (Gate layer) first portion 54: (Gate layer) second portion 55: Boundary portion 56: (Gate layer) first portion 57: (Gate layer) second portion 58: (Gate layer) third portion 59: (Gate layer) fourth portion T 1 : Thickness T 2 : Thickness X1: Al composition ratio X2: Al composition ratio X3: Al composition ratio X4: Average Al composition ratio

Claims

1. An electron transport layer; an electron supply layer formed on the electron transit layer; An Al layer containing a first impurity is formed on the electron supply layer. １－ｘ G ｘ a gate layer including an N(0<X<1)-based material; a gate electrode formed on the gate layer and connected to the gate layer in a Schottky junction; a source electrode and a drain electrode electrically connected to the electron supply layer; the electron transport layer includes a GaN-based material; the electron supply layer includes an Al 1-x Ga x N (0<x<1) based material; the gate layer has an Al composition ratio smaller than an Al composition ratio of the electron supply layer, the gate layer includes a first portion having a relatively small Al composition ratio, and a second portion formed on an opposite side of the electron supply layer with respect to the first portion and having a relatively larger Al composition ratio than the first portion; an average Al composition ratio of the first portion and the second portion is smaller than an Al composition ratio of the electron supply layer.

2. An electron transport layer; an electron supply layer formed on the electron transit layer; a gate layer formed on the electron supply layer and including an Al 1-x Ga x N (0<x<1)-based material containing a first impurity; a gate electrode formed on the gate layer and connected to the gate layer in a Schottky junction; a source electrode and a drain electrode electrically connected to the electron supply layer; a mesa structure portion that is continuous across the gate layer and the gate electrode and has a wall surface that is inclined with respect to a surface of the electron supply layer, The gate electrode has a thickness smaller than that of the gate layer.

3. 3. The nitride semiconductor device according to claim 1, wherein said gate electrode contains at least one of TiN, Ti, Al, W, Mo and TaN.

4. 4. The nitride semiconductor device according to claim 1, wherein said first impurity includes at least one of Mg and Zn.

5. The gate layer has a thickness of 60 nm or more and a thickness of 3×10 １８ cm －３ 5. The nitride semiconductor device according to claim 1, wherein the first impurity has a concentration of at least one of the above.

6. The nitride semiconductor device according to claim 5 , wherein said gate layer has a thickness of 100 nm or more.

7. the electron transport layer includes a GaN-based material; The electron supply layer is made of Al １－ｘ G ｘ N(0<X<1)-based materials, The nitride semiconductor device according to claim 2 , wherein said gate layer has an Al composition ratio smaller than an Al composition ratio of said electron supply layer.

8. the gate layer includes a first portion having a relatively small Al composition ratio, and a second portion formed on an opposite side of the electron supply layer with respect to the first portion and having a relatively larger Al composition ratio than the first portion; The nitride semiconductor device according to claim 7 , wherein an average Al composition ratio of said first portion and said second portion is smaller than an Al composition ratio of said electron supply layer.

9. 9. The nitride semiconductor device according to claim 1, wherein an Al composition ratio of said gate layer increases linearly or stepwise from said electron supply layer to said gate electrode.

10. 2. The nitride semiconductor device according to claim 1, wherein said gate electrode is formed in an inner region of said gate layer such that a step is formed between a side surface of said gate layer and a side surface of said gate electrode.

11. The nitride semiconductor device according to claim 10 , wherein said gate electrode has a thickness greater than that of said gate layer.

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