Semiconductor Device

Abstract

This semiconductor device comprises: a semiconductor chip having a major surface; a drift region of a first conductivity type formed in an upper-layer portion of the major surface; a body region of a second conductivity type formed in an upper-layer portion of the drift region; a source region of the first conductivity type formed in an upper-layer portion of the body region; a plurality of trench source structures formed on the major surface across the source region and the body region to reach the drift region, and arrayed spaced apart from each other in a first direction; a body connection region of the second conductivity type formed in a region between two of the trench source structures proximate to each other in the upper-layer portion of the body region so as to be electrically connected to the body region; and a source connection region of the first conductivity type formed in a region between two of the trench source structures proximate to each other in a region different from the body connection region in the upper-layer portion of the body region so as to be electrically connected to the source region.

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-110900 filed with the Japan Patent Office on June 26, 2020, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an n-type drift region, a p-type body region, a plurality of trench gate structures, a plurality of trench source structures, a plurality of n-type source regions, and a plurality of p-type body contact regions. The drift region is formed in the surface layer portion of the semiconductor substrate. The body region is formed in the surface layer portion of the drift region. The plurality of trench gate structures are formed in the semiconductor substrate at intervals so as to reach the drift region and are arranged in a stripe shape extending in one direction.

[0003] The plurality of trench source structures are respectively formed in regions between two adjacent trench gate structures in the semiconductor substrate and are arranged in a stripe shape extending along the trench gate structures. Each source region is formed along each trench gate structure in the surface layer portion of the body region. Each body contact region is formed along each trench source structure in the surface layer portion of the body region and is connected to each source region.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment of the present invention provides a semiconductor device that can contribute to miniaturization.

Means for Solving the Problem

[0006] One embodiment of the present invention includes a semiconductor chip having a main surface, a drift region of a first conductivity type formed in a surface layer portion of the main surface, a body region of a second conductivity type formed in a surface layer portion of the drift region, a source region of a first conductivity type formed in a surface layer portion of the body region, a plurality of trench source structures formed on the main surface so as to cross the source region and the body region and reach the drift region, and arranged at intervals in a first direction, and a body connection region of a second conductivity type formed in a region between two adjacent trench source structures in the surface layer portion of the body region so as to be electrically connected to the body region, and a source connection region of a first conductivity type formed in a region between two adjacent trench source structures in a region different from the body connection region in the surface layer portion of the body region so as to be electrically connected to the source region. A semiconductor device is provided.

[0007] The above-mentioned or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] FIG. 1 is a plan view showing a SiC semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a plan view showing the layout of the electrodes shown in FIG. 1. FIG. 3 is a plan view showing the layout of the first main surface 3 of the SiC chip 2 shown in FIG. 1. FIG. 4 is an enlarged plan view of a main part of the structure shown in FIG. 3. FIG. 5 is an enlarged plan view of another main part of the structure shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 4. FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 5.

[0010] Referring to FIGS. 1 to 10, the SiC semiconductor device 1 is, in this embodiment, an electronic component including a SiC chip 2 made of a hexagonal SiC single crystal. Further, the SiC semiconductor device 1 is, in this embodiment, a semiconductor switching device including a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor). The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example in which the SiC chip 2 is made of a 4H-SiC single crystal is shown, but other polytypes are not excluded.

[0011] The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 is a device surface on which a functional device is formed. The second main surface 4 is a non-device surface on which a functional device is not formed. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (specifically, a rectangular shape) in a plan view (hereinafter simply referred to as "plan view") as viewed from the normal direction Z thereof.

[0012] The first major surface 3 and the second major surface 4 face the c-plane of the SiC single crystal. The c-plane includes the silicon plane ((0001) plane) and the carbon plane ((000-1) plane) of the SiC single crystal. It is preferable that the first major surface 3 faces the silicon plane and the second major surface 4 faces the carbon plane. The first major surface 3 and the second major surface 4 may have an off-angle inclined at a predetermined angle in an off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be more than 0° and 10° or less. The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less.

[0013] The second major surface 4 may be composed of a rough surface having either or both of grinding marks and annealing marks (specifically, laser irradiation marks). The annealing marks may include amorphous SiC and / or SiC alloyed (silicided) with a metal (specifically, Si). The second major surface 4 preferably consists of an ohmic surface having at least annealing marks.

[0014] The first side surface 5A and the second side surface 5B extend in a first direction X along the first major surface 3 and face a second direction Y intersecting (specifically, orthogonal) to the first direction X. The first side surface 5A and the second side surface 5B form the short sides of the SiC chip 2. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first side surface 5A and the second side surface 5B form the long sides of the SiC chip 2.

[0015] In this form, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal. That is, the first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal, and the third side surface 5C and the fourth side surface 5D are formed by the m-plane of the SiC single crystal.

[0016] The first to fourth side surfaces 5A to 5D may be composed of a ground surface having grinding marks formed by cutting with a dicing blade, or may be composed of a cleavage surface having a modified layer formed by laser light irradiation. Specifically, the modified layer is composed of a region in which a part of the crystal structure of the SiC chip 2 is modified to have different properties. That is, the modified layer is composed of a region in which the density, refractive index, or mechanical strength (crystal strength), or other physical properties are modified to have properties different from those of the SiC chip 2. The modified layer may include at least one layer of an amorphous layer, a melt re-hardened layer, a defect layer, an insulation breakdown layer, or a refractive index change layer.

[0017] When the first to fourth side surfaces 5A to 5D are composed of cleavage surfaces, the first side surface 5A and the second side surface 5B may form inclined surfaces having an inclination angle due to the off angle. The inclination angle due to the off angle is an angle with respect to the normal direction Z when the normal direction Z is 0°. The first side surface 5A and the second side surface 5B may form inclined surfaces extending along the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z.

[0018] The inclination angle due to the off angle is substantially equal to the off angle. The inclination angle due to the off angle may be more than 0° and 10° or less (preferably 2° or more and 4.5° or less). Since the third side surface 5C and the fourth side surface 5D extend in the off direction (a-axis direction), they do not have an inclination angle due to the off angle. The third side surface 5C and the fourth side surface 5D extend planar in the second direction Y (a-axis direction) and the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0019] The SiC semiconductor device 1 includes an n-type (first conductivity type) drain region 6 (first semiconductor region) formed in the surface layer portion of the second main surface 4 of the SiC chip 2. The drain region 6 forms the drain of the MISFET. The drain region 6 is formed over the entire surface layer portion of the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. That is, the drain region 6 has a part of the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0020] The drain region 6 has an n-type impurity concentration that is substantially constant in the thickness direction. The n-type impurity concentration of the drain region 6 is 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. The thickness of the drain region 6 may be 5 μm or more and 300 μm or less. The thickness of the drain region 6 is typically 50 μm or more and 250 μm or less. The thickness of the drain region 6 is adjusted by grinding the second main surface 4. In this form, the drain region 6 is formed of an n-type semiconductor substrate (SiC substrate).

[0021] The SiC semiconductor device 1 includes an n-type drift region 7 (second semiconductor region) formed in the surface layer portion of the first main surface 3 of the SiC chip 2. The drift region 7 is formed over the entire surface layer portion of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. That is, the drift region 7 has a part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The drift region 7 is electrically connected to the drain region 6 and forms the drain of the MISFET together with the drain region 6.

[0022] The drift region 7 has an n-type impurity concentration that is less than the n-type impurity concentration of the drain region 6. The n-type impurity concentration of the drift region 7 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The thickness of the drift region 7 may be 5 μm or more and 20 μm or less. In this form, the drift region 7 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0023] The drift region 7 preferably has a concentration gradient in which the n-type impurity concentration increases (specifically, gradually increases) from the second main surface 4 (drain region 6) side toward the first main surface 3. That is, the drift region 7 preferably has a low-concentration region 8 located on the second main surface 4 side and a high-concentration region 9 located on the first main surface 3 side and having a higher concentration than the low-concentration region 8. The high-concentration region 9 is exposed from the first main surface 3. The n-type impurity concentration of the low-concentration region 8 may be 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less. The n-type impurity concentration of the high-concentration region 9 may be 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less.

[0024] The SiC semiconductor device 1 includes an n-type buffer region 10 (third semiconductor region) interposed between the drain region 6 and the drift region 7 in the SiC chip 2. The buffer region 10 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration of the drain region 6 toward the n-type impurity concentration of the drift region 7. The buffer region 10 is interposed throughout the region between the drain region 6 and the drift region 7 and is exposed from the first to fourth side surfaces 5A to 5D. That is, the buffer region 10 has a part of the first to fourth side surfaces 5A to 5D.

[0025] The buffer region 10 is electrically connected to the drain region 6 and the drift region 7 and forms the drain of the MISFET together with the drain region 6 and the drift region 7. The thickness of the buffer region 10 may be 1 μm or more and 10 μm or less. In this form, the buffer region 10 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0026] The SiC semiconductor device 1 includes an active region 11 set on the first main surface 3. The active region 11 is a region where a MISFET as a functional device is formed. In this form, only one active region 11 is set on the first main surface 3. That is, the SiC semiconductor device 1 consists of a discrete device including a single active region 11 in this form.

[0027] The active region 11 is set at the central portion of the first main surface 3 at a distance inward from the first to fourth side surfaces 5A to 5D. The active region 11 is set in a polygonal shape having four sides parallel to the first to fourth side surfaces 5A to 5D. In this form, the active region 11 has a concave portion 11a recessed toward the inner portion of the first main surface 3 at the central portion of the side along the first side surface 5A in plan view.

[0028] The SiC semiconductor device 1 includes an outer region 12 set on the first main surface 3. The outer region 12 is a region where no functional device is formed and is set outside the active region 11. The outer region 12 includes an annular region 12a and a pad region 12b. The annular region 12a extends in a strip shape along the first to fourth side surfaces 5A to 5D in plan view and is set in an annular shape (specifically, a square annular shape) surrounding the active region 11. The pad region 12b protrudes convexly toward the active region 11 from a portion along the first side surface 5A in the annular region 12a so as to be aligned with the concave portion 11a of the active region 11.

[0029] The SiC semiconductor device 1 includes a p-type (second conductivity type) body region 21 formed in the surface layer portion of the first main surface 3 in the active region 11. The body region 21 forms a part of the body diode of the MISFET. The p-type impurity concentration of the body region 21 is 1.0×10 16 cm -3 or more and may be 1.0×10 18 cm -3 or less.

[0030] The body region 21 is specifically formed in the surface layer portion of the drift region 7 throughout the entire active region 11. More specifically, the body region 21 is formed in the surface layer portion of the high-concentration region 9 and faces the drain region 6 (buffer region 10) across a part of the drift region 7. The body region 21 may also be formed in the surface layer portion of the first main surface 3 in the pad region 12b of the outer region 12.

[0031] The SiC semiconductor device 1 includes an n-type source region 22 formed in the surface layer portion of the body region 21. The source region 22 forms the source of the MISFET. The source region 22 has an n-type impurity concentration exceeding the n-type impurity concentration of the drift region 7 (high-concentration region 9). The n-type impurity concentration of the source region 22 is 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0032] The source region 22 is formed at an interval inward from the periphery of the body region 21 in a plan view. The source region 22 is formed at an interval from the bottom of the body region 21 toward the first main surface 3 side. The source region 22 forms the drift region 7 (high-concentration region 9) and the channel of the MISFET within the body region 21.

[0033] The SiC semiconductor device 1 includes a trench-insulated gate type MISFET formed on the first main surface 3 in the active region 11. Specifically, the SiC semiconductor device 1 includes a plurality of trench gate structures 23 formed on the first main surface 3. The plurality of trench gate structures 23 form the gate of the MISFET. The plurality of trench gate structures 23 are each formed in a strip shape (rectangular shape) extending in the first direction X in a plan view and are formed at intervals in the second direction Y.

[0034] As a result, the plurality of trench gate structures 23 are formed in a stripe shape extending in the first direction X in plan view. The plurality of trench gate structures 23 demarcate a plurality of mesa portions 24 in a stepped shape, each extending in the first direction X, on the first main surface 3 in the active region 11. That is, the plurality of trench gate structures 23 are formed alternately with the plurality of mesa portions 24 in the second direction Y in a manner of sandwiching one mesa portion 24.

[0035] Preferably, the plurality of trench gate structures 23 extend in the first direction X so as to cross a line passing through the central portion of the first main surface 3 in the second direction Y in plan view. Both end portions of the plurality of trench gate structures 23 in the first direction X are preferably located between the periphery of the body region 21 and the periphery of the source region 22 in plan view.

[0036] The plurality of trench gate structures 23 each have a first width W1. The first width W1 is the width in a direction orthogonal to the direction in which each trench gate structure 23 extends (that is, the second direction Y). The first width W1 may be 0.1 μm or more and 3 μm or less. Preferably, the first width W1 is 0.5 μm or more and 1.5 μm or less.

[0037] The plurality of trench gate structures 23 are formed with a first interval P1 in the second direction Y. The first interval P1 is the distance between two adjacent trench gate structures 23 in the second direction Y. Preferably, the first interval P1 exceeds the first width W1 (W1 < P1). The first interval P1 may be 0.4 μm or more and 5 μm or less. Preferably, the first interval P1 is 0.8 μm or more and 3 μm or less.

[0038] Each trench gate structure 23 has a first depth D1. The first depth D1 may be 0.1 μm or more and 3 μm or less. Preferably, the first depth D1 is 0.5 μm or more and 2 μm or less. The aspect ratio D1 / W1 of each trench gate structure 23 is preferably 1 or more and 5 or less. The aspect ratio D1 / W1 is the ratio of the first depth D1 to the first width W1. Particularly preferably, the aspect ratio D1 / W1 is 1.5 or more.

[0039] Each trench gate structure 23 includes side walls and a bottom wall. The portion forming the long side among the side walls of each trench gate structure 23 is formed by the a-plane of the SiC single crystal. The portion forming the short side among the side walls of each trench gate structure 23 is formed by the m-plane of the SiC single crystal. The bottom wall of each trench gate structure 23 is formed by the c-plane of the SiC single crystal.

[0040] Each trench gate structure 23 may be formed in a vertical shape having a substantially constant opening width. Each trench gate structure 23 may be formed in a tapered shape having an opening width that narrows toward the bottom wall. The bottom wall of each trench gate structure 23 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each trench gate structure 23 may have a flat surface parallel to the first main surface 3.

[0041] Each trench gate structure 23 is formed on the first main surface 3 so as to reach the drift region 7 across the body region 21 and the source region 22. Specifically, each trench gate structure 23 is formed at a distance from the bottom of the drift region 7 toward the first main surface 3 side, and faces the drain region 6 (buffer region 10) with a part of the drift region 7 interposed therebetween. In this form, each trench gate structure 23 is formed in the high-concentration region 9 and faces the low-concentration region 8 with a part of the high-concentration region 9 interposed therebetween. The side walls of each trench gate structure 23 are in contact with the drift region 7, the body region 21, and the source region 22. The bottom wall of each trench gate structure 23 is in contact with the drift region 7.

[0042] The plurality of trench gate structures 23 each include a gate trench 25, a gate insulating film 26, and a gate electrode 27. Hereinafter, one trench gate structure 23 will be described. The gate trench 25 forms the side walls and the bottom wall of the trench gate structure 23. Hereinafter, the side walls and the bottom wall of the gate trench 25 may be collectively referred to as the "wall surface (inner wall and outer wall)".

[0043] The opening edge portion of the gate trench 25 slopes obliquely downward from the first main surface 3 toward the gate trench 25. The opening edge portion is the connecting portion between the first main surface 3 and the side wall of the gate trench 25. In this form, the opening edge portion is formed in a curved shape that is recessed toward the SiC chip 2. The opening edge portion may be formed in a curved shape that curves inward toward the inside of the gate trench 25.

[0044] The gate insulating film 26 is formed in a film shape on the inner wall of the gate trench 25 and partitions a recessed space within the gate trench 25. The gate insulating film 26 covers the drift region 7, the body region 21, and the source region 22 on the inner wall of the gate trench 25. The gate insulating film 26 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the gate insulating film 26 has a single-layer structure made of a silicon oxide film.

[0045] The gate insulating film 26 includes a first portion 28, a second portion 29, and a third portion 30. The first portion 28 covers the side wall of the gate trench 25. The second portion 29 covers the bottom wall of the gate trench 25. The third portion 30 covers the opening edge portion. In this form, the third portion 30 bulges in a curved shape toward the inside of the gate trench 25 at the opening edge portion.

[0046] The thickness of the first portion 28 may be 10 nm or more and 100 nm or less. The second portion 29 may have a thickness exceeding that of the first portion 28. The thickness of the second portion 29 may be 50 nm or more and 200 nm or less. The third portion 30 has a thickness exceeding that of the first portion 28. The thickness of the third portion 30 may be 50 nm or more and 200 nm or less. Of course, a gate insulating film 26 having a uniform thickness may be formed.

[0047] The gate electrode 27 is embedded in the gate trench 25 with the gate insulating film 26 interposed therebetween. A gate potential is applied to the gate electrode 27. The gate electrode 27 controls the on / off of the channel formed in the body region 21. The gate electrode 27 is preferably made of conductive polysilicon. In this form, the gate electrode 27 contains n-type polysilicon doped with n-type impurities.

[0048] The gate electrode 27 faces the drift region 7, the body region 21, and the source region 22 with the gate insulating film 26 interposed therebetween. The gate electrode 27 has an electrode surface exposed from the gate trench 25. The electrode surface of the gate electrode 27 is formed in a curved shape recessed toward the bottom wall of the gate trench 25 and is narrowed by the third portion 30 of the gate insulating film 26.

[0049] The SiC semiconductor device 1 includes a plurality of trench source structures 33 formed on the first main surface 3 in the active region 11. The plurality of trench source structures 33 are respectively formed at intervals from each trench gate structure 23 in the region (i.e., the mesa portion 24) between two adjacent trench gate structures 23 on the first main surface 3. It is preferable that three or more trench source structures 33 are formed in each mesa portion 24.

[0050] Specifically, the plurality of trench source structures 33 are respectively formed in a strip shape extending in the first direction X in each mesa portion 24 and are formed at intervals in the first direction X. That is, the plurality of trench source structures 33 face each other in a direction (specifically, orthogonal) intersecting the facing direction of two adjacent trench gate structures 23. In other words, two adjacent trench gate structures 23 face each other in the second direction Y, while two adjacent trench source structures 33 face each other in the first direction X.

[0051] The plurality of trench source structures 33 formed in each mesa portion 24 face the plurality of trench source structures 33 formed in the adjacent mesa portion 24 with a one-to-one correspondence across one trench gate structure 23. That is, the plurality of trench source structures 33 are arranged in a matrix at intervals in the first direction X and the second direction Y as a whole in a plan view. Each trench source structure 33 is formed in a rectangular shape in a plan view. Specifically, each trench source structure 33 is formed in a rectangular shape (strip shape) extending in the first direction X in a plan view.

[0052] The plurality of trench source structures 33 each have a second width W2. The second width W2 is the width in the direction orthogonal to the direction in which each trench source structure 33 extends (that is, the second direction Y). The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less. The second width W2 may exceed the first width W1 (W1 < W2), or may be less than or equal to the first width W1 (W1 ≥ W2). In this form, the second width W2 is substantially equal to the first width W1. The second width W2 preferably has a value within the range of ±10% of the value of the first width W1.

[0053] The plurality of trench source structures 33 each have a trench length L. The trench length L is the length in the direction in which each trench source structure 33 extends (that is, the first direction X). The trench length L is arbitrary and is adjusted according to the length of each mesa portion 24 and the number of trench source structures 33 formed in each mesa portion 24.

[0054] The trench length L may be equal to or greater than the second width W2 and equal to or less than 10 times the second width W2 (W2 ≤ L ≤ 10×W2). The trench length L is preferably equal to or less than 5 times the second width W2 (L ≤ 5×W2). The trench length L may be equal to or greater than the first interval P1 (P1 ≤ L), or may be less than the first interval P1 (P1 > L). In this form, the trench length L exceeds the first interval P1 and is equal to or less than 2 times the first interval P1 (P1 < L ≤ 2×P1).

[0055] Each trench source structure 33 has a second depth D2. The second depth D2 is preferably 1.5 times or more and 3 times or less the first depth D1 of the trench gate structure 23. The second depth D2 may be 0.5 μm or more and 10 μm or less. The second depth D2 is preferably 5 μm or less. The aspect ratio D2 / W2 of each trench source structure 33 is preferably 1 or more and 5 or less. The aspect ratio D2 / W2 is particularly preferably 2 or more. The aspect ratio D2 / W2 is the ratio of the second depth D2 to the second width W2. Of course, the second depth D2 may be approximately equal to the first depth D1 of the trench gate structure 23.

[0056] The plurality of trench source structures 33 are formed in each mesa portion 24 with a second interval P2 in the first direction X. The second interval P2 is the distance between two adjacent trench source structures 33 in the first direction X. The second interval P2 may be equal to or less than the first interval P1 (P2 ≦ P1). The second interval P2 is preferably less than the first interval P1 (P2 < P1). The second interval P2 is particularly preferably 1 / 4 or more of the first interval P1 (1 / 4×P1 ≦ P2).

[0057] The second interval P2 may be equal to or greater than the first width W1 of each trench gate structure 23 (W1 ≦ P2), or less than the first width W1 (W1 > P2). The second interval P2 may be equal to or greater than the second width W2 of each trench source structure 33 (W2 ≦ P2), or less than the second width W2 (W1 > P2). The second interval P2 may be equal to or less than the trench length L (P2 ≦ L). The second interval P2 is preferably less than the trench length L (P2 < L). The second interval P2 may be 0.4 μm or more and 5 μm or less. The second interval P2 is preferably 0.8 μm or more and 3 μm or less.

[0058] A plurality of trench source structures 33 are formed with a third interval P3 therebetween in the second direction Y. The third interval P3 is the distance between two trench source structures 33 adjacent in the second direction Y. The third interval P3 may be 0.4 μm or more and 5 μm or less. Preferably, the third interval P3 is 0.8 μm or more and 3 μm or less. The third interval P3 may exceed the first interval P1 (P1 < P3), or may be less than or equal to the first interval P1 (P1 ≥ P3).

[0059] In each mesa portion 24, the plurality of trench source structures 33 partition a plurality of segment portions 34, each of which is formed from a part of each mesa portion 24. In this form, the plurality of segment portions 34 include a plurality of first segment portions 34A and a plurality of second segment portions 34B that are alternately arranged along the first direction X in each mesa portion 24. The plurality of first segment portions 34A are regions where a semiconductor region is formed, and the plurality of second segment portions 34B are regions where a semiconductor region different from the plurality of first segment portions 34A is formed.

[0060] The plurality of first segment portions 34A partitioned in each mesa portion 24 face each other in the second direction Y in a one-to-one correspondence with the plurality of first segment portions 34A partitioned in an adjacent mesa portion 24 with one trench gate structure 23 therebetween. The plurality of second segment portions 34B partitioned in each mesa portion 24 face each other in the second direction Y in a one-to-one correspondence with the plurality of second segment portions 34B partitioned in an adjacent mesa portion 24 with one trench gate structure 23 therebetween.

[0061] Each trench source structure 33 includes side walls and a bottom wall. The portion of the side wall of each trench source structure 33 that extends in the first direction X (the portion forming the long side) is formed by the a-plane of the SiC single crystal. The portion of the side wall of each trench source structure 33 that extends in the second direction Y (the portion forming the short side) is formed by the m-plane of the SiC single crystal. The bottom wall of each trench source structure 33 is formed by the c-plane of the SiC single crystal.

[0062] Each trench source structure 33 may be formed in a vertical shape having a substantially constant opening width. Each trench source structure 33 may be formed in a tapered shape having an opening width that narrows toward the bottom wall. The bottom wall of each trench source structure 33 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each trench source structure 33 may have a flat surface parallel to the first main surface 3.

[0063] Each trench source structure 33 is formed on the first main surface 3 so as to cross the body region 21 and the source region 22 and reach the drift region 7. Specifically, each trench source structure 33 is formed at a distance from the bottom of the drift region 7 toward the first main surface 3 side, and faces the drain region 6 (buffer region 10) with a part of the drift region 7 interposed therebetween. In this form, each trench source structure 33 is formed in the high-concentration region 9 and faces the low-concentration region 8 with a part of the high-concentration region 9 interposed therebetween.

[0064] The side walls of each trench source structure 33 are in contact with the drift region 7, the body region 21, and the source region 22. The bottom wall of each trench source structure 33 is in contact with the drift region 7. In this form, each trench source structure 33 is formed deeper than each trench gate structure 23. That is, the bottom wall of each trench source structure 33 is located on the bottom side of the drift region 7 (high-concentration region 9) with respect to the bottom wall of each trench gate structure 23.

[0065] The plurality of trench source structures 33 each include a source trench 35, a source insulating film 36, and a source electrode 37. Hereinafter, one trench source structure 33 will be described. The source trench 35 forms the side wall and the bottom wall of the trench source structure 33. Hereinafter, the side wall and the bottom wall of the source trench 35 may be collectively referred to as the "wall surface (inner wall and outer wall)".

[0066] The opening edge portion of the source trench 35 slopes obliquely downward from the first main surface 3 toward the source trench 35. The opening edge portion is the connecting portion of the first main surface 3 and the side wall of the source trench 35. In this form, the opening edge portion is formed in a curved shape that is recessed toward the SiC chip 2. The opening edge portion may be formed in a curved shape that curves inwardly of the source trench 35.

[0067] The source insulating film 36 is formed in a film shape on the inner wall of the source trench 35 and partitions a recessed space within the source trench 35. The source insulating film 36 covers the drift region 7, the body region 21, and the source region 22 on the inner wall of the source trench 35. The source insulating film 36 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the source insulating film 36 has a single-layer structure made of a silicon oxide film.

[0068] The source insulating film 36 includes a first portion 38, a second portion 39, and a third portion 40. The first portion 38 covers the side wall of the source trench 35. The second portion 39 covers the bottom wall of the source trench 35. The third portion 40 covers the opening edge portion. In this form, the third portion 40 bulges in a curved shape inwardly of the source trench 35 at the opening edge portion.

[0069] The thickness of the first portion 38 may be 10 nm or more and 100 nm or less. The second portion 39 may have a thickness exceeding the thickness of the first portion 38. The thickness of the second portion 39 may be 50 nm or more and 200 nm or less. The third portion 40 has a thickness exceeding the thickness of the first portion 38. The thickness of the third portion 40 may be 50 nm or more and 200 nm or less. Of course, a source insulating film 36 having a uniform thickness may be formed.

[0070] The source electrode 37 is embedded in the source trench 35 with the source insulating film 36 interposed therebetween. A source potential (for example, a reference potential) is applied to the source electrode 37. The source electrode 37 is preferably made of the same material as the gate electrode 27. That is, the source electrode 37 is preferably made of conductive polysilicon. In this form, the source electrode 37 includes n-type polysilicon doped with n-type impurities.

[0071] The source electrode 37 faces the drift region 7, the body region 21, and the source region 22 with the source insulating film 36 interposed therebetween. A source potential is applied to the source electrode 37. The source electrode 37 has an electrode surface exposed from the source trench 35. The electrode surface of the source electrode 37 is formed in a curved shape recessed toward the bottom wall of the source trench 35 and is narrowed by the third portion 30 of the source insulating film 36.

[0072] The SiC semiconductor device 1 includes a plurality of p-type body connection regions 51 formed in a region partitioned by two adjacent trench source structures 33 in the surface layer portion of the body region 21. Each body connection region 51 has a p-type impurity concentration exceeding the p-type impurity concentration of the body region 21. The p-type impurity concentration of each body connection region 51 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0073] The plurality of body connection regions 51 are each electrically connected to the body region 21. Specifically, the plurality of body connection regions 51 are formed in the surface layer portion of the body region 21 in a plurality of first segment portions 34A. Each body connection region 51 is formed in each first segment portion 34A in such a manner that the n-type impurities in the source region 22 are offset by p-type impurities and is electrically connected to the body region 21.

[0074] Each body connection region 51 is preferably in contact with at least one trench source structure 33 close to the first direction X. In this form, each body connection region 51 is in contact with the side walls of two trench source structures 33 close to the first direction X. That is, in each first segment portion 34A, each body connection region 51 faces the source electrode 37 with the source insulating film 36 of one trench source structure 33 interposed therebetween, and faces the source electrode 37 with the source insulating film 36 of the other trench source structure 33 interposed therebetween. Each body connection region 51 is formed at a distance from the bottom walls of two trench source structures 33 close to the first direction X toward the first main surface 3 side. Specifically, each body connection region 51 is formed at a distance from the middle portion in the depth direction of each trench source structure 33 toward the first main surface 3 side.

[0075] Each body connection region 51 is formed wider than the trench source structure 33 in plan view and projects toward one or both of the trench gate structures 23 located on both sides. In this form, each body connection region 51 is formed over the entire area of each first segment portion 34A in plan view and projects toward one trench gate structure 23 and the other trench gate structure 23.

[0076] Each body connection region 51 is formed at a distance inward from two trench gate structures 23 close to each other with respect to the second direction Y so as to expose a part of the source region 22 from the first main surface 3 in plan view. In this form, each body connection region 51 is formed at a distance from a plurality of adjacent second segment portions 34B toward the first segment portion 34A side. Therefore, each body connection region 51 exposes the entire area of the plurality of second segment portions 34B.

[0077] Each body connection region 51 has a third width W3 in the second direction Y. The third width W3 is less than the first interval P1 of the plurality of trench gate structures 23 (W3 < P1). The third width W3 is preferably equal to or greater than the second width W2 of each trench source structure 33 (W2 ≤ W3). Of course, the third width W3 may be less than the second width W2 (W2 > W3).

[0078] The SiC semiconductor device 1 includes a plurality of n-type source connection regions 52 formed in a region partitioned by two trench source structures 33 that are adjacent to each other in a region different from the body connection region 51 in the surface layer portion of the body region 21. Each source connection region 52 has an n-type impurity concentration exceeding the n-type impurity concentration of the drift region 7 (high-concentration region 9). The n-type impurity concentration of each source connection region 52 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less.

[0079] The plurality of source connection regions 52 are each electrically connected to the source region 22. Specifically, the plurality of source connection regions 52 are formed in the second segment portion 34B. That is, the plurality of source connection regions 52 are formed in a segment portion 34 different from the plurality of body connection regions 51. Also, the plurality of source connection regions 52 are alternately formed in each mesa portion 24 with the plurality of body connection regions 51 and the plurality of trench source structures 33 interposed therebetween.

[0080] In this form, each source connection region 52 is formed over the entire area of each second segment portion 34B in plan view. In each second segment portion 34B, each source connection region 52 faces the source electrode 37 with the source insulating film 36 of the trench source structure 33 on one side interposed therebetween and also faces the source electrode 37 with the source insulating film 36 of the trench source structure 33 on the other side interposed therebetween. Also, each source connection region 52 faces each body connection region 51 in the first direction X with the trench source structure 33 interposed therebetween.

[0081] In this form, each source connection region 52 is formed by using a part of the source region 22. Therefore, each source connection region 52 has an n-type impurity concentration substantially equal to that of the source region 22. Of course, each source connection region 52 may have an n-type impurity concentration exceeding that of the source region 22. Each source connection region 52 may partially contain p-type impurities compensated by n-type impurities and may have an n-type impurity concentration exceeding that of the n-type impurity concentration in the drift region 7 (high-concentration region 9) as a whole. In this case, the n-type impurity concentration of each source connection region 52 may be less than the n-type impurity concentration of the source region 22.

[0082] As described above, in a cross-section cutting each mesa portion 24 in the first direction X, a plurality of trench source structures 33, a plurality of body connection regions 51, and a plurality of source connection regions 52 are formed side by side in the first direction X. Also, in a cross-section cutting the first segment portion 34A in the second direction Y, a plurality of trench gate structures 23, a plurality of body connection regions 51, and a plurality of source regions 22 are formed side by side in the second direction Y.

[0083] Also, in a cross-section cutting the second segment portion 34B in the second direction Y, a plurality of trench gate structures 23, a plurality of source connection regions 52, and a plurality of source regions 22 are formed side by side in the second direction Y. That is, the SiC semiconductor device 1 does not have a body connection region 51 and a source connection region 52 adjacent in the direction (i.e., the second direction Y) intersecting each trench source structure 33 in each mesa portion 24.

[0084] In other words, the plurality of source connection regions 52 are separately arranged from the plurality of body connection regions 51 by the plurality of trench source structures 33 and do not have a portion directly connected to the plurality of body connection regions 51. The plurality of source connection regions 52 are electrically connected to the plurality of body connection regions 51 via the source region 22.

[0085] The SiC semiconductor device 1 includes a plurality of p-type trench connection regions 53 formed in a region along the wall surfaces of a plurality of trench source structures 33 in the drift region 7. Each trench connection region 53 has a p-type impurity concentration exceeding the p-type impurity concentration of the body region 21. The p-type impurity concentration of each trench connection region 53 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0086] The plurality of trench connection regions 53 are each electrically connected to a plurality of body connection regions 51. Specifically, each trench connection region 53 is composed of a region drawn from each body connection region 51 to the wall surface of the adjacent trench source structure 33. In this form, two trench connection regions 53 are drawn from each body connection region 51 toward the wall surface of the trench source structure 33 on one side and the wall surface of the trench source structure 33 on the other side. That is, each trench connection region 53 has a p-type impurity concentration substantially equal to the p-type impurity concentration of each body connection region 51. Also, the plurality of trench connection regions 53 are each formed in a one-to-one correspondence with the plurality of trench source structures 33 in a plan view.

[0087] In this form, each trench connection region 53 extends in the first direction X so as to cross the middle portion of the trench source structure 33 in a plan view. Each trench connection region 53 partially covers the wall surface of the trench source structure 33 so as to expose a part of the wall surface of the trench source structure 33. Specifically, each trench connection region 53 is formed at an interval from each second segment portion 34B toward each first segment portion 34A.

[0088] Therefore, each trench connection region 53 exposes the end portions (side walls and bottom wall) on the second segment portion 34B side of the trench source structure 33. Also, each trench connection region 53 exposes the source connection region 52 (second segment portion 34B). Each trench connection region 53 is formed with a space inward from two adjacent trench gate structures 23 so as to expose a part of the source region 22 from the first main surface 3 in the second direction Y.

[0089] Each trench connection region 53 covers the side walls and the bottom wall of each trench source structure 33 in the drift region 7. Each trench connection region 53 is connected to the body connection region 51 at a portion of the side wall of each trench source structure 33 that partitions the first segment portion 34A.

[0090] The bottom of each trench connection region 53 is formed with a space from the bottom of the drift region 7 toward the first main surface 3 side, and faces the drain region 6 (buffer region 10) with a part of the drift region 7 interposed therebetween. In this form, each trench connection region 53 is formed in the high-concentration region 9 and faces the low-concentration region 8 with a part of the high-concentration region 9 interposed therebetween. Each trench connection region 53 faces the source electrode 37 with the source insulating film 36 interposed therebetween.

[0091] The SiC semiconductor device 1 includes a plurality of p-type well regions 54 respectively formed in regions along the wall surfaces of the plurality of trench source structures 33 in the drift region 7. Each well region 54 has a p-type impurity concentration lower than the p-type impurity concentration of each trench connection region 53. The p-type impurity concentration of each well region 54 may be 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less.

[0092] The plurality of well regions 54 are each formed in a one-to-one correspondence with the plurality of trench source structures 33. Each well region 54 is formed in a strip shape extending along each trench source structure 33 in a plan view. Each well region 54 is formed at a distance from the trench gate structure 23 toward the trench source structure 33 side, exposing the trench gate structure 23.

[0093] Each well region 54 covers the side walls and the bottom wall of each trench source structure 33. Each well region 54 is formed at a distance from the bottom of the drift region 7 (high-concentration region 9) toward the first main surface 3 side, and faces the drain region 6 (buffer region 10) with a part of the drift region 7 interposed therebetween. In this form, each well region 54 is formed in the high-concentration region 9 and faces the low-concentration region 8 with a part of the high-concentration region 9 interposed therebetween.

[0094] Each well region 54 covers the side walls of each trench source structure 33 over the entire circumference of each trench source structure 33. That is, each well region 54 includes portions located in the first segment portion 34A and the second segment portion 34B. Each well region 54 covers each trench source structure 33 with each trench connection region 53 interposed therebetween. That is, each well region 54 includes a portion that directly covers each trench source structure 33 and a portion that covers each trench source structure 33 with each trench connection region 53 interposed therebetween. Each well region 54 is connected to the body region 21 at a portion that covers the side walls of each trench source structure 33.

[0095] Preferably, the thickness of the portion of each well region 54 that covers the bottom wall of each trench source structure 33 exceeds the thickness of the portion of each well region 54 that covers the side walls of each trench source structure 33. The thickness of the portion of each well region 54 that covers the side walls of the trench source structure 33 is the thickness in the normal direction of the side walls of the trench source structure 33. The thickness of the portion of each well region 54 that covers the bottom wall of the trench source structure 33 is the thickness in the normal direction of the bottom wall of the trench source structure 33.

[0096] The portion covering the bottom walls of the plurality of trench source structures 33 in the plurality of well regions 54 is formed at a substantially constant depth. The plurality of well regions 54 form a pn junction with the drift region 7 (high-concentration region 9) and expand the depletion layer toward the trench gate structure 23 (gate trench 25). The plurality of well regions 54 bring the trench-insulated gate type MISFET closer to the structure of a pn junction diode and relax the electric field within the SiC chip 2.

[0097] The plurality of well regions 54 are preferably formed such that the depletion layer overlaps the bottom walls of the adjacent trench gate structures 23. Also, the plurality of well regions 54 are preferably formed such that the depletion layer overlaps the bottom walls of the adjacent trench source structures 33. The high-concentration region 9 intervening between the plurality of well regions 54 reduces the JFET (Junction Field Effect Transistor) resistance. The high-concentration region 9 located directly below the plurality of well regions 54 reduces the current spreading resistance. The low-concentration region 8 increases the breakdown voltage of the SiC chip 2 in such a structure.

[0098] The SiC semiconductor device 1 includes, in the first direction X, a plurality of p-type gate well regions 55 formed in regions along the wall surfaces at both ends of the plurality of trench gate structures 23 in the drift region 7. Each gate well region 55 has a p-type impurity concentration less than the p-type impurity concentration of each trench connection region 53. The p-type impurity concentration of each gate well region 55 may be 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. It is preferable that each gate well region 55 is substantially equal to the p-type impurity concentration of each well region 54.

[0099] The plurality of gate well regions 55 are respectively formed in at least the region between the peripheral portion of the body region 21 and the peripheral portion of the source region 22. Each gate well region 55 is formed in a strip shape extending along each trench gate structure 23 in plan view. Each gate well region 55 is formed at a distance from the trench source structure 33 toward the trench gate structure 23 side, exposing the portion of the trench gate structure 23 along the source region 22.

[0100] Each gate well region 55 covers the side wall and the bottom wall of each trench gate structure 23. Each gate well region 55 is formed at a distance from the bottom of the drift region 7 (high concentration region 9) toward the first main surface 3 side, and faces the drain region 6 (buffer region 10) with a part of the drift region 7 interposed therebetween. In this form, each gate well region 55 is formed in the high concentration region 9 and faces the low concentration region 8 with a part of the high concentration region 9 interposed therebetween. Each gate well region 55 is connected to the body region 21 at the portion covering the side wall of each trench gate structure 23.

[0101] The bottoms of the plurality of gate well regions 55 are located on the bottom wall side of the trench gate structure 23 with respect to the bottoms of the plurality of well regions 54. It is preferable that the thickness of the portion of each gate well region 55 covering the bottom wall of each trench gate structure 23 exceeds the thickness of the portion of each gate well region 55 covering the side wall of each trench gate structure 23. The thickness of the portion of each gate well region 55 covering the side wall of the trench gate structure 23 is the thickness in the normal direction of the side wall of the trench gate structure 23. The thickness of the portion of each gate well region 55 covering the bottom wall of the trench gate structure 23 is the thickness in the normal direction of the bottom wall of the trench gate structure 23.

[0102] The portion covering the bottom walls of the plurality of trench gate structures 23 at the bottoms of the plurality of gate well regions 55 is formed at a substantially constant depth. The plurality of gate well regions 55 form a pn junction with the drift region 7 (high-concentration region 9) and expand the depletion layer toward the trench gate structure 23 and the trench source structure 33. The plurality of gate well regions 55 bring the trench-insulated gate type MISFET closer to the structure of a pn junction diode and relax the electric field in the SiC chip 2.

[0103] The SiC semiconductor device 1 includes an interlayer insulating film 60 covering the first main surface 3. In this form, the interlayer insulating film 60 has a laminated structure including a first insulating film 61 and a second insulating film 62 laminated in this order from the side of the first main surface 3.

[0104] The first insulating film 61 is formed in a film shape along the first main surface 3 and is continuous with the plurality of gate insulating films 26 and the plurality of source insulating films 36. The first insulating film 61 exposes the plurality of gate electrodes 27 and the plurality of source electrodes 37. The first insulating film 61 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the first insulating film 61 includes an NSG (Nondoped Silicate Glass) film as an example of a silicon oxide film. The thickness of the first insulating film 61 may be 10 nm or more and 300 nm or less.

[0105] The second insulating film 62 is formed in a film shape along the first insulating film 61 and selectively covers the plurality of trench gate structures 23 and the plurality of trench source structures 33. The second insulating film 62 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the second insulating film 62 includes a PSG (Phosphor Silicate Glass) film as an example of a silicon oxide film. The thickness of the second insulating film 62 may be 50 nm or more and 500 nm or less. It is preferable that the thickness of the second insulating film 62 exceeds the thickness of the first insulating film 61.

[0106] The interlayer insulating film 60 includes a plurality of gate openings 63, a plurality of first source openings 64, a plurality of second source openings 65, and a plurality of third source openings 66. The gate opening 63 is an opening for the trench gate structure 23. The first source opening 64 is an opening for the trench source structure 33. The second source opening 65 is an opening for the body connection region 51. The third source opening 66 is an opening for the source connection region 52.

[0107] The plurality of gate openings 63 are respectively formed on both end sides of the plurality of trench gate structures 23, and expose the plurality of trench gate structures 23 (specifically, the gate electrodes 27) in a one-to-one correspondence. The planar shape of each gate opening 63 is arbitrary, and each gate opening 63 may be formed in a square shape, a rectangular shape, a circular shape, or the like.

[0108] The plurality of first source openings 64 expose the plurality of trench source structures 33 (specifically, the source electrodes 37) in a one-to-one correspondence. Each first source opening 64 is formed in a region surrounded by the side walls of each trench source structure 33 in a plan view. Specifically, each first source opening 64 is formed at an interval inward from the side walls of each trench source structure 33, and only the source electrode 37 is exposed. The planar shape of each first source opening 64 is arbitrary, and each first source opening 64 may be formed in a square shape, a rectangular shape, a circular shape, or the like.

[0109] The plurality of second source openings 65 expose the plurality of body connection regions 51 in a one-to-one correspondence. Looking at each mesa portion 24, the plurality of second source openings 65 are formed at an interval in the first direction X from the plurality of first source openings 64, and face the plurality of first source openings 64 in the first direction X respectively. The planar shape of each second source opening 65 is arbitrary, and each second source opening 65 may be formed in a square shape, a rectangular shape, a circular shape, or the like.

[0110] The plurality of third source openings 66 expose the plurality of source connection regions 52 in a one-to-one correspondence. Looking at each mesa portion 24, the plurality of third source openings 66 are formed at intervals in the first direction X from the plurality of first source openings 64 and the plurality of second source openings 65, and face the plurality of first source openings 64 and the plurality of second source openings 65 in the first direction X, respectively.

[0111] The planar shape of each third source opening 66 is arbitrary, and each third source opening 66 may be formed in a square shape, a rectangular shape, a circular shape, or the like. Looking at each mesa portion 24, the plurality of first source openings 64, the plurality of second source openings 65, and the plurality of third source openings 66 are arranged at intervals on a line connecting the plurality of trench source structures 33 in the first direction X in a plan view.

[0112] The SiC semiconductor device 1 includes a gate main surface electrode 71 disposed on the interlayer insulating film 60. The gate main surface electrode 71 is an external terminal externally connected to a conducting wire (for example, a bonding wire), and a gate potential is applied to the gate main surface electrode 71. The gate main surface electrode 71 is electrically connected to the plurality of trench gate structures 23 (gate electrodes 27) and transmits the input gate potential (gate signal) to the plurality of trench gate structures 23 (gate electrodes 27).

[0113] The gate potential may be 10 V or more and 50 V or less (for example, about 30 V). The gate main surface electrode 71 is disposed on the pad region 12b. The gate main surface electrode 71 faces the pad region 12b with the interlayer insulating film 60 interposed therebetween. In this form, the gate main surface electrode 71 is formed in a rectangular shape having four sides parallel to the first main surface 3 in a plan view.

[0114] The SiC semiconductor device 1 includes a gate wiring electrode 72 drawn from the gate main surface electrode 71 onto the interlayer insulating film 60. The gate wiring electrode 72 transmits the gate potential applied to the gate main surface electrode 71 to other regions. The gate wiring electrode 72 extends in a strip shape so as to partition the active region 11 from a plurality of directions in plan view. In this form, the gate wiring electrode 72 extends in a strip shape along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D so as to partition the active region 11 from three directions in plan view.

[0115] The gate wiring electrode 72 intersects (specifically, is orthogonal to) both ends of a plurality of trench gate structures 23 in plan view. The gate wiring electrode 72 enters a plurality of gate openings 63 from above the interlayer insulating film 60 and is electrically connected to a plurality of gate electrodes 27. Thereby, the gate potential applied to the gate main surface electrode 71 is transmitted to a plurality of trench gate structures 23 via the gate wiring electrode 72.

[0116] The SiC semiconductor device 1 includes a source main surface electrode 73 disposed on the interlayer insulating film 60 at a distance from the gate main surface electrode 71 and the gate wiring electrode 72. The source main surface electrode 73 is an external terminal externally connected to a conducting wire (for example, a bonding wire), and a source potential is applied to the source main surface electrode 73.

[0117] The source main surface electrode 73 is electrically connected to a plurality of trench source structures 33 (source electrodes 37), a plurality of body connection regions 51, and a plurality of source connection regions 52, and transmits the input source potential to the plurality of trench source structures 33 (source electrodes 37), the plurality of body connection regions 51, and the plurality of source connection regions 52. The source potential may be a reference potential (for example, a ground potential).

[0118] Specifically, the source main surface electrode 73 is disposed in a region partitioned by the gate main surface electrode 71 and the gate wiring electrode 72 in the interlayer insulating film 60 and faces the active region 11. In this form, the source main surface electrode 73 has a concave portion 73a that is recessed from the central portion of the side along the first side surface 5A toward the inner portion so as to be aligned with the gate main surface electrode 71 in a plan view. The source main surface electrode 73 faces all of the plurality of trench gate structures 23 and all of the plurality of trench source structures 33.

[0119] The source main surface electrode 73 enters the plurality of first source openings 64, the plurality of second source openings 65, and the plurality of third source openings 66 from above the interlayer insulating film 60 and is electrically connected to the plurality of source electrodes 37, the plurality of body connection regions 51, and the plurality of source connection regions 52. Thereby, the source potential applied to the source main surface electrode 73 is transmitted to the plurality of source electrodes 37, the plurality of body connection regions 51, and the plurality of source connection regions 52.

[0120] The source potential is transmitted to the body region 21, the source region 22, the plurality of trench connection regions 53, the plurality of well regions 54, and the plurality of gate well regions 55 through the plurality of body connection regions 51 and the plurality of source connection regions 52. Looking at each mesa portion 24, the source main surface electrode 73 is electrically connected to the plurality of trench source structures 33, the plurality of body connection regions 51, and the plurality of source connection regions 52 on a line connecting the plurality of trench source structures 33 in the first direction X.

[0121] The gate main surface electrode 71, the gate wiring electrode 72, and the source main surface electrode 73 each have a stacked structure including a first electrode film 74 and a second electrode film 75 stacked in this order from the side of the interlayer insulating film 60.

[0122] The first electrode film 74 is formed in a film shape along the interlayer insulating film 60. In this form, the first electrode film 74 is made of a Ti-based metal film. The first electrode film 74 includes at least one of a titanium film and a titanium nitride film. The first electrode film 74 may have a single-layer structure composed of a titanium film or a titanium nitride film. In this form, the first electrode film 74 has a laminated structure including a titanium film and a titanium nitride film laminated in this order from the side of the first main surface 3.

[0123] The second electrode film 75 is formed in a film shape along the main surface of the first electrode film 74. The first electrode film 74 is made of a Cu-based metal film or an Al-based metal film. The first electrode film 74 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this form, the first electrode film 74 has a single-layer structure composed of an AlCu alloy film.

[0124] The SiC semiconductor device 1 includes a top insulating film 80 that selectively covers the gate main surface electrode 71, the gate wiring electrode 72, and the source main surface electrode 73 on the interlayer insulating film 60. The top insulating film 80 has a first pad opening 81 that covers the entire area of the gate wiring electrode 72 and exposes the gate main surface electrode 71, and a second pad opening 82 that exposes the source main surface electrode 73.

[0125] The planar shape of the first pad opening 81 and the planar shape of the second pad opening 82 are arbitrary. The top insulating film 80 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and partitions a dicing street 83 that exposes the interlayer insulating film 60 between the first to fourth side surfaces 5A to 5D. The width of the dicing street 83 may be 1 μm or more and 50 μm or less. The width of the dicing street 83 is the width in a direction orthogonal to the direction in which the dicing street 83 extends.

[0126] In this form, the uppermost insulating film 80 has a laminated structure including an inorganic insulating film 84 and an organic insulating film 85 laminated in this order from the interlayer insulating film 60 side. The inorganic insulating film 84 is made of an inorganic insulator having a relatively high density and has a barrier property (shielding property) against moisture (humidity). The inorganic insulating film 84 shields moisture (humidity) from the outside and protects the SiC chip 2, the gate main surface electrode 71, the gate wiring electrode 72, the source main surface electrode 73, etc. from undesired oxidation. The inorganic insulating film 84 may be referred to as a passivation film.

[0127] The inorganic insulating film 84 may have a laminated structure including a plurality of insulating films or may have a single-layer structure composed of a single insulating film. The inorganic insulating film 84 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 84 may have a laminated structure including a plurality of silicon oxide films, a laminated structure including a plurality of silicon nitride films, or a laminated structure including a plurality of silicon oxynitride films.

[0128] The inorganic insulating film 84 may have a laminated structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are laminated in an arbitrary order. The inorganic insulating film 84 may have a single-layer structure composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this form, the inorganic insulating film 84 has a single-layer structure composed of a silicon nitride film. That is, the inorganic insulating film 84 is made of an insulator different from the interlayer insulating film 60. The thickness of the inorganic insulating film 84 may be 0.1 μm or more and 5 μm or less. The thickness of the inorganic insulating film 84 is preferably 1 μm or more and 3 μm or less.

[0129] The organic insulating film 85 has a hardness lower than that of the inorganic insulating film 84. In other words, the organic insulating film 85 has a modulus of elasticity smaller than that of the inorganic insulating film 84 and functions as a buffer material against external forces. The organic insulating film 85 protects the SiC chip 2, the gate main surface electrode 71, the gate wiring electrode 72, the source main surface electrode 73, etc. from external forces.

[0130] The organic insulating film 85 preferably contains a photosensitive resin. The photosensitive resin may be of a negative type or a positive type. The organic insulating film 85 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this form, the organic insulating film 85 contains a polybenzoxazole film. The thickness of the organic insulating film 85 may be 1 μm or more and 50 μm or less. The thickness of the organic insulating film 85 preferably exceeds the thickness of the inorganic insulating film 84. The thickness of the organic insulating film 85 is preferably 5 μm or more and 20 μm or less.

[0131] The SiC semiconductor device 1 includes a drain electrode 91 that covers the second main surface 4. The drain electrode 91 covers the entire area of the second main surface 4 and is continuous with the first to fourth side surfaces 5A to 5D. The drain electrode 91 is electrically connected to the drain region 6 (second main surface 4). Specifically, the drain electrode 91 forms an ohmic contact with the drain region 6 (second main surface 4).

[0132] In this form, the drain electrode 91 includes a Ti film 92, a Ni film 93, a Pd film 94, an Au film 95, and an Ag film 96 laminated in this order from the second main surface 4 side. The drain electrode 91 only needs to include at least the Ti film 92, and the presence or absence of the Ni film 93, the Pd film 94, the Au film 95, and the Ag film 96 is arbitrary respectively. As an example, the drain electrode 91 may have a laminated structure including the Ti film 92, the Ni film 93, and the Au film 95.

[0133] As described above, the SiC semiconductor device 1 includes an SiC chip 2 (semiconductor chip), an n-type drift region 7, a p-type body region 21, an n-type source region 22, a plurality of trench source structures 33, a p-type body connection region 51, and an n-type source connection region 52. The SiC chip 2 has a first main surface 3. The drift region 7 is formed in the surface layer portion of the first main surface 3. The body region 21 is formed in the surface layer portion of the drift region 7. The source region 22 is formed in the surface layer portion of the body region 21.

[0134] A plurality of trench source structures 33 are formed on the first main surface 3 so as to cross the source region 22 and the body region 21 and reach the drift region 7, and are arranged on the first main surface 3 at intervals in the first direction X. The body connection region 51 is formed in a region between two adjacent trench source structures 33 in the surface layer portion of the body region 21 so as to be electrically connected to the body region 21. The source connection region 52 is formed in a region between two adjacent trench source structures 33 in a region different from the body connection region 51 in the surface layer portion of the body region 21 so as to be electrically connected to the source region 22.

[0135] According to this SiC semiconductor device 1, the trench source structure 33, the body connection region 51, and the source connection region 52 are formed side by side in the first direction X. Therefore, it is not necessary to form the body connection region 51 and the source connection region 52 adjacent to each other in the second direction Y intersecting the first direction X.

[0136] Thereby, an increase in size in the second direction Y due to the trench source structure 33, the body connection region 51, and the source connection region 52 can be suppressed. Further, since it is not necessary to make the body connection region 51 and the source connection region 52 adjacent to each other in the second direction Y, the alignment margin of the body connection region 51 and the alignment margin of the source connection region 52 can be relaxed respectively. Therefore, the SiC semiconductor device 1 that can contribute to miniaturization can be provided.

[0137] The source connection region 52 preferably faces the body connection region 51 in the first direction X with the trench source structure 33 interposed therebetween. The plurality of trench source structures 33 are preferably each formed in a strip shape extending in the first direction X.

[0138] The body connection region 51 preferably has a p-type impurity concentration exceeding the p-type impurity concentration of the body region 21. The source region 22 preferably has an n-type impurity concentration exceeding the n-type impurity concentration of the drift region 7. The source connection region 52 preferably has an n-type impurity concentration exceeding the n-type impurity concentration of the drift region 7. The source connection region 52 is preferably formed using a part of the source region 22.

[0139] Preferably, a plurality of body connection regions 51 are formed and a plurality of source connection regions 52 are formed. In this case, the plurality of source connection regions 52 are preferably formed alternately with the plurality of body connection regions 51 along the first direction X. According to this structure, in-plane variations caused by the plurality of body connection regions 51 and the plurality of source connection regions 52 can be suppressed with respect to the electrical characteristics of the MISFET.

[0140] The SiC semiconductor device 1 preferably includes a plurality of trench gate structures 23. The plurality of trench gate structures 23 are formed on the first main surface 3 so as to cross the source region 22 and the body region 21 and reach the drift region 7, extend respectively in the first direction X, and are arranged on the first main surface 3 at intervals in the second direction Y intersecting the first direction X. In this case, the plurality of trench source structures 33 are preferably arranged on the first main surface 3 at intervals in the first direction X between two adjacent trench gate structures 23.

[0141] According to this structure, between two adjacent trench gate structures 23, the trench source structure 33, the body connection region 51, and the source connection region 52 are formed side by side in the first direction X. That is, the body connection region 51 and the source connection region 52 are not adjacent in the second direction Y between two adjacent trench gate structures 23. Thereby, the distance between two adjacent trench gate structures 23 can be narrowed. Therefore, the SiC semiconductor device 1 that can contribute to miniaturization can be provided.

[0142] In this structure, it is preferable that the body connection region 51 is formed at a distance from the plurality of trench gate structures 23. Each trench source structure 33 is preferably formed deeper than each trench gate structure 23. The plurality of trench gate structures 23 are arranged with a first interval P1 in the second direction Y, and the plurality of trench source structures 33 are preferably arranged with a second interval P2 (P2 < P1) less than the first interval P1 in the first direction X.

[0143] Specifically, the plurality of trench gate structures 23 partition a plurality of mesa portions 24 each extending in the first direction X on the first main surface 3. On the other hand, the plurality of trench source structures 33 partition a plurality of segment portions 34 each formed from a part of the mesa portion 24 in the mesa portion 24. In this structure, the body connection region 51 is formed in the segment portion 34, and the source connection region 52 is formed in a segment portion 34 different from the segment portion 34 in which the body connection region 51 is formed. According to this structure, the formation portion of the body connection region 51 can be defined as the segment portion 34, and the formation portion of the source connection region 52 can be defined as the segment portion 34. Therefore, the body connection region 51 and the source connection region 52 can be appropriately formed respectively.

[0144] In this case, it is preferable that the plurality of segment portions 34 include a plurality of first segment portions 34A and a plurality of second segment portions 34B alternately arranged along the first direction X. In this structure, it is preferable that the plurality of body connection regions 51 are formed in the plurality of first segment portions 34A, and the plurality of source connection regions 52 are formed in the plurality of second segment portions 34B. According to this structure, regarding the electrical characteristics of the MISFET, the in-plane variation caused by the plurality of body connection regions 51 and the plurality of source connection regions 52 can be suppressed.

[0145] The SiC semiconductor device 1 preferably includes a p-type trench connection region 53. The trench connection region 53 preferably has a p-type impurity concentration exceeding the p-type impurity concentration of the body region 21. The trench connection region 53 is preferably drawn out from the body connection region 51 along the wall surface of at least one trench source structure 33 in the surface layer portion of the drift region 7.

[0146] According to this structure, the potential (specifically, the source potential) applied to the body connection region 51 can be transmitted to the region on the trench source structure 33 side via the trench connection region 53. The trench connection region 53 preferably covers the side wall and the bottom wall of the trench source structure 33. Further, the trench connection region 53 preferably partially covers the wall surface of the trench source structure 33 so as to expose a part of the wall surface of the trench source structure 33.

[0147] The SiC semiconductor device 1 preferably includes a p-type well region 54. The well region 54 preferably has a p-type impurity concentration less than the p-type impurity concentration of the body connection region 51. The well region 54 is preferably formed in a region along the wall surface of at least one trench source structure 33 so as to cover the trench connection region 53 in the surface layer portion of the drift region 7. According to this structure, the breakdown voltage can be improved by the well region 54. The well region 54 preferably has a portion covering the trench source structure 33 with the trench connection region 53 interposed therebetween and a portion directly covering the trench source structure 33.

[0148] The SiC semiconductor device 1 preferably includes a source main surface electrode 73. The source main surface electrode 73 is formed on the first main surface 3 and is preferably electrically connected to the trench source structure 33, the body connection region 51, and the source connection region 52 on a line connecting the trench source structure 33, the body connection region 51, and the source connection region 52.

[0149] The SiC semiconductor device 1 preferably includes an interlayer insulating film 60. The interlayer insulating film 60 preferably covers the first main surface 3 and has a plurality of openings that expose the trench source structure 33, the body connection region 51, and the source connection region 52. In this case, the source main surface electrode 73 is preferably electrically connected to the trench source structure 33, the body connection region 51, and the source connection region 52 within the plurality of openings.

[0150] In this form, the interlayer insulating film 60 includes a first source opening 64 that exposes the trench source structure 33, a second source opening 65 that exposes the body connection region 51, and a third source opening 66 that exposes the source connection region 52. The source main surface electrode 73 enters the first source opening 64, the second source opening 65, and the third source opening 66 from above the interlayer insulating film 60 and is electrically connected to the trench source structure 33, the body connection region 51, and the source connection region 52.

[0151] From another perspective, the SiC semiconductor device 1 has a structure that contributes to miniaturization. That is, the SiC semiconductor device 1 includes a SiC chip 2 (semiconductor chip), an n-type drift region 7, a p-type body region 21, an n-type source region 22, a plurality of trench gate structures 23, a trench source structure 33, a p-type body connection region 51, and an n-type source connection region 52. The SiC chip 2 has a first main surface 3. The drift region 7 is formed in the surface layer portion of the first main surface 3. The body region 21 is formed in the surface layer portion of the drift region 7. The source region 22 is formed in the surface layer portion of the body region 21.

[0152] A plurality of trench gate structures 23 each extend in a first direction X, are arranged at intervals in a second direction Y intersecting the first direction X, and are formed on a first main surface 3 so as to reach a drift region 7 across a source region 22 and a body region 21. A trench source structure 33 is formed on the first main surface 3 so as to reach the drift region 7 across the source region 22 and the body region 21 between two adjacent trench gate structures 23. The trench source structure 33 has one end on one side in the first direction X and the other end on the other side in the first direction X.

[0153] A body connection region 51 is formed in a region on one end side of the trench source structure 33 in the surface layer portion of the body region 21 so as to be electrically connected to the body region 21. A source connection region 52 is formed in a region on the other end side of the trench source structure 33 in the surface layer portion of the body region 21 so as to be electrically connected to the source region 22.

[0154] According to this structure, between two adjacent trench gate structures 23, a trench source structure 33, a body connection region 51, and a source connection region 52 are formed side by side in the first direction X. That is, the body connection region 51 and the source connection region 52 are not adjacent in the second direction Y in the mesa portion 24. Thereby, the distance between two adjacent trench gate structures 23 can be narrowed. In addition, the alignment margin of the body connection region 51 and the alignment margin of the source connection region 52 can be relaxed respectively. Therefore, the SiC semiconductor device 1 that can contribute to miniaturization can be provided.

[0155] FIG. 11 corresponds to FIG. 4 and is a plan view for explaining the structure of the SiC semiconductor device 101 according to the second embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and the descriptions thereof are omitted.

[0156] Referring to FIG. 11, in this form, the plurality of mesa portions 24 include a plurality of first mesa portions 24A and a plurality of second mesa portions 24B that are alternately arranged in the second direction Y. In each first mesa portion 24A, a plurality of first segment portions 34A and a plurality of second segment portions 34B are alternately arranged along the first direction X.

[0157] In each second mesa portion 24B, a plurality of first segment portions 34A and a plurality of second segment portions 34B are alternately arranged along the first direction X. The plurality of first segment portions 34A of each second mesa portion 24B face the plurality of second segment portions 34B of each first mesa portion 24A in the second direction Y. The plurality of second segment portions 34B of each second mesa portion 24B face the plurality of first segment portions 34A of each first mesa portion 24A in the second direction Y.

[0158] The plurality of body connection regions 51 are formed in regions partitioned by two adjacent trench source structures 33 in the surface layer portion of the body region 21. Specifically, the plurality of body connection regions 51 are respectively formed in the plurality of first segment portions 34A in each first mesa portion 24A and each second mesa portion 24B.

[0159] On the other hand, the source connection region 52 is formed in a region partitioned by two adjacent trench source structures 33 in a region different from the body connection region 51 in the surface layer portion of the body region 21. Specifically, the plurality of source connection regions 52 are respectively formed in the plurality of second segment portions 34B in each first mesa portion 24A and each second mesa portion 24B. That is, the plurality of body connection regions 51 of each second mesa portion 24B face the plurality of source connection regions 52 of each first mesa portion 24A in the second direction Y. Also, the plurality of source connection regions 52 of each second mesa portion 24B face the plurality of body connection regions 51 of each first mesa portion 24A in the second direction Y.

[0160] As described above, the SiC semiconductor device 101 also exhibits the same effects as those described for the SiC semiconductor device 1.

[0161] FIG. 12 corresponds to FIG. 4 and is a plan view for explaining the structure of the SiC semiconductor device 111 according to the third embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and the descriptions thereof are omitted.

[0162] Referring to FIG. 12, in this embodiment, the plurality of mesa portions 24 include a plurality of first mesa portions 24A and a plurality of second mesa portions 24B that are alternately arranged in the second direction Y. In each first mesa portion 24A, a plurality of trench source structures 33 are arranged at intervals in the first direction X. The plurality of trench source structures 33 partition a plurality of segment portions 34 in each first mesa portion 24A. The plurality of segment portions 34 of each first mesa portion 24A include a plurality of first segment portions 34A and a plurality of second segment portions 34B that are alternately arranged along the first direction X.

[0163] In each second mesa portion 24B, a plurality of trench source structures 33 are arranged at intervals in the first direction X. The plurality of trench source structures 33 in each second mesa portion 24B are arranged shifted in the first direction X with respect to the plurality of trench source structures 33 in each first mesa portion 24A so as to face the plurality of segment portions 34 in each first mesa portion 24A in the second direction Y. In this embodiment, the plurality of trench source structures 33 in each second mesa portion 24B are arranged shifted by a half pitch in the first direction X with respect to the plurality of trench source structures 33 in each first mesa portion 24A. That is, the plurality of trench source structures 33 are arranged in a staggered pattern with intervals in the first direction X and the second direction Y as a whole in plan view.

[0164] A plurality of trench source structures 33 partition a plurality of segment portions 34 in each second mesa portion 24B. The plurality of segment portions 34 of each second mesa portion 24B include a plurality of first segment portions 34A and a plurality of second segment portions 34B that are alternately arranged along the first direction X. The plurality of first segment portions 34A of each second mesa portion 24B respectively face the plurality of trench source structures 33 of each first mesa portion 24A in the second direction Y. The plurality of second segment portions 34B of each second mesa portion 24B respectively face the plurality of trench source structures 33 of each first mesa portion 24A in the second direction Y.

[0165] A plurality of body connection regions 51 are formed in regions partitioned by two adjacent trench source structures 33 in the surface layer portion of the body region 21. Specifically, the plurality of body connection regions 51 are respectively formed in the plurality of first segment portions 34A in each first mesa portion 24A and each second mesa portion 24B. That is, the plurality of body connection regions 51 of each first mesa portion 24A face the plurality of trench source structures 33 of each second mesa portion 24B in the second direction Y. Also, the plurality of body connection regions 51 of each second mesa portion 24B face the plurality of trench source structures 33 of each first mesa portion 24A in the second direction Y.

[0166] On the other hand, a plurality of source connection regions 52 are formed in regions partitioned by two adjacent trench source structures 33 in a region different from the body connection region 51 in the surface layer portion of the body region 21. Specifically, the plurality of source connection regions 52 are respectively formed in the plurality of second segment portions 34B in each first mesa portion 24A and each second mesa portion 24B. That is, the plurality of source connection regions 52 of each first mesa portion 24A face the plurality of trench source structures 33 of each second mesa portion 24B in the second direction Y. Also, the plurality of source connection regions 52 of each second mesa portion 24B face the plurality of trench source structures 33 of each first mesa portion 24A in the second direction Y.

[0167] The plurality of trench connection regions 53 are formed in the same manner as in the case of the first embodiment. The plurality of trench connection regions 53 preferably face a plurality of source connection regions 52 (second segment portions 34B) in the second direction Y.

[0168] As described above, the SiC semiconductor device 111 also exhibits the same effects as those described for the SiC semiconductor device 1.

[0169] FIG. 13 corresponds to FIG. 4 and is a plan view for explaining the structure of the SiC semiconductor device 121 according to the fourth embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and the descriptions thereof are omitted.

[0170] Referring to FIG. 13, the plurality of body connection regions 51 are formed in regions partitioned by two trench source structures 33 that are adjacent to each other in the surface layer portion of the body region 21. Specifically, the plurality of body connection regions 51 are respectively formed in the surface layer portion of the body region 21 at intervals from one trench source structure 33 to the other trench source structure 33 side in the plurality of segment portions 34. Each body connection region 51 is in contact with the other trench source structure 33 in the first direction X. That is, each body connection region 51 faces the source electrode 37 with the source insulating film 36 of the other trench source structure 33 interposed therebetween in each segment portion 34.

[0171] On the other hand, the plurality of source connection regions 52 are formed in regions partitioned by two trench source structures 33 that are adjacent to each other in a region different from the body connection region 51 in the surface layer portion of the body region 21. Specifically, each source connection region 52 is formed in the same segment portion 34 as each body connection region 51 so as to coexist with each body connection region 51.

[0172] The plurality of source connection regions 52 are specifically formed in the surface layer portion of the body region 21 at intervals from the trench source structure 33 on the other side to the trench source structure 33 on one side in the plurality of segment portions 34. The plurality of source connection regions 52 are adjacent to the plurality of body connection regions 51 in the first direction X. Each source connection region 52 is in contact with the trench source structure 33 on one side in the first direction X. Each source connection region 52 faces the source electrode 37 across the source insulating film 36 of the trench source structure 33 on one side in each segment portion 34.

[0173] The plurality of trench connection regions 53 are respectively drawn out from the wall surfaces of the trench source structures 33 adjacent to the plurality of body connection regions 51. In this form, one trench connection region 53 is drawn out from each body connection region 51 toward the wall surface of the adjacent trench source structure 33. That is, the plurality of trench connection regions 53 are respectively formed in a one-to-one correspondence with the plurality of trench source structures 33 in a plan view. In this form, each trench connection region 53 crosses the middle portion of the trench source structure 33 in a plan view.

[0174] Each trench connection region 53 partially covers the wall surface of the trench source structure 33 so as to expose a part of the wall surface of the trench source structure 33. Specifically, each trench connection region 53 is formed at an interval from the segment portion 34 on the source connection region 52 side to the segment portion 34 on the body connection region 51 side.

[0175] Therefore, each trench connection region 53 exposes the source connection region 52. Further, each trench connection region 53 exposes the end portions (side wall and bottom wall) of the trench source structure 33 on the source connection region 52 side. Each trench connection region 53 is formed at an interval inward from the two adjacent trench gate structures 23 so as to expose a part of the source region 22 with respect to the second direction Y from the first main surface 3.

[0176] In this form, the interlayer insulating film 60 does not have the third source opening 66 and includes a plurality of first source openings 64 and a plurality of second source openings 65. In this form, each second source opening 65 is formed as an opening for the body connection region 51 and the source connection region 52. That is, each second source opening 65 is formed in a one-to-one correspondence with each segment portion 34, exposing each body connection region 51 and each source connection region 52.

[0177] Looking at each mesa portion 24, the plurality of second source openings 65 are formed at intervals in the first direction X from the plurality of first source openings 64 and face the plurality of first source openings 64 in the first direction X, respectively. The planar shape of each second source opening 65 is arbitrary, and each second source opening 65 may be formed in a square shape, a rectangular shape, a circular shape, or the like.

[0178] As described above, the SiC semiconductor device 121 also exhibits the same effects as those described for the SiC semiconductor device 1. Of course, the structure in which the body connection region 51 and the source connection region 52 coexist in one segment portion 34 can also be applied to the second to third embodiments.

[0179] FIG. 14 corresponds to FIG. 4 and is a plan view for explaining the structure of the SiC semiconductor device 131 according to the fifth embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and the descriptions thereof are omitted.

[0180] Referring to FIG. 14, in the interlayer insulating film 60 of the SiC semiconductor device 131, the first source opening 64, the second source opening 65, and the third source opening 66 are integrally formed. That is, the interlayer insulating film 60 has a plurality of linear source openings 132 extending in the first direction X along the plurality of mesa portions 24.

[0181] Each source opening 132 exposes a plurality of trench source structures 33 (source electrodes 37), a plurality of body connection regions 51, and a plurality of source connection regions 52 in each mesa portion 24 all at once. In this case, the source main surface electrode 73 enters the plurality of source openings 132 from above the interlayer insulating film 60 and is electrically connected to the trench source structures 33, the body connection regions 51, and the source connection regions 52 of the plurality of mesa portions 24.

[0182] As described above, the SiC semiconductor device 131 also exhibits the same effects as those described for the SiC semiconductor device 1. Of course, the structure in which the interlayer insulating film 60 has a plurality of source openings 132 can also be applied to the second to fourth embodiments. In the fourth embodiment, it is preferable to employ the source opening 132 instead of the plurality of first source openings 64 and the plurality of second source openings 65.

[0183] FIG. 15 corresponds to FIG. 4 and is a plan view for explaining the structure of an SiC semiconductor device 141 according to a sixth embodiment of the present invention. FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 15. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and their descriptions are omitted.

[0184] Referring to FIGS. 15 and 16, the SiC semiconductor device 141 has a trench source structure 33 having a structure different from the trench source structure 33 according to the SiC semiconductor device 1. Specifically, the source trench 35 of each trench source structure 33 includes a first trench portion 35a on the opening side and a second trench portion 35b on the bottom wall side. The first trench portion 35a has a first trench width WT1 with respect to the second direction Y. The first trench width WT1 is the second width W2 of the trench source structure 33. The first trench portion 35a may be formed in a tapered shape in which the first trench width WT1 narrows toward the bottom wall side.

[0185] The first trench portion 35a exposes the body region 21 and the source region 22. The first trench portion 35a is preferably formed in a region on the first main surface 3 side with respect to the bottom wall of the gate trench 25. That is, the depth of the first trench portion 35a is preferably less than the first depth D1 of the trench gate structure 23. Of course, the first trench portion 35a may be formed deeper than the trench gate structure 23. The depth of the first trench portion 35a may be 0.1 μm or more and 2 μm or less.

[0186] The second trench portion 35b exposes the drift region 7. The second trench portion 35b communicates with the first trench portion 35a and extends from the first trench portion 35a toward the bottom of the drift region 7 (high-concentration region 9). In this form, the second trench portion 35b crosses the bottom wall of the trench gate structure 23. The second trench portion 35b may be formed in a vertical shape having a substantially constant opening width. The second trench portion 35b may be formed in a tapered shape having an opening width that narrows toward the bottom wall.

[0187] The depth of the second trench portion 35b with respect to the first trench portion 35a is preferably greater than the first depth D1 of the trench gate structure 23. The second trench portion 35b has a second trench width WT2 (WT2 < WT1) that is less than the first trench width WT1 in the second direction Y. The second trench width WT2 may be 0.5 μm or more and less than 3 μm.

[0188] The source insulating film 36 is formed in a film shape on the inner wall of the source trench 35 and partitions a recessed space in the source trench 35. Specifically, the source insulating film 36 has a window portion 36a that exposes the first trench portion 35a and partitions a recessed space in the second trench portion 35b.

[0189] In this form, the source insulating film 36 includes a first portion 38 and a second portion 39, and does not include a third portion 40. The first portion 38 covers the side wall of the source trench 35 (the second trench portion 35b) and defines a window portion 36a on the opening side of the source trench 35 (the first trench portion 35a side). The second portion 39 covers the bottom wall of the source trench 35 (the second trench portion 35b).

[0190] The thickness of the first portion 38 may be 10 nm or more and 250 nm or less. The second portion 39 may have a thickness exceeding that of the first portion 38. The thickness of the second portion 39 may be 50 nm or more and 500 nm or less. Of course, the source insulating film 36 having a uniform thickness may be formed.

[0191] The source electrode 37 is embedded in the source trench 35 with the source insulating film 36 interposed therebetween. Specifically, the source electrode 37 is embedded in the first trench portion 35a and the second trench portion 35b with the source insulating film 36 interposed therebetween, and has a contact portion 37a in contact with the first trench portion 35a exposed from the window portion 36a.

[0192] The contact portion 37a is electrically connected to the body region 21 and the source region 22 in the window portion 36a. That is, the contact portion 37a source-grounds the body region 21 and the source region 22 in the source trench 35. The source electrode 37 has an electrode surface exposed from the source trench 35. The electrode surface of the source electrode 37 is formed in a curved shape recessed toward the bottom wall of the source trench 35.

[0193] Each body connection region 51 is electrically connected to the contact portion 37a of the source electrode 37 exposed from the first trench portion 35a in each segment portion 34 (the first segment portion 34A). Thereby, each body connection region 51 is source-grounded in the SiC chip 2. Each body connection region 51 may cover a part of the second trench portion 35b and face the source electrode 37 with a part of the source insulating film 36 interposed therebetween.

[0194] Each source connection region 52 is electrically connected to the contact portion 37a of the source electrode 37 exposed from the first trench portion 35a in each segment portion 34 (the second segment portion 34B). Thereby, each source connection region 52 is source-grounded within the SiC chip 2. Each source connection region 52 may cover a part of the second trench portion 35b and face the source electrode 37 with a part of the source insulating film 36 interposed therebetween.

[0195] Each trench connection region 53 covers the first trench portion 35a and the second trench portion 35b of each trench source structure 33. Each trench connection region 53 is electrically connected to the contact portion 37a of the source electrode 37 exposed from the first trench portion 35a. Thereby, each trench connection region 53 is source-grounded within the SiC chip 2. Each trench connection region 53 faces the source electrode 37 with a part of the source insulating film 36 interposed therebetween on the second trench portion 35b side.

[0196] In this form, each well region 54 is electrically connected to the source electrode 37 (contact portion 37a) via the body region 21, the source region 22, the body connection region 51, the source connection region 52, and the trench connection region 53.

[0197] Since other structures are the same as those of the aforementioned SiC semiconductor device 1, their descriptions are omitted. As described above, the SiC semiconductor device 141 also exhibits the same effects as those described for the SiC semiconductor device 1. Further, in the SiC semiconductor device 141, the source electrode 37 has a contact portion 37a exposed from the side wall of the source trench 35 in the region on the opening side of the source trench 35.

[0198] The SiC semiconductor device 141 also includes a body connection region 51 electrically connected to the contact portion 37a of the source electrode 37. Thereby, the body connection region 51 can be source-grounded within the SiC chip 2. The SiC semiconductor device 141 also includes a source connection region 52 electrically connected to the contact portion 37a of the source electrode 37. Thereby, the source connection region 52 can be source-grounded within the SiC chip 2.

[0199] Thus, according to the SiC semiconductor device 141, a semiconductor region to be source-grounded can be source-grounded within the SiC chip 2 by the contact portion 37a of the source electrode 37. In this form, the body region 21, the source region 22, the body connection region 51, the source connection region 52, the trench connection region 53, and the well region 54 are electrically connected to the source electrode 37 within the SiC chip 2. Such a structure is effective in relaxing the alignment margin of the structures within the active region 11. The trench source structure 33 according to the SiC semiconductor device 141 can also be applied to the second to fifth embodiments.

[0200] FIG. 17 corresponds to FIG. 6 and is a cross-sectional view for explaining the structure of the SiC semiconductor device 151 according to the seventh embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and the descriptions thereof are omitted.

[0201] Referring to FIG. 17, in the SiC semiconductor device 151, the source insulating film 36 includes a first portion 38 and a second portion 39 and does not include a third portion 40. The first portion 38 of the source insulating film 36 covers the side wall of the source trench 35 at a distance from the opening end of the source trench 35 toward the bottom wall so as to expose the surface layer portion of the first main surface 3 from the opening end of the source trench 35. A part of the side wall of the source electrode 37 is exposed from the source insulating film 36 at the opening end of the source trench 35.

[0202] The source region 22 may be exposed from the sidewall of the source trench 35 at the open end of the source trench 35. The body connection region 51 may be exposed from the sidewall of the source trench 35 at the open end of the source trench 35. The source connection region 52 may be exposed from the sidewall of the source trench 35 at the open end of the source trench 35. The trench connection region 53 may be exposed from the sidewall of the source trench 35 at the open end of the source trench 35.

[0203] In this form, each first source opening 64 has an opening width Wop (W2 < Wop) that exceeds the second width W2 of the trench source structure 33. The opening width Wop is the width of the first source opening 64 along the second direction Y. Each first source opening 64 preferably exposes at least the source region 22, the source electrode 37, and the trench connection region 53. Each first source opening 64 may also expose the body connection region 51 and the source connection region 52.

[0204] Similar to the first source opening 64, each second source opening 65 may have an opening width Wop that exceeds the second width W2 of the trench source structure 33. Similar to the first source opening 64, each third source opening 66 may have an opening width Wop that exceeds the second width W2 of the trench source structure 33.

[0205] The source main surface electrode 73 enters the plurality of first source openings 64, the plurality of second source openings 65, and the plurality of third source openings 66 from above the interlayer insulating film 60, and is electrically connected to the plurality of source regions 22, the plurality of source electrodes 37, the plurality of body connection regions 51, the plurality of source connection regions 52, and the plurality of trench connection regions 53. The source main surface electrode 73 (specifically, the first electrode film 74) covers a part of the sidewall of the source electrode 37 in each source trench 35.

[0206] As described above, the SiC semiconductor device 151 also exhibits the same effects as those described for the SiC semiconductor device 1. The form in which the first source opening 64, the second source opening 65, and the third source opening 66 each have an opening width Wop exceeding the second width W2 of the trench source structure 33 is applicable not only to the first embodiment but also to the second to sixth embodiments. For example, in the SiC semiconductor device 131 according to the fifth embodiment, the linear source opening 132 may have an opening width Wop exceeding the second width W2 of the trench source structure 33.

[0207] FIG. 18 corresponds to FIG. 6 and is a cross-sectional view for explaining the structure of the SiC semiconductor device 161 according to the eighth embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to the structures described for the SiC semiconductor device 1, and the descriptions thereof are omitted.

[0208] Referring to FIG. 18, the SiC semiconductor device 161 includes a gate electrode 27 containing p-type polysilicon doped with p-type impurities. Specifically, the gate electrode 27 is made of p-type polysilicon. The p-type impurity concentration of the p-type polysilicon in the gate electrode 27 may be 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less. The sheet resistance of the gate electrode 27 may be 10 Ω / □ or more and 500 Ω / □ or less.

[0209] The SiC semiconductor device 161 includes a source electrode 37 containing the same conductive material as the gate electrode 27. That is, the source electrode 37 contains p-type polysilicon doped with p-type impurities. Specifically, the source electrode 37 is made of p-type polysilicon. The p-type impurity concentration of the p-type polysilicon in the source electrode 37 may be 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less. The sheet resistance of the source electrode 37 may be 10 Ω / □ or more and 500 Ω / □ or less.

[0210] The SiC semiconductor device 161 includes a first low-resistance layer 162 that covers the gate electrode 27. The first low-resistance layer 162 covers the gate electrode 27 within the gate trench 25. That is, the first low-resistance layer 162 forms a part of the trench gate structure 23. The first low-resistance layer 162 is in contact with the gate insulating film 26 within the gate trench 25. Preferably, the first low-resistance layer 162 is in contact with the corner portion (i.e., the third portion 30) of the gate insulating film 26.

[0211] The first low-resistance layer 162 includes a conductive material having a sheet resistance lower than that of the gate electrode 27. The sheet resistance of the first low-resistance layer 162 may be 0.01 Ω / sq or more and 10 Ω / sq or less. Preferably, the first low-resistance layer 162 has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less. In this form, the first low-resistance layer 162 is composed of a polysilicide layer (specifically, a p-type polysilicide layer) in which the surface layer portion of the gate electrode 27 is silicided with a metal. That is, the first low-resistance layer 162 is integrally formed with the gate electrode 27 at the surface layer portion of the gate electrode 27 and forms the electrode surface of the gate electrode 27.

[0212] The first low-resistance layer 162 may contain at least one of TiSi, TiSi 2 , NiSi, CoSi, CoSi 2 , MoSi 2 and WSi 2 . The first low-resistance layer 162 preferably contains at least one of NiSi, CoSi 2 and TiSi 2 . Particularly preferably, the first low-resistance layer 162 is composed of CoSi 2 .

[0213] The SiC semiconductor device 161 includes a second low-resistance layer 163 that covers the source electrode 37. The second low-resistance layer 163 covers the source electrode 37 within the source trench 35. That is, the second low-resistance layer 163 forms a part of the trench source structure 33. The second low-resistance layer 163 is in contact with the source insulating film 36 within the source trench 35. The second low-resistance layer 163 preferably contacts the corner portion of the source insulating film 36 (i.e., the third portion 40).

[0214] The second low-resistance layer 163 includes a conductive material having a sheet resistance lower than that of the source electrode 37. The sheet resistance of the second low-resistance layer 163 may be 0.01 Ω / sq or more and 10 Ω / sq or less. The second low-resistance layer 163 preferably has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less. In this form, the second low-resistance layer 163 is composed of a polysilicide layer (specifically, a p-type polysilicide layer) in which the surface layer portion of the source electrode 37 is silicided with a metal. That is, the second low-resistance layer 163 is integrally formed with the source electrode 37 at the surface layer portion of the source electrode 37 and forms the electrode surface of the source electrode 37.

[0215] The second low-resistance layer 163 may contain at least one of TiSi, TiSi 2 , NiSi, CoSi, CoSi 2 , MoSi 2 and WSi 2 . The second low-resistance layer 163 preferably contains at least one of NiSi, CoSi 2 and TiSi 2 . The second low-resistance layer 163 particularly preferably consists of CoSi. The second low-resistance layer 163 preferably consists of the same material as the first low-resistance layer 162. 2 From the above, the SiC semiconductor device 161 also exhibits the same effects as those described for the SiC semiconductor device 1. Also, the SiC semiconductor device 161 includes a gate electrode 27 containing p-type polysilicon and a first low-resistance layer 162 that covers the gate electrode 27.

[0216] The SiC semiconductor device 161 also exhibits the same effects as those described for the SiC semiconductor device 1. Also, the SiC semiconductor device 161 includes a gate electrode 27 containing p-type polysilicon and a first low-resistance layer 162 that covers the gate electrode 27.

[0217] According to the gate electrode 27 including p-type polysilicon, compared with the case of n-type polysilicon, the sheet resistance in the gate trench 25 increases, while the gate threshold voltage Vth can be increased by about 1V. According to the first low-resistance layer 162, the parasitic resistance in the gate trench 25 can be reduced while suppressing the decrease in the gate threshold voltage Vth. Therefore, according to the SiC semiconductor device 161, the parasitic resistance in the gate trench 25 can be reduced while increasing the gate threshold voltage Vth.

[0218] The first low-resistance layer 162 and the second low-resistance layer 163 according to the SiC semiconductor device 161 can be applied not only to the first embodiment but also to the second to seventh embodiments. When the first low-resistance layer 162 and the second low-resistance layer 163 are applied to the SiC semiconductor device 141 according to the sixth embodiment, the second low-resistance layer 163 forms a contact portion 37a that contacts the first trench portion 35a together with the source electrode 37. That is, the second low-resistance layer 163 source-grounds the body region 21 and the source region 22 in the source trench 35.

[0219] The embodiments of the present invention can be implemented in still other forms. For example, in each of the above-described embodiments, an example in which the first direction X is the m-axis direction of the SiC single crystal and the second direction Y is the a-axis direction of the SiC single crystal has been described. However, the first direction X may be the a-axis direction of the SiC single crystal and the second direction Y may be the m-axis direction of the SiC single crystal. That is, the first side surface 5A and the second side surface 5B (the two short sides of the SiC chip 2) may be formed by the m-plane of the SiC single crystal, and the third side surface 5C and the fourth side surface 5D (the two long sides of the SiC chip 2) may be formed by the a-plane of the SiC single crystal. In this case, the off direction may be the a-axis direction of the SiC single crystal. The specific configuration in this case can be obtained by replacing the m-axis direction related to the first direction X with the a-axis direction and replacing the a-axis direction related to the second direction Y with the m-axis direction in the above description and the accompanying drawings.

[0220] In each of the foregoing embodiments, a gate pad electrode as a terminal electrode may be formed on the gate main surface electrode 71, and a source pad electrode as a terminal electrode may be formed on the source main surface electrode 73. In this case, the gate pad electrode preferably includes a Ni plating film covering the gate main surface electrode 71. The gate pad electrode may include a Pd plating film and an Au plating film laminated in this order from the Ni plating film side. Further, the source pad electrode preferably includes a Ni plating film covering the source main surface electrode 73. The source pad electrode may include a Pd plating film and an Au plating film laminated in this order from the Ni plating film side.

[0221] In each of the foregoing embodiments, an Si chip made of a single crystal of Si may be employed instead of the SiC chip 2. That is, instead of the SiC semiconductor devices 1, 101, 111, 121, 131, 141, 151, 161 according to the foregoing embodiments, an Si semiconductor device may be employed.

[0222] In each of the foregoing embodiments, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been described, but the first conductivity type may be p-type and the second conductivity type may be n-type. The specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the foregoing description and the accompanying drawings.

[0223] In each of the foregoing embodiments, a p-type collector region may be employed instead of the n-type drain region 6. According to this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. The specific configuration in this case can be obtained by replacing the "source" of the MISFET with the "emitter" of the IGBT and the "drain" of the MISFET with the "collector" of the IGBT in the foregoing description.

[0224] Examples of features extracted from this specification and the drawings are shown below. The following [A1] to [A20] and [B1] to [B20] provide a semiconductor device that can contribute to miniaturization.

[0225] [A1]A semiconductor device including: a semiconductor chip (2) having a main surface (3); a drift region (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a body region (21) of a second conductivity type (p-type) formed in a surface layer portion of the drift region (7); a source region (22) of the first conductivity type (n-type) formed in a surface layer portion of the body region (21); a plurality of trench source structures (33) formed in the main surface (3) so as to cross the source region (22) and the body region (21) and reach the drift region (7), and arranged at intervals in a first direction (X); a body connection region (51) of the second conductivity type (p-type) formed in a region between two adjacent trench source structures (33) in the surface layer portion of the body region (21) so as to be electrically connected to the body region (21); and a source connection region (52) of the first conductivity type (n-type) formed in a region between two adjacent trench source structures (33) in a different region from the body connection region (51) in the surface layer portion of the body region (21) so as to be electrically connected to the source region (22).

[0226] [A2]The semiconductor device according to A1, wherein the source connection region (52) faces the body connection region (51) in the first direction (X) with the trench source structure (33) interposed therebetween.

[0227] [A3]The semiconductor device according to A1 or A2, wherein the plurality of trench source structures (33) are each formed in a strip shape extending in the first direction (X).

[0228] [A4]The semiconductor device according to any one of A1 to A3, wherein the body connection region (51) has an impurity concentration exceeding the impurity concentration of the body region (21).

[0229] [A5]The semiconductor device according to any one of A1 to A4, wherein the source region (22) has an impurity concentration exceeding the impurity concentration of the drift region (7), and the source connection region (52) has an impurity concentration exceeding the impurity concentration of the drift region (7).

[0230] [A6] The semiconductor device according to any one of A1 to A5, wherein the source connection region (52) is formed by using a part of the source region (22).

[0231] [A7] The semiconductor device according to any one of A1 to A6, wherein a plurality of the body connection regions (51) are formed and a plurality of the source connection regions (52) are formed.

[0232] [A8] The semiconductor device according to A7, wherein the plurality of the source connection regions (52) are alternately formed with the plurality of the body connection regions (51) along the first direction (X).

[0233] [A9] Further including a plurality of trench gate structures (23) formed on the main surface (3) so as to cross the source region (22) and the body region (21) and reach the drift region (7), each extending in the first direction (X), and arranged on the main surface (3) at intervals in a second direction (Y) intersecting the first direction (X), and the plurality of trench source structures (33) are arranged at intervals in the first direction (X) between two adjacent trench gate structures (23). The semiconductor device according to any one of A1 to A8.

[0234] [A10] The semiconductor device according to A9, wherein the body connection region (51) is formed at a distance from the plurality of trench gate structures (23).

[0235] [A11] The semiconductor device according to A9 or A10, wherein each trench source structure (33) is formed deeper than each trench gate structure (23).

[0236] [A12]The plurality of trench gate structures (23) partition a plurality of mesa portions (24) each extending in the first direction (X) on the main surface (3), and the plurality of trench source structures (33) partition a plurality of segment portions (34) each consisting of a part of the mesa portion (24) in the mesa portion (24). The body connection region (51) is formed in the segment portion (34), and the source connection region (52) is formed in the segment portion (34) different from the segment portion (34) in which the body connection region (51) is formed. The semiconductor device according to any one of A9 to A11.

[0237] [A13]The plurality of segment portions (34) include a plurality of first segment portions (34A) and a plurality of second segment portions (34B) alternately arranged along the first direction (X). The plurality of body connection regions (51) are formed in the plurality of first segment portions (34A), and the plurality of source connection regions (52) are formed in the plurality of second segment portions (34B). The semiconductor device according to A12.

[0238] [A14]The plurality of trench gate structures (23) are arranged at a first interval (P1) in the second direction (Y), and the plurality of trench source structures (33) are arranged at a second interval (P2) less than the first interval (P1) in the first direction (X). The semiconductor device according to any one of A9 to A13.

[0239] [A15]The semiconductor device according to any one of A1 to A14 further includes a second conductivity type (p-type) trench connection region (53) drawn out from the body connection region (51) along the wall surface of at least one trench source structure (33) in the surface layer portion of the drift region (7).

[0240] [A16]The trench connection region (53) covers the side wall and the bottom wall of the trench source structure (33). The semiconductor device according to A15.

[0241] [A17] The semiconductor device according to A15 or A16, wherein the trench connection region (53) partially covers the wall surface of the trench source structure (33) so as to expose a part of the wall surface of the trench source structure (33).

[0242] [A18] The semiconductor device according to any one of A15 to A17, further comprising a well region (54) of a second conductivity type (p-type) formed in a region along the wall surface of at least one of the trench source structures (33) so as to cover the trench connection region (53) in the surface layer portion of the drift region (7), and having an impurity concentration lower than that of the body connection region (51).

[0243] [A19] The semiconductor device according to A18, wherein the well region (54) has a portion covering the trench source structure (33) with the trench connection region (53) interposed therebetween, and a portion directly covering the trench source structure (33).

[0244] [A20] The semiconductor device according to any one of A1 to A19, further comprising a source main surface electrode (73) formed on the main surface (3) and electrically connected to the trench source structure (33), the body connection region (51), and the source connection region (52) on a line connecting the trench source structure (33), the body connection region (51), and the source connection region (52).

[0245] [B1]An SiC semiconductor device including: an SiC chip (2) having a main surface (3); a first conductivity type (n-type) drift region (7) formed in a surface layer portion of the main surface (3); a second conductivity type (p-type) body region (21) formed in a surface layer portion of the drift region (7); a first conductivity type (n-type) source region (22) formed in a surface layer portion of the body region (21); a plurality of trench gate structures (23) each extending along a first direction (X) along the main surface (3) and arranged at intervals in a second direction (Y) intersecting the first direction (X) and penetrating the source region (22) and the body region (21); a trench source structure (33) formed in the main surface (3) so as to penetrate the source region (22) and the body region (21) between two adjacent trench gate structures (23) and having one end portion on one side of the first direction (X) and the other end portion on the other side of the first direction (X); a second conductivity type (p-type) body connection region (51) formed in a region on one end side of the trench source structure (33) in the surface layer portion of the body region (21) so as to be electrically connected to the body region (21); and a first conductivity type (n-type) source connection region (52) formed in a region on the other end side of the trench source structure (33) in the surface layer portion of the body region (21) so as to be electrically connected to the source region (22).

[0246] [B2]The SiC semiconductor device according to B1, wherein the source connection region (52) faces the body connection region (51) in the first direction (X) with the trench source structure (33) interposed therebetween.

[0247] [B3]The SiC semiconductor device according to B1 or B2, wherein the body connection region (51) is formed at a distance from the plurality of trench gate structures (23).

[0248] [B4]The SiC semiconductor device according to any one of B1 to B3, wherein the body connection region (51) has an impurity concentration exceeding the impurity concentration of the body region (21).

[0249] [B5]The source region (22) has an impurity concentration exceeding that of the drift region (7), and the source connection region (52) has an impurity concentration exceeding that of the drift region (7). The SiC semiconductor device according to any one of B1 to B4.

[0250] [B6]The source connection region (52) is formed using a part of the source region (22). The SiC semiconductor device according to any one of B1 to B5.

[0251] [B7]The trench source structure (33) is formed in a strip shape extending in the first direction (X). The SiC semiconductor device according to any one of B1 to B6.

[0252] [B8]The trench source structure (33) is formed deeper than the trench gate structure (23). The SiC semiconductor device according to any one of B1 to B7.

[0253] [B9]A plurality of the trench source structures (33) are arranged at intervals in the first direction (X) between a plurality of the trench gate structures (23). The body connection region (51) is formed in a region partitioned by two adjacent trench source structures (33) in the surface layer portion of the body region (21). The source connection region (52) is formed in a region partitioned by two adjacent trench source structures (33) in a region different from the body connection region (51) in the surface layer portion of the body region (21). The SiC semiconductor device according to any one of B1 to B8.

[0254] [B10]A plurality of the trench gate structures (23) are arranged at a first interval (P1) in the second direction (Y). A plurality of the trench source structures (33) are arranged at a second interval (P2) equal to or less than the first interval (P1) in the first direction (X). The SiC semiconductor device according to B9.

[0255] [B11]The SiC semiconductor device according to B10, wherein the second interval (P2) is less than the length (L) in the first direction (X) of each of the trench source structures (33).

[0256] [B12]The SiC semiconductor device according to any one of B1 to B11, further comprising a p-type trench connection region (53) formed in a region along the wall surface of the trench source structure (33) in the drift region (7) so as to be electrically connected to the body connection region (51) in the surface layer portion of the main surface (3).

[0257] [B13]The SiC semiconductor device according to B12, wherein the trench connection region (53) has an impurity concentration exceeding the impurity concentration of the body region (21).

[0258] [B14]The SiC semiconductor device according to B12 or B13, wherein the trench connection region (53) covers the side wall and the bottom wall of the trench source structure (33).

[0259] [B15]The SiC semiconductor device according to any one of B12 to B14, wherein the trench connection region (53) partially covers the wall surface of the trench source structure (33) so as to expose a part of the wall surface of the trench source structure (33).

[0260] [B16]The SiC semiconductor device according to any one of B12 to B15, further comprising a p-type well region (54) formed in a region along the wall surface of the trench source structure (33) so as to cover the trench connection region (53) and having an impurity concentration lower than the impurity concentration of the trench connection region (53).

[0261] [B17]The SiC semiconductor device according to B16, wherein the well region (54) has a portion covering the trench source structure (33) with the trench connection region (53) interposed therebetween and a portion directly covering the trench source structure (33).

[0262] [B18] The SiC semiconductor device according to any one of B1 to B17, further comprising a source main surface electrode (73) formed on the main surface (3) and electrically connected to the trench source structure (33), the body connection region (51), and the source connection region (52) on a line connecting the trench source structure (33), the body connection region (51), and the source connection region (52).

[0263] [B19] The SiC semiconductor device according to B18, further comprising an interlayer insulating film (60) covering the main surface (3) and having one or more openings (64, 65, 66, 132) exposing the trench source structure (33), the body connection region (51), and the source connection region (52), wherein the source main surface electrode (73) is formed on the interlayer insulating film (60) and is electrically connected to the trench source structure (33), the body connection region (51), and the source connection region (52) within one or more of the openings (64, 65, 66, 132).

[0264] Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is defined by the appended claims.

Explanation of Reference Numerals

[0265] 1 SiC semiconductor device (semiconductor device) 2 SiC chip (semiconductor chip) 3 First main surface 7 Drift region 21 Body region 22 Source region 23 Trench gate structure 24 Mesa portion 33 Trench source structure 34 Segment portion 34A First segment portion 34B Second segment portion 51 Body connection region 52 Source connection region 53 Trench connection region 54 Well region 73 Source main surface electrode 101 SiC semiconductor device (semiconductor device) 111 SiC semiconductor device (semiconductor device) 121 SiC semiconductor device (semiconductor device) 131 SiC semiconductor device (semiconductor device) 141 SiC semiconductor device (semiconductor device) 151 SiC semiconductor device (semiconductor device) 161 SiC semiconductor device (semiconductor device) P1 First interval P2 Second interval X First direction Y Second direction

Claims

1. a semiconductor chip having a major surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the drift region; a first conductivity type source region formed in a surface layer portion of the body region; a plurality of trench source structures formed in the major surface, the trench source structures extending across the source region and the body region and reaching the drift region, the trench source structures being arranged at intervals in a first direction; a body connection region of a second conductivity type formed in a region between two adjacent trench source structures in a surface layer portion of the body region so as to be electrically connected to the body region; a source connection region of a first conductivity type formed in a surface portion of the body region in a region different from the body connection region and between two adjacent trench source structures so as to be electrically connected to the source region.

2. The semiconductor device according to claim 1 , wherein the source connection region faces the body connection region in the first direction across the trench source structure.

3. The semiconductor device according to claim 1 , wherein the plurality of trench source structures are each formed in a strip shape extending in the first direction.

4. 4. The semiconductor device according to claim 1, wherein the body connection region has an impurity concentration higher than an impurity concentration of the body region.

5. the source region has an impurity concentration that exceeds an impurity concentration of the drift region; 5. The semiconductor device according to claim 1, wherein the source connection region has an impurity concentration higher than an impurity concentration of the drift region.

6. 6. The semiconductor device according to claim 1, wherein the source connection region is formed by utilizing a part of the source region.

7. A plurality of said body connection regions are formed; 7. The semiconductor device according to claim 1, wherein a plurality of said source connection regions are formed.

8. The semiconductor device according to claim 7 , wherein the plurality of source connection regions are alternately formed with the plurality of body connection regions along the first direction.

9. a plurality of trench gate structures formed on the main surface to cross the source region and the body region and reach the drift region, each of which extends in the first direction and is arranged on the main surface at intervals in a second direction intersecting the first direction; 9. The semiconductor device according to claim 1, wherein the plurality of trench source structures are arranged at intervals in the first direction between two adjacent trench gate structures.

10. The semiconductor device according to claim 9 , wherein the body connection region is formed at a distance from the plurality of trench gate structures.

11. 11. The semiconductor device according to claim 9, wherein each of said trench source structures is formed deeper than each of said trench gate structures.

12. The plurality of trench gate structures define a plurality of mesa portions on the main surface, each of the mesa portions extending in the first direction, The plurality of trench source structures partition the mesa portion into a plurality of segment portions each consisting of a portion of the mesa portion, the body connection region is formed in the segment portion, 12. The semiconductor device according to claim 9, wherein the source connection region is formed in a segment part different from the segment part in which the body connection region is formed.

13. the plurality of segment portions include a plurality of first segment portions and a plurality of second segment portions alternately arranged along the first direction, A plurality of the body connection regions are formed in a plurality of the first segment portions, The semiconductor device according to claim 12 , wherein a plurality of said source connection regions are formed in a plurality of said second segment portions.

14. The trench gate structures are arranged at first intervals in the second direction, 14. The semiconductor device according to claim 9, wherein the plurality of trench source structures are arranged in the first direction at second intervals that are less than the first intervals.

15. The semiconductor device according to any one of claims 1 to 14, further comprising a second conductivity type trench connection region extending from the body connection region to a region along a wall surface of at least one of the trench source structures in a surface portion of the drift region.

16. 16. The semiconductor device of claim 15, wherein the trench connection region covers sidewalls and a bottom wall of the trench source structure.

17. 17. The semiconductor device according to claim 15, wherein the trench connection region partially covers a wall surface of the trench source structure so as to expose a part of the wall surface of the trench source structure.

18. The semiconductor device according to any one of claims 15 to 17, further comprising a well region of a second conductivity type having a lower impurity concentration than the body connection region, the well region being formed in a region along a wall surface of at least one of the trench source structures so as to cover the trench connection region in a surface layer portion of the drift region.

19. 19. The semiconductor device according to claim 18, wherein the well region has a portion covering the trench source structure with the trench connection region interposed therebetween, and a portion directly covering the trench source structure.

20. The semiconductor device according to any one of claims 1 to 19, further comprising a source main surface electrode formed on the main surface and electrically connected to the trench source structure, the body connection region, and the source connection region on a line connecting the trench source structure, the body connection region, and the source connection region.

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