Method and system for ultraviolet LED construction - Patents.com

Abstract

An exemplary processing method for forming an LED structure may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The method may include heating the aluminum nitride layer to a temperature of about 1500° C. or higher. The method may include forming an ultraviolet light emitting diode structure on the aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 17 / 345,992, filed on June 11, 2021, entitled "METHOD AND SYSTEMS FOR UV LED STRUCTURES", the entire content of which is incorporated herein by reference.

[0002]

[0002] This technology relates to semiconductor processing and materials. More specifically, this technology relates to the formation processes and materials of LED components.

Background Art

[0003]

[0003] An LED panel or device can be formed of a number of light sources that operate as pixels on the device. After the pixels are formed of single - color light sources, they can be supplied through a conversion layer to generate color, or the pixels can be formed of individual red, blue, and green light sources respectively. In either scenario, any number of light sources, up to millions, can be formed, connected, and operated. Visible LEDs are well - developed, but LEDs operating in the ultraviolet spectrum have significantly degraded performance.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high - quality devices and structures. These and other needs are addressed by this technology.

Summary of the Invention

[0005]

[0005] An exemplary processing method for forming an LED structure can include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The method can include heating the aluminum nitride layer to a temperature of about 1500 °C or higher. The method can include forming an ultraviolet light - emitting diode structure on the aluminum nitride layer using metal - organic chemical vapor deposition or molecular beam epitaxy.

[0006]

[0006] In some embodiments, the method may include transferring the substrate to a carrier after depositing the aluminum nitride layer. The carrier may be carbon or may contain carbon, and the carrier may define a ledge on which the substrate can sit. The first cover wafer may be disposed on the substrate on the carrier. The second cover wafer may be disposed under the substrate on the carrier. Each of the first cover wafer and the second cover wafer may be a substrate having an aluminum nitride layer. The first cover wafer and the second cover wafer may be oriented in substantially the same direction as the substrate. The substrate may be disposed downwardly on the carrier. At least two substrates may be disposed in direct contact between the first cover wafer and the second cover wafer on the carrier. The aluminum nitride layer may be heated to a temperature of about 1600 °C to about 1800 °C. The aluminum nitride layer may be heated to about 1000 °C or higher for at least 100 minutes. The full width at half maximum of the X-ray rocking curve along the (102) crystal direction of the aluminum nitride layer may be about 300 arcseconds or less. After heating the aluminum nitride layer, the substrate may maintain a coverage of about 85% or more of the aluminum nitride layer.

[0007]

[0007] Some embodiments of the present technology may include a method of forming an LED structure. The method may include depositing an aluminum nitride layer on a first substrate and a second substrate via a physical vapor deposition process. The method may include positioning the first substrate downwardly on a carrier. The method may include positioning the second substrate downwardly in contact with the first substrate. The method may include heating the first substrate and the second substrate to a temperature of about 1500 °C or higher.

[0008]

[0008] In some embodiments, the method may include forming an ultraviolet light emitting diode structure on an aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy. The aluminum nitride layer may be heated to a temperature of about 1600 °C to about 1800 °C. The carrier may be carbon or may contain carbon, and the carrier may define a ledge on which both the first substrate and the second substrate sit. Positioning the first substrate downwardly on the carrier may include positioning the first substrate on a first cover wafer. The method may include positioning a second cover wafer on the second substrate on the carrier. Each of the first cover wafer and the second cover wafer may be a substrate having an aluminum nitride layer. Each of the first cover wafer, the second cover wafer, the first substrate, and the second substrate may be oriented in substantially the same direction.

[0009]

[0009] Some embodiments of the present technology may include a method of forming an LED structure. The method may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The method may include positioning the substrate downwardly on a first cover wafer positioned on a carrier. The method may include positioning a second cover wafer on the substrate. The method may include heating the aluminum nitride layer to a temperature of about 1500 °C or higher. The method may include forming an ultraviolet light emitting diode ("LED") structure on the aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy. In some embodiments, the full width at half maximum of the X-ray rocking curve along the (102) crystal direction of the aluminum nitride layer may be about 300 arcseconds or less.

[0010]

[0010] The above technology can provide numerous advantages over conventional systems and techniques. For example, the present technology can provide a method for forming a high-quality buffer layer characterized by a reduction in threading dislocations. Further, the present technology can utilize carrier and positioning arrangements to manufacture ultraviolet light-emitting diodes characterized by improved performance over conventional devices. These and other embodiments will be described in more detail below in conjunction with the following description and the accompanying drawings, along with their many advantages and features.

[0011]

[0011] A further understanding of the nature and advantages of the disclosed technology can be obtained by reference to the remainder of the present specification and the drawings.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0013]

[0019] Some of the figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes only and should not be regarded as to scale unless a specific scale is indicated. Further, as schematic diagrams, the figures are provided to assist understanding and may not include all aspects or information, and may include exaggerated material for the purpose of explanation, as compared to a realistic representation.

[0014]

[0020] In the accompanying figures, the same reference labels may be used for similar components and / or features. Further, various components of the same type may be distinguished by attaching letters after the reference label to distinguish the similar components. When only a first reference label is used in this specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0015]

[0021] Deep ultraviolet light refers to light generated within a wavelength range of approximately 280 nm to approximately 200 nm, and has conventionally been generated by a mercury gas discharge lamp. However, as more environmentally friendly methods of generating UV light become widespread, the conventional technology has been unable to cope with these wavelengths with sufficient operating efficiency. Many conventional ultraviolet light-emitting diodes (“LEDs”) are formed on an aluminum nitride buffer physically deposited on a sapphire substrate. This type of substrate can operate effectively in the configuration of a standard blue LED, but may not operate effectively in a UVLED. For example, since a blue LED is characterized by a quantum efficiency of 50% or more, sufficient light may be generated even with a relatively low-quality LED structure. However, UVLEDs are characterized by much lower quantum efficiencies, such as 10% or less, 5% or less, or less than that, due to several structural and material problems. For example, a material with low crystal quality can be a limiting factor that can critically degrade the performance of a UVLED.

[0016]

[0022] As described above, many of the gallium nitride-based structures used in LEDs may include a substrate that can be silicon or sapphire. To improve the operation of the device, in this technique, a buffer layer can be formed on the substrate before forming the LED structure by metalorganic chemical vapor deposition or molecular beam epitaxy. However, the buffer layer, which may be a dielectric material such as aluminum nitride as a non-limiting example, may be characterized by a different crystal structure compared to sapphire. This can result in a lattice mismatch between the materials, and the structure of the buffer layer may relax, potentially causing threading dislocations in the buffer layer. These dislocations can penetrate the subsequent device layers formed, including the LED active region, and can further reduce the quantum efficiency of the device.

[0017]

[0023] This technique can overcome these problems by performing a high-temperature anneal of the buffer layer after formation. The anneal process can promote the rearrangement and improvement of the crystal structure of the buffer layer and can reduce or eliminate threading dislocations within the buffer layer. This can improve the quality of the subsequently formed LED structure and can facilitate an improvement in the quantum efficiency of the device. In the remaining disclosure, while specific LED materials and processes using the disclosed technique are always specified, it will be readily understood that the system and method are equally applicable to a variety of materials and processes that can be used to manufacture displays. Therefore, this technique should not be considered limited to use only in UV processes. After describing an exemplary chamber system that can be used in accordance with some embodiments of this technique, methods and components for manufacturing high-quality devices will be described.

[0018]

[0024] FIG. 1 is a top view showing a multi-chamber processing system 100 that can be specifically configured to implement aspects or processes according to some embodiments of the present technology. The multi-chamber processing system 100 can be configured to perform one or more manufacturing processes on individual substrates such as any number of semiconductor substrates to form semiconductor devices. The multi-chamber processing system 100 can include a transfer chamber 106, a buffer chamber 108, single-wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122 and 124, preheat chambers 123 and 125, and part or all of robots 126 and 128. The single-wafer load locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. The processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 are disposed between the transfer chamber 106 and the buffer chamber 108 and can facilitate transfer between the robots 126 and 128. The platforms 102, 104 may be open to the transfer chamber and the buffer chamber, or the platforms may be selectively isolated or sealed from the chambers so as to maintain different operating pressures between the transfer chamber 106 and the buffer chamber 108. Each of the transfer platforms 102, 104 may include one or more tools 105 for processes such as orientation or measurement.

[0019]

[0025] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 can include any device or combination of devices configured to perform the steps described below. Thus, the computer system 130, when executed, can be a controller or an array of controllers configured with software stored on a non-transitory computer-readable medium that can execute the steps described in connection with the methods according to embodiments of the present technology, and / or a general-purpose computer. The processing chambers 114, 116, 118, 120, 122, and 124 can each be configured to perform one or more process steps in the manufacture of semiconductor structures. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 can be equipped to perform a number of substrate processing steps, including, among any other number of substrate processes, dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0020]

[0026] Referring to FIG. 2, selected steps of a manufacturing method 200 for forming an LED structure are illustrated. Method 200 may include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the steps described. For example, in some embodiments, a degassing step may be performed on a substrate such as a silicon substrate or a sapphire substrate to prepare the substrate for deposition. The method may include a number of optional steps that may or may not be particularly relevant to some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader scope of structure formation, but are not important for the present technology, or, as will be further described, can be performed by alternative methodologies. Method 200 is described with reference to the steps schematically shown in FIG. 3, which illustration is described in conjunction with the steps of method 200. FIG. 3 shows only a partial schematic view, and it should be understood that the substrate may include any number of LED sections having the illustrated configuration, as well as alternative structural configurations that can also benefit from aspects of the present technology.

[0021]

[0027] Method 200 may include optional steps for developing a structure in a particular manufacturing process. As shown in FIG. 3, an LED source substrate 305 can be used to facilitate the formation or growth of a plurality of LEDs on the substrate. Only one LED structure is illustrated, but the substrate may have hundreds, thousands, millions, or more LEDs formed thereon, and it should be understood that the present technology may include micro-LEDs among any other type of LED structure and may be of any size. Substrate 305 can be any substrate on which a structure can be formed, such as a silicon-containing material, an aluminum material including sapphire, or any other material that can be used in display or semiconductor manufacturing. The substrate can be of any size, including 2 inches, 3 inches, 4 inches, 6 inches, or a size larger than the substrate sizes in embodiments of the present technology. The substrate can be cleaned or processed, for example, as preparation for depositing one or more layers of material on the substrate to manufacture LEDs, but any number of other semiconductor structures can similarly benefit from aspects of the present technology. The present technology can be applied to manufacture any type of LED structure, and in some embodiments, the structure can be a blue LED, such as a deep UV LED.

[0022]

[0028] Method 200 may include forming or depositing a buffer layer of material, such as buffer layer 310, on the substrate, as shown in FIG. 3. The buffer layer is formed of a material that can facilitate the formation of a structure on the buffer layer and can be manufactured, for example, by metalorganic chemical vapor deposition or molecular beam epitaxy. By including a buffer layer between the substrate and the LED structure, the performance of the device can be improved. The buffer layer can be any number of materials and, in some embodiments, can be aluminum nitride. The buffer layer can be formed by any number of processes for deposition or formation, but in some embodiments, the aluminum nitride buffer layer can be formed by a physical vapor deposition process. Forming the buffer layer by physical vapor deposition can reduce the heat budget of LED manufacturing, improve the crystal orientation and morphology between layers, enable faster deposition compared to the prior art, and potentially reduce the formation of threading dislocations.

[0023]

[0029] As described above, the aluminum nitride layer may be characterized by a crystal structure different from that of the underlying substrate such as sapphire. Thus, due to this lattice mismatch, the aluminum nitride layer may be formed under stress. When the structure relaxes after being formed, the structure may be adjusted, and through dislocations such as dislocation 312 shown in FIG. 3 may be formed within the layer. During formation, a large number of dislocations may be formed throughout the buffer layer, and these dislocations, if untreated, may extend through the subsequently formed LED structure. Thus, the present technique may include an additional step of processing or repositioning the buffer layer structure in order to limit or reduce the number of remaining dislocations. By reducing the number of through dislocations, the quality of the LED structure can be improved, and the quantum efficiency of the formed LED structure can be enhanced.

[0024]

[0030] To improve the crystalline quality of the buffer layer and reduce the number of threading dislocations, the present technique may perform an annealing process on the buffer layer. Annealing can be performed in any of the processing chambers on a system such as system 100, although in some embodiments, the annealing step may be performed in a separate chamber. For example, a substrate including a buffer layer such as aluminum nitride can be transferred to a carrier after depositing the aluminum nitride layer in optional step 210. The carrier can then be positioned in a furnace chamber or other chamber that can heat the substrate. The method 200 may then include heating the substrate, or the buffer layer, to a temperature sufficient to improve crystalline quality and remove threading dislocations in step 215. Following the heating step, an LED structure can be formed on the reconditioned buffer layer in step 220, which may include forming a UVLED structure. The LED structure can be formed by an organometallic chemical vapor deposition process or molecular beam epitaxy, as well as any other formation technique capable of fabricating any number of LED structures such as the structure shown in FIG. 3. For example, a structure including any number of materials and / or layers can be formed on buffer layer 310. As one non-limiting example, the structure may include an n-doped layer 315 such as aluminum gallium nitride. A multiple quantum well layer 320 can be formed on the n-doped region, and an electron blocking layer 325 can be formed on the multiple quantum well layer. In some embodiments, both layers may be aluminum gallium nitride, although any number of other materials can similarly be used.

[0025]

[0031] A p-doped layer 330 can be formed on the electron blocking layer, and then a subsequent p-doped layer 335 can be formed on layer 330. These layers may also be, or may include, aluminum gallium nitride, gallium nitride, or any number of other materials. Thereafter, the structure can be patterned and contacts can be formed. For example, an n-metal contact can be formed on the n-doped layer 315, and a p-metal contact can be formed on the p-doped layer 335. Since threading dislocations 312 may penetrate the structure, annealing can be performed according to embodiments of the present technology to limit the dislocations extending through the structure and improve the quantum efficiency. For example, by using the processes according to some embodiments of the present technology, the efficiency of a deep UV LED may be about 1% or more, about 2% or more, or about 5% or more.

[0026]

[0032] The annealing process can be carried out to reduce through - dislocations in the layer and promote the rearrangement of the crystal structure, and the heating can be performed at a temperature sufficient to repair defects in the crystal structure. For example, in the aluminum nitride buffer layer, the substrate and / or the aluminum nitride layer can be heated to about 1000 °C or higher, about 1100 °C or higher, about 1200 °C or higher, about 1300 °C or higher, about 1400 °C or higher, about 1500 °C or higher, about 1550 °C or higher, about 1600 °C or higher, about 1650 °C or higher, about 1700 °C or higher, about 1750 °C or higher, about 1800 °C or higher, about 1850 °C or higher, or higher. Although there is no intention to limit the present technology to any particular theory, there may exist a temperature at which the activation energy is sufficient to repair crystal defects and improve the crystal structure of the buffer layer. However, as the temperature continues to rise, thermal roughening of the surface occurs, and there is a possibility of losing edge material. For example, due to the deposition process, the thickness of the edge region of the substrate decreases, and a film more sensitive to losses during the annealing process can be manufactured. Furthermore, defects such as damage to aluminum nitride may begin to occur on the surface of the buffer layer, and the operating efficiency may decrease. Therefore, in some embodiments, the temperature can be maintained at about 1850 °C or lower, and also at about 1800 °C or lower, about 1750 °C or lower, about 1600 °C to about 1800 °C, about 1650 °C to about 1750 °C, or about 1675 °C to about 1725 °C so as to reliably remove through - dislocations while limiting material loss and defect generation.

[0027]

[0033] The pressure within the processing chamber may be variable, and thus, in some embodiments, the pressure may be maintained at a slight vacuum of about 700 Torr or less, about 600 Torr or less, about 500 Torr or less, about 400 Torr or less, or less than that. Further, annealing can be performed in an inert environment such as a nitrogen environment, for example. To provide a more uniform treatment across the entire substrate, the treatment time at any of the above temperatures can be maintained at about 60 minutes or more, about 80 minutes or more, about 100 minutes or more, about 110 minutes or more, about 120 minutes or more, about 130 minutes or more, about 140 minutes or more, about 150 minutes or more, about 160 minutes or more, about 170 minutes or more, about 180 minutes or more, about 190 minutes or more, about 200 minutes or more, or more. By performing annealing for a sufficient time, the uniformity of crystal quality may further spread across the entire substrate. For example, FIG. 3B is a diagram showing a rocking curve scan along the x direction or a rocking curve scan parallel to the wafer flat part, indicating that the film quality is substantially uniform across the entire substrate and the full width at half maximum measurement value is less than 260 arc seconds across the entire wafer. However, the longer the treatment can be carried out, the more likely there is a further loss of buffer layer material across the entire substrate. Thus, in some embodiments of the present technology, a carrier for seating the substrate during the annealing process may be used to maintain the material and improve the annealing process.

[0028]

[0034] FIG. 4 is a schematic diagram showing a carrier 400 for high-temperature treatment according to some embodiments of the present technology, which can be used, for example, in the annealing step described with respect to method 200. Carrier 400 is illustrated to show exemplary features of carriers encompassed by the present technology, and the carrier is not limited by any particular features shown. Carriers according to some embodiments of the present technology can be configured to seat one or more substrates, such as a substrate on which a buffer layer is deposited. For example, carrier 400 can include a housing 405 that can define a ledge 410 on which one or more substrates 415 can seat. The one or more substrates, each including a substrate, can include a buffer layer 416 disposed on a first surface of the substrate.

[0029]

[0035] One ledge and a set of substrates are illustrated, but a carrier according to an embodiment of the present technology may include a plurality of ledges, each of which may support one or more substrates and / or cover wafers, as described below. The carrier may have a generally open design as illustrated, such as having two, three, four, or more posts 420 that define one or more ledges along the length of the post. A removable rod or element 425 may be fitted into one of the posts or into a gap between the posts and may be screwed into the carrier or otherwise removably seated. For example, the element 425 may be accessible through the head of the carrier and may be seated in a recess formed in the base of the carrier. Components such as springs or detent mechanisms may be included to seat or unseat the post, but in some embodiments, the carrier may not explicitly include these components because the carrier may be exposed to high temperature processes. The element 425 can be removed to deposit or remove substrates from one or more ledges of the carrier, and then the element can be replaced to secure the substrate prior to processing.

[0030]

[0036] The carrier 400 may be, or may include, one or more materials configured to withstand the furnace environment and to limit thermal stress issues between the carrier and between the carrier and one or more substrates. For example, in some embodiments, the carrier 400 may be, or may include, carbon or a carbon-containing material. For example, the carrier may be graphite, or a coated graphite such as a graphite material coated with silicon carbide, or any other material capable of withstanding a high-temperature environment, or may include the same. In some embodiments, the substrate may be positioned to contact at least one additional substrate or other component as shown. Further, the substrate may be oriented in one or more ways within the carrier. For example, the substrate may be oriented face-to-face or back-to-back within the carrier, but in some embodiments, the substrate can be oriented in substantially the same direction as at least one additional substrate, and in some of the illustrated embodiments, each substrate can be oriented in the same direction. By orienting the substrates in substantially the same direction, the coverage of the buffer layer can be improved and significantly improved compared to other orientations.

[0031]

[0037] For example, tests have shown that when the substrates are positioned face-to-face, such that the buffer layer of a first substrate faces the buffer layer of a second substrate, there may be an increase in the loss of buffer layer material and a decrease in the quality of the material. For example, a face-to-face orientation may be characterized by having a coverage of about 80% or less, about 75% or less, about 65% or less, about 60% or less, or less than that over the entire surface of the substrate after annealing, for example due to evaporation of material during annealing. However, when the substrates are oriented downward in the same direction as shown, the substrates can maintain a coverage of about 80% or more, about 85% or more, about 90% or more, or more over the entire surface of the substrate after annealing.

[0032]

[0038] Furthermore, the substrate orientation may affect the film stress effect caused by the duration at high temperature. For example, when the substrate is maintained in a state that is neither the upper substrate nor the bottom substrate, the film stress may be less susceptible to the influence of annealing compared to the upper substrate or the bottom substrate. A substrate on which an aluminum nitride film is formed can be characterized by a certain degree of warpage due to the internal stress characteristics of the film. When a number of substrates are stacked as shown, the outer substrates such as the first and last substrates or the upper and lower substrates can be characterized by a further increase in the substrate warpage, which can increase by about 10 μm or more, about 15 μm or more, about 20 μm or more, about 25 μm or more, or even more. This can lead to film peeling or an increase in losses on the substrate. However, the inner substrates can be characterized by an increase in warpage of about 10 μm or less, including no increase in wafer warpage and even a decrease in wafer warpage of about 1 μm or more, about 3 μm or more, about 5 μm or more, or even more, i.e., an increase in warpage of about 5 μm or less, about 3 μm or less, about 1 μm or less, or less than that. For example, as shown in FIG. 5, the wafers located in the center of the wafer stack are characterized in some embodiments by having a limited or substantially no warpage regardless of the orientation.

[0033]

[0039] Thus, in some embodiments, the processing step may include using one or more cover wafers during the positioning of the substrate on the carrier. The cover wafer can be formed of any material that can withstand the annealing environment, but in some embodiments, the cover wafer may include a film similar to the internal substrate being annealed. By including a similar substrate such as sapphire having a layer of a similar material such as physically vapor deposited aluminum nitride, the cover wafer can be characterized by a wafer bow similar to other substrates being processed and can improve the annealing effect on the internal wafer. For example, a first cover wafer can be seated on the ledge 410 of the carrier and one or more substrates to be annealed can be seated on the first cover wafer. Although two such substrates are illustrated, in embodiments encompassed by the present technology, about one or more substrates, about two or more substrates, about three or more substrates, about four or more substrates, about five or more substrates, about six or more substrates, about seven or more substrates, about eight or more substrates, about nine or more substrates, about ten or more substrates, or more substrates can be stacked on the first cover wafer.

[0034]

[0040] Next, a second cover wafer can be positioned on one or more of the internal substrates of the stack. As a result, the processed substrate may not be seated directly on the carrier and may contact only in an unobtrusive position such as a point contact against the outer rail of the carrier. In some embodiments, the internal substrates of the stack may hardly contact the carrier or may not contact the carrier at all. Further, in some embodiments, the cover wafer may be characterized as having a diameter larger than the substrate being processed, thereby further ensuring that the substrate does not contact or only minimally contacts the carrier and any temperature effects across the substrate can be reduced.

[0035]

[0041] As shown, the substrates may be positioned in direct contact with each other, and in some embodiments, a buffer layer formed on a first surface of a substrate may be positioned in contact with a second surface of the substrate opposite the first surface, such as the back side of the substrate, of an adjacent substrate or cover wafer being processed. The substrates may all be oriented in the same direction, and in some embodiments, all of the substrates and cover wafers may be positioned downwardly within a stack of carriers. Positioning the substrates downwardly may allow stress imposed by the film to be at least partially canceled by the orientation, and may further facilitate reducing or limiting an increase in film stress or wafer bow during an anneal process. Thus, an internal substrate processed in accordance with an embodiment of the present technology, or any substrate, may be characterized by improved coverage as described above by limiting exposure of the film during anneal, and may limit evaporation or other losses.

[0036]

[0042] X-ray diffraction of the tested substrates has shown that the quality of the substrate or buffer film can be improved by annealing the substrate or buffer film at a sufficient temperature for a sufficient time, and also, for example, while orienting the substrate in a specific configuration, which may improve the consistency across the entire substrate. For example, in an X-ray diffraction rocking curve generated from a buffer layer having an average aluminum nitride thickness of up to 300 nm, a full-width at half-maximum measurement along the (102) crystal direction of about 300 arcseconds or less may occur, and along the (102) crystal direction, a full-width at half-maximum of about 290 arcseconds or less, about 280 arcseconds or less, about 270 arcseconds or less, about 260 arcseconds or less, about 250 arcseconds or less, about 240 arcseconds or less, about 230 arcseconds or less, about 220 arcseconds or less, or less than that may occur. For example, FIGS. 6A-6B show X-ray diffraction rocking curves of aluminum nitride. FIG. 6A shows a curve along the (002) crystal direction and shows the intensity change between the curve before annealing by line 605 and the curve after annealing by curve 610. Similarly, FIG. 6B shows a curve along the (102) crystal direction and shows the intensity change between the curve before annealing by line 615 and the curve after annealing by line 620. These measurements may be consistent across both the x direction, which may be parallel to the wafer flat, and the y direction, which may be perpendicular to the wafer flat. By using the processes and materials according to embodiments of the present technology, high-quality buffer layers can be manufactured, characterized by a reduction in threading dislocations and an improvement in surface coverage. Thereby, the time to manufacture an LED structure on the buffer layer is shortened, and LEDs can be manufactured that are characterized by improved operating efficiency compared to conventionally manufactured devices.

[0037]

[0043] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0038]

[0044] Although several embodiments have been disclosed, those skilled in the art will recognize that various changes, alternative configurations, and equivalents can be used without departing from the gist of the embodiments. Further, many well-known processes and elements have not been described so as not to make the present technology unnecessarily obscure. Accordingly, the above description should not be regarded as limiting the scope of the present technology.

[0039]

[0045] When a range of values is provided, it is to be understood that each intervening value, to the minimum part of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any of the recited values or unrecited intervening values of the recited range and any other recited value or intervening value of that recited range is also included. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each range that includes one or both of the limiting values of the range, or neither of the limiting values of the range, is also included within the technology in accordance with any specifically excluded limiting value in the recited range. When one or both of the limiting values of the recited range are included, ranges excluding one or both of those included limiting values are also included.

[0040]

[0046] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, reference to "LED" includes reference to one or more LEDs well known to those skilled in the art and their equivalents, and the like.

[0041]

[0047] Also, as used in this specification and the following claims, the terms "comprise," "comprising," "contain," "containing," "include," and "including" are intended to specify the presence of the stated feature, integer, component, or step, but do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A method of forming an LED structure, comprising: depositing an aluminum nitride layer onto a substrate via a physical vapor deposition process; transferring the substrate to a carrier after depositing the aluminum nitride layer, wherein a first cover wafer is disposed above the substrate on the carrier and a second cover wafer is disposed below the substrate on the carrier, each of the first cover wafer and the second cover wafer comprising a cover wafer substrate having an aluminum nitride layer thereon, each of the first cover wafer and the second cover wafer being larger in diameter than the substrate; heating the aluminum nitride layer on the substrate to a temperature of about 1500° C. or greater; forming an ultraviolet light emitting diode ("LED") structure on the aluminum nitride layer on the substrate using metal organic chemical vapor deposition or molecular beam epitaxy; The method includes:

2. A method for forming an LED structure as described in claim 1, wherein the carrier comprises carbon, and the carrier defines a ledge on which the substrate sits.

3. 10. The method of claim 1, wherein the first cover wafer and the second cover wafer are oriented in substantially the same direction as the substrate.

4. The method for forming an LED structure as claimed in claim 1 , wherein the substrate is placed face down on the carrier.

5. 10. The method for forming an LED structure of claim 1, wherein at least two substrates are placed in direct contact between the first cover wafer and the second cover wafer on the carrier.

6. The method of claim 1, wherein the aluminum nitride layer on the substrate is heated to a temperature of about 1600°C to about 1800°C.

7. The method of claim 1, wherein the aluminum nitride layer on the substrate is heated to above about 1000° C. for at least 100 minutes.

8. The method for forming an LED structure as described in claim 1, wherein the full width at half maximum of an X-ray diffraction rocking curve along the (102) crystallographic direction of the aluminum nitride layer on the substrate is less than or equal to about 300 arc seconds.

9. The method of claim 1, wherein after heating the aluminum nitride layer on the substrate, the substrate maintains greater than about 85% coverage of the aluminum nitride layer on the substrate.

10. 1. A method of forming an LED structure, comprising: depositing an aluminum nitride layer on the first substrate and the second substrate via a physical vapor deposition process; Positioning the first substrate face down in a carrier and on a first cover wafer; positioning the second substrate face-down in contact with the first substrate; positioning a second cover wafer over the second substrate on the carrier; heating the first substrate and the second substrate to a temperature of about 1500° C. or greater; Including, each of the first cover wafer and the second cover wafer comprises a cover wafer substrate having an aluminum nitride layer thereon, and each of the first cover wafer and the second cover wafer has a larger diameter than each of the first substrate and the second substrate. method.

11. forming an ultraviolet light emitting diode structure on the first substrate and the aluminum nitride layer on the second substrate using metal organic chemical vapor deposition or molecular beam epitaxy; The method for forming an LED structure according to claim 10, further comprising:

12. The method of claim 10, wherein the aluminum nitride layers on the first substrate and the second substrate are heated to a temperature of about 1600°C to about 1800°C.

13. 11. The method of claim 10, wherein the carrier comprises carbon, the carrier defining a ledge upon which both the first substrate and the second substrate sit.

14. 11. The method of forming an LED structure of claim 10, wherein the first cover wafer, the second cover wafer, the first substrate, and the second substrate are each oriented in approximately the same direction.

15. 1. A method of forming an LED structure, comprising: depositing an aluminum nitride layer on a substrate via a physical vapor deposition process; positioning the substrate face down on a first cover wafer positioned on a carrier; Positioning a second cover wafer over the substrate; heating the aluminum nitride layer on the substrate to a temperature of about 1500° C. or greater; forming an ultraviolet light emitting diode ("LED") structure on the aluminum nitride layer on the substrate using metal organic chemical vapor deposition or molecular beam epitaxy; Including, each of the first cover wafer and the second cover wafer includes a cover wafer substrate having an aluminum nitride layer thereon, and each of the first cover wafer and the second cover wafer has a larger diameter than the substrate. method.

16. The method for forming an LED structure of claim 15, wherein the full width at half maximum of an X-ray diffraction rocking curve along the (102) crystallographic direction of the aluminum nitride layer on the substrate is less than or equal to about 300 arc seconds.

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