Light emitting diode device having a current spreading layer - Patents.com

Abstract

A light emitting diode (LED) device is described, the LED device comprising: a plurality of mesas defining pixels, each mesa including a semiconductor layer; an N-contact material in a space between each of the plurality of mesas; a dielectric material insulating a P-type layer and sidewalls of an active region from metal; a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; a hard mask layer over the second portion of the current spreading layer, the hard mask layer having sidewalls defining a hard mask opening; a liner layer conformally deposited in the hard mask opening over the first portion of the current spreading layer and on the sidewalls of the hard mask layer; a P metal material plug on the liner layer; a passivation layer on the hard mask layer; and an underbump metallization on the passivation layer.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to light emitting diode (LED) devices and methods of making the same. More specifically, embodiments are directed to light emitting diode devices that include a current spreading layer. [Background technology]

[0002] A light-emitting diode (LED) is a semiconductor light source that emits visible light when an electric current passes through it. LEDs combine P-type and N-type semiconductors. LEDs typically use III-V compound semiconductors, which are stable at higher temperatures than devices using other semiconductors. III-V compounds are usually fabricated on a sapphire aluminum oxide (Al 2 O 3 ) or silicon carbide (SiC).

[0003] Various emerging display applications, such as wearable devices, head-mounted displays, and large-area displays, require small chips composed of dense arrays of micro-LEDs (μLEDs or uLEDs) with lateral dimensions of less than 100 μm by 100 μm. Micro-LEDs (uLEDs) typically have dimensions smaller than about 50 μm in diameter or width and are used to fabricate color displays by closely arranging micro-LEDs containing red, blue, and green wavelengths. Generally, two approaches have been utilized to assemble displays constructed from individual micro-LED dies. The first is a pick-and-place approach, in which individual blue, green, and red wavelength micro-LEDs are picked up, aligned, and attached to a backplane, which is then electrically connected to a driver integrated circuit. Due to the small size of each micro-LED, this assembly sequence is slow and subject to manufacturing errors. Furthermore, as die sizes decrease to meet the high resolution requirements of displays, more and more dies need to be transferred in each pick-and-place operation to place displays of the required dimensions. The second approach is to bond a group of LEDs, for example a monolithic die or an array or matrix, to a backplane, which eliminates the handling of individual LEDs associated with pick-and-place. Therefore, a method must be developed to efficiently prepare a group of LEDs that may later be used for bonding to an LED backplane. Summary of the Invention

[0004] An embodiment of the present disclosure is directed to a light emitting diode (LED) device, the LED device comprising: a plurality of mesas defining pixels, each mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active region and a P-type layer, each mesa having a height less than or equal to its width; an N-contact material in the space between each mesa, the N-contact material providing optical isolation between each mesa and electrically contacting the N-type layer of each mesa along sidewalls of the N-type layer; a dielectric material insulating the P-type layer and sidewalls of the active region from the N-contact material; a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; a hardmask layer over the second portion of the current spreading layer, the hardmask layer having sidewalls defining a hardmask opening; a liner layer conformally deposited in the hardmask opening over the first portion of the current spreading layer and on the sidewalls of the hardmask layer; A P metal material plug on the liner layer; a passivation layer on the hardmask layer; an under-bump metallization on the passivation layer;

[0005] Additionally, embodiments of the present disclosure are directed to a method of manufacturing a light emitting diode device (LED device), the method comprising: depositing a plurality of semiconductor layers on a substrate, the semiconductor layers including an N-type layer, an active region, and a P-type layer; depositing a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; depositing a hard mask layer over the current spreading layer; partially etching the hard mask layer, the current spreading layer, and the semiconductor layer to form a plurality of mesas and trenches that define pixels, each of the plurality of mesas including the semiconductor layer, each of the mesas having a height that is less than or equal to its width; depositing a first dielectric material in the trench; etching the hardmask layer to form sidewalls in the hardmask layer and define a hardmask opening with a first portion of the current spreading layer; depositing a liner layer over the substrate in the trench and in the hardmask opening; depositing a metal on a liner layer on the substrate; planarizing the substrate to form an N-contact material that provides optical isolation between each mesa and electrically contacts the N-type layer of each mesa along sidewalls of the N-type layer and a P metal material plug on a liner layer; depositing a passivation layer over the substrate and forming an opening therein; depositing an under bump metallization over the substrate, over the passivation layer and within the opening in the passivation layer. [Brief description of the drawings]

[0006] So that the above features of the present disclosure can be understood in detail, a more particular description of the disclosure briefly summarized above can be had by reference to some embodiments illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the present disclosure and are therefore not to be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments. The embodiments described herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references denote like elements. [Figure 1A] FIG. 1A illustrates a cross-sectional view of a stack of semiconductor layers, metal layers (eg, a p-contact layer), and dielectric layers (eg, a hardmask layer) deposited on a substrate in accordance with one or more embodiments. [Figure 1B] FIG. 1B illustrates a cross-section of a stack after a step during the manufacture of an LED device according to one or more embodiments. [Figure 1C] FIG. 1C illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1D] FIG. 1D illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1E] FIG. 1E illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1F]FIG. IF illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1G] FIG. 1G illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1H] FIG. 1H illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1I] FIG. 1I illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1J] FIG. 1J illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1K] FIG. 1K illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1L] FIG. 1L illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1M] FIG. 1M illustrates a cross-section of the stack after a step during the fabrication of an LED device according to one or more embodiments. [Figure 1N] FIG. 1N is an enlarged view of a portion of the stack of FIG. 1E, indicated by the dotted edge 1N in FIG. 1E. [Figure 1O] FIG. 1O illustrates a cross-section of a completed stack at a step during the manufacture of an LED device according to one or more embodiments. [Diagram 2] FIG. 2 is a diagram illustrating a top view of an LED array according to one or more embodiments. [Figure 3A] FIG. 3A illustrates a process flow diagram of a manufacturing method according to one or more embodiments. [Figure 3B] FIG. 3B illustrates a process flow diagram of a manufacturing method according to one or more embodiments. [Figure 3C]FIG. 3C illustrates a process flow diagram of a manufacturing method according to one or more embodiments. [Figure 3D] FIG. 3D illustrates a process flow diagram of a manufacturing method according to one or more embodiments. [Figure 3E] FIG. 3E illustrates a process flow diagram of a manufacturing method according to one or more embodiments. [Figure 3F] FIG. 3F illustrates a process flow diagram of a manufacturing method according to one or more embodiments. [Figure 4] FIG. 4 illustrates a cross-sectional view of an LED device according to one or more embodiments. [Figure 5A] FIG. 5A shows a variation of FIG. 1G for an embodiment creating a pixelated common cathode. [Figure 5B] FIG. 5B shows a variant of FIG. 1O based on further processing of the stack according to FIG. 5A.

[0007] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the drawings. The drawings are not drawn to scale. For example, the height and width of the mesas are not drawn to scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Before describing several example embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of structure or process steps set forth in the following description, as the methods and apparatuses may be implemented in other embodiments, practiced, or carried out in various ways.

[0009] In accordance with one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process acts. Furthermore, references to a substrate in some embodiments may refer to only a portion of the substrate unless the context clearly indicates otherwise. Furthermore, references to deposition on a substrate in accordance with some embodiments include deposition on a bare substrate or deposition on a substrate having one or more films, features or materials deposited or formed thereon.

[0010] In one or more embodiments, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. In exemplary embodiments, the substrate surface on which treatment is performed includes silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and other suitable materials such as metals, metal nitrides, III-nitrides (e.g., GaN, AlN, InN, alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, light emitting diode (LED) devices. The substrate in some embodiments is exposed to a pretreatment process that polishes, etches, reduces, oxidizes, hydroxylates, anneals, UV cures, e-beam cures, and / or bakes the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, in some embodiments, any of the disclosed film treatment steps are also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0011] The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, as used herein, a wafer serves as a substrate for the formation of the LED devices described herein.

[0012] Micro LEDs (uLEDs) refer to light emitting diodes that have one or more characteristic dimensions (e.g., height, width, depth, thickness, etc.) that are less than 100 micrometers. In one or more embodiments, one or more of the dimensions height, width, depth, and thickness have a value in the range of 2 to 25 micrometers.

[0013] 1A is a cross-sectional view of a stack of semiconductor layers, metal layers (e.g., p-contact layers), and dielectric layers (e.g., hardmask layers) deposited on a substrate during a step of fabricating an LED device according to one or more embodiments. Referring to FIG. 1A, a semiconductor layer 104 is grown on a substrate 102. The semiconductor layer 104 according to one or more embodiments includes an epitaxial layer, a III-nitride layer, or an epitaxial III-nitride layer.

[0014] The substrate may be any substrate known to one of skill in the art. In one or more embodiments, the substrate comprises one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate is unpatterned prior to growth of the epitaxial layer(s). Thus, in some embodiments, the substrate is unpatterned and can be considered to be flat or substantially flat. In other embodiments, the substrate can be patterned, for example a patterned sapphire substrate (PSS).

[0015] In one or more embodiments, the semiconductor layer 104 comprises a III-nitride material, and in particular embodiments, an epitaxial III-nitride material. In some embodiments, the III-nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layer 104 comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (InAlN), aluminum indium gallium nitride (AlInGaN), and the like. In one or more specific embodiments, the semiconductor layer 104 comprises a p-type layer, an active region, and an n-type layer. In one or more embodiments, the semiconductor layer 104 comprises a III-nitride material, and in particular embodiments, an epitaxial III-nitride material. In some embodiments, the III-nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layer 104 is comprised of one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc. In one or more specific examples, the semiconductor layer 104 includes a p-type layer, an active region, and an n-type layer.

[0016] In one or more embodiments, the substrate 102 is placed into a metalorganic vapor phase epitaxy (MOVPE) reactor to epitaxy the LED device layers to grow the semiconductor layer 104 .

[0017] In one or more embodiments, the semiconductor layer 104 is comprised of a stack of undoped and doped III-nitride materials. The III-nitride materials can be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg), depending on whether a p-type or n-type III-nitride material is desired. In a specific embodiment, the semiconductor layer 104 is comprised of an N-type layer 104n, an active region 106, and a P-type layer 104p.

[0018] In one or more embodiments, the semiconductor layer 104 has a composite thickness in the range of about 2 μm to about 10 μm, including ranges of about 2 μm to about 9 μm, 2 μm to about 8 μm, 2 μm to about 7 μm, 2 μm to about 6 μm, 2 μm to about 5 μm, 2 μm to about 4 μm, 2 μm to about 3 μm, 3 μm to about 10 μm, 3 μm to about 9 μm, 3 μm to about 8 μm, 3 μm to about 7 μm, 3 μm to about 6 μm, 3 μm to about 5 μm, 3 μm to about 4 μm, , 4 μm to about 10 μm, 4 μm to about 9 μm, 4 μm to about 8 μm, 4 μm to about 7 μm, 4 μm to about 6 μm, 4 μm to about 5 μm, 5 μm to about 10 μm, 5 μm to about 9 μm, 5 μm to about 8 μm, 5 μm to about 7 μm, 5 μm to about 6 μm, 6 μm to about 10 μm, 6 μm to about 9 μm, 6 μm to about 8 μm, 6 μm to about 7 μm, 7 μm to about 10 μm, 7 μm to about 9 μm, or 7 μm to about 8 μm.

[0019] In one or more embodiments, the active region 106 is formed between the n-type layer 104n and the p-type layer 104p. The active region 106 may be composed of any suitable material known to one of ordinary skill in the art. In one or more embodiments, the active region 106 is composed of a multiple quantum well (MQW) of III-nitride material and a III-nitride electron blocking layer.

[0020] In one or more embodiments, the P contact layer 105 and the hard mask layer 108 are deposited on the p-type layer 104p. As shown, the P contact layer is deposited on the p-type layer 104p and the hard mask layer 108 is on the P contact layer. In some embodiments, the P contact layer 105 is deposited directly on the p-type layer 104p. In other embodiments, there may be one or more additional layers between the p-type layer 104p and the P contact layer 105, not shown. In some embodiments, the hard mask layer 108 is deposited directly on the P contact layer 105. In other embodiments, there may be one or more additional layers between the hard mask layer 108 and the P contact layer 105, not shown. The hard mask layer 108 and the P contact layer 105 may be deposited by any suitable technique known to one of skill in the art. In one or more embodiments, the hard mask layer 108 and the P contact layer 105 are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0021] "Sputter deposition" here refers to the physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material, such as a metal, is ejected from a source, or target, onto a substrate. The technique is based on ion bombardment of the source material, or target, which results in a purely physical process, i.e. the sputtering of the target material into vapor.

[0022] As used by some embodiments herein, "atomic layer deposition" (ALD) or "cyclical deposition" refers to a gas-phase technique used to deposit thin films on a substrate surface. The process of ALD involves exposing a surface of a substrate or a portion of a substrate to alternating precursors, i.e., two or more reactive compounds, to deposit layers of material on the substrate surface. When a substrate is exposed to alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a processing chamber, and the substrate or a portion of the substrate is exposed to the precursors separately.

[0023] According to some embodiments, as used herein, "chemical vapor deposition (CVD)" refers to a process in which a film of material is deposited from the gas phase by decomposition of chemicals on a substrate surface. In CVD, the substrate surface is exposed to precursors and / or co-reactants simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either simultaneous flow or where there is a significant overlap in the exposure of the precursors.

[0024] As used herein in accordance with some embodiments, "plasma-enhanced atomic layer deposition (PEALD)" refers to a technique for depositing thin films on a substrate. In some instances of PEALD processes compared to thermal ALD processes, materials can be formed from the same chemical precursors, but at higher deposition rates and lower temperatures. PEALD processes generally sequentially introduce reactant gases and reactant plasmas into a process chamber with a substrate in the chamber. A first reactant gas is pulsed into the process chamber and adsorbed on the substrate surface. A reactant plasma is then pulsed into the process chamber and reacts with the first reactant gas to form a deposited material, such as a thin film, on the substrate. As with thermal ALD processes, a purge step can be performed between the delivery of each reactant.

[0025] As used herein according to one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing thin films on a substrate. In a PECVD process, a source material in a gas or liquid phase, for example, a liquid phase III-nitride material vapor or a gas phase III-nitride material entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiating gas is also introduced into the chamber. When a plasma is generated in the chamber, excited radicals are generated. The excited radicals chemically bond to the surface of a substrate placed in the chamber to form a desired film thereon.

[0026] In one or more embodiments, the hard mask layer 108 can be fabricated using materials and patterning techniques known in the art. In some embodiments, the hard mask layer 108 comprises a metal or a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that the use of a formula such as SiO to represent silicon oxide does not imply a particular stoichiometric relationship between elements. The formula simply identifies the basic components of the film.

[0027] In one or more embodiments, the P contact layer 105 may include any suitable metal known to one of ordinary skill in the art, hi one or more embodiments, the P contact layer 105 includes silver (Ag).

[0028] 1B is a cross-sectional view of a stack after a step in the fabrication of an LED device 100 according to one or more embodiments. With reference to FIG. 1B, the hard mask layer 108 and the P contact layer 105 are patterned to form at least one opening 110 in the hard mask layer 108 and the P contact layer 105 to expose a top surface 104t of the semiconductor layer 104 and sidewalls 108s, 105s of the hard mask layer 108 and the P contact layer 105, respectively.

[0029] In one or more embodiments, the hardmask layer 108 and the P contact layer 105 are patterned by any suitable patterning technique known to one of ordinary skill in the art. In one or more embodiments, the hardmask layer 108 and the P contact layer 105 are patterned by etching. According to one or more embodiments, conventional masking, wet etching and / or dry etching processes can be used to pattern the hardmask layer 108 and the P contact layer 105.

[0030] In other embodiments, nanoimprint lithography is used to transfer the pattern into the hard mask layer 108 and the P contact layer 105. In one or more embodiments, the substrate 102 is etched in a reactive ion etching (RIE) tool using conditions that effectively etch the hard mask layer 108 and the P contact layer 105, but very slowly or not at all the p-type layer 104p. In other words, the etch is selective to the P contact layer 105 and the hard mask layer 108 over the p-type layer 104p. It is understood that the patterning step can use masking techniques to achieve the desired pattern.

[0031] FIG. 1C is a cross-sectional view of the stack after one step in the manufacturing stage of the LED device 100 according to one or more embodiments. Referring to FIG. 1C, an inner spacer 112 is deposited on the top surface 104t of the semiconductor layer 104 and on the sidewalls 108s, 105s of the hard mask layer 108 and the P-contact layer 105. The inner spacer 112 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer 112 comprises a dielectric material. The deposition of the material forming the inner spacer is typically performed conformally with the substrate surface, followed by etching to obtain the inner spacer on the sidewalls 108s, 105s but not on the top surface 104b of the semiconductor layer 104.

[0032] The term "dielectric" as used herein refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the inner spacer 112 includes, but is not limited to, oxides, such as, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), and nitrides, such as, for example, silicon nitride (Si3N4). In one or more embodiments, the dielectric inner spacer 112 includes, but is not limited to, silicon nitride (Si3N4). 3 N 4 In another embodiment, the inner spacer 112 comprises silicon oxide (SiO 2 ). In some embodiments, the inner spacer 112 composition is non-stoichiometric with respect to an ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxycarbides (e.g., silicon carbide (SiOC)), and oxynitrocarbides (e.g., silicon oxycarbonitride (SiNCO)).

[0033] In some embodiments, the inner spacer 112 can be a distributed Bragg reflector (DBR). As used herein, a "distributed Bragg reflector" refers to a structure (e.g., a mirror) formed from a multi-layer stack of alternating thin-film materials with varying refractive indices, e.g., high and low refractive indices.

[0034] In one or more embodiments, the inner spacer 112 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0035] In one or more embodiments, the inner spacer 112 has a thickness in the range of about 200 nm to about 1 μm, e.g., about 300 nm to about 1 μm, about 400 nm to about 1 μm, about 500 nm to about 1 μm, about 600 nm to about 1 μm, about 700 nm to about 1 μm, about 800 nm to about 1 μm, about 900 nm to about 1 μm, about 200 nm to about 900 nm, about 300 nm to about 900 nm, about 400 nm to about 900 nm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 200 nm to about 800 nm, about 300 nm to about 8 ...1 μm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 400 nm to about 1 μm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 200 nm to about 800 nm, about 300 In one embodiment, the thickness of the film is about 00 nm to about 800 nm, about 500 nm to about 800 nm, about 600 nm to about 800 nm, about 700 nm to about 800 nm, about 200 nm to about 700 nm, about 300 nm to about 700 nm, about 400 nm to about 700 nm, about 500 nm to about 700 nm, about 600 nm to about 700 nm, about 200 nm to about 600 nm, about 300 nm to about 600 nm, about 400 nm to about 600 nm, about 500 nm to about 600 nm, about 200 nm to about 500 nm, about 300 nm to about 500 nm, about 300 nm to about 400 nm, about 200 nm to about 400 nm, or about 300 nm to about 400 nm. About 400 nanometers to about 500 nanometers, about 300 nanometers to about 400 nanometers, about 200 nanometers to about 400 nanometers or about 300 nanometers.

[0036] FIG 1D is a cross-sectional view of a stack after a step in the fabrication of an LED device 100 according to one or more embodiments. Referring to FIG 1D, the semiconductor layer 104 is etched to form at least one mesa, e.g., a first mesa 150a and a second mesa 150b. In the embodiment shown in FIG 1D, the first mesa 150a and the second mesa 150b are separated by a trench 111, referred to as trench 111. Each trench 111 has a sidewall 113.

[0037] FIG. 1E is a cross-sectional view of the stack after one step in the manufacturing stage of the LED device 100 according to one or more embodiments. Referring to FIG. 1E, an outer spacer 114 is deposited on the sidewall 113 of the trench 111. The outer spacer 114 can be composed of any suitable material known to those skilled in the art. In one or more embodiments, the outer spacer 114 comprises a dielectric material. As described below with reference to FIG. 1I, the dielectric material insulates the sidewalls of the P-type layer 104p (sidewall 104s) and the sidewalls of the active area 106 (sidewall 106s) from the metal deposited in the trench 111. The deposition of the material forming the outer spacer is typically performed conformally with the substrate surface and then etched to obtain the outer spacer on the sidewall of the trench, but not on the side of the trench or on top of the hard mask layer.

[0038] In one or more embodiments, the outer spacer 114 may be made of, for example, silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), for example, silicon nitride (Si 3 In one or more embodiments, the outer spacer 114 may include a nitride such as silicon nitride (SiN4). 3 N 4 In another embodiment, the outer spacer 114 comprises silicon oxide (SiO 2 ). In some embodiments, the outer spacer 114 can be a distributed Bragg reflector (DBR).

[0039] In one or more embodiments, the outer spacer 114 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0040] FIG. 1N is an enlarged view of a portion of the stack of FIG. 1E, indicated by the dotted edge 1N in FIG. 1E.

[0041] In one or more embodiments, a dark space or dark space gap 117 is formed between adjacent edges 105e of the P contact layer 105 on the first mesa 150a and the second mesa 150b, as shown in Figures 1B, 1E, and 1N. In one or more embodiments, the dark space gap 117 formed between adjacent edges 105e of the P contact layer 105 on the first mesa 150a and the second mesa 150b is formed to be in the range of 10 μm to 0.5 μm, or in the range of 9 μm to 0.5 μm, or in the range of 8 μm to 0.5 μm, or in the range of 7 μm to 0.5 μm, or in the range of 6 μm to 0.5 μm, or in the range of 5 μm to 0.5 μm, or in the range of 4 μm to 0.5 μm, or in the range of 3 μm to 0.5 μm. In other embodiments, the dark space gap 117 formed between adjacent edges 105e of the P contact layer 105 on the first mesa 150a and the second mesa 150b is in the range of 10 μm to 4 μm, such as in the range of 8 μm to 4 μm. In an embodiment of the LED device 100, each of the plurality of spaced apart mesas 150a, 150b comprises a conductive and reflective P contact layer 105 extending across a portion of each of the plurality of mesas 150a, 150b including the edge 105e, and a trench 11 between each of the plurality of spaced apart mesas, resulting in a pixel pitch in the range of 1 μm to 100 μm, 40 μm to 100 μm, 41 μm to 100 μm, and all values ​​and subranges therebetween, and a dark space gap 117 between adjacent edges of the P contact layer that is less than 20% of the pixel pitch. In some examples, the pixel pitch is in the range of 5 μm to 100 μm, 10 μm to 100 μm, or 15 μm to 100 μm. In some embodiments, when the pixel pitch is in the range of 10 μm to 100 μm, the dark space gap 117 between adjacent edges of the P contact layer is greater than 1% of the pixel pitch and is less than 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, or 5% of the pixel pitch.

[0042] In one or more embodiments, each of the spaced apart mesas 150a, 150b includes a sidewall 104s, each sidewall having a first segment 104s1 and a second segment 104s2 (shown in FIG. 1M). The first segment 104s1 defines an angle "a" (as shown in FIG. 1N) ranging from 60 degrees to 90 degrees from a horizontal plane 129 parallel to the N-type layer 104n and the P-type layer 104p. In some embodiments, angle "a" is in the range of 60 degrees to 85 degrees, 60 degrees to 80 degrees, 60 degrees to 75 degrees, 60 degrees to 70 degrees, 65 degrees to 90 degrees, 65 degrees to 85 degrees, 65 degrees to 80 degrees, 65 degrees to 75 degrees, 65 degrees to 70 degrees, 70 degrees to 90 degrees, 70 degrees to 85 degrees, 70 degrees to 80 degrees, 70 degrees to 75 degrees, 75 degrees to 90 degrees, 75 degrees to 85 degrees, 75 degrees to 80 degrees, 80 degrees to 90 degrees, or 80 degrees to 85 degrees. In one or more embodiments, the second segment 104s2 of the sidewall forms an angle with the top surface of the substrate on which the mesa is formed that is in the range of 75° to less than 90°.

[0043] 1F is a cross-sectional view of the stack after one step in the manufacturing stage of the LED device 100 according to one or more embodiments. Referring to FIG. 1F, the semiconductor layer 104 is etched to widen the trench 111 (i.e., increase the depth of the trench) and expose the top surface 102t of the substrate 102. In one or more embodiments, the etch is selective, so that outer spacers 114 remain on the sidewalls of the trench 111. In one or more embodiments, the trench 111 has a bottom 111b and sidewalls 113. In one or more embodiments, the trench 111 has a depth in the range of about 0.5 μm to about 2 μm from the top surface 104t of the semiconductor layer that forms the mesa.

[0044] 1G is a cross-sectional view of a stack after a step in the fabrication of LED device 100 in accordance with one or more embodiments. Referring to FIG. 1G, first mesa 150a and second mesa 150b are patterned to form via openings 116 in the top surfaces of the mesas, exposing the top surface of semiconductor layer 104 and / or the top surface of P-contact layer 105. In one or more embodiments, first mesa 150a and second mesa 150b can be patterned by any suitable technique known to one of ordinary skill in the art, such as masking and etching processes used in semiconductor processing.

[0045] 1H is a cross-sectional view of the stack after one step in the manufacturing stage of the LED device 100 according to one or more embodiments. Referring to FIG. 1H, a reflective liner 130 is deposited on the substrate, on the sidewalls 113 and bottom 111b of the trench 111, on the sidewalls of the outer spacer 114, and along the hard mask layer 108 surface and the top surface of the semiconductor layer 104 and / or the top surface of the P-contact layer 105. The reflective liner 130 can be composed of any suitable material known to one of ordinary skill in the art. In one or more embodiments, the reflective liner 130 is composed of aluminum (Al).

[0046] In one or more embodiments, the reflective liner 130 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD), etc. In one or more embodiments, the deposition of the reflective liner 130 is selective, such that the reflective liner 130 is deposited only on the sidewalls 113 of the trench 111 and the sidewalls of the outer spacers 114.

[0047] FIG. 1I is a cross-sectional view of a stack after one step in the manufacturing stage of an LED device according to one or more embodiments. Referring to FIG. 1I, an electrode metal 118 for obtaining, for example, an N-contact material 118n and / or a P-metal material plug 118p and / or a conductive metal 118c in the final product is deposited on the substrate, including the top of the mesas 150a, 150b, the via opening 116, and the trench 111. The electrode metal 118 may include any suitable material known to those skilled in the art. In one or more embodiments, the electrode metal 118 includes copper, and the electrode metal material 118 is deposited by electrochemical deposition (ECD) of copper.

[0048] 1J is a cross-sectional view of the stack after a step in the fabrication of LED device 100 according to one or more embodiments. Referring to FIG. 1J, electrode metal 118 is planarized, etched, or polished. N contact material 118n and P metal material plug 118p result from electrode metal 118. As used herein, the term "planarized" refers to a process that smoothes a surface, including, but not limited to, chemical mechanical polishing / planarization (CMP), etching, and the like.

[0049] FIG. 1K is a cross-sectional view of a stack after one step in the manufacturing stage of an LED device 100 according to one or more embodiments. Referring to FIG. 1K, a passivation layer 120 is deposited on the substrate. In some embodiments, the passivation layer 120 is deposited directly on the planarized N contact material 118n, the planarized P metal material plug 118p, the top surface of the inner spacer 112, the top surface of the outer spacer 114, and the top surface of the hard mask layer 108. In other embodiments, there can be one or more additional layers between the passivation layer 120 and the planarized N contact material 118n, the planarized P metal material plug 118p, the top surface of the inner spacer 112, the top surface of the outer spacer 114, and the top surface of the hard mask layer 108. In some embodiments, the passivation material comprises the same material as the hard mask layer 108. In other embodiments, the passivation layer 120 comprises a different material than the hard mask layer 108.

[0050] In one or more embodiments, the passivation layer 120 may be deposited by any suitable technique known to one of skill in the art. In one or more embodiments, the passivation layer 120 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0051] In one or more embodiments, the passivation layer 120 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the passivation layer 120 includes a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof.

[0052] 1L is a cross-sectional view of a stack after a step in the fabrication of an LED device 100 according to one or more embodiments. Referring to FIG. 1L, the passivation layer 120 is patterned to form at least one opening 122, exposing a top surface of the P metal material plug 118p. Two openings 122 are shown. The passivation layer 120 can be patterned using any suitable technique known to one of ordinary skill in the art, including, but not limited to, lithography, wet etching, or dry etching.

[0053] FIG. 1M is a cross-sectional view of the stack after one step in the manufacturing phase of the LED device 100 according to one or more embodiments. Referring to FIG. 1M, an under bump metallization (UBM) material forms an under bump metallization (UBM) layer 124a, which is deposited in the opening 122. As used herein, "under bump metallization (UBM)" refers to a metal layer required to connect a die to a substrate with solder bumps for flip chip packaging. In one or more embodiments, the UBM layer 124a can be a thin film stack of patterned materials that provide electrical connection from the die to the solder bumps, provide a barrier function to limit undesired diffusion from the bumps to the die, and provide mechanical interconnection of the solder bumps to the die through adhesion to the die passivation and attachment to the solder bump pads. The UBM layer 124a can include any suitable metal known to one of ordinary skill in the art. In one or more embodiments, the UBM layer 124a can include gold (Au).

[0054] In one or more embodiments, the under bump metallization (UBM) can be achieved by any technique known to one of ordinary skill in the art, including, but not limited to, dry vacuum sputtering combined with electroplating, which in one or more embodiments consists of multi-metal layers sputtered in a high temperature gas phase system.

[0055] In FIG. 1M, the UBM layer 124a is patterned (e.g., by masking and etching). The UBM layer 124a can be patterned using any suitable technique known to one of ordinary skill in the art, including, but not limited to, lithography, wet etching, or dry etching. The patterning of the UBM layer 124a provides an anode pad in first mesa 150a and second mesa 150b that contacts the P metal material plug 118p across the P contact layer 105.

[0056] FIG. 1O is a diagram illustrating a cross section of a completed LED device according to one or more embodiments. Referring to FIG. 1O, the completed LED device 100 includes the features shown in FIG. 1M and further includes a common electrode (common cathode) 140 formed at an edge of the device 100 in cross section. The UBM material is patterned to provide an anode pad 124a that contacts a P metal material plug 118p across the P contact layer 105 in the first mesa 150a and the second mesa 150b. The common cathode 140 includes a conductive metal 118c. Additionally, an under bump metallization (UBM) material provides a cathode pad 124c that contacts the common cathode 140, patterned similarly to the UBM layer 124a. In one or more embodiments, the plurality of spaced apart mesas 150a, 150b define a matrix of pixels, which are surrounded by the common electrode 140.

[0057] In one or more embodiments, the common electrode 140 is a pixelated common cathode including multiple semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stack includes a semiconductor layer 104, which, according to one or more embodiments, includes an epitaxial layer, a III-nitride layer, or an epitaxial III-nitride layer. In certain embodiments, one or more of the semiconductor layers includes GaN.

[0058] To fabricate the pixelated common electrode, processing proceeds according to Figures 1A to 1F, but this time, instead of preparing the via opening 116 as shown in Figure 1G, a portion of the mesa is etched to expose the top surface of the semiconductor layer. Referring to Figure 5A, the third mesa 150c and the fourth mesa 150d are etched to expose the top surface 104t of the semiconductor layer 104, forming the semiconductor stacks 151c and 151d, respectively. That is, the inner spacer 112, the hard mask layer 108, and the P contact layer 105 on the third mesa 150c and the fourth mesa 150d are removed. The sidewalls of the third mesa 150c and the fourth mesa 150d are exposed by etching the outer spacer 114. Processing of the third mesa 150c and the fourth mesa 150d then proceeds according to the following: FIG. 1H Adding a reflective liner layer 130; FIG. 1I Depositing electrode material 118. 1J-1M As shown in FIG. 5B, a pixelated common cathode is formed.

[0059] In the embodiment of FIG. 5B, the completed LED device 101 includes the features shown in FIG. 5A and then processed according to FIGS. 1H-1M, including a common electrode (common cathode) 141 formed at the edge of the device 101 as viewed in cross section in FIG. 1M. The UBM material is patterned to provide an anode pad 124a that contacts the P metal material plug 118p across the P contact layer 105 in the first mesa 150a and the second mesa 150b. The third mesa 150c and the fourth mesa 150d define or form semiconductor stacks 151c and 151d, respectively, surrounded by conductive metal 118c. The semiconductor stacks 151c and 151d are inactive in that they do not generate light. Additionally, the under bump metallization (UBM) material provides a cathode pad 124c, patterned similarly to the UBM layer 124a, that contacts the common cathode 141.

[0060] 2 shows a plan view of an LED monolithic array 200 including a plurality of pixels 155 (of which 155a and 155b are examples) defined or formed by a plurality of spaced apart mesas as described herein with respect to FIGS. 1A-1O. For example, a first mesa 150a defines or forms a first pixel 155a, and a second mesa 150b defines or forms a second pixel 155b. A third mesa 150c and a fourth mesa 150d form or provide inactive pixels or semiconductor stacks 151c and 151d. The pixels 155 are arranged in a grid and connected by a common cathode 140. In one or more embodiments, the array of spaced apart mesas includes an arrangement of mesas in two directions. For example, an array may include 2x2 mesas, 4x4 mesas, 20x20 mesas, 50x50 mesas, 100x100 mesas, or an arrangement of n1xn2 mesas, where each of n1 and n2 is a number in the range of 2 to 1000, and n1 and n2 may be equal or unequal.

[0061] One or more embodiments provide a light emitting diode (LED) device 100 including a plurality of spaced apart mesas 150a, 150b defining pixels 155a, 155b, each of the plurality of spaced apart mesas including a semiconductor layer 104, the semiconductor layer including an N-type layer 104n, an active region 106, and a P-type layer 104p, the spaced apart mesas 150a, 150b having a height H and a width W, the height H being less than or equal to the width W. The LED device 100 further includes a metal 118 in the form of a trench 111 between each of the plurality of spaced apart mesas 150a, 150b, the metal 118 providing optical isolation between each of the spaced apart mesas 150a, 150b and in electrical contact with the N-type layer 104n of each of the spaced apart mesas 150a, 150b along sidewalls of the N-type layer 104n. In one or more embodiments, the LED device 100 includes a first dielectric material 114 that insulates the sidewalls of the P-type layer 104p (sidewalls 104s) and the active region 106 (sidewalls 106s) from the N-contact material 118n. The P metal material plugs 118p are in electrical communication with the p-contact layer 105. In an embodiment of the LED device 100, the plurality of spaced apart mesas 150a, 150b each include a conductive p-contact layer 105 that extends across a portion of each of the plurality of mesas 150a, 150b to include an edge 105e, and the trenches 111 between each of the plurality of spaced apart mesas provide a pixel pitch in the range of 1 μm to 100 μm, including the range of 51 μm to 100 μm, and all values ​​and subranges therebetween, and a dark space gap 117 between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5 μm to 100 μm, 10 μm to 100 μm, or 15 μm to 100 μm. In other embodiments, the dark space gap 117 is in the range of 10 μm to 0.5 μm, such as in the range of 10 μm to 4 μm, such as in the range of 8 μm to 4 μm. As used herein in accordance with one or more embodiments and as shown in FIG. 1O, "pixel pitch" refers to the distance or spacing 119 between centers "C" of adjacent pixels provided or formed by mesas 150a, 150b. That is, pixel pitch refers to the center-to-center spacing 119 of adjacent pixels.2 is the same for adjacent pixels 155a, 155b and all adjacent pixels of array 200. In one or more embodiments, the pixel pitch is in the range of 5 μm to 100 μm, e.g., 5 μm to 90 μm, 5 μm to 80 μm, 5 μm to 70 μm, 5 μm to 60 μm, 5 μm to 50 μm, 5 μm to 40 μm, 5 μm to 30 μm, 10 μm to 90 μm, 10 μm to 80 μm, 10 μm to 70 μm, 10 μm to 60 μm, 10 μm to 50 μm, 10 μm to 40 μm, 10 μm to 30 μm, 20 μm to 90 μm, 20 μm to 80 μm, 20 μm to 70 μm. m, 20 μm to 60 μm, 20 μm to 50 μm, 20 μm to 40 μm, 20 μm to 30 μm, 30 μm to 90 μm, 30 μm to 80 μm, 30 μm to 70 μm, 30 μm to 60 μm, 30 μm to 50 μm, 30 μm to 40 μm, 40 μm to 90 μm, 40 μm to 80 μm, 40 μm to 70 μm, 40 μm to 60 μm, 40 μm to 50 μm, 50 μm to 90 μm, 50 μm to 80 μm, 50 μm to 70 μm, or 50 μm to 60 μm.

[0062] In one or more embodiments, a light emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas having a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each of the mesas having a height less than or equal to its width; an N-contact material in a space between each of the plurality of mesas, the N-contact material providing optical isolation between each of the plurality of mesas and electrically contacting the N-type layer of each of the mesas along a sidewall of the N-type layer; and a dielectric material insulating the sidewalls of the P-type layer and the active region from the N-contact material, each of the plurality of mesas having a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, the space between each of the plurality of mesas resulting in a pixel pitch in the range of 10 μm to 100 μm, and a dark space gap between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In one or more embodiments, the P-contact layer 105 includes a reflective metal. The LED device of claim 1 has a pixel pitch in the range of 4 to 100 μm. In one or more embodiments, the dark space gap between adjacent edges of the p-contact layer is less than 10% of the pixel pitch. Wherein, in the LED device of claim 1, the semiconductor layer is an epitaxial semiconductor layer having a thickness in the range of 2 μm to 10 μm. In one or more embodiments, the dielectric material is in the form of an external spacer comprising a material selected from the group consisting of SiO2, AlOx, and SiN having a thickness in the range of 200 nm to 1 μm. In one or more embodiments, the N-contact material has a depth in the range of 0.5 μm to 2 μm from a top surface of the mesa. In one or more embodiments, each mesa includes a sidewall having a first segment and a second segment, respectively, the first segment of the sidewall defining an angle in the range of 60° to 90° from a horizontal plane parallel to the N-type layer and the P-type layer, and the second segment of the sidewall defining an angle in the range of 75° to less than 90° with a top surface of a substrate on which the mesa is formed.

[0063] In one or more embodiments, a light emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas having a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each of the mesas having a height less than or equal to its width; metal in spaces between each of the plurality of mesas, the metal providing optical isolation between each of the plurality of mesas and electrically contacting the N-type layer of each of the mesas along a sidewall of the N-type layer; and a dielectric material insulating the sidewalls of the P-type layer and the active region from an N-contact material; each of the plurality of mesas has a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, the space between each of the plurality of mesas resulting in a pixel pitch in the range of 10 μm to 100 μm, and a dark space gap between adjacent edges of the p-contact layer in the range of 4 μm to 10 μm. The plurality of mesas includes an array of mesas. In one or more embodiments, the dark space gap is in the range of 4 μm to 8 μm. In one or more embodiments, the pixel pitch is in the range of 40 μm to 100 μm.

[0064] One or more embodiments of the present disclosure provide a method for manufacturing an LED device. FIGS. 3A-3F show process flow diagrams according to various embodiments. Referring to FIG. 3A, method 200 includes manufacturing a substrate in operation 202. The manufacturing of the substrate includes depositing a plurality of semiconductor layers on the substrate, including but not limited to an N-type layer, an active region, and a P-type layer. Once the semiconductor layers are deposited on the substrate, portions of the semiconductor layers are etched to form trenches and a plurality of spaced apart mesas. In operation 204, a die is manufactured. The manufacturing of the die includes depositing a (first) dielectric material to insulate the sidewalls of the epitaxial layers (e.g., the N-type layer, the active region, and the P-type layer), followed by depositing an electrode metal in the trenches, e.g., in the spaces between each of the plurality of spaced apart mesas. In some embodiments, the manufacturing of the die further includes depositing a P-contact layer and a hard mask, forming a current spreading film, plating a p-metal material plug, followed by under bump metallization (UBM). In operation 204, the die is manufactured. Optional microbumping can occur on a complementary metal oxide semiconductor (CMOS) backplane in operation 206. Back-end processing occurs in operation 208, whereupon the die is optionally attached to the CMOS backplane, underfill is provided, laser lift-off occurs, and then optionally phosphor is integrated.

[0065] 3B, in one embodiment, the method 210 includes depositing a plurality of semiconductor layers, including an N-type layer, an active region, and a P-type layer, on a substrate at 212. At 214, the method further includes etching a portion of the semiconductor layer to form a plurality of spaced apart mesas defining trenches and pixels, each of the plurality of spaced apart mesas including the semiconductor layer, each spaced apart mesa having a height less than or equal to its width. At 216, the method includes depositing a dielectric material that insulates sidewalls of the P-type layer and the active region from the metal. At 218, the method deposits an electrode metal in spaces between each of the plurality of spaced apart mesas, the metal providing optical isolation between each of the spaced apart mesas and electrically contacting the N-type layer of each of the spaced apart mesas along the sidewalls of the N-type layer. In one or more embodiments, each of the plurality of spaced apart mesas includes a conductive p-contact layer extending across a portion of each of the plurality of mesas and including an edge, and a space between each of the plurality of spaced apart mesas results in a pixel pitch ranging from 1 μm to 100 μm and a dark space gap between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch ranges from 5 μm to 100 μm, 10 μm to 100 μm, or 15 μm to 100 μm. In other embodiments, the dark space gap ranges from 10 μm to 0.5 μm, or 10 μm to 4 μm, such as 8 μm to 4 μm. As used herein, according to one or more embodiments, the term "dark space gap" refers to a space between adjacent edges of the p-contact layer where light is not reflected.

[0066] In some embodiments, the method includes forming an array of spaced apart mesas. In some embodiments, the metal includes a reflective metal. In some embodiments, the dark space gap is in the range of 10 μm to 0.5 μm, or in the range of 10 μm to 4 μm. In some embodiments, the plurality of spaced apart mesas are disposed within a pixel, and the pixel pitch is in the range of 5 μm to 100 μm, or in the range of 30 μm to 50 μm. In some embodiments, the thickness of the semiconductor layer 104 is in the range of 2 μm to 10 μm.

[0067] 3C, the method 220 includes the operations 212 through 218 of FIG. 3B and further includes forming a common electrode at operation 222. In one or more embodiments, the common electrode includes a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stacks include one or more layers of GaN.

[0068] 3D, method 224 includes operations 212 through 218 of FIG. 3B and further includes depositing a current spreading layer at operation 226. Some method embodiments include forming a multilayer composite film on the P-type layer, the multilayer composite film including a current spreading layer, a P contact layer on a first portion of the current spreading layer, and a (second) dielectric layer on a second portion of the current spreading layer below the hard mask layer. In one or more embodiments, the multilayer composite film includes a current spreading layer on the P-type layer, a current spreading layer having a first portion and a second portion, a dielectric layer on the second portion of the current spreading layer, a via opening defined by a sidewall of the dielectric layer and the first portion of the current spreading layer, and a P contact layer in the via opening on at least a portion of the first portion of the current spreading layer, a sidewall of the dielectric layer, and a surface of the dielectric layer. In one or more embodiments, the multilayer composite film is formed directly on the P-type layer. In other embodiments, one or more additional layers may be formed between the multilayer composite film and the P-type layer. In one or more embodiments, the multilayer composite film includes a guard layer on the P contact layer.

[0069] Some embodiments include depositing a current spreading layer over the P-type layer. Other method embodiments include depositing a current spreading layer over the P-type layer; depositing a dielectric layer on the current spreading layer; forming a via opening in the dielectric layer; conformally depositing a P contact layer in the via opening and on a top surface of the dielectric layer; depositing a guard layer on the P contact layer; depositing a hard mask layer on the guard layer; forming an opening in the hard mask layer; depositing a liner layer in the opening in the hard mask layer; and depositing a P metal material plug on the liner layer, the P metal material plug having a width; forming a passivation layer over the P metal material plug, the passivation layer having an opening defining a width, the width of the opening in the passivation layer being less than a width of the combination of the liner layer and the P metal material plug in the opening.

[0070] 3E, a method 230 includes depositing a hardmask layer above or over the P-type layer at operation 232. At operation 234, an opening is formed in the hardmask layer. At operation 236, in one or more embodiments, a liner layer is deposited in the opening in the hardmask layer. At operation 238, in one or more embodiments, a P metal material plug is deposited on the liner layer, the P metal material plug having a width, and at operation 240, a passivation layer is formed on the P metal material plug, the passivation layer having an opening defining a width, the width of the passivation layer opening being less than the width of the P metal material plug.

[0071] In one or more embodiments, a method for manufacturing a light emitting diode (LED) device includes the steps of: depositing a plurality of semiconductor layers on a substrate, the semiconductor layers including an N-type layer, an active region, and a P-type layer; depositing a hard mask layer over the P-type layer; partially etching the hard mask layer and the semiconductor layers to form a plurality of mesas and trenches that define pixels, each of the plurality of mesas having a semiconductor layer and each of the mesas having a height less than or equal to its width; depositing a dielectric material in the trenches; forming openings in the hard mask layer and etching the semiconductor layers to expose a surface of the substrate and a sidewall of the N-type layer. depositing a liner layer over the substrate, where over the substrate includes over surfaces of the substrate, the N-type layer, the dielectric material, and the openings in the hardmask layer; depositing an electrode metal over the liner layer; planarizing the substrate to form P metal material plugs on the liner layer in the openings in the hardmask layer and N-contact material along sidewalls of the N-type layer that electrically contacts the N-type layer of each mesa, where the combination of the liner layer and the P metal material plug in the openings in the hardmask layer has a width; forming a passivation layer over the substrate and forming openings in the passivation layer that define a width. In one or more embodiments, the width of each opening in the passivation layer is less than the width of the combination of the P metal material plug and the liner layer.

[0072] 3F, some method embodiments include method 240, which includes depositing a semiconductor layer in operation 212, e.g., as described with respect to FIG. 1A. Method 240 further includes depositing a current spreading film or layer and / or a P contact layer in operation 213, e.g., as described with respect to FIG. 1A. Method 240 further includes depositing and patterning a hard mask layer in operation 231, e.g., as described with respect to FIG. 1A-C. In operation 233, a trench is formed in the semiconductor layer and a dielectric material is deposited, e.g., as described with respect to FIG. 1D-G. In operation 234, an opening is formed in the hard mask layer, e.g., as described with respect to FIG. 1H. In operation 236, in one or more embodiments, a liner layer is deposited in the opening in the hard mask layer, e.g., as described with respect to FIG. 1H. In operation 237, metal is deposited in the trench and a P metal material plug is deposited, e.g., as described with respect to FIG. 1I. In operation 239, planarization is performed, e.g., as described with respect to Figure 1J. In operation 241, a passivation layer is formed and patterned, e.g., as described with respect to Figures 1K and 1L. In operation 243, an under-bump metallization layer is formed and patterned, e.g., as described with respect to Figure 1M. The operations of method 240 can be utilized in accordance with one or more embodiments to form a device, such as that shown in Figure 1O or Figure 4.

[0073] Another aspect of the present disclosure relates to an electronic system. In one or more embodiments, the electronic system is comprised of the LED monolithic devices and arrays described herein and a driver circuit configured to provide independent voltages to one or more p-contact layers. In one or more embodiments, the electronic system is selected from the group consisting of an LED-based luminaire, a light-emitting strip, a light-emitting sheet, an optical display, and a micro LED display.

[0074] 4 is a cross-sectional view of an LED device 300 showing a single mesa 350 of an LED device according to one or more embodiments. Device 300 is similar to first mesa 15a or second mesa 150b of device 100 shown in FIG. 1O. Device 300 includes semiconductor layers 304 including an n-type layer 304n, a p-type layer 304p, and an active region 306 between n-type layer 304n and p-type layer 304p.

[0075] In the illustrated embodiment, there is a multi-layer composite film 317 on the P-type layer 304. As shown, the multi-layer composite film 317 has a current spreading layer 311 on the P-type layer 304p. The multi-layer composite film further includes a dielectric layer 307 on the current spreading layer 311. In one or more embodiments, the current spreading layer 311 has a first portion 311y and a second portion 311z. The first portion 311y and the second portion 311z are lateral portions of the current spreading layer 311. The P contact layer 305 is on the first portion 311y of the current spreading layer 311 and in the via opening 319. The dielectric layer 307 is on the second portion 311z of the current spreading layer 311. In one or more embodiments, the dielectric layers 307 are separated by the via opening 319. The via opening 319 has at least one sidewall 319s and a bottom 319b, where the bottom 319b exposes the current spreading layer 311. In the illustrated embodiment, the via opening 319 is defined by opposing sidewalls 319s of the dielectric layer 307 and a bottom 319b defined by the current spreading layer 311. In the embodiment shown in FIG. 4, the via opening 319 is filled with the P contact layer 305 and the guard layer 309. As shown in FIG. 4, the P contact layer 305 is on the top surface of the dielectric layer 307, the sidewalls 319s and the bottom 31b of the via opening 319, and directly on the first portion 311y of the current spreading layer 311. As shown in the embodiment of FIG. 4, the P contact layer 305 is substantially conformal with the via opening 319. As used herein, "substantially conformal" refers to a layer that has approximately the same thickness throughout (e.g., on the hard mask layer 308, on the sidewalls 319s, and on the bottom 319b of the via opening 319). A substantially conformal layer has a thickness variation of about 5%, 2%, 1%, or 0.5% or less. In one or more examples, guard layer 309 is on P contact layer 305. Without intending to be bound by theory, according to one or more embodiments, guard layer 309 can prevent metal ions from P contact layer 305 from migrating and shorting device 300. In one or more embodiments, guard layer 309 covers the entire P contact layer 305. In one or more embodiments, guard layer 309 directly covers the entire P contact layer 305.

[0076] In one or more embodiments, the current spreading layer comprises a transparent material. The current spreading layer is separate from the reflective layer. In this way, the function of current spreading is realized in a different layer than the function of reflection. In one or more embodiments, the current spreading layer 311 comprises indium tin oxide (ITO) or other suitable conductive transparent material, for example, a transparent conductive oxide (TCO) such as indium zinc oxide (IZO), and the current spreading layer has a thickness in the range of 5 nm to 100 nm. In some embodiments, the dielectric layer 307 comprises any suitable dielectric material, for example, silicon dioxide (SiO2) or silicon oxynitride (SiON). In some embodiments, the guard layer 309 comprises titanium-platinum (TiPt), titanium-tungsten (TiW), or titanium-tungsten nitride (TiWN). In one or more embodiments, the P contact layer 305 comprises a reflective metal. In one or more embodiments, the P contact layer 305 comprises a suitable reflective material, such as, but not limited to, nickel (Ni) or silver (Ag).

[0077] Without intending to be bound by theory, according to some embodiments, the multilayer composite film 317 on the P-type layer 304p can balance absorption, reflection, and conductivity. In some embodiments, the P-contact layer 305 is a highly reflective layer. At angles close to and greater than the critical angle, the dielectric layer 307 is a better reflector than the P-contact layer 305 and may not be particularly conductive. In some embodiments, the dielectric layer 307 can include multiple dielectric layers to form a DBR (distributed Bragg reflector). In one or more embodiments, the current spreading layer 311 is optimized to minimize absorption and increase conductivity.

[0078] In one or more embodiments, the P contact layer 305 spans a width of the mesa that is smaller than the width that the current spreading layer 311 spans.

[0079] In the illustrated embodiment, a hardmask layer 308 is on the first section of the guard layer 309 above the second portion 311z of the current spreading layer 311, the hardmask layer 308 having a mask opening 347 defined therein. The hardmask layer 308 may comprise any suitable material, including a dielectric material. The hardmask layer 308 is masked and etched as described with respect to Figures 1A-1N above.

[0080] The hard mask opening 347 is partially filled with a liner layer 325 and partially filled with a P metal material plug 318p, the P metal material plug 318p having a width 339. As shown in the example of FIG. 4, the liner layer 325 is substantially conformal with the hard mask opening 347. As used herein, "substantially conformal" refers to a layer that is approximately the same in thickness throughout (e.g., on the sidewalls 347s and bottom 347b of the hard mask opening 347). A substantially conformal layer may have a thickness variation of about 5%, 2%, 1%, or 0.5% or less. In one or more embodiments, the hard mask opening 347 has at least one sidewall 347s and a bottom surface 347b. In some embodiments, the bottom surface 347b exposes the guard layer 309. In one or more embodiments, the liner layer 325 is on at least one sidewall 347s and bottom 347b of the hard mask opening 347. In certain embodiments, the liner layer 325 is substantially conformal to at least one sidewall 347s and bottom 347b of the hard mask opening 347. In the illustrated embodiment, there are two sidewalls 347s, opposing sidewalls 347s that define the hard mask opening 347. In one or more embodiments, the thickness of the liner layer 325 ranges from about 5 nm to about 2 um. In one or more embodiments, the liner layer 325 includes a seed material, and the liner layer 325 can include any suitable material, including, but not limited to, aluminum (Al), titanium nitride, Ag, indium tin oxide (ITO), titanium tungsten (TiW), and / or titanium platinum (TiP). The seed material of the liner layer 325 according to some embodiments can facilitate plating of the P metal material plug 318p. In one or more examples, the liner layer 325 functions as an electrical bridge. The liner layer 325 can be formed by any means known to one skilled in the art, such as sputtering deposition.

[0081] As shown in FIG. 4, there is a passivation film 321 on the hard mask layer 308. In one or more embodiments, the passivation film 321 includes a first passivation layer 320 and a second passivation layer 322. The first passivation layer 320 and the second passivation layer 322 can include any suitable material. In one or more embodiments, the first passivation layer 320 includes silicon oxide (SiO2) and the second passivation layer includes silicon nitride (SiN). In one or more embodiments, the passivation film 321 has a passivation film opening 348 defining a width 349 therein, the width 349 of the passivation film opening 348 being less than the width 339 of the combination of the P metal material plug 318p and the liner layer 325. In one or more embodiments, the passivation film 321 is sized to cover a surface 325f of the liner layer 325 and a portion of the P metal material plug 318p. In this manner, the passivation film openings 348, which are less than the width 339 of the P metal material plugs 318p and the liner layer 325, are effective to protect the liner layer 325 while allowing access to the P metal material plugs 318p. In one or more embodiments, each passivation film opening 348 is located at the center of the P metal material plugs 318p.

[0082] 4, a layer of P metal material, also referred to as P metal material plug 318p, is formed on liner layer 325. P metal material plug 318p may include any suitable material. In one or more embodiments, P metal material plug 318p includes copper (Cu). In one or more embodiments, inner spacer 312 contacts outer edges of P contact layer 305, guard layer 309, and hard mask layer 308. An outer spacer 314 is formed adjacent to inner spacer 312.

[0083] In one or more embodiments, a reflective liner 330 is formed on the edges of the semiconductor layers 304n, 306, and 304p, separating them from the N-contact material 318n. The difference between the LED device 300 of FIG. 4 and the LED device of FIG. 1O is the first passivation layer 320, which corresponds to the passivation layer 120 shown in FIG. 1M, and the second passivation layer 322, which in some embodiments may include silicon nitride (SiN). In some embodiments, only the first passivation layer 320 is present, while in other examples, the first passivation layer 320 and the second passivation layer 322 are present. The first passivation layer 320 and the second passivation layer 322 have a passivation film opening 348 therein. Also shown in FIG. 4 is an anode pad that includes an under bump metallization 324a, the configuration of which will be described with respect to FIG. 1M. The P metal material plug 318p has a width 339 defined by a distance from an outer edge of the liner layer 325, and a passivation film opening 348 in the passivation layer is filled with an under bump metallization 324a forming an anode pad. In one or more embodiments, the opening 348 has a width 349 that is smaller than the width 339 of the P metal material plug 318p. In some embodiments, the width of the P metal material plug 318p is in the range of 2 μm to 30 μm, such as 10 μm to 20 μm.

[0084] Purpose The LED devices disclosed herein can be monolithic arrays or matrices. The LED devices can be attached to a backplane for use in an end application. Lighting arrays and lens systems can incorporate the LED devices disclosed herein. Applications include, but are not limited to, beam steering and other applications that benefit from fine intensity, spatial, and temporal control of light distribution. These applications include, but are not limited to, precise spatial patterning of light emitted from pixel blocks or individual pixels. Depending on the application, the emitted light can be spectrally differentiated, adaptive overtime, and / or responsive to the environment. Emitting pixel arrays can provide pre-programmed distributions of light with various intensity, spatial, or temporal patterns. The associated optics can vary at the pixel, pixel block, or device level. An example emissive pixel array can include a device with a commonly controlled central block of high brightness pixels with associated common optics, while the edge pixels can have individual optics. In addition to flashlights, common applications supported by emissive pixel arrays include video lighting, automotive headlights, architectural and area lighting, and street lighting.

[0085] Embodiment Various examples are listed below, and it will be understood that the listed embodiments can be combined with all aspects and other embodiments consistent with the scope of the present invention.

[0086] Embodiment (a) 1. A light emitting diode device (LED device) comprising: a plurality of mesas defining pixels, each mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active region and a P-type layer, each mesa having a height less than or equal to its width; an N-contact material that provides optical isolation between each mesa and electrically contacts the N-type layer of each mesa along the sidewalls of the N-type layer; a dielectric material insulating the P-type layers and sidewalls of the active region from the N-contact material; a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; a hardmask layer over the second portion of the current spreading layer, the hardmask layer having sidewalls defining a hardmask opening; a liner layer conformally deposited in the hardmask opening over the first portion of the current spreading layer and on the sidewalls of the hardmask layer; A P metal material plug on the liner layer; a passivation layer on the hardmask layer; an under-bump metallization on the passivation layer;

[0087] Embodiment (b) The LED device of embodiment (a), a dielectric layer below the hard mask layer and on the second portion of the current spreading layer; a via opening defined by a sidewall of the dielectric layer and a first portion of the current spreading layer; a P contact layer below the hard mask layer and the P metal material plug; A P-contact layer is located within the via opening, on the first portion of the current spreading layer, on the sidewall within the dielectric layer, and on at least a portion of the dielectric layer.

[0088] Embodiment (c) The LED device of embodiment (b), wherein the P-contact layer comprises a reflective metal and the current spreading layer comprises a transparent material.

[0089] Embodiment (d) The LED device of any one of embodiments (a)-(c), wherein the current spreading layer comprises a transparent conductive oxide (TCO).

[0090] Embodiment (e) The LED device of one of embodiments (a)-(d), wherein the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

[0091] Embodiment (f) The LED device of any one of embodiments (b)-(e), wherein the P-contact layer comprises one or more of nickel (Ni) and silver (Ag), and the dielectric layer comprises silicon dioxide (SiO 2 ).

[0092] Embodiment (g) The LED device of any one of embodiments (b)-(f), further comprising a guard layer covering the P-contact layer.

[0093] Embodiment (h) The LED device of embodiment (g), wherein the guard layer comprises one or more of titanium-platinum (TiPt), titanium-tungsten (TiW), and titanium-tungsten nitride (TiWN).

[0094] Embodiment (i) The LED device of any one of embodiments (a)-(h), wherein the thickness of the semiconductor layer is in the range of 2 μm to 10 μm.

[0095] Embodiment (j) The LED device of any one of embodiments (a)-(i), wherein the dielectric material is SiO having a thickness in the range of 200 nm to 1 μm. 2 , AlO x and an outer spacer comprising a material selected from the group consisting of SiN.

[0096] Embodiment (k) The LED device of any one of embodiments (a)-(j), wherein the space between each mesa includes a trench having a depth ranging from 0.5 μm to 2 μm from the top surface of each mesa.

[0097] Embodiment (l) The LED device of any one of embodiments (a)-(k), wherein each mesa includes a sidewall of the semiconductor layer having a first segment and a second segment, the first segment of the sidewall defining an angle in the range of 60° to 90° from a horizontal plane parallel to the N-type layer and the P-type layer, and the second segment of the sidewall defining an angle in the range of 75° to less than 90° with a top surface of a substrate on which the mesa is formed.

[0098] Embodiment (m) The LED device of any one of embodiments (a)-(l), wherein the plurality of mesas comprises an array of mesas.

[0099] Embodiment (n) 1. A method for manufacturing a light emitting diode device (LED device), comprising: depositing a plurality of semiconductor layers on a substrate, the semiconductor layers including an N-type layer, an active region, and a P-type layer; depositing a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; depositing a hard mask layer over the current spreading layer; partially etching the hard mask layer, the current spreading layer, and the semiconductor layer to form a plurality of mesas and trenches that define pixels, each of the plurality of mesas including the semiconductor layer, each of the mesas having a height that is less than or equal to its width; depositing a first dielectric material in the trench; Etching the hardmask layer to form sidewalls in the hardmask layer to define a hardmask opening with the first portion of the current spreading layer, the hardmask layer over the second portion of the current spreading layer; depositing a liner layer over the substrate in the trench and in the hardmask opening; depositing a metal on a liner layer on the substrate; an N-contact material providing optical isolation between each mesa and electrically contacting the N-type layer of each mesa along sidewalls of the N-type layer and a P metal material plug on the liner layer; depositing a passivation layer over the substrate and forming an opening therein; depositing an under bump metallization on the substrate over the passivation layer and within the opening in the passivation layer.

[0100] Embodiment (o) The method of embodiment (n), further comprising: depositing a dielectric layer below the hard mask layer and on a second portion of the current spreading layer; forming a sidewall of a dielectric layer defining a via opening with the first portion of the current spreading layer; and depositing a P contact layer below the hard mask layer and the P metal material plug, the P contact layer located on a first portion of the current spreading layer in the via opening, on a sidewall within the dielectric layer, and on at least a portion of the dielectric layer.

[0101] Example (p) The method of embodiment (o), wherein the P-contact layer comprises a reflective metal and the current spreading layer comprises a transparent material.

[0102] Embodiment (q) The method of any one of embodiments (o)-(p), further comprising depositing a guard layer over the P contact layer.

[0103] Embodiment (r) The method of any of embodiments (n)-(q), wherein the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

[0104] Embodiment(s) The method of any of embodiments (o)-(r), wherein the P contact layer comprises one or more of nickel (Ni) and silver (Ag) and / or the dielectric layer comprises silicon dioxide (SiO2).

[0105] Embodiment (t) The method of any one of embodiments (n)-(s), wherein the pixel pitch of the plurality of mesas is in the range of 5 μm to 100 μm.

[0106] The use of the terms "a" and "an" and "the" or "the" and similar designations in the context of describing the materials and methods discussed herein (particularly in the context of the claims below) are intended to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitations of ranges of values ​​herein are merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate the materials and methods and does not pose a limitation in scope unless otherwise asserted. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0107] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0108] Although the disclosure herein has been described with reference to particular embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed methods and devices without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to cover such modifications and variations as come within the scope of the appended claims and their equivalents.

Claims

1. 1. A light emitting diode device (LED device) comprising: a plurality of mesas defining pixels, each of the mesas comprising a semiconductor layer, the semiconductor layer including an N-type layer, an active region and a P-type layer, each of the mesas having a height less than or equal to its width; an N-contact material in a space between each of the mesas, the N-contact material providing optical isolation between each of the mesas and electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layer; a dielectric material insulating the P-type layer and sidewalls of the active region from the N-contact material; a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; a hardmask layer over the second portion of the current spreading layer, the hardmask layer having sidewalls defining a hardmask opening; a liner layer conformally deposited in the hardmask opening over the first portion of the current spreading layer and on the sidewalls of the hardmask layer; a plug of P metal material on said liner layer; a passivation layer over the hardmask layer and over the N-contact material; an under-bump metallization on the passivation layer in contact with the P metal material plug, a portion of the passivation layer being located between the under-bump metallization and the hardmask layer; An LED device comprising:

2. A light emitting diode device (LED device), comprising: a plurality of mesas defining pixels, each of the mesas comprising a semiconductor layer, the semiconductor layer including an N-type layer, an active region and a P-type layer, each of the mesas having a height less than or equal to its width; an N-contact material in a space between each of the mesas, the N-contact material providing optical isolation between each of the mesas and electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layer; a dielectric material insulating the P-type layer and sidewalls of the active region from the N-contact material; a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; a hardmask layer over the second portion of the current spreading layer, the hardmask layer having sidewalls defining a hardmask opening; a liner layer conformally deposited in the hardmask opening over the first portion of the current spreading layer and on the sidewalls of the hardmask layer; a plug of P metal material on said liner layer; a passivation layer on the hard mask layer; an under-bump metallization on said passivation layer; Equipped with a dielectric layer below the hard mask layer and over the second portion of the current spreading layer; a via opening defined by a sidewall of the dielectric layer and the first portion of the current spreading layer; a P contact layer below the hard mask layer and the P metal material plug; the P-contact layer is located on the first portion of the current spreading layer within the via opening, on a sidewall within the dielectric layer, and on at least a portion of the dielectric layer. LED device.

3. the P-contact layer comprises a reflective metal; The current spreading layer comprises a transparent material.

3. The LED device of claim 2.

4. the plurality of mesas includes an array of mesas; 10. The LED device of claim 1.

5. The current spreading layer comprises a transparent conductive oxide (TCO); 10. The LED device of claim 1.

6. the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO); 6. The LED device of claim 5.

7. the P contact layer comprises at least one of nickel (Ni) and silver (Ag); The dielectric layer is silicon dioxide (SiO ２ ), 3. The LED device of claim 2.

8. A guard layer covering the P-contact layer is further provided.

3. The LED device of claim 2.

9. the guard layer comprises one or more of titanium-platinum (TiPt), titanium-tungsten (TiW) and titanium-tungsten nitride (TiWN); 9. The LED device of claim 8.

10. The thickness of the semiconductor layer is in the range of 2 μm to 10 μm.

10. The LED device of claim 1.

11. The dielectric material is SiO having a thickness in the range of 200 nm to 1 μm. ２ , AlO ｘ and an outer spacer comprising a material selected from the group consisting of SiN.

10. The LED device of claim 1.

12. the space between each mesa includes a trench having a depth ranging from 0.5 μm to 2 μm from the top surface of each mesa; 10. The LED device of claim 1.

13. each of the mesas includes a sidewall of the semiconductor layer having a first segment and a second segment, the first segment of the sidewall defines an angle in the range of 60° to 90° from a horizontal plane parallel to the N-type layer and the P-type layer; the second segment of the sidewall forms an angle in the range of 75° to less than 90° with a top surface of a substrate on which the mesa is formed.

10. The LED device of claim 1.

14. 1. A method for manufacturing a light emitting diode device (LED device), comprising: depositing a plurality of semiconductor layers over a substrate, the semiconductor layers including an N-type layer, an active region, and a P-type layer; depositing a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; depositing a hard mask layer over the current spreading layer; partially etching the hard mask layer, the current spreading layer, and the semiconductor layer to form a plurality of mesas and trenches that define pixels, each of the mesas including a semiconductor layer and each of the mesas having a height that is less than or equal to its width; depositing a first dielectric material in the trench; etching the hardmask layer to form sidewalls in the hardmask layer to define a hardmask opening with the first portion of the current spreading layer, the hardmask layer over the second portion of the current spreading layer; depositing a liner layer over the substrate and within the trench and the hardmask opening; depositing a metal on the liner layer on the substrate; planarizing the substrate to form an N-contact material that provides optical isolation between each of the mesas and electrically contacts the N-type layer of each of the mesas along sidewalls of the N-type layer and a P metal material plug on the liner layer; depositing a passivation layer over the substrate and forming an opening therein; depositing an underbump metallization on the substrate, over the passivation layer and within the opening in the passivation layer; Including, the passivation layer is formed over the hard mask layer and over the N-contact material; The method of claim 1, wherein the under bump metallization contacts the P metal material plug and a portion of the passivation layer is located between the under bump metallization and the hard mask layer.

15. A method for manufacturing a light emitting diode device (LED device), comprising the steps of: depositing a plurality of semiconductor layers over a substrate, the semiconductor layers including an N-type layer, an active region, and a P-type layer; depositing a current spreading layer on the P-type layer, the current spreading layer having a first portion and a second portion; depositing a hard mask layer over the current spreading layer; partially etching the hard mask layer, the current spreading layer, and the semiconductor layer to form a plurality of mesas and trenches that define pixels, each of the mesas including a semiconductor layer and each of the mesas having a height that is less than or equal to its width; depositing a first dielectric material in the trench; etching the hardmask layer to form sidewalls in the hardmask layer to define a hardmask opening with the first portion of the current spreading layer, the hardmask layer over the second portion of the current spreading layer; depositing a liner layer over the substrate and within the trench and the hardmask opening; depositing a metal on the liner layer on the substrate; planarizing the substrate to form an N-contact material that provides optical isolation between each of the mesas and electrically contacts the N-type layer of each of the mesas along sidewalls of the N-type layer and a P metal material plug on the liner layer; depositing a passivation layer over the substrate and forming an opening therein; depositing an underbump metallization on the substrate, over the passivation layer and within the opening in the passivation layer; depositing a dielectric layer below the hard mask layer and on the second portion of the current spreading layer; forming a sidewall of the dielectric layer defining a via opening with the first portion of the current spreading layer; depositing a P contact layer beneath the hard mask layer and the P metal material plug, the P contact layer being located on the first portion of the current spreading layer in the via opening, on sidewalls within the dielectric layer, and on at least a portion of the dielectric layer; The method further comprising:

16. the P-contact layer comprises a reflective metal; The current spreading layer comprises a transparent material.

16. The method of claim 15.

17. depositing a guard layer over the P-contact layer; 16. The method of claim 15.

18. the current spreading layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO); 15. The method of claim 14.

19. the P contact layer comprises at least one of nickel (Ni) and silver (Ag); The dielectric layer is silicon dioxide (SiO ２ ), 16. The method of claim 15.

20. The pixel pitch of the mesas is in the range of 5 μm to 100 μm.

15. The method of claim 14.

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