Majorana qubits and quantum computers

Abstract

This Majorana quantum bit has a first topological insulator layer comprising a first edge; a first s-wave superconductor layer; and a first layer that is disposed between the first edge and the first s-wave superconductor layer and that enables the penetration of Cooper pairs via a proximity effect from the first s-wave superconductor layer to the first edge.

Description

[Technical field]

[0001] The present disclosure relates to Majorana qubits and quantum computers. [Background technology]

[0002] Research is being conducted on quantum computers using Majorana particles. A technique using two-dimensional topological insulators has been proposed as a technique for generating Majorana particles. In this technique, a topological insulator is brought into contact with an s-wave superconductor, and Cooper pairs are tunneled from the s-wave superconductor to the topological insulator to generate Majorana particles. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2020-511780 [Patent Document 2] US Patent Application Publication No. 2020 / 0098990 [Non-patent literature]

[0004] [Non-Patent Document 1] Effects of large induced superconducting gap on semiconductor Majorana nanowires, WS Cole, et al., Physical Review B 92 (17), 174511 (2015) [Non-Patent Document 2] Coulomb-assisted braiding of Majorana fermions in a Josephson junction array, B. van Heck, et al., New Journal of Physics 14 (3), 035019 (2012) [Non-Patent Document 3] Minimal circuit for a flux-controlled Majorana qubit in a quantum spin-Hall insulator, B. v. Heck, et al., Physica Scripta T164, 014007 (2015) [Non-Patent Document 4] Direct visualization of a two-dimensional topological insulator in the single-layer 1T'-WTe2, ZY Jia, et al., Physical Review B 96 (4) (2017) Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional technologies that use two-dimensional topological insulators, there is a risk that the electronic state of the topological insulator will be damaged and Majorana particles will not be generated.

[0006] An object of the present disclosure is to provide a Majorana quantum bit and a quantum computer that can stably generate Majorana particles. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, there is provided a Majorana qubit having a first topological insulator layer having a first edge, a first s-wave superconductor layer, and a first layer disposed between the first edge and the first s-wave superconductor layer, the first layer enabling penetration of Cooper pairs from the first s-wave superconductor layer to the first edge due to the proximity effect. Effect of the Invention

[0008] According to the present disclosure, Majorana particles can be generated stably. [Brief description of the drawings]

[0009] [Figure 1]FIG. 1 is a top view showing a quantum bit according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing a quantum bit according to the first embodiment. [Diagram 3] FIG. 3 shows the density of states of h-BN in contact with Nb. [Figure 4] FIG. 4 is a top view showing a quantum bit according to a reference example. [Diagram 5] FIG. 5 is a cross-sectional view showing a quantum bit according to a reference example. [Figure 6] FIG. 6 is a diagram showing an intensity map of the spectral weight of WTe2 in the reference example. [Figure 7] FIG. 7 is a diagram showing the band structures of WTe2 and Nb in the reference example. [Figure 8] FIG. 8 shows the band structure of WTe2 without external influence. [Figure 9] FIG. 9 is a perspective view showing a quantum bit according to the second embodiment. [Figure 10] FIG. 10 is a top view showing a quantum bit according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 1) showing a quantum bit according to the second embodiment. [Figure 12] FIG. 12 is a second cross-sectional view showing a quantum bit according to the second embodiment. [Figure 13] FIG. 13 is a top view (part 1) showing a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 14] FIG. 14 is a top view (part 2) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 15] FIG. 15 is a top view (part 3) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 16] FIG. 16 is a top view (part 4) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 17] FIG. 17 is a fifth top view illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 18] FIG. 18 is a top view (part 6) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 19] FIG. 19 is a top view (part 7) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 20] FIG. 20 is a top view (part 8) illustrating the method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 21] FIG. 21 is a top view (part 9) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 22] FIG. 22 is a top view (part 10) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Diagram 23] FIG. 23 is a top view (part 11) illustrating a method for manufacturing a quantum bit 2 according to the second embodiment. [Figure 24] FIG. 24 is a schematic diagram (part 1) showing a method for manufacturing a quantum bit according to the third embodiment. [Diagram 25] FIG. 25 is a schematic diagram (part 2) showing a method for manufacturing a quantum bit according to the third embodiment. [Figure 26] FIG. 26 is a schematic diagram (part 3) showing a method for manufacturing a quantum bit according to the third embodiment. [Figure 27] FIG. 27 is a schematic diagram (part 4) showing a method for manufacturing a quantum bit according to the third embodiment. [Figure 28] FIG. 28 is a schematic diagram (part 5) illustrating a method for manufacturing a quantum bit according to the third embodiment. [Figure 29] FIG. 29 is a schematic diagram showing a quantum bit according to the fourth embodiment. [Diagram 30] FIG. 30 is a diagram illustrating a quantum computer according to the fifth embodiment. [Diagram 31] FIG. 31 is a schematic diagram showing a qubit including a high-order topological insulator layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description may be omitted.

[0011] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a quantum bit including a two-dimensional topological insulator. FIG. 1 is a top view showing a quantum bit according to the first embodiment. FIG. 2 is a cross-sectional view showing a quantum bit according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0012] The quantum bit 1 according to the first embodiment has a topological insulator layer 10, an s-wave superconductor layer 20, and a cap layer 30, as shown in FIGS.

[0013] The topological insulator layer 10 has an edge 11. The material of the topological insulator layer 10 is tungsten ditelluride (WTe 2 ). The material of the s-wave superconductor layer 20 is Nb. The material of the cap layer 30 is hexagonal boron nitride (h-BN). The cap layer 30 is provided between the edge 11 and the s-wave superconductor layer 20. Cooper pairs can penetrate from the s-wave superconductor layer 20 to the edge 11 through the cap layer 30 due to the proximity effect. That is, Cooper pairs can penetrate from the s-wave superconductor layer 20 to the edge 11 by tunneling through the cap layer 30. When Cooper pairs penetrate to the edge 11, the topological insulator layer 10 begins to function as a topological superconductor layer. The cap layer 30 is in direct contact with both the topological insulator layer 10 and the s-wave superconductor layer 20. The cap layer 30 is an example of a first layer.

[0014] The h-BN itself, which is the material of the cap layer 30, is an insulator with a band gap of about 6 eV. However, when the cap layer 30 contacts the s-wave superconductor layer 20 made of Nb, a chemical bond is generated between the h-BN and Nb, and the electronic state of the h-BN becomes a metallic electronic state. According to the inventor's simulation, when the cap layer 30 directly contacts the s-wave superconductor layer 20, the shortest distance between Nb and h-BN is about 2.4 Å. FIG. 3 is a diagram showing the density of states (DOS) of h-BN in contact with Nb. As shown in FIG. 3, the h-BN in contact with Nb has a density of states on the Fermi surface and does not become a barrier to Cooper pairs.

[0015] In addition, according to the inventors' simulations, when the cap layer 30 is in direct contact with the topological insulator layer 10, the WTe 2 The shortest distance between the cap layer 30 and the h-BN is about 3.0 Å. Therefore, there is no chemical bond between the cap layer 30 and the topological insulator layer 10, and the cap layer 30 is physically adsorbed on the topological insulator layer 10. The cap layer 30 and the topological insulator layer 10 may be mutually van der Waals bonded.

[0016] In the first embodiment, an appropriate cap layer 30 is provided between the edge 11 of the topological insulator layer 10 and the s-wave superconductor layer 20, so that the disturbance of the electronic state of the topological insulator layer 10 caused by the s-wave superconductor layer 20 can be suppressed, and Majorana particles can be stably generated. 2 The shortest distance between is about 5.4 Å.

[0017] The generated Majorana particles can be exchanged, for example, by grounding or floating the s-wave superconductor layer 20.

[0018] Here, a reference example will be described for comparison with the first embodiment. Fig. 4 is a top view showing a quantum bit according to the reference example. Fig. 5 is a cross-sectional view showing a quantum bit according to the reference example. Fig. 5 corresponds to a cross-sectional view taken along line VV in Fig. 4.

[0019] 4 and 5, the quantum bit 9 according to the reference example does not have a cap layer 30, and the edge 11 of the topological insulator layer 10 and the s-wave superconductor layer 20 are in direct contact with each other. The other configurations are similar to those of the first embodiment.

[0020] According to the inventors' simulations, when the s-wave superconductor layer 20 is in direct contact with the topological insulator layer 10, the Nb and WTe 2 Since the shortest distance between the topological insulator layer 10 and the s-wave superconductor layer 20 is only about 1.6 Å, a chemical bond is formed between the topological insulator layer 10 and the s-wave superconductor layer 20. As a result, the electronic state of the topological insulator layer 10 is affected by the s-wave superconductor layer 20. 2 FIG. 7 is a diagram showing an intensity map of the spectral weight of WTe in the reference example. 2 FIG. 6 shows the band structures of WTe and Nb. 2 Figure 8 shows the weighting map of the contribution of WTe 2 FIG. 1 is a diagram showing a band structure of

[0021] As shown in Figure 8, a single WTe 2 In this state, the energy difference between the top of the valence band and the bottom of the conduction band is small. 2 can function as a stable topological insulator. However, as shown in Figs. 6 and 7, Nb and WTe 2 When and are in direct contact with each other, WTe 2 This causes the band structure of WTe to become distorted. 2 Therefore, in the quantum bit 9 according to the reference example, the electronic state of the topological insulator layer 10 may be impaired, and Majorana particles may not be generated.

[0022] In contrast, in the first embodiment, as described above, an appropriate cap layer 30 is provided, so that disturbance of the electronic state of the topological insulator layer 10 caused by the s-wave superconductor layer 20 can be suppressed, and Majorana particles can be generated stably. If a layer that acts as a barrier against Cooper pairs is provided instead of the cap layer 30, the Cooper pairs cannot penetrate the topological insulator layer 10, and Majorana particles cannot be generated.

[0023] Second embodiment Next, a second embodiment will be described. The second embodiment relates to a quantum bit including a two-dimensional topological insulator, which is an application of the first embodiment. FIG. 9 is a perspective view showing a quantum bit according to the second embodiment. FIG. 10 is a top view showing a quantum bit according to the second embodiment. FIGS. 11 and 12 are cross-sectional views showing a quantum bit according to the second embodiment. FIG. 11 corresponds to a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 corresponds to a cross-sectional view taken along line XII-XII in FIG. 10.

[0024] As shown in FIGS. 9 to 12, the quantum bit 2 according to the second embodiment has a substrate 110, a lower topological insulator layer 121 extending in the Y-axis direction, and an upper topological insulator layer 122 extending in the X-axis direction. The substrate 110 is an insulating substrate such as an alumina substrate or a sapphire substrate. The X-axis direction and the Y-axis direction are directions perpendicular to the Z-axis direction perpendicular to the surface of the substrate 110. The Y-axis direction intersects with the X-axis direction, and for example, the X-axis direction and the Y-axis direction are perpendicular to each other. In the present disclosure, viewing an object from the Z-axis direction may be referred to as a planar view. The Y-axis direction is an example of a first direction, and the X-axis direction is an example of a second direction.

[0025] The lower topological insulator layer 121 is, for example, a two-dimensional topological insulator layer, and has a first edge 161 and a third edge 163 extending in the Y-axis direction. The first edge 161 is located on the +X side of the third edge 163. The lower topological insulator layer 121 may be composed of a single two-dimensional topological insulator, or may be composed of a stack of multiple two-dimensional topological insulators. The material of the lower topological insulator layer 121 is, for example, tungsten ditelluride (WTe 2 ). Although not shown in the figure, multiple lower topological insulator layers 121 may be arranged side by side in the X-axis direction. The lower topological insulator layer 121 is an example of a first topological insulator layer.

[0026] The upper topological insulator layer 122 is, for example, a two-dimensional topological insulator layer, and has a second edge 162 and a fourth edge 164 extending in the X-axis direction. The second edge 162 is located on the +Y side of the fourth edge 164. The upper topological insulator layer 122 may be composed of a single two-dimensional topological insulator, or may be composed of a stack of multiple two-dimensional topological insulators. The material of the upper topological insulator layer 122 is, for example, tungsten ditelluride (WTe 2 ). Although not shown in the figure, multiple upper topological insulator layers 122 may be arranged side by side in the Y-axis direction. The upper topological insulator layer 122 is an example of a second topological insulator layer.

[0027] A plurality of lower s-wave superconductor layers 131 are provided below the lower topological insulator layer 121. The lower s-wave superconductor layers 131 are provided along a first edge 161 and a third edge 163. The ends of each lower s-wave superconductor layer 131 in the Y-axis direction are away from the second edge 162 and the fourth edge 164 of the upper topological insulator layer 122 in a planar view. The lower s-wave superconductor layer 131 is, for example, a Nb layer. The lower s-wave superconductor layer 131 is an example of a first s-wave superconductor layer.

[0028] A cap layer 151 is provided on the upper surface of each lower s-wave superconductor layer 131. The cap layer 151 is in direct contact with the upper surface of the lower s-wave superconductor layer 131 and the lower surface of the lower topological insulator layer 121. The cap layer 151 is, for example, an h-BN layer. The h-BN layer includes one or more h-BNs stacked on each other. The cap layer 151 is provided between the first edge 161 or the third edge 163 and the lower s-wave superconductor layer 131. There is no chemical bond between the cap layer 151 and the lower topological insulator layer 121, and the cap layer 151 is in a state of being physically adsorbed on the lower topological insulator layer 121. The cap layer 151 and the lower topological insulator layer 121 may be mutually van der Waals bonded. Cooper pairs can penetrate from the lower s-wave superconductor layer 131 to the first edge 161 or the third edge 163 due to the proximity effect through the cap layer 151. That is, Cooper pairs can tunnel through the cap layer 151 from the lower s-wave superconductor layer 131 and penetrate into the first edge 161 or the third edge 163. When Cooper pairs penetrate into the first edge 161 or the third edge 163, the lower topological insulator layer 121 begins to function as a topological superconductor layer. The cap layer 151 is an example of the first layer.

[0029] A plurality of upper s-wave superconductor layers 132 are provided below the upper topological insulator layer 122. The upper s-wave superconductor layers 132 are provided along a second edge 162 and a fourth edge 164. The ends of each upper s-wave superconductor layer 132 in the X-axis direction are away from the first edge 161 and the third edge 163 of the lower topological insulator layer 121 in a planar view. The upper s-wave superconductor layer 132 is, for example, a Nb layer. The upper s-wave superconductor layer 132 is an example of a second s-wave superconductor layer.

[0030] A cap layer 152 is provided on the upper surface of each upper s-wave superconductor layer 132. The cap layer 152 is in direct contact with the upper surface of the upper s-wave superconductor layer 132 and the lower surface of the upper topological insulator layer 122. The cap layer 152 is, for example, an h-BN layer. The h-BN layer includes one or more h-BN layers stacked on each other. The cap layer 152 is provided between the second edge 162 or the fourth edge 164 and the upper s-wave superconductor layer 132. There is no chemical bond between the cap layer 152 and the upper topological insulator layer 122, and the cap layer 152 is in a state of being physically adsorbed on the upper topological insulator layer 122. The cap layer 152 and the upper topological insulator layer 122 may be mutually van der Waals bonded. Cooper pairs can penetrate from the upper s-wave superconductor layer 132 to the second edge 162 or the fourth edge 164 due to the proximity effect through the cap layer 152. That is, Cooper pairs can tunnel through the cap layer 152 from the upper s-wave superconductor layer 132 and penetrate into the second edge 162 or the fourth edge 164. When Cooper pairs penetrate into the second edge 162 or the fourth edge 164, the upper topological insulator layer 122 begins to function as a topological superconductor layer. The cap layer 152 is an example of the second layer.

[0031] A plurality of upper s-wave superconductor layers 133 are provided above the upper topological insulator layer 122. The upper s-wave superconductor layers 133 are provided along a second edge 162 and a fourth edge 164. The ends of each upper s-wave superconductor layer 133 in the X-axis direction are away from the first edge 161 and the third edge 163 of the lower topological insulator layer 121 in a planar view. The upper s-wave superconductor layer 133 is, for example, a Nb layer. The upper s-wave superconductor layer 133 is an example of a second s-wave superconductor layer.

[0032] A cap layer 153 is provided on the lower surface of each upper s-wave superconductor layer 133. The cap layer 153 is in direct contact with the lower surface of the upper s-wave superconductor layer 133 and the upper surface of the upper topological insulator layer 122. The cap layer 153 is, for example, an h-BN layer. The h-BN layer includes one or more h-BN layers stacked on each other. The cap layer 153 is provided between the second edge 162 or the fourth edge 164 and the upper s-wave superconductor layer 133. There is no chemical bond between the cap layer 153 and the upper topological insulator layer 122, and the cap layer 153 is in a state of being physically adsorbed on the upper topological insulator layer 122. The cap layer 153 and the upper topological insulator layer 122 may be mutually van der Waals bonded. Cooper pairs can penetrate from the upper s-wave superconductor layer 133 to the second edge 162 or the fourth edge 164 due to the proximity effect through the cap layer 153. That is, Cooper pairs can tunnel through the cap layer 153 from the upper s-wave superconductor layer 133 and penetrate into the second edge 162 or the fourth edge 164. When Cooper pairs penetrate into the second edge 162 or the fourth edge 164, the upper topological insulator layer 122 begins to function as a topological superconductor layer. The cap layer 153 is an example of the second layer.

[0033] For example, in a planar view, the upper s-wave superconductor layer 133 and the cap layer 153 are provided in a region of the upper topological insulator layer 122 that overlaps with the lower topological insulator layer 121, and the upper s-wave superconductor layer 132 and the cap layer 152 are provided in a region away from the lower topological insulator layer 121.

[0034] An etching stopper 140 is provided between the lower topological insulator layer 121 and the upper topological insulator layer 122. The material of the etching stopper 140 is, for example, graphene or graphite. When the material of the etching stopper 140 is graphite, the thinner the thickness, the more preferable, for example, 5 nm or less. This is because Majorana particles tunnel through the etching stopper 140 between the lower topological insulator layer 121 and the upper topological insulator layer 122.

[0035] A plurality of magnetic electrodes 141 are provided on the upper topological insulator layer 122. The magnetic electrodes 141 are provided, for example, in a plan view, between the upper s-wave superconductor layer 133 and the second edge 162 and between the upper s-wave superconductor layer 133 and the fourth edge 164 within a range where the lower topological insulator layer 121 and the upper topological insulator layer 122 overlap. The magnetic electrodes 141 generate a magnetic field that reaches the upper topological insulator layer 122 and the lower topological insulator layer 121. The material of the magnetic electrodes 141 is, for example, Fe, Co, or Ni. The magnetic electrodes 141 are an example of a first magnetic layer and a second magnetic layer.

[0036] In the quantum bit 2, Majorana particles can exist in a portion between two adjacent lower s-wave superconductor layers 131 in a plan view of the first edge 161 and in a portion between two adjacent lower s-wave superconductor layers 131 in a plan view of the third edge 163. Then, for example, among the portions where these Majorana particles can exist, a portion of the first edge 161 overlapping with the second edge 162 functions as a first region 171, and a portion of the third edge 163 overlapping with the second edge 162 functions as a third region 173. Also, for example, among the portions where these Majorana particles can exist, a portion of the first edge 161 overlapping with the fourth edge 164 functions as a fifth region 175, and a portion of the third edge 163 overlapping with the fourth edge 164 functions as a seventh region 177.

[0037] Similarly, Majorana particles can exist in a portion of the second edge 162 between the upper s-wave superconductor layer 132 and the upper s-wave superconductor layer 133 adjacent to each other in a plan view, and in a portion of the fourth edge 164 between the upper s-wave superconductor layer 132 and the upper s-wave superconductor layer 133 adjacent to each other in a plan view. Then, for example, among the portions where these Majorana particles can exist, a portion of the second edge 162 overlapping with the first edge 161 functions as a second region 172, and a portion of the fourth edge 164 overlapping with the first edge 161 functions as a sixth region 176. Also, among the portions where these Majorana particles can exist, a portion of the second edge 162 overlapping with the third edge 163 functions as a fourth region 174, and a portion of the fourth edge 164 overlapping with the third edge 163 functions as an eighth region 178.

[0038] The Majorana particles present in the first region 171 and the Majorana particles present in the second region 172 can pass through the etching stopper 140 by the tunnel effect and interact with each other. Therefore, both Majorana particles can be regarded as a single Majorana particle. The same is true for the pair of the third region 173 and the fourth region 174, the pair of the fifth region 175 and the sixth region 176, and the pair of the seventh region 177 and the eighth region 178.

[0039] In this way, in the quantum bit 2, the Majorana fermions generated in the lower topological insulator layer 121 and the Majorana fermions generated in the upper topological insulator layer 122 can be easily caused to interact with each other.

[0040] Furthermore, a cap layer 151 is provided on the upper surface of each lower s-wave superconductor layer 131, a cap layer 152 is provided on the upper surface of each upper s-wave superconductor layer 132, and a cap layer 153 is provided on the lower surface of each upper s-wave superconductor layer 133. Therefore, similarly to the first embodiment, disturbance of the electronic states of the lower topological insulator layer 121 and the upper topological insulator layer 122 can be suppressed, and Majorana particles can be generated stably. The generated Majorana particles can be replaced, for example, by grounding or floating the s-wave superconductor layers 131 to 133.

[0041] Next, a method for manufacturing the quantum bit 2 according to the second embodiment will be described. Figures 13 to 23 are top views showing the method for manufacturing the quantum bit 2 according to the second embodiment.

[0042] 13, an Nb layer 181 is formed on a substrate 110. The Nb layer 181 can be formed by, for example, a vapor deposition method.

[0043] 14, an h-BN layer 182 is formed on the Nb layer 181. The h-BN layer 182 can be formed by, for example, chemical vapor deposition (CVD) or the like.

[0044] 15, the laminate of the Nb layer 181 and the h-BN layer 182 is processed to form a laminate of the lower s-wave superconductor layer 131 and the cap layer 151, and a laminate of the upper s-wave superconductor layer 132 and the cap layer 152 (see FIGS. 11 and 12). The cap layers 151 and 152 can function as protective layers for the lower s-wave superconductor layer 131 and the upper s-wave superconductor layer 132, respectively, and can suppress oxidation of the surfaces of the lower s-wave superconductor layer 131 and the upper s-wave superconductor layer 132 in the subsequent processing.

[0045] 16, a two-dimensional topological insulator layer 121X is provided on the substrate 110 so as to cover the stack of the lower s-wave superconductor layer 131 and the cap layer 151 and the stack of the upper s-wave superconductor layer 132 and the cap layer 152. The two-dimensional topological insulator layer 121X can be provided, for example, by separately growing it on a growth substrate (not shown) and transferring it from the growth substrate.

[0046] 17, the two-dimensional topological insulator layer 121X is processed to form a plurality of lower topological insulator layers 121. The two-dimensional topological insulator layer 121X is processed by, for example, reactive ion etching (RIE). For example, a fluorocarbon gas is used as the etching gas.

[0047] 18, an etching stopper 140X is provided above the substrate 110 so as to cover the lower topological insulator layer 121. The etching stopper 140X can be provided, for example, by being separately grown on a growth substrate (not shown) and then transferred from the growth substrate.

[0048] 19, a two-dimensional topological insulator layer 122X is provided on the etching stopper 140X. The two-dimensional topological insulator layer 122X can be provided, for example, by separately growing the layer on a growth substrate (not shown) and transferring the layer from the growth substrate.

[0049] 20, the two-dimensional topological insulator layer 122X is processed to form a plurality of upper topological insulator layers 122. The two-dimensional topological insulator layer 122X is processed by, for example, RIE. For example, a fluorocarbon gas is used as the etching gas. At this time, the lower topological insulator layer is protected by an etching stopper 140X.

[0050] 21, the etching stopper 140X is processed to remove the portion of the etching stopper 140X exposed from the upper topological insulator layer 122, leaving the etching stopper 140 between the lower topological insulator layer 121 and the upper topological insulator layer 122 (see FIGS. 11 and 12). The etching stopper 140X is processed by, for example, RIE. As the etching gas, for example, oxygen gas is used.

[0051] Next, as shown in FIG. 22, a stack of a cap layer 153 and an upper s-wave superconductor layer 133 is formed on the upper topological insulator layer 122 (see FIG. 11).

[0052] Next, as shown in FIG. 23, a plurality of magnetic electrodes 141 are formed on the upper topological insulator layer 122.

[0053] In this manner, the quantum bit 2 according to the second embodiment can be manufactured.

[0054] Third embodiment Next, a third embodiment will be described. The third embodiment relates to a method for manufacturing a quantum bit. Figures 24 to 28 are schematic diagrams showing a method for manufacturing a quantum bit according to the third embodiment.

[0055] First, as shown in FIG. 24, an h-BN layer 301 is formed on a growth substrate 41, and the h-BN layer 301 is attached to a transparent polymer mass 52 provided on a slide glass 51.

[0056] Next, as shown in FIG. 25, WTe 2 The layer 302 is formed, and WTe is added to the h-BN layer 301. 2 Layer 302 is deposited. 2 The layer 302 can be formed by, for example, pulsed laser deposition (PLD) or molecular beam epitaxy. 2 WTe peeled off 2 Layer 302 may also be used.

[0057] Thereafter, as shown in FIG. 26, an h-BN layer 303 is formed on the growth substrate 43, and a WTe 2 A layer of h-BN 303 is deposited on layer 302 .

[0058] 27, an s-wave superconductor layer 310 is formed on the substrate 44, and an h-BN layer 301 and a WTe 2 The stack of layer 302 and h-BN layer 303 is pressed against an s-wave superconductor layer 310 .

[0059] 28, the transparent polymer block 52 is removed from the h-BN layer 301. As a result, the h-BN layer 301, the WTe 2 The stack of layer 302 and h-BN layer 303 is transferred onto a substrate 44 .

[0060] In this way, the s-wave superconductor layer 310 and the topological insulator WTe 2 A quantum bit 3 can be fabricated having an h-BN layer 301 sandwiched between a layer 302 and an h-BN layer 301 .

[0061] (Fourth embodiment) Next, a fourth embodiment will be described below. Fig. 29 is a schematic diagram showing a quantum bit according to the fourth embodiment.

[0062] 29, the quantum bit 4 according to the fourth embodiment has a topological insulator layer 421 having a rectangular planar shape and a topological insulator layer 422 having a rectangular planar shape. One vertex of the topological insulator layer 421 is connected to one vertex of the topological insulator layer 422. If the topological insulator layers 421 and 422 are considered as one topological insulator layer, there is a constriction at a connection portion 423 between the topological insulator layer 421 and the topological insulator layer 422.

[0063] The topological insulator layer 421 is, for example, a two-dimensional topological insulator layer, and has a first edge 461 and a third edge 463 extending from the connecting portion 423. The topological insulator layer 421 may be composed of a single two-dimensional topological insulator, or may be composed of a plurality of two-dimensional topological insulators stacked together. The material of the topological insulator layer 421 is, for example, WTe 2 It is.

[0064] The topological insulator layer 422 is, for example, a two-dimensional topological insulator layer, and has a second edge 462 and a fourth edge 464 extending from the connecting portion 423. The topological insulator layer 422 may be composed of a single two-dimensional topological insulator, or may be composed of a plurality of two-dimensional topological insulators stacked together. The material of the topological insulator layer 422 is, for example, WTe 2 It is.

[0065] An s-wave superconductor layer 431 is provided above a first edge 461 of the topological insulator layer 421. An s-wave superconductor layer 433 is provided above a third edge 463 of the topological insulator layer 421. The s-wave superconductor layers 431 and 433 are, for example, Nb layers.

[0066] A cap layer 451 is provided on the lower surface of the s-wave superconductor layer 431. The cap layer 451 is in direct contact with the lower surface of the s-wave superconductor layer 431 and the upper surface of the topological insulator layer 421. The cap layer 451 is, for example, an h-BN layer. The cap layer 451 is provided between the first edge 461 and the s-wave superconductor layer 431. There is no chemical bond between the cap layer 451 and the topological insulator layer 421, and the cap layer 451 is in a state of being physically adsorbed on the topological insulator layer 421. The cap layer 451 and the topological insulator layer 421 may be mutually van der Waals bonded. Cooper pairs can intrude from the s-wave superconductor layer 431 to the first edge 461 due to the proximity effect via the cap layer 451. That is, Cooper pairs can intrude from the s-wave superconductor layer 431 into the first edge 461 by tunneling through the cap layer 451. When the Cooper pairs penetrate into the first edge 461, the topological insulator layer 421 begins to function as a topological superconductor layer.

[0067] A cap layer 453 is provided on the lower surface of the s-wave superconductor layer 433. The cap layer 453 is in direct contact with the lower surface of the s-wave superconductor layer 433 and the upper surface of the topological insulator layer 421. The cap layer 453 is, for example, an h-BN layer. The cap layer 453 is provided between the third edge 463 and the s-wave superconductor layer 433. There is no chemical bond between the cap layer 453 and the topological insulator layer 421, and the cap layer 453 is in a state of being physically adsorbed on the topological insulator layer 421. The cap layer 453 and the topological insulator layer 421 may be mutually van der Waals bonded. Cooper pairs can intrude from the s-wave superconductor layer 433 to the third edge 463 due to the proximity effect via the cap layer 453. That is, Cooper pairs can intrude from the s-wave superconductor layer 433 into the third edge 463 by tunneling through the cap layer 453. When the Cooper pairs penetrate to the third edge 463, the topological insulator layer 421 begins to function as a topological superconductor layer.

[0068] A cap layer 452 is provided on the lower surface of the s-wave superconductor layer 432. The cap layer 452 is in direct contact with the lower surface of the s-wave superconductor layer 432 and the upper surface of the topological insulator layer 422. The cap layer 452 is, for example, an h-BN layer. The cap layer 452 is provided between the second edge 462 and the s-wave superconductor layer 432. There is no chemical bond between the cap layer 452 and the topological insulator layer 422, and the cap layer 452 is in a state of being physically adsorbed on the topological insulator layer 422. The cap layer 452 and the topological insulator layer 422 may be mutually bonded by van der Waals bonds. Cooper pairs can intrude from the s-wave superconductor layer 432 to the second edge 462 through the cap layer 452 due to the proximity effect. That is, Cooper pairs can intrude from the s-wave superconductor layer 432 into the second edge 462 by tunneling through the cap layer 452. When the Cooper pairs penetrate to the second edge 462, the topological insulator layer 422 begins to function as a topological superconductor layer.

[0069] Magnetic layers 441 and 443 are provided on the topological insulator layer 421. The magnetic layer 441 is provided at the end of the first edge 461 opposite to the connecting portion 423. The magnetic layer 443 is provided at the end of the third edge 463 opposite to the connecting portion 423. In plan view, a stack of an s-wave superconductor layer 431 and a cap layer 451 is provided between the magnetic layer 441 and the connecting portion 423, and a stack of an s-wave superconductor layer 433 and a cap layer 453 is provided between the magnetic layer 443 and the connecting portion 423. The magnetic layers 441 and 443 generate a magnetic field that extends to the topological insulator layer 421. The material of the magnetic layers 441 and 443 is, for example, Fe, Co, or Ni.

[0070] Magnetic layers 442 and 444 are provided on the topological insulator layer 422. The magnetic layer 442 is provided on the end of the second edge 462 opposite to the connecting portion 423. The magnetic layer 444 is provided on the fourth edge 464. In a plan view, a stack of an s-wave superconductor layer 432 and a cap layer 452 is present between the magnetic layer 442 and the connecting portion 423. The material of the magnetic layers 442 and 444 is, for example, Fe, Co, or Ni.

[0071] In the quantum bit 4, a portion of the first edge 461 between the magnetic layer 441 and the stack of the s-wave superconductor layer 431 and the cap layer 451 in a plan view functions as a first region 471 in which Majorana particles can exist. A portion of the second edge 462 between the magnetic layer 442 and the stack of the s-wave superconductor layer 432 and the cap layer 452 in a plan view functions as a second region 472 in which Majorana particles can exist. A portion of the third edge 463 between the magnetic layer 443 and the stack of the s-wave superconductor layer 433 and the cap layer 453 in a plan view functions as a third region 473 in which Majorana particles can exist. Furthermore, the connecting portion 423 functions as a fourth region 474 in which Majorana particles can exist.

[0072] In the fourth embodiment, a cap layer 451 is provided on the lower surface of the s-wave superconductor layer 431, a cap layer 452 is provided on the lower surface of the s-wave superconductor layer 432, and a cap layer 453 is provided on the lower surface of the s-wave superconductor layer 433. Therefore, as in the first embodiment, disturbance of the electronic states of the topological insulator layers 421 and 422 can be suppressed, and Majorana particles can be stably generated.

[0073] Fifth embodiment Next, a fifth embodiment will be described. The fifth embodiment relates to a quantum computer. Fig. 30 is a diagram showing a quantum computer according to the fifth embodiment.

[0074] The quantum computer 5 according to the fifth embodiment includes a general-purpose computer 501, a control unit 502, and a quantum bit 503. The control unit 502 controls the quantum bit 503 based on a control signal from the general-purpose computer 501. As the quantum bit 503, a quantum bit according to any of the first to fourth embodiments is used. The control unit 502 and the quantum bit 503 are housed in a cryostat 504.

[0075] The quantum computer 5 makes it possible to perform stable quantum operations.

[0076] In the present disclosure, the material of the first layer, i.e., the cap layer in the embodiment, is not limited to h-BN. When the material of the first layer is h-BN, the thickness of the first layer is preferably 1 nm or less.

[0077] For example, if the first layer is Nb 2 O 5 layer, Nb 2 O 3 Layer, NbO 2 The first layer may be an oxide layer such as a Nb layer. When the first layer is an oxide layer, the thickness of the first layer is preferably 1 nm or less. The oxide layer may be deposited on the Nb layer used as the s-wave superconductor layer, or may be formed by oxidizing the Nb layer. When the Nb layer is oxidized, the surface of the Nb layer is terminated with O atoms.

[0078] For example, the first layer may be a nitride layer such as an NbN layer or a TiN layer. The NbN layer may be relatively thick since it functions as a superconductor. Also, a part of the NbN layer may function as the first s-wave superconductor layer. The nitride layer may be deposited on the Nb layer used as the s-wave superconductor layer, may be formed by nitriding the Nb layer, or may be formed directly on the substrate. When the Nb layer is nitrided, the surface of the Nb layer is terminated with N atoms.

[0079] For example, the first layer may be a graphene layer or graphite. When the first layer is a graphene layer or graphite, the thickness of the first layer is preferably 1 nm or less. The graphene layer or graphite may be provided by transfer or the like on a Nb layer used as an s-wave superconductor layer, or may be formed by dissolving carbon (C) in the Nb layer and then precipitating C. The graphene layer includes one or more graphenes stacked together.

[0080] For example, the first layer may be a normal metal layer such as an Au layer, a Pt layer, etc. When the first layer is a normal metal layer, the thickness of the first layer is preferably 5 nm or less. The normal metal layer may be deposited on a Nb layer used as an s-wave superconductor layer.

[0081] The first layer may contain a combination of two or more of these.

[0082] In addition, the first topological insulator layer is not limited to a two-dimensional topological insulator layer, but may be a high-order topological insulator layer. Fig. 31 is a schematic diagram showing a quantum bit including a high-order topological insulator layer.

[0083] 31 has a rectangular parallelepiped high-order topological insulator layer 610, an s-wave superconductor layer 620, a cap layer 630, and a magnetic layer 640. The cap layer 630 covers a part of the high-order topological insulator layer 610, and the s-wave superconductor layer 620 covers the cap layer 630. The cap layer 630 is in direct contact with the high-order topological insulator layer 610 and the s-wave superconductor layer 620. The materials of the high-order topological insulator layer 610, the s-wave superconductor layer 620, and the cap layer 630 are, for example, WTe 2 , Nb, and h-BN. The magnetic layer 640 covers a part of the highly-ordered topological insulator layer 610 away from the cap layer 630. In the part of the highly-ordered topological insulator layer 610 between the cap layer 630 and the magnetic layer 640, Majorana particles can exist at two diagonally positioned hinges (ridges).

[0084] In the quantum bit 6, an appropriate cap layer 630 is provided between the s-wave superconductor layer 620 and the higher-order topological insulator layer 610, so that disturbance of the electronic state of the higher-order topological insulator layer 610 can be suppressed and Majorana particles can be generated stably.

[0085] The material of the topological insulator layer is WTe 2 For example, other topological insulators or Weyl semimetals may be used as the material of the topological insulator layer.

[0086] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0087] 1, 2, 3, 4, 6: qubits 5: Quantum computers 10, 121, 122, 421, 422: Topological insulator layers 11, 161, 162, 163, 164, 461, 462, 463, 464: Edge 20, 131, 132, 133, 310, 431, 432, 433, 620: s-wave superconductor layers 30, 151, 152, 153, 451, 452, 453, 630: Cap layer 141:Magnetic electrode 301, 303: h-BN layer 302:WTe 2 layer 441, 442, 443, 444, 640: Magnetic layer 610: High-order topological insulator layers

Claims

1. a first topological insulator layer having a first edge; a first s-wave superconductor layer; a first layer provided between the first edge and the first s-wave superconductor layer, the first layer allowing Cooper pairs to penetrate from the first s-wave superconductor layer to the first edge by a proximity effect; A Majorana quantum bit comprising:

2. 2. The Majorana qubit of claim 1, wherein the first layer is physically adsorbed on the first topological insulator layer.

3. 3. The Majorana qubit of claim 1, wherein the first layer has a density of states on a Fermi surface.

4. The first layer is Nb ２ O ５ layer, Nb ２ O ３ layer, NbO ２ 4. The Majorana qubit of claim 1, further comprising a layer, a NbN layer, a TiN layer, a hexagonal boron nitride layer, a graphene layer, a graphite layer, a Au layer, or a Pt layer, or any combination thereof.

5. 5. The Majorana qubit of claim 1, wherein the first topological insulator layer includes a two-dimensional topological insulator or a higher-order topological insulator.

6. 6. The Majorana qubit of claim 1, further comprising a first magnetic layer that generates a magnetic field that extends to the first topological insulator layer.

7. the first topological insulator layer extends in a first direction; a second topological insulator layer having a second edge and extending in a second direction intersecting the first direction; a second s-wave superconductor layer; and a second layer provided between the second edge and the second s-wave superconductor layer, the second layer allowing Cooper pairs to penetrate from the second s-wave superconductor layer to the second edge by a proximity effect; having the first topological insulator layer includes a first region in which a Majorana particle can exist, in a portion of the first edge that overlaps with the second edge in a plan view; the second topological insulator layer includes a second region in which a Majorana particle can exist, in a portion of the second edge that overlaps with the first edge in a plan view; 7. The Majorana quantum bit according to claim 1, wherein the Majorana fermions in the first region and the Majorana fermions in the second region are exchangeable.

8. The Majorana qubit of claim 7 , wherein the second layer is physisorbed onto the second topological insulator layer.

9. 9. The Majorana qubit of claim 7, wherein the second layer has a density of states on a Fermi surface.

10. The second layer is Nb ２ O ５ layer, Nb ２ O ３ layer, NbO ２ 10. The Majorana qubit of claim 7, further comprising a layer, a NbN layer, a TiN layer, a hexagonal boron nitride layer, a graphene layer, a graphite layer, a Au layer, or a Pt layer, or any combination thereof.

11. 11. The Majorana qubit of claim 7, wherein the second topological insulator layer comprises a two-dimensional topological insulator or a higher-order topological insulator.

12. 12. The Majorana qubit of claim 7, further comprising a second magnetic layer that generates a magnetic field that extends to the second topological insulator layer.

13. A quantum computer comprising a Majorana qubit according to any one of claims 1 to 12.

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