Semiconductor Device

Abstract

This semiconductor device includes: a semiconductor layer having a first surface and a second surface; an element structure which is formed on the first surface side of the semiconductor layer, and which includes a first region of a first electroconductivity type and a second region of a second electroconductivity type contacting the first region; a gate electrode opposing the second region via a gate insulating film; a third region of the first electroconductivity type formed on the semiconductor layer so as to contact the second region; and a first electrode which is formed on the semiconductor layer and is electrically connected to the first region and the second region. The element structure includes a first element structure and a second element structure. The first element structure further includes a first column layer of the second electroconductivity type which is separated from the second region in a direction along the first surface of the semiconductor layer, and which extends in the thickness direction of the semiconductor layer. The second element structure further includes a second electrode which opposes the third region via an insulating film and which is electrically connected to the first electrode.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a MOSFET. + A superjunction structure is provided between a semiconductor substrate containing an n-type impurity and a base layer containing a p-type impurity. The superjunction structure is configured by repeatedly arranging a first semiconductor layer containing an n-type impurity and a second semiconductor layer containing a p-type impurity in an alternating manner in a direction intersecting the direction in which the semiconductor substrate and the base layer face each other. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-261562 A Summary of the Invention [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a first surface and a second surface, an element structure formed on the first surface side of the semiconductor layer and including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region, a gate electrode facing the second region via a gate insulating film, a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region, and a first electrode formed on the semiconductor layer and electrically connected to the first region and the second region, the element structure including a first element structure and a second element structure, the first element structure being separated from the second region in a direction along the first surface of the semiconductor layer and further including a first column layer of the second conductivity type extending in a thickness direction of the semiconductor layer, and the second element structure further including a second electrode facing the third region via an insulating film and electrically connected to the first electrode. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is an enlarged view of a main portion of the portion surrounded by a two-dot chain line II in FIG. [Diagram 3] FIG. 3 is an enlarged view of a main portion of a portion surrounded by a two-dot chain line III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6A] FIG. 6A is a diagram showing a part of a manufacturing process of the semiconductor device of FIG. [Figure 6B] FIG. 6B is a diagram showing the next step of FIG. 6A. [Figure 6C] FIG. 6C is a diagram showing the next step of FIG. 6B. [Figure 6D] FIG. 6D is a diagram showing the next step of FIG. 6C. [Figure 6E] FIG. 6E is a diagram showing the next step of FIG. 6D. [Figure 6F] FIG. 6F is a diagram showing the next step of FIG. 6E. [Figure 6G] FIG. 6G is a diagram showing the next step of FIG. 6F. [Figure 7] FIG. 7 is a diagram showing a state (simulation) of depletion at the outermost surface of the epitaxial layer. [Figure 8] FIG. 8 is a diagram for comparing the recovery characteristics of Sample 1 and Sample 2. In FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present disclosure. [Figure 10A] FIG. 10A is a diagram showing a part of a manufacturing process of the semiconductor device of FIG. [Figure 10B] FIG. 10B is a diagram showing the next step of FIG. 10A. [Figure 10C]FIG. 10C is a diagram showing the next step of FIG. 10B. [Figure 10D] FIG. 10D is a diagram showing the next step of FIG. 10C. [Figure 11] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to the sixth embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to the seventh embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic plan view of a semiconductor device according to the eighth embodiment of the present disclosure. [Figure 17] FIG. 17 is an enlarged view of a main portion of a portion surrounded by a two-dot chain line XVII in FIG. [Figure 18] FIG. 18 is an enlarged view of a main portion of a portion surrounded by a two-dot chain line XVIII in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a diagram for explaining the resistance distribution of the epitaxial layer. [Figure 22A] FIG. 22A is a diagram showing a part of the manufacturing process of the semiconductor device of FIG. [Figure 22B] FIG. 22B is a diagram showing the next step of FIG. 22A. [Figure 22C] FIG. 22C is a diagram showing the next step of FIG. 22B. [Figure 22D] FIG. 22D is a diagram showing the next step of FIG. 22C. [Figure 22E] FIG. 22E is a diagram showing the next step of FIG. 22D. [Figure 22F]FIG. 22F shows the next step of FIG. 22E. [Figure 22G] FIG. 22G shows the next step of FIG. 22F. [Fig. 22H] FIG. 22H is a diagram showing the next step of FIG. 22G. [Figure 22I] FIG. 22I shows the next step of FIG. 22H. [Figure 22J] FIG. 22J shows the next step of FIG. 22I. [Figure 23] FIG. 23 is a diagram showing the simulation results (source current) of the recovery characteristics. [Figure 24] FIG. 24 is a diagram showing a simulation result of the capacitance characteristic. [Diagram 25] FIG. 25 is a diagram showing the evaluation results of the recovery characteristics of Sample 5. In FIG. [Figure 26] FIG. 26 is a diagram showing the evaluation results of the recovery characteristics of Sample 6. In FIG. [Figure 27] FIG. 27 is a diagram showing the evaluation results of the recovery characteristics of Sample 7. In FIG. [Figure 28] FIG. 28 is a diagram showing the evaluation results of the recovery characteristics of Sample 8. In FIG. [Figure 29] FIG. 29 is a diagram for comparing the recovery characteristics of Sample 5 and Sample 8. In FIG. [Diagram 30] FIG. 30 is a diagram for comparing the withstand voltage characteristics (breakdown voltage (BVDSS)) of Sample 9 and Sample 10. In FIG. [Diagram 31] FIG. 31 is a diagram for comparing the recovery characteristics of Sample 9 and Sample 10. In FIG. [Diagram 32] FIG. 32 is a schematic cross-sectional view of a semiconductor device according to the ninth embodiment of the present disclosure. [Figure 33A] FIG. 33A is a diagram showing a part of the manufacturing process of the semiconductor device of FIG. [Figure 33B] FIG. 33B is a diagram showing the next step of FIG. 33A. [Figure 33C] FIG. 33C is a diagram showing the next step of FIG. 33B. [Figure 33D] FIG. 33D shows the next step of FIG. 33C. [Diagram 34] FIG. 34 is a schematic cross-sectional view of a semiconductor device according to the tenth embodiment of the present disclosure. [Diagram 35] FIG. 35 is a schematic cross-sectional view of a semiconductor device according to an eleventh embodiment of the present disclosure. [Diagram 36] FIG. 36 is a schematic cross-sectional view of a semiconductor device according to the twelfth embodiment of the present disclosure. [Figure 37] FIG. 37 is a schematic cross-sectional view of a semiconductor device according to the thirteenth embodiment of the present disclosure. [Figure 38] FIG. 38 is a schematic cross-sectional view of a semiconductor device according to the fourteenth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] <Embodiments of the present disclosure> First, embodiments of the present disclosure will be listed and described.

[0007] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a first surface and a second surface, an element structure formed on the first surface side of the semiconductor layer and including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region, a gate electrode facing the second region via a gate insulating film, a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region, and a first electrode formed on the semiconductor layer and electrically connected to the first region and the second region, the element structure including a first element structure and a second element structure, the first element structure being separated from the second region in a direction along the first surface of the semiconductor layer and further including a first column layer of the second conductivity type extending in a thickness direction of the semiconductor layer, and the second element structure further including a second electrode facing the third region via an insulating film and electrically connected to the first electrode.

[0008] For example, if the first conductivity type is n-type and the second conductivity type is p-type, when the third region is connected to a higher potential than the first region and a control voltage equal to or greater than the threshold voltage is applied to the gate electrode, an inversion layer (channel) is formed in the second region. This forms a current path between the first region and the third region. If no control voltage is applied to the gate electrode, the inversion layer is not formed, and the current path is blocked. The pn junction between the second region and the third region forms a parasitic diode. This parasitic diode is in the on state when a forward voltage is applied, and in the off state when a reverse voltage is applied. When the parasitic diode turns off, a reverse recovery phenomenon occurs. The current that flows as a result is the reverse recovery current. Due to the movement of carriers, a depletion layer extends from the pn junction, and the parasitic diode turns off.

[0009] In this embodiment, in the first element structure, the first column layer is separated from the second region and is electrically floating with respect to the second region. Therefore, the first column layer does not contribute to the operation of the parasitic diode, so that the steep extension of the depletion layer during the reverse recovery phenomenon is suppressed. On the other hand, in the second element structure, the first electrode is connected to the second electrode, so that the density of holes in the n-type region (third region) of the first surface of the semiconductor layer is locally reduced when the parasitic diode is turned off. This makes it easier for the depletion layer to extend from the first surface of the semiconductor layer, and the timing of the extension of the depletion layer from the first surface can be made earlier. This allows the depletion layer to gradually extend from the first surface of the semiconductor layer.

[0010] In this way, by combining the effects of the first and second element structures, the extension of the depletion layer in the thickness direction of the semiconductor layer is suppressed, and the speed at which the depletion layer extends when the parasitic diode is turned off is suppressed. This reduces the rate of change of the reverse recovery current (dir / dt), improving the recovery characteristics. The parasitic capacitance characteristics can also be improved.

[0011] In the first element structure, the first column layer is separated from the second region in the lateral direction along the first surface of the semiconductor layer. In other words, the second region is not formed on an extension of the first column layer in the thickness direction of the semiconductor layer, so that the first column layer does not come into contact with the second region even if it is brought closer to the first surface. Therefore, an increase in the thickness of the semiconductor layer caused by providing a gap between the first column layer and the second region can be suppressed, and an increase in the on-resistance of the current flowing in the thickness direction of the semiconductor layer can be suppressed.

[0012] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor layer may include a first element region in which a plurality of the first element structures are arranged, and a second element region in which a plurality of the second element structures are arranged.

[0013] According to this configuration, the first element structure and the second element structure are mixed in separate regions, thereby making it possible to further improve the parasitic capacitance characteristics.

[0014] In the semiconductor device according to the embodiment of the present disclosure, the first element region may be surrounded by the second element region.

[0015] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor layer may include an active region in which the element structure is formed and a peripheral region surrounding the active region, and the second element region may be formed on the peripheral portion of the active region.

[0016] In a semiconductor device according to one embodiment of the present disclosure, the first electrode may cover the first element region and the second element region, and the second element region may be formed along a peripheral portion of the first electrode.

[0017] In a semiconductor device according to one embodiment of the present disclosure, the third region may include a first portion formed between a top of the first column layer and the second region and having a first impurity concentration, and a second portion formed on the second surface side of the semiconductor layer relative to the first portion and having a second impurity concentration lower than the first impurity concentration.

[0018] According to this configuration, by making the first impurity concentration in the region near the parasitic diode relatively high, it is possible to suppress the abrupt extension of the depletion layer in the thickness direction (vertical direction) of the semiconductor layer during the reverse recovery phenomenon, and to keep the resistance of the region low. Meanwhile, in the region closer to the second surface side than the top of the first column layer, by making the second impurity concentration relatively lower than the first impurity concentration, it is possible to facilitate the extension of the depletion layer in the lateral direction along the first surface of the semiconductor layer from the first column layer, and therefore the breakdown voltage can be maintained.

[0019] In a semiconductor device according to one embodiment of the present disclosure, the first column layer may have an uneven side surface formed by repeating convex portions and concave portions multiple times in a thickness direction of the semiconductor layer, and a top of the first column layer may include the convex portion closest to the first surface of the semiconductor layer.

[0020] In a semiconductor device according to one embodiment of the present disclosure, the gate electrode may include a first portion extending in a first direction, a second portion extending in a second direction perpendicular to the first direction, and an intersection portion where the first portion and the second portion intersect, and the first column layer may be formed below the intersection portion of the gate electrode.

[0021] In a semiconductor device according to one embodiment of the present disclosure, the second region of the first element structure may be formed in a rectangular shape in a planar view, and the first column layer may be formed adjacent to a corner of the second region.

[0022] In a semiconductor device according to an embodiment of the present disclosure, a plurality of the first column layers may be formed at intervals, and the second region of the first element structure may be formed away from a region between adjacent ones of the first column layers.

[0023] In the semiconductor device according to the embodiment of the present disclosure, the second electrode may be formed between the second regions adjacent to each other.

[0024] In a semiconductor device according to one embodiment of the present disclosure, the second element structure may further include a second column layer of a second conductivity type formed in continuity with the second region and extending in a thickness direction of the semiconductor layer from the second region toward the second surface of the semiconductor layer.

[0025] According to this configuration, the semiconductor device has a superjunction structure in which the second column layers extend from the second region. Therefore, by determining the spacing of the second column layers so that the depletion layers extending laterally from the second column layers are integrated, it is possible to realize the inherent characteristics of the superjunction structure, namely, good on-resistance and switching speed.

[0026] In the semiconductor device according to the embodiment of the present disclosure, the first column layers and the second column layers may be regularly arranged at equal intervals.

[0027] In the semiconductor device according to the embodiment of the present disclosure, the element structure may include a planar gate structure.

[0028] In the semiconductor device according to the embodiment of the present disclosure, the element structure may include a trench gate structure.

[0029] A semiconductor device according to an embodiment of the present disclosure may include a MISFET having the first region as a source region and the second region as a body region.

[0030] A semiconductor device according to one embodiment of the present disclosure may include an IGBT having the first region as an emitter region, the second region as a base region, and a collector region of a second conductivity type in contact with the third region. Detailed Description of the Embodiments of the Present Disclosure Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [First embodiment] <Overall structure of semiconductor device A1> FIG. 1 is a schematic plan view of a semiconductor device A1 according to a first embodiment of the present disclosure.

[0031] The semiconductor device A1 has a quadrangular shape in a plan view. For example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed in the semiconductor device A1. An electrode film 1 is formed on a surface of the semiconductor device A1. The electrode film 1 covers almost the entire surface of the semiconductor device A1. In this embodiment, the electrode film 1 includes a source electrode film 2 and a gate electrode film 3. In this embodiment, the source electrode film 2 may be an example of a "first electrode" recited in the claims.

[0032] The source electrode film 2 is formed so as to cover the active region 4 of the semiconductor device A1. The active region 4 is, for example, a region in which element structures 39 and 40 described below are formed. The source electrode film 2 is formed over almost the entire active region 4. A recess 5 is selectively formed in the source electrode film 2 in a plan view. In this embodiment, the recess 5 is formed in one corner of the semiconductor device A1.

[0033] The gate electrode film 3 is formed in a peripheral region 6 of the semiconductor device A1 surrounding the active region 4. The gate electrode film 3 integrally includes a pad portion 7 formed in a recess 5 of the source electrode film 2 in a plan view, and a finger portion 8 extending from the pad portion 7 along a side of the semiconductor device A1. In this embodiment, the finger portion 8 is formed in a closed ring shape surrounding the source electrode film 2. Of course, the finger portion 8 does not have to be in a closed ring shape. For example, the finger portion 8 may extend parallel to two opposing sides of the semiconductor device A1 (for example, the top and bottom sides in FIG. 1) and terminate at a corner of the semiconductor device A1.

[0034] A part of the electrode film 1 is covered with a passivation film 9 formed on the surface of the semiconductor device A1. The passivation film 9 collectively covers the source electrode film 2 and the gate electrode film 3, and has a plurality of openings 10, 11 that expose parts of the electrode films 1. In Fig. 1, a part of the source electrode film 2, a part of the pad portion 7 of the gate electrode film 3, and a finger portion 8 are indicated by dashed lines, and the dashed line parts are the parts covered with the passivation film 9.

[0035] A part of the source electrode film 2 is exposed from the first pad opening 10 as a source pad 12, and a part (pad portion 7) of the gate electrode film 3 is exposed from the second pad opening 11 as a gate pad 13. A bonding material such as a bonding wire may be bonded to each of the pads 12, 13 when packaging the semiconductor device A1.

[0036] FIG. 2 is an enlarged view of a portion surrounded by a two-dot chain line II in FIG. 1. FIG. 3 is an enlarged view of a portion surrounded by a two-dot chain line III in FIG. 1. More specifically, FIG. 2 shows the internal structure of the boundary between the region of the source electrode film 2 covered with the passivation film 9 and the source pad 12. FIG. 3 shows the internal structure of the region of the source electrode film 2 covered with the passivation film 9. The region of the source electrode film 2 covered with the passivation film 9 is a closed ring surrounding the source pad 12, and is the peripheral portion of the source electrode film 2. In addition, since this peripheral portion is the outer periphery of the active region 4 surrounding the central portion 14 of the active region 4 below the source pad 12, it may be referred to as the peripheral portion 15 of the active region 4. In addition, in FIG. 2 and FIG. 3, for convenience of understanding, a part of the gate electrode 23 is hatched (for clarity, the portion of the gate electrode 23 facing the body region 19 is not hatched).

[0037] Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2. Fig. 5 is a cross-sectional view taken along line VV in Fig. 3. For ease of explanation, three mutually perpendicular directions are defined as the X direction, the Y direction, and the Z direction. The Z direction is the thickness direction of the semiconductor device A1. The X direction is the left-right direction in the plan view of the semiconductor device A1 (see Figs. 2 and 3). The Y direction is the up-down direction in the plan view of the semiconductor device A1 (see Figs. 2 and 3).

[0038] The semiconductor device A1 may include a semiconductor substrate 16, an epitaxial layer 17, a column layer 18, a body region 19, a source region 20, a body contact region 21, a gate insulating film 22, a gate electrode 23, a p-type region 24, a p-type contact region 25, an insulating film 26, a floating electrode 27, and an interlayer insulating film 28. In this embodiment, the epitaxial layer 17, the body region 19, and the source region 20 may be examples of the "semiconductor layer," the "second region," and the "first region" recited in the claims, respectively.

[0039] In this embodiment, the semiconductor substrate 16 is + The substrate may be a semiconductor substrate of the same type (e.g., a silicon substrate). Alternatively, the substrate may be a substrate generally used for transistors, such as a SiC substrate or a GaN substrate. + The n-type semiconductor substrate 16 may be a semiconductor substrate that is grown by doping with n-type impurities. Examples of n-type impurities that can be used include P (phosphorus), As (arsenic), and Sb (antimony). + The impurity concentration of the semiconductor substrate 16 is, for example, 1.0×10 18 cm -3 ~5.0×10 20 cm -3 Semiconductor substrate 16 has a first side 29 and an opposing second side 30.

[0040] The epitaxial layer 17 is, for example, + On the semiconductor substrate 16, n-type impurities are implanted and epitaxially grown. -Examples of n-type impurities are as described above. - The impurity concentration of the epitaxial layer 17 is n + lower than the semiconductor substrate 16 of the type, for example, 1.0×10 10 cm -3 ~1.0×10 16 cm -3 In addition, the n - The area of ​​the type is n - Alternatively, the drift region 31 may be referred to as a "type drift region 31." In this embodiment, the drift region 31 may be an example of a "third region" recited in the claims.

[0041] The epitaxial layer 17 (drift region 31) has a first surface 32 and an opposite second surface 33. The first surface 32 is a surface on which element structures 39 and 40, which will be described later, are formed, and may be referred to as an element main surface. The second surface 33 is a surface that contacts the first surface 29 of the semiconductor substrate 16.

[0042] The column layer 18 may be a semiconductor layer formed by ion-implanting a p-type impurity into the epitaxial layer 17. Examples of the p-type impurity include B (boron), Al (aluminum), and Ga (gallium). The impurity concentration of the column layer 18 is, for example, 1.0×10 15 cm -3 ~1.0×10 19 cm -3 It may be to some extent.

[0043] As shown in FIGS. 4 and 5, the column layer 18 extends in the Z direction, for example, from the upper part of the epitaxial layer 17 and extends beyond the central part of the epitaxial layer 17 in the Z direction. As shown in FIGS. 2 and 3, the column layer 18 has a circular shape in plan view. Note that the shape of the column layer 18 in plan view is not limited to a circle, and may be, for example, a triangular shape, a quadrangular shape, or the like. Further, the side surface 34 of the column layer 18 along the Z direction has a plurality of convex portions 35 and concave portions 36 repeatedly formed along the Z direction, and has a concavo-convex surface that is periodically undulated. The number of the concavo-convex portions 35 and 36 generally substantially coincides with the number of stages of the n-type semiconductor layer 63 (FIGS. 6A and 6B) described later.

[0044] As shown in FIGS. 2 and 3, the column layers 18 are regularly arranged at equal intervals from each other. In this embodiment, the plurality of column layers 18 are arranged such that the intervals (pitches) in the X direction and the Y direction are the same. Further, as shown in FIG. 2, the column layers 18 are arranged in a matrix at equal intervals from each other across the peripheral portion 15 and the central portion 14 of the active region 4.

[0045] A plurality of body regions 19 are formed on the surface portion of the epitaxial layer 17. More specifically, it may be a semiconductor layer formed by ion-implanting p-type impurities into an n - -type epitaxial layer 17. Examples of the p-type impurities are as described above. Further, the impurity concentration of the body region 19 is, for example, 1.0×10 15 cm -3 ~1.0×10 19 cm -3 or so, and may be the same as that of the column layer 18. Each body region 19 has a quadrangular shape in plan view, and may have a width of, for example, 3 μm to 10 μm. Further, as shown in FIGS. 4 and 5, each body region 19 forms a parasitic diode 37 (body diode) at the interface (pn junction surface) with the drift region 31.

[0046] The source region 20 is formed in an inner region of each body region 19. The source region 20 is selectively formed in a surface portion of the body region 19 in the inner region. The source region 20 may be formed by selectively ion-implanting n-type impurities into the body region 19. Examples of n-type impurities are as described above. The impurity concentration of the source region 20 is higher than that of the drift region 31, and may be, for example, 1.0×10 18 cm -3 ~5.0×10 20 cm -3 It may be to some extent.

[0047] The source region 20 has a rectangular shape in a plan view, and is separated inward by a predetermined distance from the periphery of the body region 19 (the boundary between the body region 19 and the drift region 31). As a result, in the surface portion of the epitaxial layer 17 including the drift region 31, the body region 19, etc., the surface portion of the body region 19 is interposed between the source region 20 and the drift region 31. This interposed surface portion is a channel region 38 in which a channel is formed when an appropriate voltage is applied to the gate electrode 23.

[0048] The body contact region 21 has a rectangular shape in a plan view, and is selectively formed in a surface portion of the body region 19. The body contact region 21 extends toward the second face 33 of the epitaxial layer 17 so as to pass through the source region 20 and reach the body region 19. The body contact region 21 may be formed by selectively ion-implanting p-type impurities into the body region 19. Examples of the p-type impurities are as described above. The impurity concentration of the body contact region 21 is higher than that of the body region 19, and may be, for example, 5.0×10 17 cm -3 ~1.0×10 19 cm -3 It may be to some extent.

[0049] Furthermore, MISFET element structures 39, 40 (unit cell) are configured by the body region 19, the source region 20, and the body contact region 21. Between the element structures 39, 40 adjacent to each other, a part of the drift region 31 is exposed.

[0050] In this embodiment, the element structures 39, 40 may include a first element structure 39 and a second element structure 40. The first element structure 39 is arranged in a central portion 14 of the active region 4 as shown in FIG. 2, and the second element structure 40 is arranged in a peripheral portion 15 of the active region 4 as shown in FIGS. 2 and 3. The central portion 14 of the active region 4 is a region in which a plurality of first element structures 39 are arranged, and may be referred to as a first element region 41. On the other hand, the peripheral portion 15 of the active region 4 is a region in which a plurality of second element structures 40 are arranged, and may be referred to as a second element region 42.

[0051] 2, the first element structure 39 is an element structure including a body region 19 formed away from the column layer 18 so as not to overlap the column layer 18 in a plan view, and the column layer 18 adjacent to the body region 19. The body region 19 and the column layer 18 of the first element structure 39 may be referred to as a first body region 191 and a first column layer 181, respectively.

[0052] The first column layer 181 is physically separated from the first body region 191 in a direction along the first surface 32 of the epitaxial layer 17 (in this embodiment, a direction along the XY plane), and is a floating region in the epitaxial layer 17. As shown in FIG. 2, the first column layer 181 is formed adjacent to a corner 43 of the first body region 191 having a rectangular shape in a plan view. For example, the first column layer 181 may be formed adjacent to each of the four corners 43 of one first body region 191. In addition, the first body region 191 may be formed away from a region 44 between adjacent first column layers 181 (a region sandwiched between adjacent first column layers 181). In addition, each first column layer 181 may be shared by adjacent first element structures 39.

[0053] 4, the first column layer 181 may have a top 45 (in this embodiment, the convex portion 35 of the first column layer 181 closest to the first surface 32 of the epitaxial layer 17) at a position deeper than the bottom of the first body region 191. In other words, the distance D from the first surface 32 of the epitaxial layer 17 to the first column layer 181 C is a distance D from the first surface 32 to the bottom of the first body region 191. B It may be longer than that.

[0054] 2 and 3, the second element structure 40 is an element structure including, in a plan view, a body region 19 overlapping the column layer 18 and the column layer 18 adjacent to the body region 19. The body region 19 and the column layer 18 of the second element structure 40 may be referred to as a second body region 192 and a second column layer 182, respectively.

[0055] The second column layer 182 is formed in a region inside each second body region 192. More specifically, the second column layer 182 is formed to be continuous with a lower portion of the second body region 192, and extends from the second body region 192 toward the second surface 33 of the epitaxial layer 17. The bottom portions of the second column layer 182 and the first column layer 181 may be located at the same depth position from the first surface 32 of the epitaxial layer 17.

[0056] 2, the interval between the adjacent first body region 191 and second body region 192 may be selectively large at the boundary 46 between the first element region 41 and the second element region 42. For example, in the first element region 41 and the second element region 42, the interval between the first body region 191 and the second body region 192 (pitch P 1 ,P 2 ) is 5 μm to 20 μm and may be the same as each other. In contrast, the distance P 3 The pitch P may be 5 μm to 20 μm. 3 An example of the range is 5 μm to 20 μm, and the pitch P 1 ,P2 is the same as an example of the range, but the pitch P 3 is within the above range for the pitch P 1 , P 2 may be larger.

[0057] Also, as shown in FIG. 4, the drift region 31 may include a first portion 47 and a second portion 48 having different impurity concentrations from each other. The first portion 47 is formed between the top 45 of the first column layer 181 and the first body region 191 and has a first impurity concentration. On the other hand, the second portion 48 is formed on the second surface 33 side of the epitaxial layer 17 with respect to the first portion 47 and has a second impurity concentration lower than the first impurity concentration. More specifically, the boundary portion 49 between the first portion 47 and the second portion 48 may be set in the middle in the Z direction of the top 45 of the first column layer 181. In this embodiment, the first impurity concentration is 1×10 10 cm -3 ~1×10 13 cm -3 or so, and the second impurity concentration may be 1×10 10 cm -3 ~1×10 13 cm -3 or so. Note that an example of the first impurity concentration is 1×10 10 cm -3 ~1×10 13 cm -3 and is the same as an example of the range of the second impurity concentration, but the first impurity concentration may be larger than the second impurity concentration within the above range.

[0058] The gate insulating film 22 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, or the like. Also, the gate electrode 23 may be made of polysilicon formed by implanting impurities. When the gate insulating film 22 is made of a silicon oxide film, the MISFET may be referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0059] The gate insulating film 22 covers at least the surface of the body region 19. In this embodiment, the gate insulating film 22 covers a part of the surface of the source region 20, the surfaces of the channel region 38 and the drift region 31. More specifically, the gate insulating film 22 is formed in a pattern having openings in the body contact regions 21 of each element structure 39, 40 and a part of the source region 20 connected to the body contact regions 21.

[0060] The gate insulating film 22 is interposed between the gate electrode 23 and the epitaxial layer 17. Thereby, the gate electrode 23 faces the channel region 38 via the gate insulating film 22. The gate electrode 23 is formed in substantially the same pattern as the gate insulating film 22, thereby constituting a planar gate structure. Also, the gate insulating film 22 may have a thickness of, for example, 300 Å to 700 Å.

[0061] Also, in this embodiment, as shown in FIGS. 2 and 3, the gate electrode 23 is formed across the first element region 41 and the second element region 42. The gate electrode 23 is formed in a lattice pattern in each of the first element region 41 and the second element region 42. More specifically, in the first element region 41 and the second element region 42, the gate electrode 23 includes a first portion 50 extending in the X direction, a second portion 51 extending in the Y direction orthogonal to the X direction, and an intersection portion 52 where the first portion 50 and the second portion 51 intersect. In the first element region 41, the first column layer 181 is formed below the intersection portion 52 of the gate electrode 23.

[0062] Also, in this embodiment, the gate electrode 23 includes a dummy gate electrode 56 in the second element structure 40. The dummy gate electrode 56 is physically separated from the surrounding gate electrode 23. More specifically, the dummy gate electrode 56 is separated from the surrounding gate electrode 23 with a gap 79 therebetween. In this embodiment, the dummy gate electrode 56 may be an example of the "second electrode" described in the claims.

[0063] 2 and 3, a pair of gaps 79 are formed connecting the adjacent second body regions 192. The pair of gaps 79 face each other with a gap therebetween in the Y direction, for example. A portion of the gate electrode 23 sandwiched between the pair of gaps 79 is the dummy gate electrode 56. As a result, the dummy gate electrode 56 is formed between the adjacent second body regions 192. The gap 79 may be linear as shown in FIGS. 2 and 3, or may be curved.

[0064] In this embodiment, the dummy gate electrodes 56 are formed between the second body regions 192 adjacent to each other in the X direction. Moreover, the dummy gate electrodes 56 are formed between every other second body region 192 adjacent to each other in the X direction. As a result, in the second element region 42, a first column 57 in which the dummy gate electrodes 56 are arranged along the Y direction and a second column 58 in which the dummy gate electrodes 56 are not arranged may be formed.

[0065] Therefore, in the second element region 42, a dummy gate electrode 56 is formed between the second body regions 192 adjacent to each other in the X direction, and a gate electrode 23 is formed between the second body regions 192 adjacent to each other in the Y direction. As a result, a part of the channel region 38 formed in a closed ring shape (in this embodiment, one side of the channel region 38) faces the dummy gate electrode 56, and the remaining part (in this embodiment, the remaining three sides of the channel region 38) faces the gate electrode 23.

[0066] The insulating film 59 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, etc. The insulating film 59 is interposed between the dummy gate electrode 56 and the epitaxial layer 17. The insulating film 59 may be formed integrally with the gate insulating film 22.

[0067] A plurality of p-type regions 24 are formed on the surface of the epitaxial layer 17. More specifically, -Alternatively, the p-type region 24 may be a semiconductor layer formed by ion-implanting a p-type impurity into the p-type epitaxial layer 17. Examples of the p-type impurity are as described above. The impurity concentration of the p-type region 24 is, for example, 1.0×10 15 cm -3 ~1.0×10 19 cm -3 and may be the same as that of body region 19. Each p-type region 24 has, for example, a rectangular shape extending in the Y direction in a plan view. Furthermore, p-type regions 24 are arranged outside second element structure 40 in second element region 42.

[0068] The p-type contact region 25 has, for example, a rectangular shape in a plan view extending in the Y direction, and is selectively formed on a surface portion of the p-type region 24. As a result, the closed ring-shaped p-type region 24 is exposed around the p-type contact region 25. The p-type contact region 25 may be formed by selectively ion-implanting p-type impurities into the p-type region 24. Examples of the p-type impurities are as described above. The impurity concentration of the p-type contact region 25 is higher than that of the p-type region 24, for example, 5.0×10 17 cm -3 ~1.0×10 19 cm -3 and may be the same as the body contact region 21.

[0069] The insulating film 26 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, or a tantalum oxide film. The floating electrode 27 may be made of polysilicon formed by implanting impurities. The insulating film 26 covers the exposed portion of the closed ring-shaped p-type region 24, and the closed ring-shaped floating electrode 27 is formed on the insulating film 26. The floating electrode 27 is an electrically floating conductive layer.

[0070] The interlayer insulating film 28 is formed on the epitaxial layer 17. The interlayer insulating film 28 covers the gate electrode 23, the dummy gate electrode 56, and the floating electrode 27. The interlayer insulating film 28 may be made of an insulating material such as a silicon oxide film, a silicon nitride film, or TEOS (tetraethoxysilane).

[0071] In the interlayer insulating film 28, a first contact hole 53 exposing the body contact region 21 and the source region 20 of the MISFET, a second contact hole 54 exposing the p-type contact region 25, and a third contact hole 60 exposing the dummy gate electrode 56 are formed. The first contact hole 53 penetrates the interlayer insulating film 28 and the gate insulating film 22.

[0072] The above-mentioned electrode film 1 is formed on the interlayer insulating film 28. The electrode film 1 may be made of aluminum or other metals. Figures 4 and 5 show the source electrode film 2. The source electrode film 2 may be simply called a source electrode.

[0073] The source electrode film 2 is connected to the body contact region 21 and the source region 20 in the first contact hole 53 as shown in Figures 4 and 5, is connected to the p-type contact region 25 in the second contact hole 54 as shown in Figure 5, and is connected to the dummy gate electrode 56 in the third contact hole 60 as shown in Figures 4 and 5.

[0074] As a result, the source electrode film 2 connects in parallel the body region 19 and source region 20 of the element structure functioning as a MISFET (an active cell that can pass a current between the drain and source) and the dummy gate electrode 56 and p-type region 24 (an inactive cell that cannot pass a current between the drain and source) that do not function as a MISFET. Note that the gate electrode film 3 is connected to the gate electrode 23 at a position not shown.

[0075] A drain electrode 55 is formed on the second surface 30 of the semiconductor substrate 16. The drain electrode 55 may be made of aluminum or another metal. The drain electrode 55 is electrically connected to the drift region 31 through the semiconductor substrate 16. <Manufacturing method of semiconductor device A1> 6A to 6G are diagrams showing the manufacturing process of the semiconductor device A1 in the order of steps.

[0076] 6A, in order to manufacture the semiconductor device A1, first, an initial base layer 61 is formed by epitaxial growth on the semiconductor substrate 16. Next, a p-type impurity 62 is selectively implanted into the surface of the initial base layer 61 at a position where the column layer 18 is to be formed.

[0077] Next, referring to FIG. 6B, a plurality of n-type semiconductor layers 63 are stacked on the initial base layer 61 by multi-epitaxial growth, which repeats a process of forming an n-type semiconductor layer 63 while selectively injecting p-type impurities 62 into positions where the column layers 18 are to be formed.

[0078] 6C, the uppermost n-type semiconductor layer 64 is laminated without implanting p-type impurities. As a result, the multiple n-type semiconductor layers 63, 64 and the initial base layer 61 are integrated to form the epitaxial layer 17 (drift region 31). At this time, the impurity concentration when the uppermost n-type semiconductor layer 64 is grown is higher than the impurity concentration when the n-type semiconductor layer 63 below the uppermost n-type semiconductor layer 64 is grown. As a result, the first portion 47 and the second portion 48 of the drift region 31 can be formed.

[0079] 6D, an annealing process (1000° C. to 1200° C.) is then performed to drive-diffuse the p-type impurities in the initial base layer 61 and the multiple n-type semiconductor layers 63 and 64. As a result, a column layer 18 is formed in the epitaxial layer 17.

[0080] 6E, p-type impurities are selectively implanted into a surface portion of the epitaxial layer 17 to form a body region 19 and a p-type region 24 (not shown). In the second element region 42, the body region 19 (second body region 192) is connected to the second column layer 182. Next, n-type impurities are selectively implanted into a surface portion of the body region 19 to form a source region 20. Next, p-type impurities are selectively implanted into a surface portion of the body region 19 and a surface portion of the p-type region 24 to form a body contact region 21 and a p-type contact region 25 (not shown).

[0081] Next, referring to FIG. 6F, a gate insulating film 22, an insulating film 26 (not shown), and an insulating film 59 are formed on the epitaxial layer 17. The gate insulating film 22, the insulating film 26, and the insulating film 59 may be formed by growing an oxide film by thermal oxidation of the semiconductor crystal surface, and then patterning the oxide film. Next, a gate electrode 23 is formed on the gate insulating film 22, a floating electrode 27 (not shown) is formed on the insulating film 26, and a dummy gate electrode 56 is formed on the insulating film 59. The gate electrode 23, the floating electrode 27, and the dummy gate electrode 56 may be formed, for example, by forming a polysilicon film to which an impurity is added on the entire surface, and then selectively etching the polysilicon film by photolithography. Next, an interlayer insulating film 28 is formed so as to cover the gate electrode 23, the floating electrode 27, and the dummy gate electrode 56. Next, a first contact hole 53, a second contact hole 54 (not shown), and a third contact hole 60 are formed in the interlayer insulating film 28 by photolithography.

[0082] Next, referring to FIG. 6G, the semiconductor substrate 16 is ground from the second surface 30 side to be flattened. The amount of grinding is not particularly limited, but it is preferable that the semiconductor substrate 16 after grinding has a thickness of 90 μm to 310 μm, for example. Next, a source electrode film 2 and a gate electrode film 3 (not shown) are formed on the interlayer insulating film 28. Next, a passivation film 9 (not shown) is formed so as to cover the source electrode film 2 and the gate electrode film 3. Next, pad openings 10, 11 (not shown) are formed in the passivation film 9 by photolithography.

[0083] Thereafter, a drain electrode 55 is formed on the second surface 30 of the semiconductor substrate 16, thereby obtaining the above-mentioned semiconductor device A1. <Functions and Effects of Semiconductor Device A1> First, the operation of the MISFET of the semiconductor device A1 will be described. When the drain electrode 55 is connected to a potential higher than the source electrode film 2 and a control voltage equal to or higher than the threshold voltage is applied to the gate electrode 23, an inversion layer (channel) is formed in the body region 19 (channel region 38). This forms a current path between the source region 20 and the drift region 31. If no control voltage is applied to the gate electrode 23, no inversion layer is formed, and the current path between the source and drain is cut off. The parasitic diode 37 between the body region 19 and the drift region 31 is in an on state when a forward voltage is applied, and in an off state when a reverse voltage is applied. When the parasitic diode 37 is turned off, a reverse recovery phenomenon occurs. The current that flows as a result is the reverse recovery current. Due to the movement of carriers, a depletion layer extends from the pn junction, and the parasitic diode 37 is in an off state.

[0084] In this embodiment, in the first element structure 39, the first column layer 181 is separated from the first body region 191 and is electrically floating with respect to the first body region 191. Therefore, the first column layer 181 does not contribute to the operation of the parasitic diode 37, so that the steep extension of the depletion layer during the reverse recovery phenomenon is suppressed. This suppresses the extension of the depletion layer in the Z direction of the epitaxial layer 17, thereby suppressing the speed at which the depletion layer extends when the parasitic diode 37 is turned off.

[0085] On the other hand, in the second element structure 40, since the source electrode film 2 is connected to the dummy gate electrode 56, when the parasitic diode 37 is turned off, the n - The hole density in the n-type drift region 31 is locally decreased. This makes it easier for the depletion layer to extend from the first surface 32 of the epitaxial layer 17, and the timing of the depletion layer extending from the first surface 32 of the epitaxial layer 17 can be accelerated. This allows the depletion layer to extend gradually from the first surface 32 of the epitaxial layer 17. More specifically, the hole density distribution when the outermost surface (first surface 32) of the epitaxial layer 17 begins to be depleted was confirmed by simulation, and the result is as shown in FIG. 7. From FIG. 7, it can be seen that the hole density distribution in the n-type drift region 31 facing the gate electrode 23 is gradually increased. - The depletion layer 78 is not formed on the first surface 32 of the drift region 31, and depletion has not started. However, the n - A depletion layer 78 is formed in the first surface 32 of the n-type drift region 31. - It has been found that the timing of the extension of the depletion layer 78 can be made earlier in the first surface 32 of the drift region 31 of the type.

[0086] In this way, by combining the effects of the first element structure 39 and the second element structure 40, the extension of the depletion layer in the epitaxial layer 17 in the Z direction is suppressed, and the speed at which the depletion layer extends when the parasitic diode 37 is turned off is thereby suppressed. This reduces the rate of change (dir / dt) of the reverse recovery current, improving the recovery characteristics. In addition, the parasitic capacitance characteristics can also be improved.

[0087] For example, a simulation was performed on the structure of the semiconductor device A1 and the semiconductor device B1. In the semiconductor device B1, the dummy gate electrode 56 is not formed, and the first element structure 39 has a structure in which the column layer 18 is connected to the body region 19, similar to the second column layer 182. From these simulation results, it was confirmed that the structure of the semiconductor device A1 has a reduction effect on Crss (feedback capacitance) and Qgd (gate-drain charge amount), and also confirmed improvements in the capacitance ratio and reverse recovery time (trr).

[0088] Next, the improvement in recovery characteristics due to the structure of the semiconductor device A1 described above was verified by an experiment. FIG. 8 is a diagram for comparing the recovery characteristics of Sample 1 and Sample 2.

[0089] Sample 1 is an example having a dummy gate electrode 56, and adopting a structure in which the first column layer 181 is separated from the body region 19 as the first element structure 39 of the semiconductor device A1. Sample 2 is an example not having a dummy gate electrode 56, and adopting a structure in which the column layer 18 is connected to the body region 19, similarly to the second column layer 182, as the first element structure 39 of the semiconductor device A1. In both Sample 1 and Sample 2, the drift region 31 is irradiated with He.

[0090] 8, the recovery current waveforms of Sample 1 and Sample 2 are superimposed. It can be seen from FIG. 8 that the ringing noise in period tb of Sample 1 is significantly improved compared to Sample 2.

[0091] Furthermore, in the semiconductor device A1, the first column layer 181 is spaced apart from the first body region 191 in the lateral direction along the first surface 32 of the epitaxial layer 17. That is, in the Z direction of the epitaxial layer 17, the first body region 191 is not formed on an extension of the first column layer 181, so that even if the first column layer 181 is brought closer to the first surface 32, it will not come into contact with the first body region 191. Therefore, an increase in the thickness of the epitaxial layer 17 caused by providing a space between the first column layer 181 and the first body region 191 can be suppressed, and an increase in the on-resistance of the current flowing in the Z direction of the drift region 31 can be suppressed.

[0092] Furthermore, in the semiconductor device A1, by relatively increasing the first impurity concentration in the first portion 47 of the drift region 31, which is a region in the vicinity of the parasitic diode 37, it is possible to suppress the extension of the depletion layer in the Z direction (vertical direction) of the drift region 31 during the reverse recovery phenomenon, and to keep the resistance of the first portion 47 low. On the other hand, by relatively decreasing the second impurity concentration in the second portion 48 on the second surface 33 side from the top 45 of the first column layer 181, it is possible to easily extend the depletion layer in the lateral direction from the first column layer 181 to the first surface 32 of the epitaxial layer 17, and therefore it is possible to maintain the breakdown voltage.

[0093] Furthermore, the semiconductor device A1 has, as the second element structure 40, a superjunction structure in which the second column layers 182 extend from the second body region 192. Therefore, by determining the spacing of the second column layers 182 so that the depletion layers extending laterally from the second column layers 182 are integrated, it is possible to realize the inherent characteristics of the superjunction structure, that is, good on-resistance and switching speed. [Second embodiment] FIG. 9 is a schematic cross-sectional view of a semiconductor device A2 according to the second embodiment of the present disclosure.

[0094] The column layer 18 may have an uneven side surface 34 as in the first embodiment, or may have a flat side surface 65 as in the semiconductor device A2. In this case, the semiconductor device A2 may be manufactured through the steps shown in Figures 10A to 10D, for example.

[0095] To manufacture the semiconductor device A2, first, an initial base layer 66 is formed on the semiconductor substrate 16 by epitaxial growth, as shown in FIG. 10A.

[0096] 10B, in the initial base layer 66, a region in which the column layer 18 is to be formed is selectively removed by etching, thereby forming a trench 67 (more specifically, a deep trench).

[0097] 10C, the trenches 67 are backfilled with a semiconductor layer while implanting p-type impurities. As a result, the column layer 18 is formed in the initial base layer 66.

[0098] 10D, an n-type semiconductor layer 68 is laminated on the initial base layer 66 without implanting p-type impurities. As a result, the n-type semiconductor layer 68 and the initial base layer 66 are integrated to form the epitaxial layer 17 (drift region 31). At this time, the impurity concentration when growing the n-type semiconductor layer 68 is higher than the impurity concentration when growing the initial base layer 66. As a result, the first portion 47 and the second portion 48 of the drift region 31 can be formed.

[0099] Thereafter, the semiconductor device A2 can be obtained through steps similar to those shown in FIGS. 6E to 6G. [Third embodiment] FIG. 11 is a schematic cross-sectional view of a semiconductor device A3 according to the third embodiment of the present disclosure.

[0100] The first column layer 181 may have the top 45 at a position deeper than the bottom of the first body region 191 as in the first embodiment, but may also have the top 45 at the same depth position as the bottom of the first body region 191 as in this semiconductor device A3. That is, the distance D from the first surface 32 of the epitaxial layer 17 to the first column layer 181 C may be the same as the distance D from the first surface 32 to the bottom of the first body region 191 B . [Fourth Embodiment] FIG. 12 is a schematic cross-sectional view of a semiconductor device A4 according to the fourth embodiment of the present disclosure.

[0101] The first column layer 181 may have the top 45 at a position deeper than the bottom of the first body region 191 as in the first embodiment, but may also have the top 45 at a position shallower than the bottom of the first body region 191 as in this semiconductor device A4. That is, the distance D from the first surface 32 of the epitaxial layer 17 to the first column layer 181 C may be shorter than the distance D from the first surface 32 to the bottom of the first body region 191 B . [Fifth Embodiment] FIG. 13 is a schematic cross-sectional view of a semiconductor device A5 according to the fifth embodiment of the present disclosure.

[0102] The element structure of the semiconductor device A5 may be a planar gate structure as in the first embodiment, but may also be a trench gate structure as in this semiconductor device A5.

[0103] The semiconductor device A5 includes a gate trench 69, a gate insulating film 70, and a gate electrode 71.

[0104] The gate trench 69 penetrates the source region 20 and the body region 19 from the first surface 32 of the epitaxial layer 17. The gate insulating film 70 is formed on the inner surface of the gate trench 69. The gate electrode 71 is embedded inside the gate insulating film 70 in the gate trench 69. Thereby, a trench gate structure is formed.

[0105] The first column layer 181 may be formed below the gate trench 69 and thus separated from the first body region 191 in the direction along the first surface 32 of the epitaxial layer 17. In the semiconductor device A5, the first column layer 181 is further separated from the gate trench 69 toward the second surface 33 of the epitaxial layer 17. [Sixth embodiment] FIG. 14 is a schematic cross-sectional view of a semiconductor device A6 according to the sixth embodiment of the present disclosure.

[0106] The first column layer 181 may be separated from the gate trench 69 as in the fifth embodiment, or may be in contact with the gate trench 69 as in the semiconductor device A6. More specifically, the first column layer 181 may be formed continuous with the bottom of the gate trench 69 and extend from the gate trench 69 toward the second surface 33 of the epitaxial layer 17. [Seventh embodiment] FIG. 15 is a schematic cross-sectional view of a semiconductor device A7 according to the seventh embodiment of the present disclosure.

[0107] The element structure may be a MISFET as in the above-mentioned embodiment, but may also be an IGBT (Insulated Gate Bipolar Transistor) as in this semiconductor device A7. + The semiconductor substrate 16 is + A semiconductor substrate 72 (p + The drain electrode 55 may be referred to as a collector electrode 74, and the source electrode film 2 may be referred to as an emitter electrode film 75. + The source region 20 is n + The p-type emitter region 76 may be referred to as a p-type emitter region, and the p-type body region 19 may be referred to as a p-type base region 77 (first base region 771 and second base region 772). [Eighth embodiment] <Overall structure of semiconductor device A8> FIG. 16 is a schematic plan view of a semiconductor device A8 according to the eighth embodiment of the present disclosure.

[0108] The semiconductor device A8 has a quadrangular shape in a plan view. For example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed in the semiconductor device A8. An electrode film 201 is formed on the surface of the semiconductor device A8. The electrode film 201 covers almost the entire surface of the semiconductor device A8. In this embodiment, the electrode film 201 includes a source electrode film 202 and a gate electrode film 203. In this embodiment, the source electrode film 202 may be an example of a "first electrode" recited in the claims.

[0109] The source electrode film 202 is formed so as to cover an active region 204 of the semiconductor device A8. The active region 204 is, for example, a region in which element structures 239 and 240 described below are formed. The source electrode film 202 is formed over almost the entire active region 204. A recess 205 is selectively formed in the source electrode film 202 in a plan view. In this embodiment, the recess 205 is formed in one corner of the semiconductor device A8.

[0110] The gate electrode film 203 is formed in a peripheral region 206 of the semiconductor device A8 surrounding the active region 204. The gate electrode film 203 integrally includes a pad portion 207 formed in a recess 205 of the source electrode film 202 in a plan view, and a finger portion 208 extending from the pad portion 207 along a side of the semiconductor device A8. In this embodiment, the finger portion 208 is formed in a closed ring shape surrounding the source electrode film 202. Of course, the finger portion 208 does not have to be in a closed ring shape. For example, the finger portion 208 may extend parallel to two opposing sides of the semiconductor device A8 (for example, the upper and lower sides in FIG. 16) and terminate at a corner of the semiconductor device A8.

[0111] A part of the electrode film 201 is covered with a passivation film 209 formed on the surface of the semiconductor device A8. The passivation film 209 collectively covers the source electrode film 202 and the gate electrode film 203, and has a plurality of openings 210, 211 that expose parts of the electrode films 201. In Fig. 16, a part of the source electrode film 202, a part of the pad portion 207 of the gate electrode film 203, and the finger portion 208 are indicated by dashed lines, and the dashed line parts are the parts covered with the passivation film 209.

[0112] A part of the source electrode film 202 is exposed from a first pad opening 210 as a source pad 212, and a part (pad portion 207) of the gate electrode film 203 is exposed from a second pad opening 211 as a gate pad 213. A bonding material such as a bonding wire may be bonded to each of the pads 212, 213 when packaging the semiconductor device A8.

[0113] FIG. 17 is an enlarged view of a portion surrounded by a two-dot chain line XVII in FIG. 16. FIG. 18 is an enlarged view of a portion surrounded by a two-dot chain line XVIII in FIG. 16. More specifically, FIG. 17 shows the internal structure of the boundary between the region of the source electrode film 202 covered with the passivation film 209 and the source pad 212. FIG. 18 shows the internal structure of the region of the source electrode film 202 covered with the passivation film 209. The region of the source electrode film 202 covered with the passivation film 209 is a closed ring surrounding the source pad 212, and is the peripheral portion of the source electrode film 202. In addition, this peripheral portion is the outer periphery of the active region 204 surrounding the central portion 214 of the active region 204 below the source pad 212, and may be referred to as the peripheral portion 215 of the active region 204. 17 and 18, for ease of understanding, part of the gate electrode 223 is hatched (for clarity, the part of the gate electrode 223 facing the body region 219 is not hatched).

[0114] Fig. 19 is a cross-sectional view taken along line XIX-XIX in Fig. 17. Fig. 20 is a cross-sectional view taken along line XX-XX in Fig. 18. For ease of explanation, three mutually perpendicular directions are defined as the X direction, the Y direction, and the Z direction. The Z direction is the thickness direction of the semiconductor device A8. The X direction is the left-right direction in the plan view of the semiconductor device A8 (see Figs. 17 and 18). The Y direction is the up-down direction in the plan view of the semiconductor device A8 (see Figs. 17 and 18).

[0115] The semiconductor device A8 may include a semiconductor substrate 216, an epitaxial layer 217, a column layer 218, a body region 219, a source region 220, a body contact region 221, a gate insulating film 222, a gate electrode 223, a p-type region 224, a p-type contact region 225, an insulating film 226, a floating electrode 227, and an interlayer insulating film 228. In this embodiment, the combination of the semiconductor substrate 216 and the epitaxial layer 217, the body region 219, and the source region 220 may be examples of the "semiconductor layer," "second region," and "first region" recited in the claims, respectively.

[0116] In this embodiment, the semiconductor substrate 216 is + The substrate may be a semiconductor substrate of the same type (e.g., a silicon substrate). Alternatively, the substrate may be a substrate generally used for transistors, such as a SiC substrate or a GaN substrate. + The n-type semiconductor substrate 216 may be a semiconductor substrate that is grown by doping with n-type impurities. Examples of n-type impurities include P (phosphorus), As (arsenic), and Sb (antimony). + The impurity concentration of the semiconductor substrate 216 is, for example, 1.0×10 18 cm -3 ~5.0×10 20 cm -3 The semiconductor substrate 216 has a first side 229 and an opposing second side 230.

[0117] The epitaxial layer 217 may be, for example, +On the semiconductor substrate 216, an n-type impurity is implanted and epitaxially grown. - Examples of n-type impurities are as described above. - The impurity concentration of the epitaxial layer 217 is n + lower than the semiconductor substrate 216 of the type, for example, 1.0×10 10 cm -3 ~1.0×10 16 cm -3 In addition, the n - The area of ​​the type is n - Alternatively, the drift region 231 may be referred to as a "type drift region 231." In this embodiment, the drift region 231 may be an example of a "third region" recited in the claims.

[0118] The epitaxial layer 217 (drift region 231) has a first surface 232 and a second surface 233 on the opposite side. The first surface 232 is a surface on which element structures 239 and 240, which will be described later, are formed, and may be referred to as an element main surface. The second surface 233 is a surface that contacts the first surface 229 of the semiconductor substrate 216.

[0119] The column layer 218 may be a semiconductor layer formed by ion-implanting a p-type impurity into the epitaxial layer 217. As the p-type impurity, B (boron), Al (aluminum), Ga (gallium), etc. may be used. The impurity concentration of the column layer 218 is, for example, 1.0×10 15 cm -3 ~1.0×10 19 cm -3 It may be to some extent.

[0120] As shown in Figs. 19 and 20, the column layer 218 extends in the Z direction, and for example, extends from the upper part of the epitaxial layer 217 beyond the center of the epitaxial layer 217 in the Z direction. As shown in Figs. 17 and 18, the column layer 218 has a circular shape in a plan view. The plan view shape of the column layer 218 is not limited to a circle, and may be, for example, a triangular shape or a rectangular shape. In addition, the side surface 234 of the column layer 218 along the Z direction has a plurality of convex portions 235 and concave portions 236 repeated along the Z direction, forming a periodically undulating uneven surface. The number of the convex portions 235 and 236 is usually approximately equal to the number of steps of the n-type semiconductor layer 263 (Figs. 22A and 22B) described later.

[0121] The column layers 218 are regularly arranged at equal intervals, as shown in Figures 17 and 18. In this embodiment, the multiple column layers 218 are arranged so that the intervals (pitch) in the X direction and the Y direction are the same. Also, as shown in Figure 17, the column layers 218 are arranged in a matrix shape at equal intervals, straddling between the peripheral portion 215 of the active region 204 and the central portion 214 of the active region 204.

[0122] A plurality of body regions 219 are formed on the surface of the epitaxial layer 217. More specifically, - The body region 219 may be a semiconductor layer formed by ion-implanting a p-type impurity into the epitaxial layer 217. Examples of the p-type impurity are as described above. The impurity concentration of the body region 219 is, for example, 1.0×10 15 cm -3 ~1.0×10 19 cm -3 19 and 20, each body region 219 forms a parasitic diode 237 (body diode) at the interface (pn junction surface) with the drift region 231.

[0123] The source region 220 is formed in an inner region of each body region 219. The source region 220 is selectively formed in a surface portion of the body region 219 in the inner region. The source region 220 may be formed by selectively ion-implanting n-type impurities into the body region 219. Examples of n-type impurities are as described above. The impurity concentration of the source region 220 is higher than that of the drift region 231, and may be, for example, 1.0×10 18 cm -3 ~5.0×10 20 cm -3 It may be to some extent.

[0124] The source region 220 has a rectangular shape in a plan view, and is separated inward by a predetermined distance from the periphery of the body region 219 (the boundary between the body region 219 and the drift region 231). As a result, in the surface portion of the epitaxial layer 217 including the drift region 231 and the body region 219, the surface portion of the body region 219 is interposed between the source region 220 and the drift region 231. This interposed surface portion is a channel region 238 in which a channel is formed when an appropriate voltage is applied to the gate electrode 223.

[0125] The body contact region 221 has a rectangular shape in a plan view, and is selectively formed in a surface portion of the body region 219. The body contact region 221 extends toward the second surface 233 of the epitaxial layer 217 so as to pass through the source region 220 and reach the body region 219. The body contact region 221 may be formed by selectively ion-implanting p-type impurities into the body region 219. Examples of the p-type impurities are as described above. The impurity concentration of the body contact region 221 is higher than that of the body region 219, and may be, for example, 5.0×10 17 cm -3 ~1.0×10 19 cm -3 It may be to some extent.

[0126] Furthermore, MISFET element structures 239, 240 (unit cell) are configured by the body region 219, the source region 220, and the body contact region 221. Between the element structures 239, 240 adjacent to each other, a part of the drift region 231 is exposed.

[0127] In this embodiment, the element structures 239, 240 may include a first element structure 239 and a second element structure 240. The first element structure 239 is arranged in a central portion 214 of the active region 204 as shown in FIG. 17, and the second element structure 240 is arranged in a peripheral portion 215 of the active region 204 as shown in FIG. 17 and FIG. 18. The central portion 214 of the active region 204 is a region in which a plurality of first element structures 239 are arranged, and may be referred to as a first element region 241. On the other hand, the peripheral portion 215 of the active region 204 is a region in which a plurality of second element structures 240 are arranged, and may be referred to as a second element region 242.

[0128] 17, the first element structure 239 is an element structure including a body region 219 formed away from the column layer 218 so as not to overlap the column layer 218 in a plan view, and the column layer 218 adjacent to the body region 219. The body region 219 and the column layer 218 of the first element structure 239 may be referred to as a first body region 391 and a first column layer 381, respectively.

[0129] The first column layer 381 is physically separated from the first body region 391 in a direction along the first surface 232 of the epitaxial layer 217 (in this embodiment, a direction along the XY plane), and is a floating region in the epitaxial layer 217. As shown in FIG. 17, the first column layer 381 is formed adjacent to a corner 243 of the first body region 391 having a rectangular shape in a plan view. For example, the first column layer 381 may be formed adjacent to each of the four corners 243 of one first body region 391. In addition, the first body region 391 may be formed away from a region 244 between adjacent first column layers 381 (a region sandwiched between adjacent first column layers 381). In addition, each first column layer 381 may be shared by adjacent first element structures 239.

[0130] 19, the first column layer 381 may have a top 245 (in this embodiment, the convex portion 235 of the first column layer 381 closest to the first surface 232 of the epitaxial layer 217) at a position deeper than the bottom of the first body region 391. In other words, the distance D from the first surface 232 of the epitaxial layer 217 to the first column layer 381 C is a distance D from the first surface 232 to the bottom of the first body region 391. B It may be longer than that.

[0131] 17 and 18, the second element structure 240 is an element structure including, in a plan view, a body region 219 overlapping the column layer 218 and the column layer 218 adjacent to the body region 219. The body region 219 and the column layer 218 of the second element structure 240 may be referred to as a second body region 392 and a second column layer 382, ​​respectively.

[0132] The second column layer 382 is formed in a region inside each second body region 392. More specifically, the second column layer 382 is formed to be continuous with a lower portion of the second body region 392, and extends from the second body region 392 toward the second surface 233 of the epitaxial layer 217. The bottoms of the second column layer 382 and the first column layer 381 may be located at the same depth position from the first surface 232 of the epitaxial layer 217.

[0133] 17, the interval between the adjacent first body region 391 and second body region 392 may be selectively large at the boundary 246 between the first element region 241 and the second element region 242. For example, in the first element region 241 and the second element region 242, the interval between the first body region 391 and the second body region 392 (pitch P 1 ,P 2 ) is 5 μm to 20 μm and may be the same as each other. In contrast, the distance P 3 The pitch P may be 5 μm to 20 μm. 3 An example of the range is 5 μm to 20 μm, and the pitch P 1 ,P 2 The same range as above, but with pitch P 3 is the pitch P within the above range. 1 ,P 2 It could be larger.

[0134] 19, the drift region 231 may include a first portion 247 and a second portion 248 having different impurity concentrations. The first portion 247 is formed between the top 245 of the first column layer 381 and the first body region 391, and has a first impurity concentration. On the other hand, the second portion 248 is formed on the second surface 233 side of the epitaxial layer 217 with respect to the first portion 247, and has a second impurity concentration lower than the first impurity concentration. More specifically, the boundary portion 249 between the first portion 247 and the second portion 248 may be set at a middle portion in the Z direction of the top 245 of the first column layer 381. In this embodiment, the first impurity concentration is 1×10 10 cm-3 ~1×10 13 cm -3 The second impurity concentration is about 1×10 10 cm -3 ~1×10 13 cm -3 An example of the first impurity concentration is about 1×10 10 cm -3 ~1×10 13 cm -3 is the same as one example of the range of the second impurity concentration, but the first impurity concentration may be greater than the second impurity concentration within the above range.

[0135] The gate insulating film 222 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, or the like. The gate electrode 223 may be made of polysilicon formed by injecting impurities. When the gate insulating film 222 is made of a silicon oxide film, the MISFET may be called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0136] The gate insulating film 222 covers at least the surface of the body region 219. In this embodiment, the gate insulating film 222 covers a part of the surface of the source region 220, the channel region 238, and the surface of the drift region 231. More specifically, the gate insulating film 222 is formed in a pattern having openings in the body contact region 221 of each of the element structures 239 and 240 and in a part of the source region 220 connected to the body contact region 221.

[0137] The gate insulating film 222 is interposed between the gate electrode 223 and the epitaxial layer 217. As a result, the gate electrode 223 faces the channel region 238 via the gate insulating film 222. The gate electrode 223 is formed in substantially the same pattern as the gate insulating film 222, thereby forming a planar gate structure. The gate insulating film 222 may have a thickness of, for example, 300 Å to 700 Å.

[0138] In this embodiment, the gate electrode 223 is formed across the first element region 241 and the second element region 242, as shown in FIG. 17 and FIG. 18. The gate electrode 223 is formed in a lattice pattern in each of the first element region 241 and the second element region 242. More specifically, in the first element region 241 and the second element region 242, the gate electrode 223 includes a first portion 250 extending in the X direction, a second portion 251 extending in the Y direction perpendicular to the X direction, and an intersection 252 where the first portion 250 and the second portion 251 intersect. In the first element region 241, the first column layer 381 is formed below the intersection 252 of the gate electrode 223.

[0139] A plurality of p-type regions 224 are formed on the surface of the epitaxial layer 217. More specifically, - Alternatively, the p-type region 224 may be a semiconductor layer formed by ion-implanting a p-type impurity into the p-type epitaxial layer 217. Examples of the p-type impurity are as described above. The impurity concentration of the p-type region 224 may be, for example, 1.0×10 15 cm -3 ~1.0×10 19 cm -3 and may be the same as body region 219. Each p-type region 224 has, for example, a rectangular shape extending in the Y direction in a plan view. Furthermore, p-type regions 224 are arranged outside second element structure 240 in second element region 242.

[0140] The p-type contact region 225 has, for example, a rectangular shape in a plan view extending in the Y direction, and is selectively formed on a surface portion of the p-type region 224. As a result, the closed ring-shaped p-type region 224 is exposed around the p-type contact region 225. The p-type contact region 225 may be formed by selectively ion-implanting p-type impurities into the p-type region 224. Examples of the p-type impurities are as described above. The impurity concentration of the p-type contact region 225 is higher than that of the p-type region 224, for example, 5.0×10 17 cm -3 ~1.0×1019 cm -3 and may be the same as the body contact region 221.

[0141] The insulating film 226 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, or a tantalum oxide film. The floating electrode 227 may be made of polysilicon formed by implanting impurities. The insulating film 226 covers the exposed portion of the closed ring-shaped p-type region 224, and a closed ring-shaped floating electrode 227 is formed on the insulating film 226. The floating electrode 227 is an electrically floating conductive layer.

[0142] The interlayer insulating film 228 is formed on the epitaxial layer 217. The interlayer insulating film 228 covers the gate electrode 223 and the floating electrode 227. The interlayer insulating film 228 may be made of an insulating material such as a silicon oxide film, a silicon nitride film, or TEOS (tetraethoxysilane).

[0143] A first contact hole 253 exposing the body contact region 221 and the source region 220 of the MISFET, and a second contact hole 254 exposing the p-type contact region 225 are formed in the interlayer insulating film 228. The first contact hole 253 penetrates the interlayer insulating film 228 and the gate insulating film 222.

[0144] The electrode film 201 described above is formed on the interlayer insulating film 228. The electrode film 201 may be made of aluminum or other metals. Figures 19 and 20 show a source electrode film 202. The source electrode film 202 may be simply called a source electrode.

[0145] The source electrode film 202 is connected to the body contact region 221 and the source region 220 in the first contact hole 253, as shown in Figures 19 and 20, and is connected to the p-type contact region 225 in the second contact hole 254, as shown in Figure 20.

[0146] As a result, the source electrode film 202 connects in parallel the body region 219 and the source region 220 of the element structure functioning as a MISFET (active cell capable of passing current between the drain and the source), and the p-type region 224 that does not function as a MISFET (inactive cell incapable of passing current between the drain and the source). Note that the gate electrode films 203 are connected to the gate electrodes 223 at positions not shown, respectively.

[0147] A drain electrode 255 is formed on the second surface 230 of the semiconductor substrate 216. The drain electrode 255 may be made of aluminum or other metal. The drain electrode 255 is electrically connected to the drift region 231 through the semiconductor substrate 216. <<Resistance Distribution of Epitaxial Layer 217>> FIG. 21 is a diagram for explaining the resistance distribution of the epitaxial layer 217. In FIG. 21, the first body region 391 and the second body region 392 are collectively shown as the body region 219, and the first column layer 381 and the second column layer 382 are collectively shown as the column layer 218.

[0148] As shown in FIG. 21, the resistance distribution in the thickness direction (Z direction) of the epitaxial layer 217 can be described based on the resistance distribution curve 256. The resistance distribution curve 256 is a curve graph showing the relationship between the depth position (vertical axis) from the first surface 232 of the epitaxial layer 217 and the resistance value at that position (horizontal axis). In this embodiment, the resistance distribution curve 256 shows the resistance distribution below the gate electrode 223 (that is, the region where the drift region 231 is exposed on the first surface 232 of the epitaxial layer 217), and shows how the resistance value of the epitaxial layer 217 changes from the first surface 232 to the second surface 233 of the epitaxial layer 217. Such a resistance distribution curve 256 can be created, for example, based on the resistance distribution measured by a scanning spread resistance microscope (SSRM).

[0149] The resistance distribution curve 256 includes a baseline 257 and a convex line 258 that bulges convexly relative to the baseline 257 .

[0150] The baseline 257 may be a line indicating that the resistance value is almost constant from the first surface 232 to the second surface 233 of the epitaxial layer 217. Here, "almost constant resistance value" does not mean that the resistance value of the epitaxial layer 217 is completely constant along the Z direction, but means that there is no abrupt change in the resistance value, unlike, for example, the boundary between the baseline 257 and the convex line 258.

[0151] The baseline 257 includes a first baseline 773 formed on the first surface 232 side of the epitaxial layer 217 and a second baseline 774 formed on the second surface 233 side, and a convex line 258 is formed between the first baseline 773 and the second baseline 774.

[0152] Convex line 258 indicates a bimodal resistance distribution, and has multiple peaks 259, 260. Note that convex line 258 does not have to be a bimodal resistance distribution, as shown by the two-dot chain line in Fig. 21. In other words, convex line 258 does not have to have a clear peak.

[0153] In this embodiment, the convex line 258 includes a first convex line 781 formed on the first surface 232 side of the epitaxial layer 217 and a second convex line 782 formed on the second surface 233 side. The first convex line 781 has a first peak 259, and the second convex line 782 has a second peak 260. The first convex line 781 and the second convex line 782 are connected via a valley portion 280 between the first peak 259 and the second peak 260.

[0154] Both the first peak 259 and the second peak 260 are formed at a depth where the column layer 218 exists.

[0155] More specifically, the second peak 260 is formed at the bottom of the column layer 218, and is, for example, a distance D from the lower end 278 of the column layer 218 to the first surface 232 side. 2 In other words, the second peak 260 may be formed at the depth position of the convex portion 235 formed on the lowermost end 278 side of the column layer 218.

[0156] On the other hand, the first peak 259 is formed in the center of the column layer 218 in the Z direction. For example, the distance D 1 In this embodiment, the length L of the column layer 218 in the Z direction is in the range of 20 μm to 30 μm. C is, for example, 40 μm to 50 μm.

[0157] Moreover, the first peak 259 and the second peak 260 are preferably spaced apart by, for example, 15 μm to 30 μm.

[0158] In the resistance distribution curve 256, the height H of the first peak 259 relative to the baseline 257 1 (The size of the horizontal axis) is the height H of the second peak 260 relative to the baseline 257. 2 Therefore, in the epitaxial layer 217, the resistance value of the center part of the column layer 218 in the Z direction is higher than the resistance value of the bottom part of the column layer 218.

[0159] In addition, in the resistance distribution curve 256, the width W 1 is 20μm or more. 1 may be defined based on the length of a straight line connecting the half value 279 of the first convex line 781 and the half value 279 of the second convex line 782, for example.

[0160] Thus, in the epitaxial layer 217, a region having a certain thickness corresponding to the convex line 258 has a higher resistance than the region corresponding to the baseline 257, and this region may be set as the high-resistance region 281. The thickness of the high-resistance region 281 may be, for example, 20 μm or more, preferably 40 μm to 60 μm.

[0161] Further, a crystal defect region 282 is formed in the epitaxial layer 217. The crystal defect region 282 is a region formed by irradiating light ions from the second surface 230 of the semiconductor substrate 216, as will be described later. The crystal defect region 282 has many recombination centers that trap carriers and cause them to recombine and disappear. Thereby, carriers can be quickly disappeared during the reverse recovery phenomenon to shorten the carrier lifetime, so that the reverse recovery time and the reverse recovery current can be reduced.

[0162] The crystal defect region 282 is locally formed so as to thinly spread (for example, with a thickness of about 10 μm to 15 μm) at a predetermined depth position from the second surface 230 of the semiconductor substrate 216 within the epitaxial layer 217.

[0163] The crystal defect region 282 may include, for example, a first crystal defect region 1021 formed in a region corresponding to the first convex line 781 and a second crystal defect region 1022 formed in a region corresponding to the second convex line 782. The first crystal defect region 1021 is formed at the central portion in the Z direction of the column layer 218, and the second crystal defect region 1022 is formed at the bottom of the column layer 218. ≪Manufacturing Method of Semiconductor Device A8≫ Figs. 22A to 22J are diagrams showing the manufacturing process of the semiconductor device A8 in the order of the processes. In Figs. 22A to 22J, the configuration shown in Fig. 21 is omitted except that the crystal defect region 282 is shown in Figs. 22H and 22I.

[0164] 22A, in order to manufacture the semiconductor device A8, first, an initial base layer 261 is formed by epitaxial growth on a wafer-shaped semiconductor substrate 216. Next, a p-type impurity 262 is selectively implanted into the surface of the initial base layer 261 at a position where the column layer 218 is to be formed.

[0165] Next, referring to FIG. 22B, multiple n-type semiconductor layers 263 are stacked on the initial base layer 261 by multi-epitaxial growth, which repeats a process of forming an n-type semiconductor layer 263 while selectively injecting a p-type impurity 262 into a position where the column layer 218 is to be formed.

[0166] 22C, the uppermost n-type semiconductor layer 264 is laminated without injecting p-type impurities. As a result, the multiple n-type semiconductor layers 263, 264 and the initial base layer 261 are integrated to form the epitaxial layer 217 (drift region 231). At this time, the impurity concentration when the uppermost n-type semiconductor layer 264 is grown is higher than the impurity concentration when the n-type semiconductor layer 263 below the uppermost n-type semiconductor layer 264 is grown. As a result, the first portion 247 and the second portion 248 of the drift region 231 can be formed.

[0167] 22D, an annealing process (1000° C. to 1200° C.) is performed to drive-diffuse the p-type impurities in the initial base layer 261 and the multiple n-type semiconductor layers 263 and 264. As a result, a column layer 218 is formed in the epitaxial layer 217.

[0168] 22E, p-type impurities are selectively implanted into a surface portion of the epitaxial layer 217 to form a body region 219 and a p-type region 224 (not shown). In the second element region 242, the body region 219 (second body region 392) is connected to the second column layer 382. Next, n-type impurities are selectively implanted into a surface portion of the body region 219 to form a source region 220. Next, p-type impurities are selectively implanted into a surface portion of the body region 219 and a surface portion of the p-type region 224 to form a body contact region 221 and a p-type contact region 225 (not shown).

[0169] Next, referring to FIG. 22F, a gate insulating film 222 and an insulating film 226 (not shown) are formed on the epitaxial layer 217. The gate insulating film 222 and the insulating film 226 may be formed by growing an oxide film by thermal oxidation of the semiconductor crystal surface and then patterning the oxide film. Next, a gate electrode 223 is formed on the gate insulating film 222, and a floating electrode 227 (not shown) is formed on the insulating film 226. The gate electrode 223 and the floating electrode 227 may be formed, for example, by forming a polysilicon film to which an impurity is added on the entire surface and then selectively etching the polysilicon film by photolithography. Next, an interlayer insulating film 228 is formed so as to cover the gate electrode 223 and the floating electrode 227. Next, a first contact hole 253 and a second contact hole 254 (not shown) are formed in the interlayer insulating film 228 by photolithography.

[0170] 22G, semiconductor substrate 216 is ground and flattened from the second surface 230 side. The amount of grinding is not particularly limited, but it is preferable that semiconductor substrate 216 after grinding has a thickness of 90 μm to 310 μm, for example.

[0171] Next, referring to Figures 22H and 22I, two-stage irradiation of light ions is performed. As described later, the two-stage irradiation is performed by irradiating the epitaxial layer 217 with light ions at different depths in two stages. In contrast, irradiation of the epitaxial layer 217 with light ions once at a predetermined depth position may be called one-stage irradiation.

[0172] First, referring to FIG. 22H, a first light ion irradiation is performed from the second surface 230 side of the semiconductor substrate 216. The light ions irradiated at this time include, for example, protons, 3 He ++ , 4 He ++ The range of light ions (implantation depth D 3 ) adjusts the acceleration energy of the light ions or an absorber that decelerates the energy of the light ions so that the first crystal defect region 1021 (see FIG. 21) is formed in the vicinity of the center of the column layer 218 in the Z direction. 3 He ++ The irradiation energy of the light ions (e.g. 3 He ++ ) is, for example, 1×10 10 pieces / cm 2 ~1×10 16 pieces / cm 2 In this manner, the first crystal defect region 1021 is formed.

[0173] 22I, a second light ion irradiation is performed from the second surface 230 side of the semiconductor substrate 216. The light ions irradiated at this time include, for example, protons, 3 He ++ , 4 He ++ However, the same type of irradiation as the first light ion irradiation described above (in this embodiment, 3 He ++ or 4 He ++ It is preferable to use ions with a range of light ions (implantation depth D 4) adjusts the acceleration energy of the light ions or an absorber that decelerates the energy of the light ions so that the second crystal defect region 1022 (see FIG. 21) is formed near the bottom of the column layer 218. 3 He ++ The irradiation energy of the light ions (for example) may be smaller than that of the first light ion irradiation, and may be about 5 MeV to 40 MeV. 3 He ++ ) is lower than that of the first light ion irradiation, for example, 1×10 10 pieces / cm 2 ~1×10 16 pieces / cm 2 It should be about that extent.

[0174] An example of the range of the irradiation energy and the dose in the second light ion irradiation is 5 MeV to 40 MeV and 1×10 10 pieces / cm 2 ~1×10 16 pieces / cm 2 and are the same as the example of the range of the irradiation energy and dose amount in the first light ion irradiation. However, the irradiation energy and dose amount in the second light ion irradiation may be smaller than the irradiation energy and dose amount in the first light ion irradiation within the above ranges.

[0175] As a result, second crystal defect regions 1022 are formed at positions shallower than first crystal defect regions 1021 with respect to second surface 230 of semiconductor substrate 216. For example, it is preferable that first crystal defect region 1021 and second crystal defect region 1022 are formed so as to be spaced apart by 15 μm to 30 μm.

[0176] Thereafter, for example, a heat treatment is performed to activate the irradiated light ions. As a result, a bimodal resistance distribution shown by a resistance distribution curve 256 in FIG. 21 can be obtained due to the first crystal defect region 1021 and the second crystal defect region 1022 formed at different depth positions. 3 He ++In the case where the above is selected, the introduced 3 He ++ Depending on the conditions of this heat treatment, the resistance distribution curve 256 may not have two peaks 259 and 260, and may have a shape shown by the two-dot chain line in FIG.

[0177] 22J, a source electrode film 202 and a gate electrode film 203 (not shown) are formed on the interlayer insulating film 228. Next, a passivation film 209 (not shown) is formed so as to cover the source electrode film 202 and the gate electrode film 203. Next, pad openings 210, 211 (not shown) are formed in the passivation film 209 by photolithography.

[0178] Thereafter, a drain electrode 255 is formed on the second surface 230 of the semiconductor substrate 216, thereby obtaining the above-mentioned semiconductor device A8. <Function and effect of semiconductor device A8> First, the operation of the MISFET of the semiconductor device A8 will be described. When the drain electrode 255 is connected to a potential higher than that of the source electrode film 202 and a control voltage equal to or higher than the threshold voltage is applied to the gate electrode 223, an inversion layer (channel) is formed in the body region 219 (channel region 238). This forms a current path between the source region 220 and the drift region 231. If no control voltage is applied to the gate electrode 223, no inversion layer is formed, and the current path between the source and drain is cut off. The parasitic diode 237 between the body region 219 and the drift region 231 is in an on state when a forward voltage is applied, and in an off state when a reverse voltage is applied. When the parasitic diode 237 is turned off, a reverse recovery phenomenon occurs. The current that flows as a result is the reverse recovery current. Due to the movement of carriers, a depletion layer extends from the pn junction, and the parasitic diode 237 is in an off state.

[0179] In this embodiment, the first column layer 381 is separated from the first body region 391 and is electrically floating with respect to the first body region 391. Therefore, the first column layer 381 does not contribute to the operation of the parasitic diode 237, so that the steep extension of the depletion layer during the reverse recovery phenomenon is suppressed. This suppresses the extension of the depletion layer in the Z direction of the epitaxial layer 217, thereby suppressing the speed at which the depletion layer extends when the parasitic diode 237 is turned off. This reduces the rate of change (dir / dt) of the reverse recovery current, improving the recovery characteristics.

[0180] Fig. 23 is a diagram showing a simulation result (source current) of the recovery characteristics, and Fig. 24 is a diagram showing a simulation result of the capacitance characteristics.

[0181] Next, the improvement of the recovery characteristics by the structure of the semiconductor device A8 described above was determined by simulation. In Fig. 23 and Fig. 24, "Sample 3" is an example in which the first element structure 239 of the semiconductor device A8 has a structure in which the first column layer 381 is separated from the body region 219, and "Sample 4" is an example in which the first element structure 239 of the semiconductor device A8 has a structure in which the column layer 218 is connected to the body region 219, similarly to the second column layer 382. In addition, "With He" and "Without He" in "Sample 4" respectively indicate a structure in which the drift region 231 is irradiated with He and a structure in which it is not irradiated with He at the middle part in the Z direction. In addition, in "Sample 3", the conditions for He irradiation are not set.

[0182] As a result of the simulation, it was confirmed that in "sample 3", as shown in Fig. 23, the reverse current (Irr) can be reduced without He irradiation, as in the case of sample 4_He, compared to the case of sample 4_He not being present. Therefore, according to the semiconductor device A8 of this embodiment, the reverse recovery characteristic of the parasitic diode 237 can be made closer to the soft recovery characteristic, compared to the case of sample 4_He not being present. Moreover, since He irradiation is not required, crystal defects that are an obstacle to the current (source-drain current) flowing in the Z direction of the drift region 231 can be reduced, compared to the case of sample 4_He being present, and therefore an increase in the on-resistance can be suppressed.

[0183] Next, the parasitic capacitances of Sample 3 and Sample 4 were compared. As a result, as shown in FIG. 24, all of Cgs (gate-source capacitance), Cds (drain-source capacitance) and Cgd (gate-drain capacitance) were reduced compared to Sample 4. Therefore, by adjusting the combination ratio of first element structure 239 and second element structure 240, both the recovery characteristics and the parasitic capacitance can be controlled. For example, when semiconductor device A8 is intended for in-vehicle use and it is desired to set the lifetime control weaker, the ratio of first element structure 239 can be set to a smaller value.

[0184] Next, the improvement in recovery characteristics due to the structure of the semiconductor device A8 described above was verified by experiments. Fig. 25 to Fig. 27 are diagrams showing evaluation results of the recovery characteristics of Samples 5 to 7, respectively. Fig. 28 is a diagram showing evaluation results of the recovery characteristics of Sample 8. Fig. 29 is a diagram for comparing the recovery characteristics of Sample 5 and Sample 8.

[0185] All of the samples 5 to 7 are examples of the semiconductor device A8 in which the first element structure 239 has a structure in which the first column layer 381 is separated from the body region 219. The difference between them is the thickness of the uppermost n-type semiconductor layer 264 (see FIG. 22C) of the multi-epitaxial growth. The uppermost n-type semiconductor layer 264 of the sample 5 is the thickest among the three samples 5 to 7, the next thickest being the sample 6, and the thinnest being the sample 7. Sample 8 is an example of the semiconductor device A8 in which the column layer 218 is connected to the body region 219, similarly to the second column layer 382. In all of the samples 5 to 7 and sample 8, the drift region 231 is irradiated with He in one step.

[0186] 25 to 28, it can be seen that, in Samples 5 to 7, the ringing noise during period tb, which is the time from the peak value of the reverse recovery time (trr) to returning to zero, is improved compared to Sample 8. For a more detailed understanding, FIG. 29 superimposes the recovery current waveforms of Sample 5 and Sample 8. It can also be seen from FIG. 29 that the ringing noise during period tb of Sample 5 is significantly improved compared to Sample 8.

[0187] Furthermore, in the semiconductor device A8, the first column layer 381 is separated from the first body region 391 in the lateral direction along the first surface 232 of the epitaxial layer 217. That is, in the Z direction of the epitaxial layer 217, the first body region 391 is not formed on an extension of the first column layer 381, so that even if the first column layer 381 is brought closer to the first surface 232, it does not come into contact with the first body region 391. Therefore, an increase in the thickness of the epitaxial layer 217 caused by providing a gap between the first column layer 381 and the first body region 391 can be suppressed, and an increase in the on-resistance of the current flowing in the Z direction of the drift region 231 can be suppressed.

[0188] In the semiconductor device A8, by relatively increasing the first impurity concentration in the first portion 247 of the drift region 231, which is a region in the vicinity of the parasitic diode 237, it is possible to suppress the extension of the depletion layer in the Z direction (vertical direction) of the drift region 231 during the reverse recovery phenomenon, and to keep the resistance of the first portion 247 low. On the other hand, by relatively decreasing the second impurity concentration in the second portion 248 on the second surface 233 side from the top 245 of the first column layer 381, it is possible to easily extend the depletion layer in the lateral direction from the first column layer 381 to the first surface 232 of the epitaxial layer 217, and therefore it is possible to maintain the breakdown voltage.

[0189] Furthermore, the semiconductor device A8 has, as the second element structure 240, a superjunction structure in which the second column layers 382 extend from the second body region 392. Therefore, by determining the spacing of the second column layers 382 so that the depletion layers extending laterally from the second column layers 382 are integrated, it is possible to realize the inherent characteristics of the superjunction structure, that is, good on-resistance and switching speed.

[0190] FIG. 30 shows the breakdown voltage characteristics (BV DSS 31 is a diagram for comparing the recovery characteristics of Sample 9 and Sample 10.

[0191] Next, the improvement of the withstand voltage characteristics and the improvement of the recovery characteristics due to the resistance distribution (bimodal distribution) shown by the resistance distribution curve 256 in FIG. 21 were verified by an experiment.

[0192] 30 and 31, Sample 10 is an example in which a structure in which the column layer 218 is connected to the body region 219, similar to the second column layer 382, ​​is adopted as the first element structure 239 of the semiconductor device A8, and a single stage of He irradiation is performed at a predetermined depth position.

[0193] In contrast, sample 9 is at a depth position D 102, the epitaxial layer 217 is formed at a depth position (D 10 +10μm and D 10 This is an example that adopts the same structure as Sample 10, except that He was irradiated (two-stage irradiation) from a depth (D 10 The dose at the time of irradiation of +10μm is fixed, and the relatively shallower (D 10 The dose of the laser beam (-10μm) was classified into conditions A, B, C and D in ascending order.

[0194] As can be seen from FIG. 30, the breakdown voltage (BV DSS 31, it was confirmed that the ringing noise during the period tb from the peak value of the reverse recovery time (trr) until it returns to zero was improved in Sample 9 compared to Sample 10. [Ninth embodiment] FIG. 32 is a schematic cross-sectional view of a semiconductor device A9 according to the ninth embodiment of the present disclosure.

[0195] The column layer 218 may have an uneven side surface 234 as in the eighth embodiment, or may have a flat side surface 265 as in the semiconductor device A9. In this case, the semiconductor device A9 may be manufactured through the steps shown in Figures 33A to 33D, for example.

[0196] To manufacture the semiconductor device A9, first, with reference to FIG. 33A, an initial base layer 266 is formed on a semiconductor substrate 216 by epitaxial growth.

[0197] 33B, in the initial base layer 266, a region in which the column layer 218 is to be formed is selectively removed by etching, thereby forming a trench 267 (more specifically, a deep trench).

[0198] 33C, the trenches 267 are backfilled with a semiconductor layer while implanting p-type impurities. As a result, the column layers 218 are formed in the initial base layer 266.

[0199] Next, referring to Fig. 33D, an n-type semiconductor layer 268 is laminated on the initial base layer 266 without implanting p-type impurities. As a result, the n-type semiconductor layer 268 and the initial base layer 266 are integrated to form the epitaxial layer 217 (drift region 231). At this time, the impurity concentration when growing the n-type semiconductor layer 268 is higher than the impurity concentration when growing the initial base layer 266. As a result, the first portion 247 and the second portion 248 of the drift region 231 can be formed.

[0200] Thereafter, the semiconductor device A9 can be obtained through steps similar to those shown in FIGS. 22E to 22J. [Tenth embodiment] FIG. 34 is a schematic cross-sectional view of a semiconductor device A10 according to the tenth embodiment of the present disclosure.

[0201] The first column layer 381 may have the top 245 at a position deeper than the bottom of the first body region 391 as in the eighth embodiment, but may have the top 245 at the same depth as the bottom of the first body region 391 as in this semiconductor device A10. In other words, the distance D from the first surface 232 of the epitaxial layer 217 to the first column layer 381 C is a distance D from the first surface 232 to the bottom of the first body region 391. B may be the same as [Eleventh embodiment] FIG. 35 is a schematic cross-sectional view of a semiconductor device A11 according to the eleventh embodiment of the present disclosure.

[0202] The first column layer 381 may have the top 245 at a position deeper than the bottom of the first body region 391 as in the eighth embodiment, but may have the top 245 at a position shallower than the bottom of the first body region 391 as in this semiconductor device A11. In other words, the distance D from the first surface 232 of the epitaxial layer 217 to the first column layer 381 C is a distance D from the first surface 232 to the bottom of the first body region 391. B It may be shorter than that. [Twelfth embodiment] FIG. 36 is a schematic cross-sectional view of a semiconductor device A12 according to the twelfth embodiment of the present disclosure.

[0203] The element structure of the semiconductor device A12 may be a planar gate structure as in the eighth embodiment, but may also be a trench gate structure as in this semiconductor device A12.

[0204] The semiconductor device A12 includes a gate trench 269, a gate insulating film 270, and a gate electrode 271.

[0205] The gate trench 269 penetrates from the first surface 232 of the epitaxial layer 217 through the source region 220 and the body region 219. The gate insulating film 270 is formed on the inner surface of the gate trench 269. The gate electrode 271 is embedded inside the gate insulating film 270 in the gate trench 269. This forms a trench gate structure.

[0206] The first column layer 381 may be formed below the gate trench 269 and thus separated from the first body region 391 in the direction along the first surface 232 of the epitaxial layer 217. In this semiconductor device A12, the first column layer 381 is further separated from the gate trench 269 toward the second surface 233 of the epitaxial layer 217. [Thirteenth embodiment] FIG. 37 is a schematic cross-sectional view of a semiconductor device A13 according to the thirteenth embodiment of the present disclosure.

[0207] The first column layer 381 may be separated from the gate trench 269 as in the twelfth embodiment, or may be in contact with the gate trench 269 as in the semiconductor device A13. More specifically, the first column layer 381 may be formed continuous with the bottom of the gate trench 269 and extend from the gate trench 269 toward the second surface 233 of the epitaxial layer 217. [Fourteenth embodiment] FIG. 38 is a schematic cross-sectional view of a semiconductor device A14 according to the fourteenth embodiment of the present disclosure.

[0208] The element structure may be a MISFET as in the above-mentioned embodiment, but may also be an IGBT (Insulated Gate Bipolar Transistor) as in this semiconductor device A14. + The semiconductor substrate 216 is + A semiconductor substrate 272 (p + The drain electrode 255 may be referred to as a collector electrode 274, and the source electrode film 202 may be referred to as an emitter electrode film 275. + The source region 220 is n + The p-type body region 219 may be referred to as a p-type emitter region 276, and the p-type body region 219 may be referred to as a p-type base region 277 (first base region 971 and second base region 972).

[0209] Although the embodiment of the present disclosure has been described above, the present disclosure can be embodied in other forms.

[0210] For example, the conductivity type of each semiconductor portion of the semiconductor devices A1 to A14 may be inverted. For example, in the semiconductor devices A1 to A14, the p-type portions may be n-type, and the n-type portions may be p-type.

[0211] Also, in FIG. 21, an example is given in which the resistance distribution curve 256 has two peaks 259, 260, but the resistance distribution curve 256 may have three or more peaks.

[0212] Furthermore, in the semiconductor devices A8 to A14, the first column layer 381 of the first element structure 239 may be connected to the body region 219 (first body region 391) like the second column layer 382 of the second element structure 240.

[0213] The presently disclosed embodiments are to be considered in all respects as illustrative and not restrictive, and are intended to include modifications in all respects.

[0214] The following characteristics can be extracted from the description of this specification and the drawings. [Appendix 1-1] a semiconductor layer having a first surface and a second surface; an element structure formed on the first surface side of the semiconductor layer, the element structure including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region; a gate electrode facing the second region via a gate insulating film; a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region; a first column layer of a second conductivity type spaced apart from the second region in a direction along the first surface of the semiconductor layer and extending in a thickness direction of the semiconductor layer.

[0215] For example, if the first conductivity type is n-type and the second conductivity type is p-type, when the third region is connected to a higher potential than the first region and a control voltage equal to or greater than the threshold voltage is applied to the gate electrode, an inversion layer (channel) is formed in the second region. This forms a current path between the first region and the third region. If no control voltage is applied to the gate electrode, the inversion layer is not formed, and the current path is blocked. The pn junction between the second region and the third region forms a parasitic diode. This parasitic diode is in the on state when a forward voltage is applied, and in the off state when a reverse voltage is applied. When the parasitic diode turns off, a reverse recovery phenomenon occurs. The current that flows as a result is the reverse recovery current. Due to the movement of carriers, a depletion layer extends from the pn junction, and the parasitic diode turns off.

[0216] In the configuration of Supplementary Note 1-1, the first column layer is separated from the second region and is electrically floating with respect to the second region. Therefore, the first column layer does not contribute to the operation of the parasitic diode, so that the steep extension of the depletion layer during the reverse recovery phenomenon is suppressed. This suppresses the extension of the depletion layer in the thickness direction of the semiconductor layer, thereby suppressing the speed at which the depletion layer extends when the parasitic diode is turned off. This reduces the rate of change (dir / dt) of the reverse recovery current, improving the recovery characteristics.

[0217] In addition, the first column layer is separated from the second region in the lateral direction along the first surface of the semiconductor layer. In other words, since the second region is not formed on an extension of the first column layer in the thickness direction of the semiconductor layer, the first column layer does not come into contact with the second region even if it is brought closer to the first surface side. Therefore, an increase in the thickness of the semiconductor layer caused by providing a gap between the first column layer and the second region can be suppressed, and an increase in the on-resistance of the current flowing in the thickness direction of the semiconductor layer can be suppressed. [Appendix 1-2] The semiconductor device described in Appendix 1-1, wherein the third region includes a first portion formed between a top of the first column layer and the second region and having a first impurity concentration, and a second portion formed on the second surface side of the semiconductor layer relative to the first portion and having a second impurity concentration lower than the first impurity concentration.

[0218] According to this configuration, by making the first impurity concentration in the region near the parasitic diode relatively high, it is possible to suppress the abrupt extension of the depletion layer in the thickness direction (vertical direction) of the semiconductor layer during the reverse recovery phenomenon, and to keep the resistance of the region low. Meanwhile, in the region closer to the second surface side than the top of the first column layer, by making the second impurity concentration relatively lower than the first impurity concentration, it is possible to facilitate the extension of the depletion layer in the lateral direction along the first surface of the semiconductor layer from the first column layer, and therefore the breakdown voltage can be maintained. [Appendix 1-3] the first column layer has an uneven side surface formed by repeating a plurality of convex portions and concave portions in a thickness direction of the semiconductor layer, The semiconductor device according to claim 1-2, wherein the top of the first column layer includes the convex portion closest to the first surface of the semiconductor layer. [Appendix 1-4] the gate electrode includes a first portion extending in a first direction, a second portion extending in a second direction perpendicular to the first direction, and an intersection portion where the first portion and the second portion intersect; The semiconductor device according to any one of claims 1-1 to 1-3, wherein the first column layer is formed below the intersection portion of the gate electrodes. [Appendix 1-5] The second region is formed in a quadrangular shape in a plan view, The semiconductor device according to any one of claims 1-1 to 1-4, wherein the first column layer is formed adjacent to a corner of the second region. [Appendix 1-6] A plurality of the first column layers are formed at intervals, The semiconductor device according to any one of claims 1-1 to 1-5, wherein the second region is formed away from a region between the first column layers adjacent to each other. [Appendix 1-7] The semiconductor device according to any one of Appendix 1-1 to Appendix 1-6, further including a second column layer of a second conductivity type formed in continuity with the second region and extending in a thickness direction of the semiconductor layer from the second region toward the second surface of the semiconductor layer.

[0219] According to this configuration, the semiconductor device has a superjunction structure in which the second column layers extend from the second region. Therefore, by determining the spacing of the second column layers so that the depletion layers extending laterally from the second column layers are integrated, it is possible to realize the inherent characteristics of the superjunction structure, namely, good on-resistance and switching speed. [Appendix 1-8] The semiconductor device described in Appendix 1-7, wherein the element structure includes a first element structure including the first column layer and the second region adjacent to the first column layer, and a second element structure including the second region to which the second column layer is connected. [Appendix 1-9] The semiconductor device according to claim 1-8, wherein the semiconductor layer includes a first element region in which a plurality of the first element structures are arranged, and a second element region in which a plurality of the second element structures are arranged. [Appendix 1-10] The semiconductor device according to claim 1-9, wherein the first element region is surrounded by the second element region. [Appendix 1-11] the semiconductor layer includes an active region in which the element structure is formed and a peripheral region surrounding the active region; The semiconductor device according to claim 1-9 or 1-10, wherein the second element region is formed in a peripheral portion of the active region. [Appendix 1-12] a first electrode covering the element structure and electrically connected to the first region; The semiconductor device according to any one of claims 1-9 to 1-11, wherein the second element region is formed along a peripheral portion of the first electrode. [Appendix 1-13] The semiconductor device according to any one of claims 1-7 to 1-12, wherein the first column layers and the second column layers are regularly arranged at equal intervals. [Appendix 1-14] The semiconductor device according to any one of claims 1-1 to 1-13, wherein the element structure includes a planar gate structure. [Appendix 1-15] The semiconductor device according to any one of claims 1-1 to 1-13, wherein the element structure includes a trench gate structure. [Appendix 1-16] The semiconductor device according to any one of Appendix 1-1 to Appendix 1-15, comprising a MISFET having the first region as a source region and the second region as a body region. [Appendix 1-17] The semiconductor device according to any one of Appendix 1-1 to Appendix 1-15, comprising an IGBT having the first region as an emitter region, the second region as a base region, and a collector region of a second conductivity type in contact with the third region. [Appendix 2-1] a semiconductor layer having a first surface and a second surface; an element structure formed on the first surface side of the semiconductor layer, the element structure including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region; a gate electrode facing the second region via a gate insulating film; a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region; a column layer of a second conductivity type extending in a thickness direction of the semiconductor layer; A semiconductor device, wherein a resistance distribution curve of the semiconductor layer in a thickness direction of the semiconductor layer has a plurality of peaks.

[0220] According to this configuration, it is possible to provide a semiconductor device capable of improving the breakdown voltage and the recovery characteristics. [Appendix 2-2] the resistance distribution curve includes a baseline indicating that a resistance value is substantially constant from the first surface to the second surface of the semiconductor layer; the plurality of peaks includes a first peak that is relatively high with respect to the baseline and a second peak that is relatively lower than the first peak, The semiconductor device according to claim 2-1, wherein a width of the resistance distribution curve at half the resistance value of the second peak is 20 μm or more. [Appendix 2-3] the second peak is formed within a range of 1 μm to 5 μm from the lower end of the column layer; The semiconductor device according to appendix 2-2, wherein the first peak is formed within a range of 20 μm to 30 μm from a lower end of the column layer. [Appendix 2-4] The semiconductor device according to any one of Appendix 2-1 to Appendix 2-3, wherein the column layer has a length of 40 μm to 60 μm in a thickness direction of the semiconductor layer. [Appendix 2-5] the column layer has an uneven side surface formed by repeating a plurality of convex portions and concave portions in a thickness direction of the semiconductor layer, The semiconductor device according to any one of Appendix 2-1 to Appendix 2-4, wherein at least one peak of the resistance distribution curve is formed at the position of a convex portion formed on the lowermost end side of the column layer. [Appendix 2-6] a semiconductor layer having a first surface and a second surface; an element structure formed on the first surface side of the semiconductor layer, the element structure including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region; a gate electrode facing the second region via a gate insulating film; a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region; a column layer of a second conductivity type extending in a thickness direction of the semiconductor layer; the semiconductor layer includes a high resistance region corresponding to a distribution portion that bulges in a convex shape of a resistance distribution curve of the semiconductor layer when the resistance distribution curve of the semiconductor layer in a thickness direction of the semiconductor layer is drawn, The high resistance region has a thickness of 20 μm or more. [Appendix 2-7] forming a column layer of a second conductivity type extending in a thickness direction of a semiconductor layer of a first conductivity type having a first surface and a second surface; forming an element structure including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region, the first region being closer to the first surface of the semiconductor layer than the column layer; forming a gate electrode facing the second region via a gate insulating film; irradiating the semiconductor layer with first light ions at a first depth position from the second surface; A method for manufacturing a semiconductor device, comprising a step of irradiating a second light ion at a second depth position different from the first depth position from the second surface of the semiconductor layer.

[0221] According to this method, a semiconductor device capable of improving breakdown voltage and improving recovery characteristics can be provided. [Appendix 2-8] The step of irradiating the first light ion includes a step of irradiating the first light ion with a first dose amount. The step of irradiating the second light ion includes a step of irradiating the second light ion at the second depth position shallower than the first depth position with a second dose amount lower than the first dose amount. The manufacturing method of the semiconductor device according to Appendix 2-7. [Appendix 2-9] The first light ion and the second light ion include the same kind of light ion. The manufacturing method of the semiconductor device according to Appendix 2-7 or Appendix 2-8. [Appendix 2-10] The first light ion and the second light ion are protons, 3 He ++ , 4 He ++ The manufacturing method of the semiconductor device according to any one of Appendices 2-7 to 2-9, including any one of them.

[0222] This application corresponds to Japanese Patent Application No. 2020-062479 filed with the Japan Patent Office on March 31, 2020, Japanese Patent Application No. 2020-062480 filed with the Japan Patent Office on March 31, 2020, and Japanese Patent Application No. 2020-062481 filed with the Japan Patent Office on March 31, 2020. The entire disclosures of these applications are incorporated herein by reference.

Explanation of Reference Numerals

[0223] 1: Electrode film 2: Source electrode film 3: Gate electrode film 4: Active region 5: Concave portion 6: Peripheral region 7: Pad portion 8: Finger section 9: Passivation film 10: First pad opening 11: Second pad opening 12: Source Pad 13: Gate pad 14: Central part 15: Periphery 16: Semiconductor substrate 17: Epitaxial layer 18: Column layer 19: Body region 20: Source area 21: Body contact area 22: Gate insulating film 23: Gate electrode 24:p-type region 25: p-type contact region 26: Insulating film 27: Floating electrode 28: Interlayer insulating film 29: 1st page 30: 2nd side 31: Drift region 32: 1st page 33: 2nd side 34: Side 35: Convex 36: Recess 37: Parasitic diode 38: Channel region 39: First element structure 40: Second element structure 41: First element region 42: Second element region 43: Corner 44 :Area 45:Top 46: Boundary 47 :1st part 48:Second part 49: Boundary 50: 1st part 51:Second part 52: Intersection 53: First contact hole 54: Second contact hole 55: Drain electrode 56: Dummy gate electrode 57 :1st column 58: 2nd column 59: Insulating film 60: 3rd contact hole 61: Initial base layer 62: p-type impurity 63: n-type semiconductor layer 64: n-type semiconductor layer 65: Side 66: Initial base layer 67: Trench 68: n-type semiconductor layer 69: Gate trench 70: Gate insulating film 71: Gate electrode 72: Semiconductor substrate 73: Type collector layer 74: Collector electrode 75: Emitter electrode film 76: Emitter area 77: Base area 78: Depletion layer 79: Gap 181: First column layer 182: Second column layer 191: First body region 192: Second body region 201: Electrode membrane 202: Source electrode film 203: Gate electrode film 204: Active area 205: Recess 206: Outer area 207: Pad section 208: Finger section 209: Passivation film 210: First pad opening 211: Second pad opening 212: Source Pad 213: Gate pad 214: Central part 215: Periphery 216: Semiconductor substrate 217: Epitaxial layer 218: Column layer 219: Body area 220: Source area 221: Body contact area 222: Gate insulating film 223: Gate electrode 224 :p-type region 225: p-type contact region 226: Insulating film 227: Floating electrode 228: Interlayer insulating film 229: 1st page 230: 2nd side 231: Drift region 232: 1st page 233: 2nd side 234: Side 235: Convex 236: Recess 237: Parasitic diode 238: Channel region 239: First element structure 240: Second element structure 241: First element region 242: Second element region 243: Corner 244: area 245:Top 246: Boundary 247 :1st part 248 :Second part 249: Boundary 250: 1st part 251 :Second part 252: Intersection 253: First contact hole 254: Second contact hole 255: Drain electrode 256: Resistance distribution curve 257 : Baseline 258: Convex line 259: First Peak 260: Second Peak 261: Initial base layer 262 : p-type impurities 263: n-type semiconductor layer 264: n-type semiconductor layer 265: Side 266: Initial base layer 267: Trench 268: n-type semiconductor layer 269: Gate trench 270: Gate insulating film 271: Gate electrode 272: Semiconductor substrate 273: Type collector layer 274: Collector electrode 275: Emitter electrode film 276: Emitter area 277: Base area 278: Bottom edge 278 Bottom edge 279: Half price 280: Valley 281: High resistance area 282: Crystal defect area 381: First column layer 382: Second column layer 391: First body region 392: Second body region 771: First base area 772: Second base area 773: First Baseline 774: Second Baseline 781: First convex line 782: Second convex line 971: First base area 972: Second base area 1021: First crystal defect region 1022: Second crystal defect region A1: Semiconductor device A2: Semiconductor equipment A3: Semiconductor device A4: Semiconductor device A5: Semiconductor device A6: Semiconductor device A7: Semiconductor device A8: Semiconductor device A9: Semiconductor device A10: Semiconductor device A11: Semiconductor device A12: Semiconductor device A13: Semiconductor device A14: Semiconductor device B1: Semiconductor device

Claims

1. a semiconductor layer having a first surface and a second surface; an element structure formed on the first surface side of the semiconductor layer, the element structure including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region; a gate electrode facing the second region via a gate insulating film; a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region; a first electrode formed on the semiconductor layer and electrically connected to the first region and the second region; the element structure includes a first element structure and a second element structure, the first element structure further includes a first column layer of a second conductivity type that is spaced apart from the second region in a direction along the first surface of the semiconductor layer and extends in a thickness direction of the semiconductor layer; the second element structure further includes a second electrode facing the third region via an insulating film and electrically connected to the first electrode; the semiconductor layer includes a first element region in which a plurality of the first element structures are arranged, and a second element region in which a plurality of the second element structures are arranged, the first electrode covers the first element region and the second element region, The second element region is formed along a peripheral portion of the first electrode.

2. A semiconductor layer having a first surface and a second surface; an element structure formed on the first surface side of the semiconductor layer, the element structure including a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region; a gate electrode facing the second region via a gate insulating film; a third region of the first conductivity type formed in the semiconductor layer so as to be in contact with the second region; a first electrode formed on the semiconductor layer and electrically connected to the first region and the second region; the element structure includes a first element structure and a second element structure, the first element structure further includes a first column layer of a second conductivity type that is spaced apart from the second region in a direction along the first surface of the semiconductor layer and extends in a thickness direction of the semiconductor layer; the second element structure further includes a second electrode facing the third region via an insulating film and electrically connected to the first electrode; the third region includes a first portion that is formed between a top of the first column layer and the second region and has a first impurity concentration, and a second portion that is formed on the second surface side of the semiconductor layer with respect to the first portion and has a second impurity concentration lower than the first impurity concentration; the first column layer has an uneven side surface formed by repeating a plurality of convex portions and concave portions in a thickness direction of the semiconductor layer, a top of the first column layer includes the convex portion closest to the first surface of the semiconductor layer.

3. 3. The semiconductor device according to claim 2, wherein the semiconductor layer includes a first element region in which a plurality of the first element structures are arranged, and a second element region in which a plurality of the second element structures are arranged.

4. 4. The semiconductor device according to claim 1, wherein the first element region is surrounded by the second element region.

5. the semiconductor layer includes an active region in which the element structure is formed and a peripheral region surrounding the active region; 5. The semiconductor device according to claim 3, wherein the second element region is formed on a periphery of the active region.

6. the first electrode covers the first element region and the second element region, The semiconductor device according to claim 3 , wherein said second element region is formed along a peripheral edge of said first electrode.

7. 2. The semiconductor device according to claim 1, wherein the third region includes a first portion having a first impurity concentration, the first portion being formed between a top of the first column layer and the second region, and a second portion being formed on the second surface side of the semiconductor layer relative to the first portion, the second portion having a second impurity concentration lower than the first impurity concentration.

8. the gate electrode includes a first portion extending in a first direction, a second portion extending in a second direction perpendicular to the first direction, and an intersection portion where the first portion and the second portion intersect; 8. The semiconductor device according to claim 1, wherein the first column layer is formed below the intersection of the gate electrodes.

9. the second region of the first element structure is formed in a quadrangular shape in a plan view, 9. The semiconductor device according to claim 1, wherein said first column layer is formed adjacent to a corner of said second region.

10. A plurality of the first column layers are formed at intervals, 10. The semiconductor device according to claim 1, wherein the second region of the first element structure is formed away from a region between the first column layers adjacent to each other.

11. 11. The semiconductor device according to claim 1, wherein the second electrode is formed between the second regions adjacent to each other.

12. The semiconductor device according to any one of claims 1 to 11, wherein the second element structure further includes a second column layer of a second conductivity type formed in continuity with the second region and extending in a thickness direction of the semiconductor layer from the second region toward the second surface of the semiconductor layer.

13. The semiconductor device according to claim 12 , wherein the first column layers and the second column layers are regularly arranged at equal intervals from each other.

14. 14. The semiconductor device according to claim 1, wherein the element structure includes a planar gate structure.

15. 14. The semiconductor device according to claim 1, wherein the element structure includes a trench gate structure.

16. 16. The semiconductor device according to claim 1, comprising a MISFET having the first region as a source region and the second region as a body region.

17. The semiconductor device according to any one of claims 1 to 15, comprising an IGBT having the first region as an emitter region, the second region as a base region, and a collector region of a second conductivity type in contact with the third region.

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