Imaging device and electronic device

Abstract

Provided is an imaging device that has an image processing function and that can operate at high speeds. The imaging device, having additional functions such as image processing, uses a pixel unit to binarize image data acquired in an imaging operation, and performs a product-sum operation using the binarized data. The pixel unit is provided with a storage circuit to hold a weighting factor used in the product-sum operation. The foregoing eliminates the need for reading a weighting factor from the outside each time the operation is performed, thereby reducing power consumption. In addition, by stacking circuits such as a pixel circuit and a storage circuit onto a circuit such as a product-sum operation circuit, the wiring length between the circuits can be shortened, and low power consumption operations and high-speed operations can be performed.

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their operating methods, or their manufacturing methods can be cited as an example.

[0003] Note that in this specification or the like, the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. In addition, storage devices, display devices, imaging devices, and electronic devices may have semiconductor devices.

Background Art

[0004] Techniques for constructing transistors using oxide semiconductor thin films formed on a substrate have attracted attention. For example, Patent Document 1 discloses an imaging device configured to use a transistor having an extremely low off-current with an oxide semiconductor in a pixel circuit.

[0005] In addition, Patent Document 2 discloses a technique for adding an arithmetic function to an imaging device.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

[0007] In imaging devices mounted on portable devices, etc., a function capable of acquiring high-resolution images has become common. In the next generation, imaging devices are required to be equipped with even more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted to digital data, and after being taken out, image processing is performed as necessary. If this processing can be performed within the imaging device, linking with external devices will become faster, improving user convenience. In addition, the load and power consumption of peripheral devices can be reduced.

[0009] In addition, when adding functions to an imaging device, it is preferable to stack elements such as additional circuits. For example, by arranging multiple circuits so as to overlap with pixel circuits, it is possible to suppress an increase in area and form a compact imaging device with high functionality. In addition, the wiring length between stacked circuits can be shortened, enabling high-speed and low-power operation to be achieved.

[0010] Therefore, one object of one embodiment of the present invention is to provide an imaging device capable of performing image processing. Another object is to provide a highly functional and small imaging device. Another object is to provide an imaging device that can operate at high speed. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to an imaging device having an image processing function and capable of high-speed operation.

[0013] One embodiment of the present invention is an imaging device having a plurality of pixel blocks, the pixel blocks having a first layer and a second layer, the first layer having an area overlapping with the second layer, the pixel blocks having a plurality of pixel circuits and a plurality of first memory circuits in the first layer, and a plurality of product-accumulation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and the pixel circuits and the first memory circuits have transistors having metal oxide in their channel formation regions.

[0014] Another embodiment of the present invention is an imaging device having a plurality of pixel blocks, the pixel blocks having a first layer, a second layer, and a third layer, the first layer being located between the second layer and the third layer or the third layer being between the first layer and the second layer, the first layer to the third layer having an overlapping region, the pixel blocks having a plurality of pixel circuits in the first layer, a plurality of product-accumulation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and a plurality of first memory circuits in the third layer, and the pixel circuits and the first memory circuits have transistors having metal oxide in their channel formation regions.

[0015] The product-sum operation circuit, the first binarization circuit and the second binarization circuit preferably have transistors having silicon in their channel formation regions.

[0016] The number of pixel circuits and the number of first binarization circuits are the same, and each pixel circuit can be electrically connected to one first binarization circuit.

[0017] One first binarization circuit can be electrically connected to a plurality of product-sum calculation circuits.

[0018] One first memory circuit can be electrically connected to a plurality of product-sum calculation circuits.

[0019] The number of product-sum calculation circuits and second binarization circuits is the same, and one product-sum calculation circuit can be electrically connected to one second binarization circuit.

[0020] A driver circuit for the pixel circuit and a driver circuit for the first memory circuit can be provided in the second layer.

[0021] The input terminal of the second memory circuit may be electrically connected to the plurality of second binarization circuits, and the output terminal of the second memory circuit may be electrically connected to the plurality of product-accumulation circuits.

[0022] The digital signal processing device may further include a third memory circuit and a third binarization circuit, and the third memory circuit may be electrically connected to the plurality of product-sum calculation circuits via the third binarization circuit.

[0023] The second memory circuit, the third memory circuit, and the third binarization circuit can be provided in a second layer.

[0024] The metal oxide preferably comprises In, Zn, and M (wherein M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0025] The first memory circuit may have a memory cell, and the memory cell may have a capacitor having a ferroelectric layer. Effect of the Invention

[0026] By using one embodiment of the present invention, an imaging device capable of performing image processing can be provided. Alternatively, a highly functional and small imaging device can be provided. Alternatively, an imaging device capable of operating at high speed can be provided. Alternatively, an imaging device with low power consumption can be provided. Alternatively, an imaging device with high reliability can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a driving method of the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief description of the drawings]

[0027] FIG. 1 is a diagram illustrating an imaging device. 2A to 2C are diagrams illustrating a pixel portion. FIG. 3 is a diagram illustrating a pixel block. FIG. 4 is a diagram illustrating a pixel block. FIG. 5 is a diagram illustrating a pixel block. Fig. 6A is a diagram for explaining a product-sum calculation circuit, and Fig. 6B is a diagram for explaining a binarization circuit. FIG. 7 is a diagram illustrating a pixel block. FIG. 8 is a diagram illustrating a pixel block and a readout circuit. FIG. 9 is a timing chart illustrating the operation of the read circuit. 10A to 10C are diagrams illustrating a pixel circuit. Fig. 11A is a diagram illustrating a memory circuit, and Figs. 11B to 11D are diagrams illustrating a memory cell. Fig. 12A is a diagram illustrating a memory circuit, and Fig. 12B and Fig. 12C are diagrams illustrating a memory cell. Fig. 13A is a diagram illustrating the hysteresis characteristic of a ferroelectric layer, and Fig. 13B is a timing chart illustrating the operation of a memory cell. 14A and 14B are diagrams for explaining the layout of a pixel circuit. FIG. 15 is a diagram for explaining the operation of reading data from a pixel block. FIG. 16 is a diagram for explaining the operation of distributing data to pixel blocks. Fig. 17A is a diagram for explaining the operation of reading data from a pixel block, and Fig. 17B is a diagram for explaining a circuit 25. Fig. 18A is a diagram illustrating a read circuit, and Fig. 18B is a timing chart illustrating the operation of the read circuit. 19A to 19D are diagrams illustrating the configuration of a pixel of an imaging device. 20A to 20C are diagrams illustrating the configuration of a photoelectric conversion device. FIG. 21 is a cross-sectional view illustrating a pixel. 22A to 22C are diagrams illustrating a Si transistor. FIG. 23 is a cross-sectional view illustrating a pixel. FIG. 24 is a cross-sectional view illustrating a pixel. FIG. 25 is a cross-sectional view illustrating a pixel. 26A to 26D illustrate OS transistors. FIG. 27 is a cross-sectional view illustrating a pixel. FIG. 28 is a cross-sectional view illustrating a pixel. FIG. 29 is a cross-sectional view illustrating a pixel. FIG. 30 is a cross-sectional view illustrating a pixel. 31A to 31C are perspective views (cross-sectional views) illustrating a pixel. Fig. 32A is a diagram illustrating a package that houses an imaging device, and Fig. 32B is a diagram illustrating a module that houses an imaging device. 33A to 33F are diagrams illustrating an electronic device. 34A and 34B are diagrams for explaining a moving body. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

[0029] In addition, even if a circuit diagram shows a single element, the element may be configured as a plurality of elements as long as there is no functional problem. For example, a plurality of transistors operating as a switch may be connected in series or parallel. A capacitor may also be divided and placed in multiple positions.

[0030] In addition, one conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0031] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0032] One embodiment of the present invention is an imaging device having additional functions such as image processing. The imaging device binarizes analog data (image data) acquired in an imaging operation in a pixel portion, and performs a product-sum operation using the binarized data. The pixel portion is provided with a memory circuit that holds weighting coefficients (also called weighting data or filters) used in the product-sum operation. Therefore, the operation can be performed without reading the weighting coefficients from the outside each time, and power consumption can be reduced.

[0033] In addition, in an imaging device according to one embodiment of the present invention, a pixel circuit, a memory circuit, or the like, and a product-sum calculation circuit or the like are stacked, so that the wiring length between circuits can be shortened and low power consumption and high-speed operation can be achieved.

[0034] <Imaging device> 1 is a perspective view illustrating an imaging device of one embodiment of the present invention. The imaging device includes a layer 10 and a layer 20. The layer 10 can be provided over the layer 20. The imaging device includes a pixel portion 11 in which a pixel circuit, a memory circuit, and the like are provided. The pixel portion 11 includes elements provided in the layer 10 and elements provided in the layer 20.

[0035] The layer 10 may be provided with a pixel circuit and a memory circuit. The layer 20 may be provided with a driving circuit for the circuits in the layer 10, a calculation circuit for data acquired by the circuits in the layer 10, a data conversion circuit, a memory circuit, and the like. For example, the layer 20 may be provided with a calculation unit 21, a row driver 31 and a column driver 32 for driving the pixel circuits, a row driver 33 and a column driver 34 for driving the memory circuit, and the like. The layer 20 may also be provided with a circuit 35, a circuit 36, and the like having a data selection function, a storage function, a conversion function, a readout function, and the like, as necessary.

[0036] The circuits in layer 10 and the circuits in layer 20 can be electrically connected by electrodes or wiring that penetrate layer 10. Note that some of the circuits described above can also be provided in a layer opposite to that described above or outside the imaging device.

[0037] 2A is a diagram illustrating details of the pixel section 11. The pixel section 11 has a plurality of pixel blocks 12 arranged in a matrix. Furthermore, the pixel block 12 has a 3×3 pixel block 13. Furthermore, the pixel block 13 has 3×3 pixels 14. That is, the pixel block 12 has 9×9 pixels 14. The pixels 14 have a pixel circuit 15 and a memory circuit 16.

[0038] In one embodiment of the present invention, various calculations and the like are performed on the assumption that the pixel block 13 has 3×3 pixels 14, but the number of pixels is not limited to the above, and may be, for example, 2×2, 4×4, 5×5, or 25×25. Alternatively, the number of pixels 14 in the horizontal and vertical directions may be different. Also, some of the pixel blocks 13 may be shared by adjacent pixel blocks 12. Also, some of the pixels 14 may be shared by adjacent pixel blocks 13. The number of pixel blocks 13 included in a pixel block 12 may also be changed as appropriate.

[0039] The pixel 14 shown in Fig. 2A is an example in which the pixel circuit 15 and the memory circuit 16 are provided side by side in the layer 10, but the pixel circuit 15 may be provided overlapping the memory circuit 16 as shown in Fig. 2B. Alternatively, the memory circuit 16 may be provided overlapping the pixel circuit 15 as shown in Fig. 2C.

[0040] 3 is a diagram illustrating components of pixel block 13. Pixel block 13 has 3×3 pixels 14. Therefore, pixel block 13 has nine pixel circuits 15 and nine memory circuits 16 in layer 10. In addition, in a region (layer 20) overlapping with pixel circuits 15 or memory circuits 16, a plurality of binarization circuits 22, a plurality of product-sum calculation circuits 23, and a plurality of binarization circuits 24 are provided as a calculation unit 21.

[0041] The number of binarization circuits 22 is the same as the number of pixel circuits 15, i.e., nine. The binarization circuits 22 are provided at positions having overlapping areas with the pixel circuits 15. Fig. 4 is a diagram showing the connection relationship between the pixel circuits 15 and the binarization circuits 22, and one pixel circuit 15 is electrically connected to one binarization circuit 22 having an overlapping area.

[0042] The binarization circuit 22 is a circuit that binarizes the image data (analog data) acquired by the pixel circuit 15 by determining it using a preset threshold value, and may be, for example, a comparator.

[0043] A plurality of product-sum calculation circuits 23 are provided in one pixel block 13, and in this embodiment, an example is shown in which six product-sum calculation circuits 23 are provided. The number of product-sum calculation circuits 23 can be appropriately increased or decreased depending on the purpose. An input terminal of the product-sum calculation circuit 23 is electrically connected to the storage circuit 16 and the binarization circuit 22.

[0044] 5 is a diagram showing the connection relationship between the product-sum calculation circuit 23, the storage circuit 16, and the binarization circuits 22. In order to clearly show the connection relationship, only nine binarization circuits 22 are illustrated.

[0045] The pixel block 13 has nine storage circuits 16, each of which has a plurality of memory cells. A 1-bit weighting coefficient can be written in advance in each of the plurality of memory cells. Each of the nine storage circuits 16 is electrically connected to each of the six product-sum calculation circuits 23. Therefore, a 9-bit weighting coefficient can be supplied to each of the product-sum calculation circuits 23. Since weighting coefficients can be supplied from one storage circuit 16 to six product-sum calculation circuits 23, the operation can be performed here as long as at least a 1-bit weighting coefficient is written in one storage circuit 16.

[0046] Each of the binarization circuits 22 can output image data converted to 1 bit. Each of the nine binarization circuits 22 is electrically connected to each of the six product-sum calculation circuits 23. Since one binarization circuit 22 can supply image data to the six product-sum calculation circuits 23, 9-bit image data is supplied to each of the product-sum calculation circuits 23.

[0047] 6A is a diagram for briefly explaining the configuration and operation of the product-sum calculation circuit 23. The product-sum calculation circuit 23 can be configured to have, for example, nine multipliers 23a and one adder 23b. Each multiplier 23a receives image data (X1 to X9) converted to 1 bit by the binarization circuit 22 and a 1-bit weighting coefficient (W1 to W9) read from the storage circuit 16, performs a multiplication operation, and outputs 1-bit data to the adder 23b. The adder 23b adds the data input from each multiplier 23a and outputs the result to the binarization circuit 24. Here, the data output from the adder 23b (product-sum calculation circuit 23) has values ​​of 0 to 9, and is therefore 4-bit data.

[0048] FIG. 6B is a diagram for explaining the binarization circuit 24. The number of binarization circuits 24 is the same as the number of product-sum calculation circuits 23, that is, six. As shown in FIG. 6A, FIG. 6B, and FIG. 7, one binarization circuit 24 is electrically connected to one product-sum calculation circuit 23. As shown in FIG. 6A and FIG. 6B, data input to the binarization circuit 24 is 4-bit digital data corresponding to 0 to 9. When the binarization circuit 24 judges that the input data is 5 or more, it outputs 1, and when the input data is judged to be 4 or less, it outputs 0. That is, the binarization circuit 24 is a circuit having a function of converting 4-bit data into 1 bit.

[0049] As shown in Fig. 7, 6-bit calculation data can be output from one pixel block 13. Fig. 8 is a diagram for explaining reading of calculation data from pixel blocks 12 (pixel blocks 13[1,1] to 13[3,3]).

[0050] Each of the six binarization circuits 24 in the pixel block 13 has a selection transistor 24S that controls the output. The gates of the six selection transistors 24S are electrically connected to wirings RSEL (wirings RSEL[0], RSEL[1], and RSEL[2]). The wirings RSEL are shared by the pixel blocks 13 arranged in the row direction. In addition, six output lines OUT (OUT[0] to OUT[5]) to which the six binarization circuits 24 are electrically connected are shared by the pixel blocks 13 arranged in the column direction.

[0051] The six output lines OUT are electrically connected to a readout circuit 40. The readout circuit 40 has a switch 40S, a switch 41S, and a switch 42S that are electrically connected to the six output lines OUT of each column, respectively.

[0052] The switches 40S to 42S each include a plurality of transistors. A gate of the transistor included in the switch 40S is electrically connected to a wiring CSEL[0]. A gate of the transistor included in the switch 41S is electrically connected to a wiring CSEL[1]. A gate of the transistor included in the switch 42S is electrically connected to a wiring CSEL[2].

[0053] Every three wirings on the output side of the switches 40S to 42S are electrically connected to one output line OUT. With this configuration, data for each pixel block 13 can be output.

[0054] It should be noted that the readout circuit 40 may be provided in the layer 20 as an element of the circuit 35 or the circuit 36 ​​shown in FIG.

[0055] 9 is a timing chart for explaining the reading of calculation data from pixel blocks 12 (pixel blocks 13[1,1] to 13[3,3]). Note that all calculations in each pixel block 13 are completed before time T1, and the calculation data is held in the binarization circuit 24. In the following explanation, a potential (high potential) that makes a transistor conductive is expressed as "H", and a potential (low potential) that makes a transistor non-conductive is expressed as "L".

[0056] At time T1, when the potential of the wiring RSEL[0] is set to “H”, the selection transistors 24S of all the binarization circuits 24 in the pixel block 13 arranged in the 0th row are turned on, and the operation data is output to the readout circuit 40.

[0057] In addition, when the potential of the wiring CSEL[0] is set to “H” at time T1, the switch 40S, whose gate is electrically connected to the wiring CSEL[0], is turned on, and the calculation data of the pixel block 13[1,1] is output to the output lines OUT[0] to OUT[5].

[0058] At time T2, when the potential of the wiring CSEL[0] is set to “L” and the potential of the wiring CSEL[1] is set to “H”, the switch 40S becomes non-conductive, the switch 41S, whose gate is electrically connected to the wiring CSEL[1], becomes conductive, and the calculation data of the pixel block 13[1,2] is output to the output lines OUT[0] to OUT[5].

[0059] At time T3, when the potential of the wiring CSEL[1] is set to “L” and the potential of the wiring CSEL[2] is set to “H”, the switch 41S becomes non-conductive, the switch 42S, whose gate is electrically connected to the wiring CSEL[2], becomes conductive, and the calculation data of the pixel block 13[1,3] is output to the output lines OUT[0] to OUT[5].

[0060] At time T4, the potential of the wiring RSEL[0] is set to “L”, the potential of the wiring CSEL[2] is set to “L”, and the output of the calculation data of the pixel block 13 in the 0th row (pixel block 13[1,1] to pixel block 13[1,3]) is terminated.

[0061] From time T4 to time T7, the potential of the wiring RSEL[1] is set to “H”, and the same operation as described above is performed to output the calculation data of the pixel block 13 in the first row (pixel block 13[2,1] to pixel block 13[2,3]).

[0062] Also, from time T7 to time T10, the potential of the wiring RSEL[2] is set to “H”, and the same operation as described above is performed to output the calculation data of the pixel block 13 in the second row (pixel block 13[3,1] to pixel block 13[3,3]).

[0063] Here, if the calculation operation is completed in one clock and the read operation of one pixel block 13 is performed in one clock, one pixel block 12 can be read out in a total of 10 clocks. Note that by providing the same number of readout circuits 40 as the number of columns of pixel blocks 12, one row of pixel blocks 12 can be read out in parallel.

[0064] <Pixel circuit> The pixel circuit 15 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 106, as shown in FIG. 10A.

[0065] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105.

[0066] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 111. The gate of the transistor 102 is electrically connected to a wiring 114. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 112. The gate of the transistor 103 is electrically connected to a wiring 115. The other of the source and the drain of the transistor 104 is electrically connected to a wiring 113. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 117. The gate of the transistor 105 is electrically connected to a wiring 116.

[0067] Here, the electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104 is referred to as a node N.

[0068] The wirings 111, 112, and 113 can function as power supply lines. For example, the wiring 111 can function as a low-potential power supply line, and the wirings 112 and 113 can function as high-potential power supply lines. Note that the wirings 112 and 113 may be electrically connected. The wirings 114, 115, and 116 can function as signal lines that control the conduction of each transistor. The wiring 117 can function as a wiring that electrically connects the pixel circuit 15 and the binarization circuit 22.

[0069] A photodiode can be used as the photoelectric conversion device 101. When it is desired to increase the light detection sensitivity at low illuminance, it is preferable to use an avalanche photodiode.

[0070] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 104 can have a function of causing a current to flow in response to the potential of the node N. The transistor 105 can have a function of selecting a pixel.

[0071] Note that the connection direction of the pair of electrodes of the photoelectric conversion device 101 may be reversed. In this case, the wiring 111 may function as a high-potential power line, and the wiring 112 may function as a low-potential power line.

[0072] It is preferable to use a transistor (OS transistor) whose channel formation region is made of metal oxide for the transistors 102 and 103. An OS transistor has an extremely low off-state current. By using an OS transistor for the transistors 102 and 103, the period during which charge can be held at the node N can be made extremely long. Furthermore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration and operation method.

[0073] On the other hand, there are cases where it is desirable for the transistor 104 to have excellent amplification characteristics. In addition, there are cases where it is preferable to use a transistor with high mobility that can operate at high speed as the transistor 105. Therefore, the transistors 104 and 105 may be transistors that use silicon for a channel formation region (Si transistors).

[0074] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. All the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single crystal silicon).

[0075] As shown in FIG. 10B, a transistor may be provided with a back gate (second gate). By electrically connecting the back gate to the front gate, the on-state current of the transistor can be increased. Furthermore, by supplying an appropriate constant potential to the back gate, the threshold voltage of the transistor can be controlled. Note that the structure in which a transistor is provided with a back gate can also be applied to other circuits in this specification. Furthermore, a circuit may be configured by mixing transistors with and without a back gate.

[0076] 10C, a transistor 107 and a transistor 108 may be added to the structure of FIG. 10A. The gate of the transistor 107 is electrically connected to the gate of the transistor 104. The one of the source and the drain of the transistor 107 is electrically connected to the one of the source and the drain of the transistor 108. The other of the source and the drain of the transistor 107 is electrically connected to a wiring 113. The gate of the transistor 108 is electrically connected to a wiring 118. The other of the source and the drain of the transistor 108 is electrically connected to a wiring 119.

[0077] Here, the wiring 118 can function as a signal line that controls the conduction of the transistor 108. The wiring 119 can be electrically connected to a circuit 60. The circuit 60 is an image reading circuit, and for example, a CDS circuit (correlated double sampling circuit) or the like can be used. By using this configuration, image data can be output to the wiring 117 and the wiring 119. The image data output to the wiring 117 is input to a binarization circuit 22, and then a product-sum operation is performed. The image data output to the wiring 119 is read out to the outside via the circuit 60. These operations can be performed in parallel. Also, only the operation (image processing) or only the reading out of the image data can be performed.

[0078] It should be noted that circuitry 60 may be provided on layer 20 as an element of circuitry 35 or circuitry 36 shown in FIG.

[0079] <Memory circuit 1> 2, the memory circuit 16 is provided in the pixel 14. The memory circuit 16 has a plurality of memory cells, and each memory cell stores 1-bit data corresponding to a weighting coefficient.

[0080] 11A is a diagram showing the connection relationship between the memory cells 150, the row driver 33, and the column driver 34 of the memory circuit 16. A plurality of memory cells 150 are provided in the layer 10 as the memory circuit 16. The row driver 33 and the column driver 34 are driving circuits for the memory cells 150, and can be provided in the layer 20. A sense amplifier or the like may be used to read out data.

[0081] The memory circuit 16 has m×n memory cells 150 in a row (m is an integer of 1 or more), with m in a column and n in a row (n is an integer of 1 or more), and the memory cells 150 are arranged in a matrix.

[0082] 11B to 11D are diagrams for explaining memory cells 150a to 150c that can be applied to the memory cell 150. In the following description, the bit lines can be electrically connected to the column driver 34. The word lines can be electrically connected to the row driver 33. The bit lines are also electrically connected to the product-sum operation circuit 23, but this is not shown here.

[0083] For example, a decoder or a shift register can be used for the row driver 33 and the column driver 34. Note that a plurality of row drivers 33 and a plurality of column drivers 34 may be provided.

[0084] 11B shows an example of a circuit configuration of a DRAM type memory cell 150a. The memory cell 150a includes a transistor 271 and a capacitor 274.

[0085] One of the source or drain of the transistor 271 is connected to one electrode of the capacitor 274, the other of the source or drain of the transistor 271 is connected to a wiring BIL, the gate of the transistor 271 is connected to a wiring WL, and the back gate of the transistor 271 is connected to a wiring BGL. The other electrode of the capacitor 274 is connected to a wiring GNDL. The wiring GNDL is a wiring that provides a low-level potential (reference potential).

[0086] The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 271. The threshold voltage of the transistor 271 can be increased or decreased by applying an appropriate potential to the wiring BGL. Alternatively, the wiring BGL may be electrically connected to the wiring WL. The on-state current of the transistor 271 can be increased by applying the same potential as the wiring WL to the wiring BGL.

[0087] Data is written and read by applying a high-level potential to the wiring WL to turn on the transistor 271 and electrically connect the wiring BIL to one electrode of the capacitor 274. For example, a sense amplifier is electrically connected to the wiring BIL, and the potential of the wiring BIL can be amplified and read by the sense amplifier.

[0088] An OS transistor is preferably used as the transistor 271. In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).

[0089] An OS transistor using an oxide semiconductor containing indium, gallium, or zinc has the characteristic of having an extremely small off-state current. By using an OS transistor as the transistor 271, the leakage current of the transistor 271 can be made extremely low. That is, written data can be held by the transistor 271 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated.

[0090] 11C shows an example of a circuit configuration of a memory cell 150b of a gain cell type (also called a "2Tr1C type") having two transistors and one capacitor. The memory cell 150b includes a transistor 273, a transistor 272, and a capacitor 275.

[0091] One of the source or drain of the transistor 273 is connected to one electrode of the capacitor 275, the other of the source or drain of the transistor 273 is connected to the wiring WBL, the gate of the transistor 273 is connected to the wiring WL, and the back gate of the transistor 273 is connected to the wiring BGL. The other electrode of the capacitor 275 is connected to the wiring RL. One of the source or drain of the transistor 272 is connected to the wiring RBL, the other of the source or drain of the transistor 272 is connected to the wiring SL, and the gate of the transistor 272 is connected to one electrode of the capacitor 275.

[0092] The wiring WBL functions as a write bit line. The wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor 275. When writing data and while holding the data, it is preferable to apply a reference potential to the wiring RL.

[0093] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 273. The threshold voltage of the transistor 273 can be increased or decreased by applying an appropriate potential to the wiring BGL. Alternatively, the wiring BGL may be electrically connected to the wiring WL. The current characteristics of the transistor 273 can be improved by applying the same potential as that of the wiring WL to the wiring BGL.

[0094] Data is written by applying a high-level potential to the wiring WL to turn on the transistor 273 and electrically connecting the wiring WBL to one electrode of the capacitor 275. Specifically, when the transistor 273 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring WBL, and the potential is written to one electrode of the capacitor 275 and the gate of the transistor 272. After that, a low-level potential is applied to the wiring WL to turn off the transistor 273, thereby holding the potential of one electrode of the capacitor 275 and the potential of the gate of the transistor 272.

[0095] Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor 272 and the potential of one of the source or drain of the transistor 273 are determined by the potential of the gate of the transistor 272 and the potential of the other of the source or drain of the transistor 273. Therefore, by reading the potential of the wiring RBL connected to one of the source or drain of the transistor 272, the potential held in one electrode of the capacitor 275 (or the gate of the transistor 272) can be read. In other words, information written in this memory cell can be read from the potential held in one electrode of the capacitor 275 (or the gate of the transistor 272). Alternatively, the presence or absence of information written in this memory cell can be known.

[0096] 11D, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. The memory cell 150c shown in FIG. 11D is configured such that the wiring WBL and the wiring RBL of the memory cell 150b are combined into a single wiring BIL, and the other of the source or the drain of the transistor 273 and one of the source or the drain of the transistor 272 are connected to the wiring BIL. In other words, the memory cell 150c is configured to operate the write bit line and the read bit line as a single wiring BIL.

[0097] In the memory cells 150b and 150c, it is preferable to use an OS transistor as the transistor 273. A storage device using an OS transistor as the transistor 273 and using a 2Tr1C type memory cell such as the memory cells 150b and 150c is called a non-volatile oxide semiconductor random access memory (NOSRAM). Note that the circuit configuration of the memory cells can be changed as appropriate.

[0098] <Memory circuit 2> The memory circuit 16 may have the configuration shown in Fig. 12A. The memory circuit 16 having the configuration shown in Fig. 12A can use a memory cell 150d shown in Fig. 12B.

[0099] The memory cell 150d includes a transistor 276 and a capacitor 277. One of the source and drain of the transistor 276 is connected to one electrode of the capacitor 277, the other of the source and drain of the transistor 276 is connected to a wiring BIL, and the gate of the transistor 276 is connected to a wiring WL. The other electrode of the capacitor 277 is connected to a wiring PL.

[0100] The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring PL is a wiring that provides a plate potential required for writing or reading data to the capacitor 277. The circuit 37 shown in FIG. 12A is a circuit that supplies the plate potential, and can be provided in the layer 20 as an element of the circuit 35 or the circuit 36. A sense amplifier may be electrically connected to the wiring BIL. The potential of the wiring BIL can be amplified and read out by the sense amplifier.

[0101] A Si transistor, an OS transistor, or the like can be used as the transistor 276. When an OS transistor is used as the transistor 276, a back gate electrically connected to a wiring BGL is preferably provided as shown in FIG. 12C. The threshold voltage of the transistor 271 can be increased or decreased by applying an appropriate potential to the wiring BGL. Alternatively, the wiring BGL may be electrically connected to the wiring WL. The current characteristics of the transistor 271 can be improved by applying the same potential as that of the wiring WL to the wiring BGL.

[0102] In addition, an OS transistor has a characteristic of being able to withstand high voltage. Therefore, by using an OS transistor as the transistor 276, even if the transistor 276 is miniaturized, a high voltage can be applied to the transistor 276. By miniaturizing the transistor 276, the area occupied by the memory cell 150d can be reduced.

[0103] The capacitor 277 has a material having ferroelectricity as a dielectric layer between two electrodes. Hereinafter, the dielectric layer of the capacitor 277 is referred to as a ferroelectric layer. A capacitor having a ferroelectric layer can be referred to as a ferroelectric capacitor. A configuration in which a switch such as a transistor and a ferroelectric capacitor are combined can be referred to as a ferroelectric memory.

[0104] Materials that can have ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0), materials in which element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, and materials in which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. Also, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as lead titanate (PT), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. can be used. As a material that can have ferroelectricity, for example, a mixture or compound containing multiple materials selected from the materials listed above can be used. Alternatively, the ferroelectric layer can have a laminated structure made of multiple materials selected from the materials listed above.

[0105] Among these, materials that can have ferroelectricity include hafnium oxide or materials that contain hafnium oxide and zirconium oxide, which can retain ferroelectricity even when processed into a thin film of a few nm. The ability to thin the ferroelectric layer improves compatibility with the transistor miniaturization process.

[0106] In addition, HfZrO is a material that can have ferroelectric properties. XWhen using a ferroelectric material, it is preferable to form the film by atomic layer deposition (ALD), particularly by thermal ALD. When using thermal ALD to form a film of a material that may have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called Hydro Carbon, HC) as a precursor. When either or both of hydrogen and carbon are contained in the material that may have ferroelectricity, crystallization of the material that may have ferroelectricity may be inhibited. For this reason, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that may have ferroelectricity. For example, a chlorine-based material is an example of a precursor that does not contain hydrocarbons. Note that a material that contains hafnium oxide and zirconium oxide (HfZrO x ) is used as a precursor, HfCl 4 , and / or ZrCl 4 can be used.

[0107] When a film is formed using a material that can have ferroelectricity, impurities in the film, here at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed to form a film having high purity and intrinsic ferroelectricity. A film having high purity and intrinsic ferroelectricity and a high purity and intrinsic oxide semiconductor shown in the embodiment described later have a very high compatibility in manufacturing process. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0108] In addition, HfZrO is a material that can have ferroelectric properties. X When using hafnium oxide and zirconium oxide, it is preferable to form films alternately using a thermal ALD method so that the composition is 1:1.

[0109] In addition, when a material that can have ferroelectric properties is deposited using the thermal ALD method, the oxidizing agent is H 2 O or O 3 However, the oxidizing agent for the thermal ALD method is not limited to this. For example, O2 , O 3 , N 2 O, NO 2 , H 2 O and H 2 O 2 The present invention may include any one or more selected from the above.

[0110] In addition, the crystal structure of the material that can have ferroelectricity is not particularly limited. For example, the crystal structure of the material that can have ferroelectricity may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic. In particular, the material that can have ferroelectricity is preferably an orthorhombic crystal structure because it exhibits ferroelectricity. Alternatively, the material that can have ferroelectricity may be a composite structure having an amorphous structure and a crystalline structure.

[0111] Fig. 13A is a graph showing an example of the hysteresis characteristic of the ferroelectric layer. In Fig. 13A, the horizontal axis indicates the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode of the capacitor 277. In Fig. 13A, the vertical axis indicates the polarization amount of the ferroelectric layer.

[0112] 13A, the hysteresis characteristic of the ferroelectric layer can be represented by a curve 71 and a curve 72. The voltages at the intersections of the curve 71 and the curve 72 are defined as VSP and -VSP. It can be said that VSP and -VSP have opposite polarities.

[0113] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization amount of the ferroelectric layer increases according to curve 71. On the other hand, when a voltage equal to or more than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization amount of the ferroelectric layer decreases according to curve 72. Here, VSP and -VSP can be called saturation polarization voltages. For example, VSP may be called the first saturation polarization voltage and -VSP may be called the second saturation polarization voltage. Also, in FIG. 13A, the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, but they may be different.

[0114] Here, when the amount of polarization of the ferroelectric layer changes according to the curve 71, the voltage (coercive voltage) at which the amount of polarization of the ferroelectric layer becomes zero is defined as Vc. When the amount of polarization of the ferroelectric layer changes according to the curve 72, the voltage (coercive voltage) at which the amount of polarization of the ferroelectric layer becomes zero is defined as -Vc. It can be said that the values ​​of Vc and -Vc are between -VSP and VSP. For example, Vc may be called the first coercive voltage, and -Vc may be called the second coercive voltage. Although FIG. 13A shows an example in which the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, they may be different.

[0115] As described above, the voltage applied to the ferroelectric layer of the capacitor 277 can be expressed by the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode of the capacitor 277. The other electrode of the capacitor 277 is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitor 277 can be controlled.

[0116] <An example of a memory cell driving method> An example of a method for driving the memory cell 150d shown in Fig. 12B will be described below. In the following description, the voltage applied to the ferroelectric layer of the capacitor 277 is the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode (wiring PL) of the capacitor 277. The transistor 276 is an n-channel transistor.

[0117] Fig. 13B is a timing chart showing an example of a method for driving the memory cell 150d shown in Fig. 12B. Fig. 13B shows an example of writing and reading binary digital data to and from the memory cell 150d.

[0118] A sense amplifier is electrically connected to the wiring BIL, and Vref is supplied to the sense amplifier as a reference potential. For example, when the potential of the wiring BIL is higher than Vref, data "1" can be read out. When the potential of the wiring BIL is lower than Vref, data "0" can be read out.

[0119] First, the operation of writing data "1" into the memory cell 150d from time T01 to time T03 will be described.

[0120] At time T01 to time T02, when the potential of the wiring WL is set to a high potential H, the transistor 276 is turned on. Furthermore, the potential of the wiring BIL is set to Vw. Since the transistor 276 is in the on state, the potential of one electrode of the capacitor 277 is Vw. Furthermore, the potential of the wiring PL is set to GND. With this operation, the voltage applied to the ferroelectric layer of the capacitor 277 becomes "Vw-GND". Therefore, data "1" can be written to the memory cell 150d.

[0121] Here, Vw is preferably equal to or greater than VSP, and may be equal to VSP, for example. GND may be, for example, the ground potential or 0V, but may be another potential.

[0122] Next, at time T02, when the potential of the wiring BIL and the potential of the wiring PL are set to GND, the voltage applied to the ferroelectric layer of the capacitor 277 becomes 0V. When the voltage "Vw-GND" applied to the ferroelectric layer of the capacitor 277 is equal to or higher than VSP from time T01 to time T02, the polarization amount of the ferroelectric layer of the capacitor 277 changes to the position of 0V in accordance with the curve 72 shown in Fig. 13A from time T02 to time T03. Therefore, the polarization direction is maintained in the ferroelectric layer of the capacitor 277.

[0123] When the potential of the wiring BIL and the potential of the wiring PL are set to GND and then the potential of the wiring WL is set to a low potential L, the transistor 276 is turned off. In this manner, the write operation is completed and data "1" is held in the memory cell 150d.

[0124] Next, the data read operation from time T03 to time T04 will be described.

[0125] From time T03 to time T04, when the potential of the wiring WL is set to a high potential H, the transistor 276 is turned on. Also, the potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitor 277 becomes "GND-Vw".

[0126] At this time, the voltage applied to the ferroelectric layer of the capacitor 277 is inverted from "Vw-GND" to "GND-Vw", causing polarization inversion in the ferroelectric layer of the capacitor 277. Since a current flows through the wiring BIL during polarization inversion, the potential of the wiring BIL becomes higher than Vref. Therefore, the data "1" held in the memory cell 150d can be read by the operation of the sense amplifier. Note that, although a case where Vref is higher than GND and lower than Vw is illustrated, it may be higher than Vw, for example.

[0127] Next, the data rewrite operation from time T04 to time T05 will be described.

[0128] Since the read operation is a destructive read that reverses the polarization direction, the data "1" stored in the memory cell 150d is lost. Therefore, between time T04 and time T05, the potential of the wiring BIL is set to Vw and the potential of the wiring PL is set to GND, and the data "1" is rewritten in the memory cell 150d.

[0129] At time T05, the potentials of the wiring BIL and the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential L. This completes the rewrite operation, and data "1" is held in the memory cell 150d.

[0130] Next, the read operation from time T11 to time T13 and the write operation of data "0" to the memory cell 150d will be described.

[0131] From time T11 to time T12, the potential of the wiring WL is set to a high potential H, and the potential of the wiring PL is set to Vw. Since data "1" is stored in the memory cell 150d, the potential of the wiring BIL becomes higher than Vref, and the data "1" stored in the memory cell 150d is read out.

[0132] From time T12 to time T13, the potential of the wiring BIL is set to GND. Since the transistor 276 is on, the potential of one electrode of the capacitor 277 is set to GND. In addition, the potential of the wiring PL is set to Vw. As a result, the voltage applied to the ferroelectric layer of the capacitor 277 is "GND-Vw". Therefore, data "0" can be written to the memory cell 150d.

[0133] Subsequently, at time T13, when the potential of wiring BIL and the potential of wiring PL are set to GND, the voltage applied to the ferroelectric layer of capacitor 277 becomes 0V. When the voltage "GND - Vw" applied to the ferroelectric layer of capacitor 277 from time T12 to time T13 is -VSP or less, from time T13 to time T14, the polarization amount of the ferroelectric layer of capacitor 277 changes to the position of 0V according to the curve 71 shown in Fig. 13A. Therefore, the direction of polarization in the ferroelectric layer of capacitor 277 is maintained.

[0134] After setting the potential of wiring BIL and the potential of wiring PL to GND, when the potential of wiring WL is set to the low potential L, transistor 276 turns off. Thus, the write operation is completed, and the data "0" is retained in memory cell 150d.

[0135] Next, the data read operation from time T14 to time T15 will be described.

[0136] At time T14 to time T15, when the potential of wiring WL is set to the high potential H, transistor 276 turns on. Also, the potential of wiring PL is set to Vw. By setting the potential of wiring PL to Vw, the voltage applied to the ferroelectric layer of capacitor 277 becomes "GND - Vw".

[0137] At this time, since the voltage applied to the ferroelectric layer of capacitor 277 is the same "GND - Vw" as when writing data, no polarization inversion occurs in the ferroelectric layer of capacitor 277. Therefore, the current flowing through wiring BIL becomes smaller than the case where polarization inversion occurs in the ferroelectric layer of capacitor 277. Thus, the rising width of the potential of wiring BIL also becomes smaller. Specifically, the potential of wiring BIL becomes Vref or less, and the data "0" retained in memory cell 150d can be read by the operation of the sense amplifier.

[0138] Next, the data rewrite operation from time T15 to time T17 will be described.

[0139] From time T15 to time T16, the potential of the wiring BIL is set to GND, and the potential of the wiring PL is set to Vw. Through this operation, data "0" is rewritten to the memory cell 150d.

[0140] From time T16 to time T17, the potentials of the wiring BIL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential L. In this manner, the rewrite operation is completed, and data "0" is held in the memory cell 150d.

[0141] Next, the data read operation and the data "1" write operation to the memory cell 150d from time T17 to time T19 will be described.

[0142] From time T17 to time T18, the potential of the wiring WL is set to a high potential H, and the potential of the wiring PL is set to Vw. Since data "0" is stored in the memory cell 150d, the potential of the wiring BIL becomes lower than Vref, and the data "0" stored in the memory cell 150d is read out.

[0143] From time T18 to time T19, the potential of the wiring BIL is set to Vw. Since the transistor 276 is on, the potential of one electrode of the capacitor 277 is Vw. In addition, the potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor 277 is "Vw-GND." Therefore, data "1" can be written to the memory cell 150d.

[0144] After time T19, the potentials of the wiring BIL and the wiring PL are set to GND, and then the potential of the wiring WL is set to the low potential L. This completes the write operation, and data "1" is held in the memory cell 150d.

[0145] The above is an example of the operation of the memory cell 150d, but operations such as writing, reading, and rewriting data may be performed by other methods.

[0146] <Layout> 14A and 14B are examples of a layout (top view) that can be used for a pixel circuit of one embodiment of the present invention. 14A and 14B are layouts of the pixel circuit shown in FIG. 10B, and FIG. 14A shows a back-gate wiring 170, a metal oxide layer 175, and a source-drain wiring 180. Here, the metal oxide layer 175 is a layer in which a channel formation region of an OS transistor is provided.

[0147] In order to improve the resolution of an imaging device, it is necessary to miniaturize pixel circuits. In the miniaturization process, adjacent structures affect each other, so randomly arranging the structures will increase the variation in wiring width, etc. Therefore, as shown in Figure 14A, it is preferable to arrange the structures at equal intervals in the horizontal direction (X direction) and vertical direction (Y direction).

[0148] Fig. 14B shows a configuration in which gate wiring 185 and wiring 190 electrically connected to gate wiring 185 are added to Fig. 14A. By overlapping each element in this manner, transistor 102, transistor 103, transistor 104, and transistor 105 shown in Fig. 10B are formed. In addition, a plurality of transistors 109 are formed. Transistor 109 is a dummy transistor that is not involved in the circuit operation, but such a configuration can improve the uniformity of wiring width, etc., and suppress variations in transistor characteristics, etc.

[0149] According to one embodiment of the present invention described in this embodiment, an imaging device which has an image processing function and can operate at high speed can be provided.

[0150] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0151] (Embodiment 2) In this embodiment, an imaging device having a different configuration from that of embodiment 1 will be described with reference to the drawings. The imaging device described in embodiment 1 is configured to perform a multiply-and-accumulate operation on image data once and extract the calculated data, but the imaging device described in this embodiment is configured to perform a multiply-and-accumulate operation on image data multiple times and extract the calculated data.

[0152] The basic configuration of the pixel 14 and the pixel blocks (pixel block 12, pixel block 13) is the same as in the first embodiment, so a detailed description thereof will be omitted.

[0153] The imaging device has two registers as elements for performing multiply-and-accumulate operations multiple times and extracting the operation data. Fig. 15 is a diagram for explaining the connection relationship between the pixel block 12 and register 51, which is one of the two registers (register 51 and register 52). Note that a selection circuit can be provided between the pixel block 13 and register 51 to reduce the number of wirings.

[0154] The pixel block 12 shown in Fig. 15 is a simplified diagram of the pixel block 12 shown in Fig. 8, and indicates that the calculation data output from each pixel block 13 after the first multiply-and-accumulate operation is 6 bits (1 bit x 6). The 6 bits of calculation data output from each pixel block 13 are input to and stored in a register 51. Here, the 6 bits of calculation data output from nine pixel blocks 13 are input to the register 51, so that a total of 54 bits of calculation data (6 bits x 9) is stored.

[0155] Next, as shown in Fig. 16, the 54-bit calculation data stored in the register 51 is redistributed to each pixel block 13. Each pixel block 13 is provided with six product-sum calculation circuits 23 capable of processing 9-bit data shown in Fig. 6A, and 9-bit calculation data is distributed to each product-sum calculation circuit 23. In addition, each product-sum calculation circuit 23 is supplied with 9-bit weighting coefficients from the nine memory circuits 16 that the pixel block 13 has. Therefore, each product-sum calculation circuit 23 can perform a second product-sum calculation.

[0156] 17A, the 4-bit operation data output by each product-sum operation circuit 23 is input to circuits 25, the number of which is the same as the number of pixel blocks 13. Since there are six product-sum operation circuits 23, the operation data input to the circuits 25 is 24 bits (4 bits×6).

[0157] FIG. 17B is a diagram for explaining the circuit 25. The circuit 25 has an adder circuit 26a and a binarization circuit 26b. Since 4-bit (corresponding to 0 to 9) operation data is input to the adder circuit 26a from each of the six product-sum calculation circuits 23, the output of the adder circuit 26a becomes 6-bit (corresponding to 0 to 54) operation data. The 6-bit data is input to the binarization circuit 26b. The binarization circuit 26b can convert the input data to 1 bit, outputting 1 when the data is 28 or more and 0 when the data is 27 or less. Although the circuit 25 is illustrated inside the pixel block 12 in FIG. 17, it may be provided outside the pixel block 12.

[0158] The 1-bit operation data output from each circuit 25 (total of 9-bit data) is input to and stored in the register 52. Here, the 9-bit operation data can be read out as necessary. Note that a selection circuit can be provided between the circuit 25 and the register 52 to reduce the number of wirings.

[0159] In this embodiment, the operation of repeating the product-sum operation by further changing the weighting coefficient will be described. After the above operation, the product-sum operation circuit 23 of the pixel block 13 holds 54 bits of operation data redistributed from the register 51, and by changing the weighting coefficient supplied from the storage circuit 16, the product-sum operation can be performed again to obtain different operation data. Then, the operation data is stored in the register 52 in the same manner as the operation data obtained by the previous product-sum operation. Therefore, a total of 18 bits of operation data is stored in the register 52.

[0160] FIG. 18A is a diagram for explaining a read circuit 41 connected to the output side of the register 52. A plurality of six output lines are provided on the output side of the register 52 so that arithmetic data can be read every 6 bits. The read circuit 41 is electrically connected to the six output lines. The read circuit 41 includes switches 43S, 44S, and 45S that are electrically connected to the six output lines respectively.

[0161] The switches 43S to 45S have a plurality of transistors. The gate of the transistor included in the switch 43S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in the switch 44S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in the switch 45S is electrically connected to the wiring CSEL[2].

[0162] The output-side wirings of the switches 43S to 45S are electrically connected to one output line OUT (OUT[0] to OUT[5]) every three. With this configuration, arithmetic data can be output every 6 bits.

[0163] Note that the register 51, the register 52, and the read circuit 41 can be provided in the layer 20 as elements of the circuit 35 or the circuit 36 shown in FIG. 1.

[0164] FIG. 18B is a timing chart for explaining the reading of the arithmetic data stored in the register 52. It is assumed that all the arithmetic data (for 18 bits) is held in the register 52 before the time T1. In the following description, the potential (high potential) that makes the transistor conductive is expressed as “H”, and the potential (low potential) that makes the transistor non-conductive is expressed as “L”.

[0165] When the potential of the wiring CSEL[0] is set to “H” at the time T1, the switch 43S whose gate is electrically connected to the wiring CSEL[0] conducts, and the first 6-bit arithmetic data is output to the output lines OUT[0] to OUT[5].

[0166] When the potential of wiring CSEL[0] is set to "L" and the potential of wiring CSEL[1] is set to "H" at time T2, switch 43S becomes non-conductive, and switch 44S with its gate electrically connected to wiring CSEL[1] becomes conductive, and the second 6-bit arithmetic data different from the first data is output to output lines OUT[0] to OUT[5].

[0167] When the potential of wiring CSEL[1] is set to "L" and the potential of wiring CSEL[2] is set to "H" at time T3, switch 44S becomes non-conductive, and switch 45S with its gate electrically connected to wiring CSEL[2] becomes conductive, and the third 6-bit arithmetic data different from the first and second data is output to output lines OUT[0] to OUT[5].

[0168] Here, it is assumed that storing 54-bit arithmetic data in register 51 is performed in the first clock, storing the first 9-bit arithmetic data in register 52 is performed in the second clock, and storing the second 9-bit arithmetic data in register 52 is performed in the third clock. Then, if reading the first 6-bit arithmetic data from register 52 is performed in the fourth clock, reading the second 6-bit arithmetic data is performed in the fifth clock, and reading the third 6-bit arithmetic data is performed in the sixth clock, all operations can be completed in 6 clocks.

[0169] The operations in the first to third clocks and the operations in the fourth to sixth clocks can be parallel operations. If the period from time T1 to time T2 in the timing chart shown in Fig. 18B corresponds to the fourth clock, the period from time T2 to time T3 corresponds to the fifth clock, and the period from time T3 to time T4 corresponds to the sixth clock, then at time T4 to time T7, the next 18-bit arithmetic data can be read. Also, at time T7 to time T10, the next 18-bit arithmetic data can be read.

[0170] In addition, the operation of reading out the calculation data from the pixel block 12 in the first and second embodiments corresponds to an operation of stride 3, and the pooling process is omitted, but the calculation data may be further compressed by performing the pooling process.

[0171] According to one embodiment of the present invention described in this embodiment, an imaging device which has an image processing function and can operate at high speed can be provided.

[0172] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0173] (Embodiment 3) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0174] <Structure example> FIG. 19A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0175] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 20A. Note that the layer may be referred to as a region in some cases.

[0176] 20A is a pn junction photodiode, and may use, for example, a p-type semiconductor for the layer 565a and an n-type semiconductor for the layer 565b. Alternatively, the layer 565a may be an n-type semiconductor, and the layer 565b may be a p-type semiconductor.

[0177] The pn junction photodiode can be typically formed using single crystal silicon. A photodiode using single crystal silicon as a photoelectric conversion layer has a relatively wide spectral sensitivity characteristic from ultraviolet light to near infrared light, and can detect light of various wavelengths by combining it with an optical conversion layer described later.

[0178] Alternatively, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode. Examples of the compound semiconductor include gallium arsenic phosphide (GaAsP), gallium phosphide (GaP), indium gallium arsenide (InGaAs), lead sulfur compound (PbS), lead selenium compound (PbSe), indium arsenide compound (InAs), indium antimony compound (InSb), and mercury cadmium telluride compound (HgCdTe).

[0179] The compound semiconductor is preferably a compound semiconductor having a Group 13 element (aluminum, gallium, indium, etc.) and a Group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.) (also called a Group 3-5 compound semiconductor), or a compound semiconductor having a Group 12 element (magnesium, zinc, cadmium, mercury, etc.) and a Group 16 element (oxygen, sulfur, selenium, tellurium, etc.) (also called a Group 2-6 compound semiconductor).

[0180] Compound semiconductors allow the band gap to be changed depending on the combination of constituent elements and their atomic ratios, making it possible to form photodiodes that are sensitive to a wide range of wavelengths, from ultraviolet light to infrared light.

[0181] In addition, the wavelength of ultraviolet light can generally be defined as being around 0.01 μm to around 0.38 μm, the wavelength of visible light as being around 0.38 μm to around 0.75 μm, the wavelength of near-infrared light as being around 0.75 μm to around 2.5 μm, the wavelength of mid-infrared light as being around 2.5 μm to around 4 μm, and the wavelength of far-infrared light as being around 4 μm to around 1000 μm.

[0182] For example, to form a photodiode having photosensitivity from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from ultraviolet light to near infrared light, silicon or GaAsP or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from near infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.

[0183] The photodiode using the compound semiconductor may have a pin junction instead of a pn junction. The pn junction and the pin junction are not limited to a homojunction structure, and may have a heterojunction structure.

[0184] For example, in a heterojunction, a first compound semiconductor can be used in one layer of a pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the other layer. Also, a first compound semiconductor can be used in one or two layers of a pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the remaining layers. Either the first compound semiconductor or the second compound semiconductor can be a simple semiconductor such as silicon.

[0185] Note that the photoelectric conversion layer of the photodiode may be formed using a different material for each pixel. By using this configuration, an imaging device having two or three types of pixels, such as pixels that detect ultraviolet light, pixels that detect visible light, and pixels that detect infrared light, can be formed.

[0186] Furthermore, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 566a, 566b, 566c, and 566d, as shown in Fig. 20B. The photoelectric conversion device 101 shown in Fig. 20B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0187] Layer 566a is preferably a low resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0188] The layer 566d is preferably a conductive layer having a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0189] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material that is a p-type semiconductor, and the layer 566c is made of gallium oxide or the like that is an n-type semiconductor.

[0190] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In such photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. In addition, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production in that the photoelectric conversion layer can be made as a thin film. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering methods.

[0191] As selenium-based materials, crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium can be used. These have photosensitivity from ultraviolet light to visible light. In addition, compounds of copper, indium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used. These have photosensitivity from ultraviolet light to near infrared light.

[0192] The n-type semiconductor is preferably made of a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer, and can reduce dark current.

[0193] Furthermore, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e, as shown in Fig. 20C. The photoelectric conversion device 101 shown in Fig. 20C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0194] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0195] For the hole transport layer, for example, molybdenum oxide can be used. For the electron transport layer, for example, C 60 , C 70 or derivatives thereof can be used.

[0196] The photoelectric conversion layer can be a mixed layer (bulk heterojunction structure) of n-type organic semiconductor and p-type organic semiconductor. There are various types of organic semiconductors, and it is sufficient to select a material that has photosensitivity to the desired wavelength for the photoelectric conversion layer.

[0197] For example, a silicon substrate can be used as the layer 563 shown in FIG. 19A. The silicon substrate has Si transistors and the like. Using the Si transistors, in addition to pixel circuits, circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, and the like can be formed. Also, memory circuits such as DRAMs (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), and the like may be formed. In this embodiment, the above circuits excluding the pixel circuits are called functional circuits.

[0198] For example, some or all of the transistors included in the functional circuits (such as the calculation unit 21, row driver 31, column driver 32, row driver 33, column driver 34, circuit 35, circuit 36, etc.) provided in layer 20 described in embodiment 1 can be provided in layer 563.

[0199] Also, the layer 563 may be a laminate of multiple layers as shown in FIG. 19B. Although FIG. 19B illustrates three layers, 563a, 563b, and 563c, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and the functional circuits can be distributed among multiple layers and the pixel circuits and the functional circuits can be stacked, so that a small-sized, highly functional imaging device can be manufactured.

[0200] Alternatively, the pixel may have a stacked structure of a layer 561, a layer 562, and a layer 563 as shown in FIG. 19C.

[0201] The layer 562 corresponds to the layer 10 described in Embodiment 1 and can include an OS transistor. One or more of the functional circuits described above may be formed using an OS transistor. Alternatively, one or more of the functional circuits may be formed using a Si transistor included in the layer 563 and an OS transistor included in the layer 562. Alternatively, the layer 563 may be used as a supporting substrate such as a glass substrate, and a pixel circuit and a functional circuit may be formed using the OS transistor included in the layer 562.

[0202] For example, a normally-off CPU (also referred to as an "NoffCPU (registered trademark)") can be realized using OS transistors and Si transistors. Note that an NoffCPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when the gate voltage is 0 V.

[0203] The NoffCPU can stop the power supply to circuits in the NoffCPU that are not required to operate, and put the circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the NoffCPU can minimize power consumption. The NoffCPU can also retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite the setting conditions, etc. In other words, high-speed return from the standby state is possible. In this way, the NoffCPU can reduce power consumption without significantly reducing the operating speed.

[0204] Also, layer 562 may be a laminate of multiple layers as shown in Fig. 19D. Although two layers, layers 562a and 562b, are illustrated in Fig. 19D, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 and a layer formed on layer 561.

[0205] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal, and is suitable for transistors that emphasize reliability. In addition, CAC-OS has high mobility characteristics, and is suitable for transistors that operate at high speed.

[0206] OS transistors have a large energy gap in the semiconductor layer, and therefore exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm of channel width). OS transistors also have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short channel effects, and can form highly reliable circuits with high voltage resistance. OS transistors are also less susceptible to variations in electrical characteristics caused by non-uniformity in crystallinity, which is a problem with Si transistors.

[0207] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn oxide can be typically formed by a sputtering method. Alternatively, it may be formed by an ALD (atomic layer deposition) method.

[0208] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide by the sputtering method preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0209] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Less than 1×10, more preferably 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Less than 1×10, more preferably 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above oxide semiconductors can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and has stable characteristics.

[0210] Note that the composition is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0211] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase and the semiconductor layer becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0212] In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0213] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons that act as carriers are generated, which increases the carrier density and makes the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0214] Furthermore, when hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0215] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration rather than its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor rather than a donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration".

[0216] Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0217] The semiconductor layer may have a non-single crystal structure. The non-single crystal structure includes, for example, a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0218] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or has, for example, a completely amorphous structure and does not include a crystalline portion.

[0219] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0220] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single crystal semiconductor layer.

[0221] CAC-OS is, for example, a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

[0222] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0223] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y 4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0224] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0225] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0226] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0227] On the other hand, CAC-OS is a material composition of oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly distributed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0228] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0229] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0230] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0231] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, for example, 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0232] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0233] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0234] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0235] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0236] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is expressed. X2 Zinc Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0237] On the other hand, GaO X3 The region where the main components are In X2Zinc Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing these as main components is distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved.

[0238] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0239] In addition, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0240] <Laminated structure 1> Next, the laminated structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Alternatively, some of the elements shown below may be omitted. Also, the laminated structure shown below can be formed using a bonding process, a polishing process, etc., as necessary.

[0241] FIG. 21 is an example of a cross-sectional view of a laminate having layers 560, 561, and 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0242] <layer 563b> Layer 563b can have functional circuits provided on silicon substrate 611. Here, as some of the transistors included in the functional circuits, transistors 223, 224, and 225 are shown. Note that transistor 225 is exemplified as a transistor included in binarization circuit 22.

[0243] Silicon substrate 611, insulating layers 612, 613, 614, 616, 617, and 618 are provided on layer 563b. Insulating layer 612 has a function as a protective film. Insulating layers 613, 614, 616, and 617 have functions as interlayer insulating films and planarization films. Insulating layer 618 and conductive layer 619 have functions as bonding layers. Conductive layer 619 is electrically connected to the gate of transistor 225.

[0244] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarization film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. The bonding layer will be described later.

[0245] Note that as the conductors that can be used as wirings, electrodes, and plugs for electrical connection between devices, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys containing the above-described metal elements as components, or alloys combining the above-described metal elements, etc. may be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers composed of different materials.

[0246] <Layer 563a> The layer 563a includes elements of the pixel 14. It may also include elements of a functional circuit. Here, the transistor 102 and the transistor 105 included in the pixel circuit 15 are shown as some of the elements of the pixel 14. In the cross-sectional view shown in FIG. 21, electrical connection between them is not shown.

[0247] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638, and conductive layers 636 and 639.

[0248] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 and the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. The insulating layer 638 may be formed of the same material as the insulating layer 631.

[0249] The conductive layer 639 is electrically connected to the other of the source and the drain of the transistor 105 and the conductive layer 619. In addition, the conductive layer 636 is electrically connected to the wiring 111 (see FIG. 10A).

[0250] The Si transistor shown in Fig. 21 is a fin type having a channel formation region in a silicon substrate (silicon substrates 611 and 632). A cross section in the channel width direction (a cross section of A1-A2 shown in layer 563a in Fig. 21) is shown in Fig. 22A. The Si transistor may be a planar type as shown in Fig. 22B.

[0251] 22C, it may be a transistor having a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 632.

[0252] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 21 shows a configuration in which the organic photoconductive film shown in Fig. 20C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Here, the layer 567a is a cathode, and the layer 567e is an anode.

[0253] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655.

[0254] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101, and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. It is preferable to use an organic insulating film or the like as the element isolation layer.

[0255] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 included in the layer 563a through the conductive layer 655.

[0256] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0257] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

[0258] When the photoelectric conversion device 101 has sensitivity to visible light, a color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel. For example, as shown in the perspective view (including the cross section) of FIG. 31A, a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to each different pixel.

[0259] Furthermore, in a suitable combination of the photoelectric conversion device 101 and the optical conversion layer 672, by using a wavelength cut filter in the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0260] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths equal to or shorter than visible light in the optical conversion layer 672. A far-infrared imaging device can be formed by using a filter that blocks light with wavelengths equal to or shorter than near-infrared light in the optical conversion layer 672. An ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths equal to or longer than visible light in the optical conversion layer 672.

[0261] In addition, a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 31B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0262] 31C, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0263] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 101. An imaging device having such a configuration may also be used for a radiation detector or the like.

[0264] Scintillators contain materials that absorb the energy of radiation, such as X-rays or gamma rays, and emit visible or ultraviolet light when irradiated with the radiation. For example, Gd 2 O 2 S: Tb, Gd 2 O 2 S: Pr, Gd 2 O 2 S:Eu, BaFCl:Eu, NaI, CsI, CaF 2 , BaF 2 , CeF 3 , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0265] By imaging with infrared or ultraviolet light, it is possible to provide the imaging device with an inspection function, a security function, a sensor function, etc. For example, by imaging with infrared light, it is possible to perform non-destructive inspection of produce, sorting of agricultural products (such as a sugar content meter function), vein authentication, medical testing, etc. Furthermore, by imaging with ultraviolet light, it is possible to detect ultraviolet light emitted from a light source or flame, and it is possible to manage light sources, heat sources, production equipment, etc.

[0266] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below, and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass that is highly translucent to light of the target wavelength.

[0267] <Lamination> Next, the bonding of the layer 563b and the layer 563a will be described.

[0268] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0269] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0270] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0271] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferably used because of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0272] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded to each other at a boundary between them.

[0273] The conductive layers 619 and 639 may have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0274] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Also, it makes it possible to obtain a connection between the insulating layer 618 and the insulating layer 631 that has sufficient mechanical strength.

[0275] To bond metal layers together, a surface activation bonding method can be used, in which oxide films and adsorbed layers of impurities on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0276] In addition, for bonding insulating layers, a hydrophilic bonding method can be used in which high flatness is achieved by polishing, etc., and then the surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them through heat treatment. Hydrophilic bonding also produces bonds at the atomic level, and therefore can provide mechanically excellent bonds.

[0277] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0278] For example, a method of cleaning the surface after polishing, subjecting the surface of the metal layer to an anti-oxidation treatment, and then subjecting it to a hydrophilic treatment and bonding can be used. The surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0279] By the above-mentioned bonding, the circuit included in the layer 563b and the element of the pixel 14 included in the layer 563a can be electrically connected to each other.

[0280] <Modification of Laminate Structure 1> FIG. 23 shows a modified example of the stacked structure shown in FIG. 21, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and a bonding surface is also provided between the layer 561 and the layer 563a.

[0281] Layer 561 includes photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers 685,686.

[0282] The photoelectric conversion device 101 is a pn junction type photodiode, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example is shown in which a pn junction type photodiode is formed on a silicon substrate. The photoelectric conversion device 101 is a buried type photodiode, and a thin p-type region (part of layer 565b) provided on the surface side (current extraction side) of layer 565a can suppress dark current and reduce noise.

[0283] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer.

[0284] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to prevent carriers generated in the photoelectric conversion device 101 from flowing out to adjacent pixels. The insulating layer 665 also has a function of preventing the intrusion of stray light. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0285] The insulating layer 664 can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin can be used as the insulating layer 665. The insulating layer 665 may have a multi-layer structure. A space may be provided in a part of the insulating layer 665. The space may contain a gas such as air or an inert gas. The space may be in a reduced pressure state.

[0286] A layer 565a (n-type region, corresponding to a cathode) of the photoelectric conversion device 101 is electrically connected to a conductive layer 685. A layer 565b (p-type region, corresponding to an anode) is electrically connected to a conductive layer 686. The conductive layers 685 and 686 have regions embedded in an insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0287] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. In addition, a conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0288] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have a region buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0289] Here, the conductive layers 683, 684, 685, and 686 are the same bonding layers as the above-mentioned conductive layers 619 and 639. The insulating layers 638 and 661 are the same bonding layers as the above-mentioned insulating layers 618 and 631.

[0290] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 111 (see FIG. 10A). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 563a.

[0291] 24 shows a modified example different from the above, in which the transistor 102 is provided in a layer 561. In this configuration, one of the source and the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and the drain acts as a node N. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred, and an imaging device with low noise can be obtained.

[0292] Here, the other of the source and the drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692. The gate of the transistor 104 included in the layer 563 is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0293] <Laminated structure 2> FIG. 25 is an example of a cross-sectional view of a laminate having layers 560, 561, 562, 563 and no bonding surface. An Si transistor is provided in layer 563. An OS transistor is provided in layer 562. Note that since the configurations of layer 563, layer 561, and layer 560 are the same as those shown in FIG. 21, description thereof is omitted here.

[0294] <Layer 562> Layer 562 is formed over layer 563. Layer 562 has an OS transistor. Here, transistors 102 and 105 are shown. In the cross-sectional view shown in FIG. 25, the electrical connection between the two is not illustrated.

[0295] Insulating layers 621, 622, 623, 624, 625, 626, 628 are provided in layer 562. In addition, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to wiring 111 (see FIG. 10A).

[0296] Insulating layer 621 has a function as a blocking layer. Insulating layers 622, 623, 625, 626, 628 have functions as an interlayer insulating film and a planarization film. Insulating layer 624 has a function as a protective film.

[0297] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In an Si device, hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of the OS transistor becomes one of the factors for generating carriers in the oxide semiconductor layer and deteriorates reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0298] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

[0299] The other of the source and the drain of the transistor 105 is electrically connected to the gate of the transistor 225 through a plug. In addition, the conductive layer 627 is electrically connected to the wiring 111 (see FIG. 10A).

[0300] One of the source and the drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561.

[0301] Fig. 26A shows details of an OS transistor. The OS transistor shown in Fig. 26A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0302] The OS transistor can have a structure including a channel formation region 708, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0303] As shown in FIG. 26B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0304] Alternatively, as shown in FIG. 26C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0305] Although the OS transistor has a back gate 735, it may have a structure without a back gate. The back gate 735 may be electrically connected to the front gate of the transistor provided opposite to the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in Fig. 26D. Note that Fig. 26D shows the cross section of the transistor taken along line B1-B2 in Fig. 26A as an example, but the same applies to transistors having other structures. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 735.

[0306] <Modification of Laminate Structure 2> FIG. 27 shows a modified example of the stacked structure shown in FIG. 25, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and a portion of the configuration of the layer 562 are different, and a bonding surface is provided between the layers 561 and 562.

[0307] The photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode, and has the same configuration as that shown in FIG.

[0308] In the layer 562, an insulating layer 648 is formed over the insulating layer 628. In addition, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0309] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have a region buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 688 and 689 are flattened so that they are at the same height.

[0310] Here, the conductive layers 688 and 689 are the same lamination layer as the above-mentioned conductive layers 619 and 639. The insulating layer 648 is the same lamination layer as the above-mentioned insulating layers 618 and 631.

[0311] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 111 (see FIG. 10A). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 562.

[0312] When stacking multiple Si devices, the polishing and bonding processes are required multiple times. This poses issues such as a large number of steps, the need for dedicated equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking on a semiconductor substrate on which devices are already formed, eliminating the need for the bonding process.

[0313] Note that the structure in which the transistor 102 is provided in the layer 561 shown in FIG. 24 may be applied to this structure.

[0314] 28 shows a configuration in which transistors 102, 105, etc., which are elements of a pixel circuit, and a transistor 278 and a capacitor 279, which are elements of a memory cell 150, are provided in a layer 563a. In this case, the transistors of the memory cell 150 can be formed of Si transistors. If the combination of the transistor 271 and the capacitor 274 of the memory cell 150a shown in FIG. 11B is used as the transistor 278 and the capacitor 279, it can be operated as a DRAM. If the combination of the transistor 276 and the capacitor 277 of the memory cell 150d shown in FIG. 12B or FIG. 12C is used as the transistor 278 and the capacitor 279, it can be operated as a ferroelectric memory.

[0315] Also, the memory cell 150 can be provided in a layer 562 having an OS transistor. FIG. 29 shows a configuration in which transistors 102, 105, etc., which are elements of a pixel circuit, and a transistor 278 and a capacitor 279, which are elements of the memory cell 150, are provided on the same surface of the layer 562. If the combination of the transistor 271 and the capacitor 274 of the memory cell 150a shown in FIG. 11B is used as the transistor 278 and the capacitor 279, it can be operated as a DOSRAM. If the combination of the transistor 276 and the capacitor 277 of the memory cell 150d shown in FIG. 12B or FIG. 12C is used as the transistor 278 and the capacitor 279, it can be operated as a ferroelectric memory.

[0316] 30 shows a structure in which transistors 102, 104, 105, etc., which are elements of a pixel circuit, are stacked in a layer 562 so as to have an overlapping region with transistors 272, 273, etc., which are elements of a memory cell 150b shown in FIG. 11C or a memory cell 150c shown in FIG. 11D. This structure can reduce the circuit area and form a high-performance, small-sized imaging device. In addition, the length of the wiring electrically connecting the stacked elements can be shortened, enabling high-speed operation with low power consumption.

[0317] 29 and 30 may be applied to the structure in which the transistor 102 is provided in the layer 561 shown in Fig. 24. Also, the structure of the photoelectric conversion device 101 shown in Fig. 25 may be applied.

[0318] <Package, module> 32A is a perspective view of the exterior of a package containing an image sensor chip. The package is a CSP (Chip Size Package), and includes an image sensor bare chip 450, a cover glass 440, and an adhesive 430 for bonding the two together.

[0319] An electrode pad 425 provided on the outside of the pixel array 455 is electrically connected to the back electrode 415 via a through electrode 420. The electrode pad 425 is electrically connected to a circuit constituting the image sensor by wiring or wires. The bare chip 450 may be a laminated chip in which circuits having various functions are laminated.

[0320] 32 shows a BGA (Ball Grid Array) in which bumps 410 are formed by solder balls on rear surface electrodes 415. The present invention is not limited to BGA, and may be LGA (Land Grid Array) or PGA (Pin Grid Array). Alternatively, a package in which bare chip 450 is mounted on QFN (Quad Flat No-lead package) or QFP (Quad Flat Package) may be used.

[0321] 32B is a perspective view of the top surface of a camera module in which an image sensor chip and a lens are combined. The camera module has a lens cover 460, a plurality of lenses 470, and the like on the configuration of FIG. 32A. An optical filter 480 that absorbs light of a specific wavelength is provided between the lens 470 and the cover glass 440 as necessary. For example, an infrared cut filter can be used as the optical filter 480 in the case of an image sensor that mainly captures visible light.

[0322] By housing the image sensor chip in a package of the above-mentioned type, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0323] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0324] (Embodiment 4) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in Figures 33A to 33F.

[0325] 33A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the mobile phone.

[0326] 33B shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919, and the characters can be output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal.

[0327] FIG. 33C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and the like, and can capture images of the entire surroundings by installing it on the ceiling. The imaging device and its operating method according to one embodiment of the present invention can be applied to the elements for acquiring images in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0328] 33D shows a drive recorder, which includes a frame 941, a camera 942, an operation button 943, and an attachment part 944. By installing the drive recorder on the front window of a vehicle via the attachment part 944, the view ahead while the vehicle is traveling can be recorded. Note that a display panel that displays recorded images is provided on the back side (not shown). The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to the camera 942.

[0329] 33E shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this digital camera.

[0330] 33F shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal.

[0331] 34A shows a drone, which is an example of a moving object, and includes a frame 921, an arm 922, a rotor 923, a blade 924, a camera 925, and a battery 926, and has a function of flying autonomously, a function of remaining stationary in the air, etc. The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to the camera 925.

[0332] FIG. 34B illustrates an external view of an automobile as an example of a moving object. The automobile 890 has a plurality of cameras 891 and the like, and can acquire information on the front, rear, left, right, and above the automobile 890. The imaging device and its operation method according to one embodiment of the present invention can be applied to the camera 891. The automobile 890 also includes various sensors (not shown), such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 890 can analyze images acquired by the camera 891 in a plurality of imaging directions 892, determine surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and perform automatic driving. The automobile 890 can also be used in a system that performs road guidance, hazard prediction, and the like.

[0333] In the imaging device of one embodiment of the present invention, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0334] In the above description, the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen automobile, and the like. The moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle, airplane, rocket), and the like. The computer according to one embodiment of the present invention may be applied to these moving objects to provide a system using artificial intelligence. [Explanation of symbols]

[0335] 10: layer, 11: pixel section, 12: pixel block, 13: pixel block, 14: pixel, 15: pixel circuit, 16: memory circuit, 20: layer, 21: calculation section, 22: binarization circuit, 23: product-sum calculation circuit, 23a: multiplier, 23b: adder, 24: binarization circuit, 24S: selection transistor, 25: circuit, 26a: addition circuit, 26b: binarization circuit, 31: row driver, 32: column driver, 33: row driver, 34: column driver, 35: circuit, 36: circuit, 37: circuit, 40: circuit, 40S: switch, 41: circuit, 41S: switch, 42S: switch, 4 3S: switch, 44S: switch, 45S: switch, 51: register, 52: register, 60: circuit, 71: curve, 72: curve, 101: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: capacitor, 107: transistor, 108: transistor, 109: transistor, 111: wiring, 112: wiring, 113: wiring, 114: wiring, 115: wiring, 116: wiring, 117: wiring, 118: wiring, 119: wiring, 150: memory cell, 150a: memory cell, 150b: Memory cell, 150c: memory cell, 150d: memory cell, 170: back gate wiring, 175: metal oxide layer, 180: source-drain wiring, 185: gate wiring, 190: wiring, 223: transistor, 224: transistor, 225: transistor, 271: transistor, 272: transistor, 273: transistor, 274: capacitor, 275: capacitor, 276: transistor, 277: capacitor, 278: transistor, 279: capacitor, 410: bump, 415: back electrode, 420: through electrode, 425: electrode pad, 430: adhesive, 440: cover glass, 450: bare chip, 455: pixel array, 460: lens cover, 470: lens, 480: optical filter, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 562b: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer,614: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: Insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light shielding layer, 672: optical conversion layer, 672B: color filter, 672G: color filter, 672IR: infrared filter, 672R: color filter, 672UV: ultraviolet filter, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 691: conductive layer, 692: Conductive layer, 701: Gate electrode, 702: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 708: Channel formation region, 735: Back gate, 890: Automobile, 891: Camera, 892: Imaging direction, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Frame, 922: Arm, 923: Rotor, 924: Blade, 925: Camera, 9 26: battery, 932: display unit, 933: housing / wristband, 939: camera, 941: frame, 942: camera, 943: operation button, 944: parts, 951: support stand, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

1. An imaging device having a plurality of pixel blocks, The pixel block has a first layer and a second layer, the first layer has an area overlapping with the second layer, The pixel block is The first layer includes a plurality of pixel circuits and a plurality of first memory circuits, the second layer includes a plurality of product-sum circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits; the pixel circuit and the first memory circuit each include a transistor having a metal oxide in a channel formation region, the first memory circuit has a memory cell; The memory cell includes a capacitor having a ferroelectric layer.

2. An imaging device having a plurality of pixel blocks, the pixel block has a first layer, a second layer, and a third layer; the first layer is located between the second layer and the third layer, or the third layer is located between the first layer and the second layer; the first layer, the second layer, the third layer, and the like have overlapping regions; The pixel block is The first layer has a plurality of pixel circuits, the second layer includes a plurality of product-sum circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits; the third layer includes a plurality of first memory circuits; the pixel circuit and the first memory circuit each include a transistor having a metal oxide in a channel formation region, the first memory circuit has a memory cell; The memory cell includes a capacitor having a ferroelectric layer.

3. In claim 1 or 2, The product-sum operation circuit, the first binarization circuit, and the second binarization circuit each include a transistor having silicon in a channel formation region.

4. In any one of claims 1 to 3, the number of the pixel circuits and the number of the first binarization circuits are the same; an imaging device, wherein the pixel circuit is electrically connected to one of the first binarization circuits;

5. In any one of claims 1 to 4, an imaging device, wherein one of the first binarization circuits is electrically connected to the plurality of product-sum calculation circuits;

6. In any one of claims 1 to 5, an imaging device, wherein one of the first memory circuits is electrically connected to the plurality of product-sum calculation circuits;

7. In any one of claims 1 to 6, the number of the multiply-and-accumulate circuits is the same as the number of the second binarization circuits; an imaging device, wherein one of the multiply-accumulate circuits is electrically connected to one of the second binarization circuits;

8. In any one of claims 1 to 7, A drive circuit for the pixel circuit and a drive circuit for the first memory circuit are provided in the second layer.

9. In any one of claims 1 to 8, a second memory circuit; an input terminal of the second storage circuit is electrically connected to a plurality of the second binarization circuits; an output terminal of the second memory circuit electrically connected to the plurality of product-sum calculation circuits;

10. In claim 9, a third memory circuit and a third binarization circuit; the third storage circuit is electrically connected to the plurality of product-sum calculation circuits via the third binarization circuit.

11. In claim 10, The imaging device, wherein the second memory circuit, the third memory circuit, and the third binarization circuit are provided in the second layer.

12. In any one of claims 1 to 11, The metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

13. An electronic device comprising: the imaging device according to claim 1 ; and a display device.

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