Light emitting package

Abstract

The light emitting package includes: a first LED subunit having opposing first and second surfaces; a second LED subunit arranged on the second surface of the first LED subunit; a third LED subunit arranged on the second LED subunit; a plurality of connection electrodes having side surfaces and electrically connected to at least one of the first, second, and third LED subunits, the connection electrodes covering the side surfaces of at least one of the first, second, and third LED subunits; a first passivation layer surrounding at least the side surfaces of the connection electrodes, the first passivation layer exposing at least a portion of the first surface of the first LED subunit; a substrate having opposing first and second surfaces, the first surface facing the plurality of LED subunits; and a first electrode arranged on the first surface of the substrate and connected to at least one of the connection electrodes.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Exemplary embodiments of the present invention relate to a light-emitting chip for a display and a manufacturing method thereof, and more particularly to a micro light-emitting chip having a stacked structure and a manufacturing method thereof. [Background technology]

[0002] Light-emitting diodes (LEDs), which are inorganic light sources, are used in a variety of technical fields, including displays, automotive lamps, general lighting, etc. Light-emitting diodes have features such as long life, low power consumption, and high responsiveness, and are rapidly becoming more and more popular as replacements for existing light sources.

[0003] Light-emitting diodes have been used primarily as a backlight source for display devices, but recently micro-LED displays have been developed that can directly display images using light-emitting diodes.

[0004] Typically, a display device uses mixtures of blue, green and red light to achieve various colors. The display device includes pixels having sub-pixels corresponding to the colors blue, green and red, the color of a pixel is determined based on the color of its sub-pixels, and images can be displayed by selectively activating combinations of pixels.

[0005] Since LEDs can emit various colors depending on the material they are made of, displays can usually have individual LED chips that emit blue, green, and red light arranged on a two-dimensional plane. However, if one LED chip is provided for each subpixel, the number of LED chips required to form a display device can be very large, for example, hundreds of thousands or even millions, and the mounting work can be very time-consuming and labor-intensive. Furthermore, since the subpixels are arranged on a two-dimensional plane of the display device, a relatively large area is required for one pixel, including the subpixels for blue, green, and red light, and there is a problem that the brightness of the subpixels deteriorates if the light-emitting area of ​​each subpixel is reduced.

[0006] In addition, micro LEDs are typically very small, with a surface area of ​​approximately 10,000 square micrometers or less, which causes various technical problems. For example, an array of micro LEDs may be formed on a substrate, and the substrate may be cut to singulate the micro LEDs into individual micro LED chips. The micro LED chips may then be mounted on another substrate, such as a printed circuit board, using various transfer techniques. However, during these transfer steps, each micro LED chip is typically difficult to handle due to its small size and fragile structure. In addition, the electrodes formed on the substrate, such as a display device, are typically spaced from each other at a pitch that corresponds to the pitch of the electrodes of a conventional pixel, in which multiple subpixels are arranged on a two-dimensional plane.

[0007] The above information disclosed in this Background is intended solely to provide an understanding of the background of the inventive concept, and may therefore contain information that is not prior art. Summary of the Invention [Problem to be solved by the invention]

[0008] Light emitting chips constructed in accordance with the principles of the present invention and some exemplary embodiments can protect the light emitting stack during various transfer processes.

[0009] Light emitting chips, such as micro LEDs, and displays using the same constructed according to the principles of the present invention and some exemplary embodiments thereof have a simplified structure and can shorten the time of the mounting process during manufacturing.

[0010] Light emitting chips, such as micro LEDs, constructed in accordance with the principles of the present invention and some exemplary embodiments have an enhanced internal structure that facilitates handling and transport, and can be implemented into conventional display devices.

[0011] Light emitting chips, such as micro LEDs, constructed in accordance with the principles of the present invention and some exemplary embodiments have an enhanced internal structure that facilitates handling and transport, and can be implemented into conventional display devices.

[0012] Light emitting packages, e.g., micro LEDs, constructed in accordance with the principles of the present invention and certain exemplary embodiments have improved light efficiency and color purity achieved by removing a substrate of the light emitting stack, such as the growth substrate of one of the LED stacks.

[0013] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the inventive concepts. [Means for solving the problem]

[0014] A light emitting package according to an exemplary embodiment includes a first LED subunit having opposing first and second surfaces, a second LED subunit disposed on the second surface of the first LED subunit, a third LED subunit disposed on the second LED subunit, a plurality of connection electrodes having side surfaces and electrically connected to at least one of the first, second, and third LED subunits, the connection electrodes covering at least one side surface of the first, second, and third LED subunits, a first passivation layer surrounding at least side surfaces of the connection electrodes, the first passivation layer exposing at least a portion of a first surface of the first LED subunit, a substrate having opposing first and second surfaces, the first surface facing the plurality of LED subunits, and a first electrode disposed on the first surface of the substrate and connected to at least one of the connection electrodes.

[0015] The plurality of connection electrodes may overlap at least one of the first, second and third LED subunits.

[0016] The light emitting package may further include a second passivation layer in contact with at least some side surfaces of the plurality of connecting electrodes.

[0017] The second passivation layer may be disposed between the plurality of connecting electrodes.

[0018] The first passivation layer may include at least one of a black epoxy molding compound and a polyimide film.

[0019] The first electrode may include a plurality of contact electrodes, each spaced apart from one another by a first distance and corresponding to one of the plurality of connection electrodes, and the light emitting package may further include a plurality of second electrodes disposed on the second surface of the substrate, each of the plurality of second electrodes being spaced apart from one another by a second distance and connected to a respective one of the plurality of contact electrodes, and the second distance may be greater than the first distance.

[0020] The first passivation layer and the second passivation layer may comprise different materials.

[0021] The first LED subunit may include a first LED light emitting stack, the second LED subunit may include a second LED light emitting stack, and the third LED subunit may include a third LED light emitting stack, the first, second and third LED light emitting stacks may have successively smaller areas overlapping the substrate, and at least one of the LED light emitting stacks may include a micro LED having a surface area of ​​less than about 10,000 square microns.

[0022] The LED may further include a second passivation layer disposed between the plurality of connecting electrodes and the third LED subunit, and an angle defined between a side of the second passivation layer and a first surface of the first LED subunit may be less than approximately 80°.

[0023] At least one of the plurality of connection electrodes may cover at least a side surface and an upper surface of the second passivation layer.

[0024] A light emitting package according to an exemplary embodiment includes a first LED subunit having opposing first and second surfaces, a second LED subunit disposed on the second surface of the first LED subunit, a third LED subunit disposed on the second LED subunit, a plurality of connection electrodes having side surfaces and electrically connected to at least one of the first, second, and third LED subunits, the plurality of connection electrodes covering at least one side surface of the first, second, and third LED subunits, a first passivation layer surrounding at least side surfaces of the plurality of connection electrodes and having a portion covering at least a portion of the first surface of the first LED subunit, a substrate having opposing first and second surfaces, the first surface facing the plurality of LED subunits, and a first electrode disposed on the first surface of the substrate and connected to at least one of the plurality of connection electrodes.

[0025] The portion of the first passivation layer covering the first face of the first LED subunit may have a thickness of less than about 100 μm.

[0026] The first passivation layer may contact the first surface of the first LED subunit.

[0027] The light emitting package may further include a second electrode disposed on the second surface of the substrate and connected to the first electrode, and the second electrode may include a first portion overlapping at least one of the plurality of LED subunits and having a first area, and a second portion not overlapping at least one of the plurality of LED subunits and having a second area larger than the first area.

[0028] The light emitting package may further include a second passivation layer in contact with at least side surfaces of the plurality of connection electrodes.

[0029] The first passivation layer and the second passivation layer may comprise different materials.

[0030] At least one of the plurality of connection electrodes may be in contact with a side surface and an upper surface of the second passivation layer.

[0031] At least one of the plurality of connection electrodes may have an angular shape.

[0032] The first passivation layer may be disposed between the plurality of connecting electrodes.

[0033] At least one of the multiple connection electrodes has opposing first and second surfaces, the first surface may face the multiple LED subunits, and the first surface of the connection electrode may have an area larger than an area of ​​the second surface.

[0034] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. [Brief description of the drawings]

[0035] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and, together with the description, serve to explain the concepts of the invention.

[0036] [Figure 1] 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with an exemplary embodiment of the present invention; [Diagram 2] 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with another exemplary embodiment of the present invention. [Diagram 3] 1 is a schematic cross-sectional view of a light emitting stack constructed in accordance with an illustrative embodiment. [Figure 4A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 4B] 4B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 4A in accordance with an exemplary embodiment. [Figure 5A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 5B] 5B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 5A in accordance with an exemplary embodiment. [Figure 6A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 6B] 6B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 6A in accordance with an exemplary embodiment. [Figure 7A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 7B] 7B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 7A in accordance with an exemplary embodiment. [Figure 8A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 8B] 8B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 8A in accordance with an exemplary embodiment. [Figure 9A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 9B] 9B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 9A in accordance with an exemplary embodiment. [Figure 10A] 1A to 1C are schematic plan views illustrating a manufacturing process of a light emitting chip according to an exemplary embodiment. [Figure 10B] FIG. 10B is a schematic cross-sectional view taken along line AA' in FIG. 10A. [Figure 10C] FIG. 10B is a schematic cross-sectional view taken along line BB' in FIG. 10A. [Figure 11] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 12]2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 13] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 14] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 15] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 16] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 17] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps of the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 18] 3A-3C are schematic cross-sectional views illustrating a manufacturing process of the light emitting package of FIG. 2 according to another exemplary embodiment. [Figure 19] 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with an exemplary embodiment of the present invention; [Figure 20] 4 is a schematic cross-sectional view of a light emitting package constructed in accordance with another exemplary embodiment of the present invention. [Figure 21A] 11A to 11C are plan views illustrating a manufacturing process of a light-emitting chip according to another exemplary embodiment. [Figure 21B] 21B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 21A according to another exemplary embodiment. [Figure 22A] 11A to 11C are plan views illustrating a manufacturing process of a light-emitting chip according to another exemplary embodiment. [Figure 22B] 22B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 22A according to another exemplary embodiment. [Diagram 23] 5A to 5C are schematic cross-sectional views illustrating manufacturing steps of a light emitting package according to an exemplary embodiment. [Figure 24] 5A to 5C are schematic cross-sectional views illustrating manufacturing steps of a light emitting package according to an exemplary embodiment. [Diagram 25]It is a schematic cross-sectional view showing a process for manufacturing the light-emitting package of FIG. 19 according to an exemplary embodiment. [Figure 26] It is a schematic cross-sectional view showing a process for manufacturing the light-emitting package of FIG. 19 according to an exemplary embodiment. [Figure 27] It is a schematic cross-sectional view showing a process for manufacturing the light-emitting package of FIG. 19 according to an exemplary embodiment. [Figure 28] It is a schematic cross-sectional view showing a process for manufacturing the light-emitting package of FIG. 19 according to an exemplary embodiment. [Figure 29] It is a schematic cross-sectional view showing a process for manufacturing the light-emitting package of FIG. 19 according to an exemplary embodiment. [Diagram 30] It is a schematic cross-sectional view showing a process for manufacturing the light-emitting package of FIG. 20 according to another exemplary embodiment.

Mode for Carrying Out the Invention

[0037] In the following description, for the sake of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable terms that are non-limiting examples of an apparatus or method that employs one or more of the inventive concepts disclosed herein. However, it is clear that the various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Further, the various exemplary embodiments may be different but need not be exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept of the present invention.

[0038] Unless otherwise stated, the illustrated exemplary embodiments should be understood as providing illustrative features of various details of some of the ways in which the concepts of the present invention may be practically practiced. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be combined, separated, interchanged and / or rearranged in other manners without departing from the concepts of the present invention.

[0039] The use of cross-hatching and / or shading in the accompanying drawings is generally for clarifying boundaries between adjacent elements. As such, the use of cross-hatching or shading, whether or not present, is not intended to convey or indicate preferences or requirements for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements and / or other properties, attributes, characteristics, etc. of the elements, unless otherwise specified. Additionally, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or explanation purposes. When the exemplary embodiments may be implemented differently, certain processing sequences may be performed differently than described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the described order. Additionally, like reference numerals refer to like elements.

[0040] When an element, such as a layer, is described as being "on" or "connected" to another element or layer, it may be directly on, connected to, or connected to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is described as being "directly on" or "directly connected" to or directly connected to another element or layer, there are no intervening elements or layers. Thus, the term "connected" may refer to a physical, electrical, and / or fluid connection, with or without intervening elements. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x-, y-, and z-axes, but may be interpreted in a broader sense. For example, the D1, D2, and D3 axes may be orthogonal to each other, or may represent different directions that are not orthogonal to each other. For purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] In this specification, terms such as "first" and "second" may be used to describe various types of elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below can be called a second element without departing from the teachings of the present disclosure.

[0042] For purposes of explanation, spatially relative terms such as below, below, under, lower, above, upper, over, higher, side (e.g., as in sidewall) may be used herein to describe the relationship of an element to other elements shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), in which case the spatially relative descriptors used herein are interpreted accordingly.

[0043] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, as used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that the terms "substantially," "about," and other similar terms are used herein as terms of approximation, not degree, and are utilized to account for inherent deviations in measurements, calculations, and provided values ​​that would be recognized by one of ordinary skill in the art.

[0044] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments disclosed herein should not be construed as necessarily limited to the shape of a particular illustrated region, which may include, for example, deviations in shape that result from manufacturing. As such, the regions illustrated in the drawings are schematic in nature and the shapes of these regions may not reflect the actual shape of a region of a device, and as such are not necessarily intended to be limiting.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure is a part. Terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning in the context of the relevant art, unless expressly so defined herein, and should not be interpreted in an idealized or overly formal sense.

[0046] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As used herein, a light emitting stack structure, a light emitting chip, a light emitting package, or a light emitting module according to exemplary embodiments may include a micro LED having a surface area of ​​less than about 10,000 μm2, as known in the art. In other exemplary embodiments, the micro LED may have a surface area of ​​less than about 4,000 μm2 or a surface area of ​​less than about 2,500 μm2, depending on the particular application.

[0047] FIG. 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with an exemplary embodiment of the present invention.

[0048] 1, a light-emitting package 110 according to the illustrated exemplary embodiment includes a light-emitting chip 100, a passivation layer 90 surrounding at least a side surface of the light-emitting chip 100, a molding layer 91 surrounding at least a side surface of the passivation layer 90, and a circuit board 11p. An array of light-emitting chips may be formed on a board, and the light-emitting chip 100 included in the light-emitting package 110 in FIG. 1 is an example of a chip separated from the array, which is further processed to form the light-emitting package 110.

[0049] The light emitting chip 100 according to the exemplary embodiment may include at least two or more light emitting subunits or light emitting stacks arranged vertically or otherwise stacked. In this way, the light emitting chip 100 can display various colors of light depending on the operating state of each light emitting stack, whereas the conventional light emitting device can display various colors by combining a plurality of light emitting cells emitting light of a single color. More specifically, the conventional light emitting device generally includes light emitting cells emitting different colors of light, for example, red, green, and blue, spaced apart from one another along a two-dimensional plane to realize a full-color display. Therefore, the conventional light emitting cells may occupy a relatively large area. However, the light emitting chip 100 configured according to the exemplary embodiment can emit light having various colors by stacking a plurality of light emitting stacks, thereby achieving a high degree of integration and implementing a full color spectrum in a much smaller area than the conventional light emitting device.

[0050] In addition, when the light emitting chip 100 including the light emitting stack structure is mounted on another substrate to manufacture, for example, a display device, the number of chips to be mounted can be significantly reduced compared to conventional light emitting devices due to the stack structure. In this way, the manufacture of a display device employing the light emitting stack structure can be substantially simplified, especially when hundreds of thousands or millions of pixels are formed in one display device. The light emitting chip 100 may include a light emitting stack structure as shown in FIG. 3, which includes three light emitting stacks and a plurality of connection electrodes connected to the light emitting stacks, which will be described in detail below.

[0051] According to an exemplary embodiment, the passivation layer 90 may be formed around the light emitting stack structure. More specifically, as shown in FIG. 1, the passivation layer 90 may be formed between the connection electrodes of the light emitting stack structure. According to the illustrated exemplary embodiment, the passivation layer 90 may be formed to be substantially flush with the upper surface of the connection electrodes, may include an epoxy molding compound (EMC), and may be formed to have various colors, such as black and transparent, but is not limited thereto. However, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the passivation layer 90 may include a polyimide (PID), where the PID may be provided as a dry film rather than a liquid type to enhance flatness when applied to the light emitting stack structure. In some exemplary embodiments, the passivation layer 90 may include a material having photosensitivity. In this way, the passivation layer 90 can protect the light emitting structure from external impacts that may be applied in subsequent steps, and can provide a sufficient contact area for the light emitting chip 100 to facilitate handling in the subsequent transfer step. In addition, the passivation layer 90 can prevent light from leaking towards the sides of the light-emitting chips 100, and prevent or at least suppress the interference of light emitted from adjacent light-emitting chips 100.

[0052] The molding layer 91 may surround at least a side of the light emitting chip 100 to protect the light emitting chip 100 from external impact. According to the illustrated exemplary embodiment, the molding layer 91 may expose at least one surface of the light emitting chip 100 to enhance light efficiency and color purity. In this case, in the illustrated exemplary embodiment, the substrate on which the light emitting stack structure is grown is removed, so that the brightness and purity of the light emitted from the light emitting package 110 can be increased. According to the exemplary embodiment, the molding layer 91 may include an organic or inorganic polymer. In some exemplary embodiments, the molding layer 91 may include substantially the same material as the passivation layer 90. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the molding layer 91 and the passivation layer 90 may include different materials from each other.

[0053] The circuit board 11p may include a lower circuit electrode 11pa, a middle circuit electrode 11pb, and an upper circuit electrode 11pc, which are connected to each other. The upper circuit electrodes 11pc may be spaced apart from each other at a predetermined pitch P, for example, the pitch (or distance) of the upper circuit electrodes 11pc may correspond to the pitch of the electrodes of a target substrate such as a display device. In this manner, the light emitting package 110 according to the exemplary embodiment may be mounted on a conventional display device without changing the configuration of the target substrate of the display device.

[0054] FIG. 2 is a schematic cross-sectional view of a light emitting package according to another exemplary embodiment.

[0055] 2, the light emitting package 120 according to the illustrated exemplary embodiment is substantially the same as the light emitting package 110 of FIG. 1 except for the shape of the molding layer 91. More specifically, the molding layer 91 according to the illustrated exemplary embodiment covers the upper surface of the light emitting chip 100. In this manner, the molding layer 91 can protect the light emitting chip 100 from external impact and from intrusion of external particles such as dust and moisture into the light emitting stack structure, and can also prevent external light from being reflected by the substrate 11 toward the user. In addition, as shown in FIG. 2, when the molding layer 91 covers the upper surface of the light emitting chip 100, the light transmittance can be controlled by adjusting the thickness of the molding layer 91 or forming the molding layer 91 from a material that can obtain a desired light transmittance. Note that the light emitting package 120 is substantially the same as the light emitting package 110 of FIG. 1 except for the shape of the molding layer 91, and therefore repeated description of its components will be omitted to avoid redundancy.

[0056] FIG. 3 is a schematic cross-sectional view of a light emitting stack structure constructed in accordance with an illustrative embodiment.

[0057] Referring to FIG. 3, the light emitting stack structure according to the illustrated exemplary embodiment includes a first LED subunit, a second LED subunit, and a third LED subunit disposed on a substrate 11. The first LED subunit may include a first light emitting stack 20, the second LED subunit may include a second light emitting stack 30, and the third LED subunit may include a third light emitting stack 40. Although the drawing shows a light emitting stack structure including three light emitting stacks 20, 30, and 40, the concept of the present invention is not limited to a particular number of light emitting stacks formed in the light emitting stack structure. For example, in some exemplary embodiments, the light emitting stack structure may include two or more light emitting stacks therein. The light emitting stack structure will be described below with reference to the three light emitting stacks 20, 30, and 40 according to the exemplary embodiment.

[0058] The substrate 11 may include a light-transmitting insulating material for transmitting light. However, in some exemplary embodiments, the substrate 11 may be formed to be semi-transparent, transmitting only light having a specific wavelength, or partially transparent, transmitting only a portion of light having a specific wavelength. The substrate 11 may also be a growth substrate on which the third light-emitting stack 40 can be epitaxially grown, such as a sapphire substrate. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the substrate 11 may include various other transparent insulating materials. For example, the substrate 11 may be glass, quartz, silicon, an organic polymer, or an organic-inorganic composite material, such as silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (GaO), or the like. 2 O 3 ) or a silicon substrate, etc. As another example, the substrate 11 in some exemplary embodiments may be a printed circuit board or composite substrate that includes electrical wiring therein for providing light emitting signals and a common voltage to each of the light emitting stacks formed thereon.

[0059] Each of the first, second and third light emitting stacks 20, 30 and 40 is configured to emit light toward the substrate 11. Thus, for example, light emitted from the first light emitting stack 20 may pass through the second and third light emitting stacks 30 and 40. According to an exemplary embodiment, the light emitted from each of the first, second and third light emitting stacks 20, 30 and 40 may have different wavelength bands, and the light emitting stack disposed further from the substrate 11 may emit light having a longer wavelength band. For example, the first, second and third light emitting stacks 20, 30 and 40 may emit red light, green light and blue light, respectively. However, the concept of the present invention is not limited thereto. As another example, the first, second and third light emitting stacks 20, 30 and 40 may emit red light, blue light and green light, respectively. In another aspect, when the substrate 11 is removed from the light emitting chip 100 as shown in FIG. 1, the first, second and third light emitting stacks 20, 30 and 40 of the light emitting stack structure can be considered to be sequentially arranged on the circuit substrate 11p shown in FIG. 1. In this case, the first, second and third light emitting stacks 20, 30 and 40 can emit green light, blue light and red light, respectively. As yet another example, one or more light emitting stacks may emit light having substantially the same wavelength band. As yet another example, when the light emitting stack structure includes micro LEDs having a surface area of ​​less than about 10,000 μm2 as known in the art, or less than about 4,000 μm2 or 2,500 μm2 in other exemplary embodiments, due to the small form factor of the micro LEDs, light emitting stacks located farther from the substrate 11 may emit light having a shorter wavelength band than light emitted from those located closer to the substrate 11 without adversely affecting operation. In this case, it may not be necessary to provide a separate color filter between the light emitting stacks because the micro LEDs can be operated at a lower operating voltage. Hereinafter, first, second and third light emitting stacks 20, 30 and 40 will be illustratively described as emitting red, green and blue light, respectively, according to an exemplary embodiment.

[0060] The first light emitting stack 20 includes a first type semiconductor layer 21, an active layer 23, and a second type semiconductor layer 25. According to an exemplary embodiment, the first light emitting stack 20 may include red light emitting semiconductor materials such as, but not limited to, aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), and gallium phosphide (GaP).

[0061] The first upper contact electrode 21n may be disposed on the first-type semiconductor layer 21 and form an ohmic contact with the first-type semiconductor layer 21, and the first lower contact electrode 25p may be disposed under the second-type semiconductor layer 25 of the first light emitting stack 20. According to an exemplary embodiment, a portion of the first-type semiconductor layer 21 may be patterned, and the first upper contact electrode 21n may be disposed in the patterned region of the first-type semiconductor layer 21 to enhance the level of ohmic contact therebetween. The first upper contact electrode 21n may have a single-layer structure or a multi-layer structure, and may include, but is not limited to, Al, Ti, Cr, Ni, Au, Ag, Sn, W, Cu, or alloys thereof, such as Au-Te alloy and Au-Ge alloy. In an exemplary embodiment, the first upper contact electrode 21n has a thickness of about 100 nm and may include a metal with high reflectivity to enhance the light emitting efficiency in the downward direction toward the substrate 11.

[0062] The second light emitting stack 30 includes a first-type semiconductor layer 31, an active layer 33, and a second-type semiconductor layer 35. According to an exemplary embodiment, the second light emitting stack 30 may include a semiconductor material that emits green light, such as, but not limited to, indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), aluminum gallium phosphide (AlGaP). A second bottom contact electrode 35p is disposed below the second-type semiconductor layer 35 of the second light emitting stack 30.

[0063] The third light emitting stack 40 includes a first type semiconductor layer 41, an active layer 43, and a second type semiconductor layer 45. According to an exemplary embodiment, the third light emitting stack 40 may include a semiconductor material that emits blue light, such as, but not limited to, gallium nitride (GaN), indium gallium nitride (InGaN), zinc selenide (ZnSe), etc. A third bottom contact electrode 45p is disposed on the second type semiconductor layer 45 of the third light emitting stack 40.

[0064] According to exemplary embodiments, the first-type semiconductor layers 21, 31, and 41, respectively, and the second-type semiconductor layers 25, 35, and 45, respectively, of the first, second, and third light emitting stacks 20, 30, and 40 may have a single layer structure or a multi-layer structure, and in some exemplary embodiments may include a superlattice layer. Furthermore, the active layers 23, 33, and 43 of the first, second, and third light emitting stacks 20, 30, and 40 may have a single quantum well structure or a multiple quantum well structure.

[0065] Each of the first, second and third lower contact electrodes 25p, 35p and 45p may include a transparent conductive material for transmitting light. For example, the lower contact electrodes 25p, 35p and 45p may include, but are not limited to, tin oxide (SnO), indium oxide (InO 2 ), zinc oxide (ZnO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), or other transparent conductive oxides (TCOs).

[0066] A first adhesive layer 61 is disposed between the first light emitting stack 20 and the second light emitting stack 30, and a second adhesive layer 63 is disposed between the second light emitting stack 30 and the third light emitting stack 40. The first adhesive layer 61 and the second adhesive layer 63 may contain a non-conductive material that transmits light. For example, the first adhesive layer 61 and the second adhesive layer 63 may each contain OCA (Optical Clear Adhesive), and may contain, without being limited thereto, epoxy, polyimide, SU8, SOG (Spin-on Glass), BCB (Benzocyclobutene), or the like.

[0067] According to an exemplary embodiment, each of the first, second and third light emitting stacks 20, 30 and 40 may be driven independently. More specifically, a common voltage Sc is applied to one of the first and second type semiconductor layers of each light emitting stack, and a respective light emitting signal S R , S G and S B may be applied. For example, according to the illustrated exemplary embodiment, the first-type semiconductor layers 21, 31, and 41 of each light-emitting stack may be n-type, and the second-type semiconductor layers 25, 35, and 45 of each light-emitting stack may be p-type. In this case, the third light-emitting stack 40 may have a stacking order reversed compared to the first light-emitting stack 20 and the second light-emitting stack 30, such that the p-type semiconductor layer 45 is disposed on the active layer 43, in order to simplify the manufacturing process. Hereinafter, according to the illustrated exemplary embodiment, the first-type semiconductor layer and the second-type semiconductor layer may be interchangeably referred to as p-type and n-type, respectively.

[0068] Although the light emitting stack structures according to the illustrated exemplary embodiments have a common p-type structure, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the first type semiconductor layers 21, 31 and 41 of each light emitting stack may be p-type, and the second type semiconductor layers 25, 35 and 45 of each light emitting stack may be n-type to form a common n-type light emitting stack structure. Furthermore, in some exemplary embodiments, the stacking order of each light emitting stack may be variously changed without being limited to that shown in the drawings. Hereinafter, the light emitting stack structures according to the illustrated exemplary embodiments will be described with reference to a common p-type light emitting stack structure.

[0069] According to exemplary embodiments, the light-emitting stack structure may further include various additional components to improve the purity and efficiency of the light emitted therefrom. For example, in some exemplary embodiments, a wavelength pass filter may be formed between adjacent light-emitting stacks to prevent or at least inhibit light having a shorter wavelength from moving toward a light-emitting stack emitting a longer wavelength. Furthermore, in some exemplary embodiments, a roughness may be formed on the light-emitting surface of at least one light-emitting stack to balance the brightness of the light between the light-emitting stacks. For example, since green light is generally more visible than red light or blue light, in some exemplary embodiments, a roughness may be formed on the light-emitting stack emitting red light or blue light to improve its light efficiency and balance the visibility between the lights emitted from the light-emitting stacks.

[0070] Hereinafter, a method for forming a light emitting chip will be described based on an exemplary embodiment with reference to the drawings.

[0071] Figures 4A, 5A, 6A, 7A, 8A, and 9A are plan views showing the manufacturing process of the light-emitting chip according to an exemplary embodiment. Figures 4B, 5B, 6B, 7B, 8B, and 9B are cross-sectional views taken along line A-A' of the corresponding plan views shown in Figures 4A, 5A, 6A, 7A, 8A, and 9A according to an exemplary embodiment.

[0072] Returning to FIG. 3, the first-type semiconductor layer 41, the third active layer 43, and the second-type semiconductor layer 45 of the third light-emitting stack 40 may be sequentially grown on the substrate 11 by, for example, a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. The third bottom contact electrode 45p may be formed on the third p-type semiconductor layer 45 by, for example, a physical vapor deposition method or a chemical vapor deposition method, and may include a transparent conductive oxide (TCO). When the third light-emitting stack 40 emits blue light according to an exemplary embodiment, the substrate 11 may be made of Al 2 O 3(e.g., a sapphire substrate), and the third bottom contact electrode 45p is made of tin oxide (SnO), indium oxide (InO 2 The first light emitting stack 20 and the second light emitting stack 30 may each include, but are not limited to, a transparent conductive oxide (TCO) such as zinc oxide (ZnO), indium tin oxide (ITO), or indium tin zinc oxide (ITZO). Similarly, the first light emitting stack 20 and the second light emitting stack 30 may each be formed by sequentially growing a first-type semiconductor layer, an active layer, and a second-type semiconductor layer on a temporary substrate, and a lower contact electrode including a transparent conductive oxide may each be formed on the second-type semiconductor layer by, for example, physical vapor deposition or chemical vapor deposition.

[0073] According to an exemplary embodiment, the first and second light emitting stacks 20 and 30 may be adjacent to each other with the first adhesive layer 61 therebetween, and at least one of the temporary substrates of the first and second light emitting stacks 20 and 30 may be removed, for example, by a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, a roughness may be formed on the exposed light emitting stack to improve light efficiency. Thereafter, the first and second light emitting stacks 20 and 30 may be adjacent to the third light emitting stack 40 with the second adhesive layer 63 therebetween, and the remaining one of the temporary substrates of the first and second light emitting stacks 20 and 30 may be removed, for example, by a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, a roughness may be formed on the exposed remaining light emitting stack to improve light efficiency.

[0074] In another exemplary embodiment, the second adhesive layer 63 may be formed on the third light emitting stack 40. The second light emitting stack 30 may then be adjacent to the third light emitting stack 40 with the second adhesive layer 63 interposed therebetween, and the temporary substrate of the second light emitting stack 30 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. The first adhesive layer 61 may then be formed on the second light emitting stack 30. Thus, the first light emitting stack 20 may be adjacent to the second light emitting stack 30 with the first adhesive layer 61 interposed therebetween. Once the first light emitting stack 20 is bonded to the second light emitting stack 30 bonded to the third light emitting stack 40, the temporary substrate of the first light emitting stack 20 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like.

[0075] 4A and 4B, various portions of each of the first, second and third light emitting stacks 20, 30 and 40 may be patterned, such as via an etching process, to expose portions of the first-type semiconductor layer 21, the first bottom contact electrode 25p, the first-type semiconductor layer 31, the second bottom contact electrode 35p, the third bottom contact electrode 45p and the first-type semiconductor layer 41. According to the illustrated exemplary embodiment, the first light emitting stack 20 has the smallest area among the light emitting stacks 20, 30 and 40. However, the concept of the present invention is not limited to the relative sizes of the light emitting stacks 20, 30 and 40.

[0076] 5A and 5B, a part of the top surface of the first-type semiconductor layer 21 of the first light-emitting stack 20 may be patterned, for example, via wet etching, to form a first upper contact electrode 21n thereon. In this way, the level of ohmic contact between the first-type semiconductor layer 21 and the first upper contact electrode 21n may be increased. The first upper contact electrode 21n may have a single-layer structure or a multi-layer structure, and may include, but is not limited to, Al, Ti, Cr, Ni, Au, Ag, Sn, W, Cu, or alloys thereof, such as Au-Te alloy and Au-Ge alloy. In an exemplary embodiment, the first upper contact electrode 21n has a thickness of about 100 nm and may include a metal with high reflectivity to increase the light-emitting efficiency in the downward direction toward the substrate 11.

[0077] 6A and 6B, a first insulating layer 81 may be disposed on at least a portion of the side surfaces of the first light emitting stack 20, the second light emitting stack 30, and the third light emitting stack 40. The first insulating layer 81 may be formed of a material such as polyimide, SiO 2 , SiNx, Al 2 O 3 For example, the first insulating layer 81 may include a distributed Bragg reflector (DBR). As another example, the first insulating layer 81 may include a black organic polymer. In some exemplary embodiments, an electrically floating metal reflective layer may be further disposed on the first insulating layer 81 to reflect light emitted from the light emitting stacks 20, 30, and 40 toward the substrate 11. In some exemplary embodiments, the first insulating layer 81 may have a single layer structure or a multilayer structure formed of two or more insulating layers having different refractive indices from each other.

[0078] According to an exemplary embodiment, a portion of the first insulating layer 81 may be removed to form the first, second, third and fourth contact holes 20CH, 30CH, 40CH and 50CH. The first contact hole 20CH is defined on the first n-type contact electrode 21n to expose a portion of the first n-type contact electrode 21n.

[0079] The second contact hole 30CH may expose a portion of the first-type semiconductor layer 31 of the second light-emitting stack 30. The third contact hole 40CH may expose a portion of the first-type semiconductor layer 41 of the third light-emitting stack 40. The fourth contact hole 50CH may expose a portion of the first, second, and third lower contact electrodes 21p, 31p, and 41p. The fourth contact hole 50CH may include a first sub-contact hole 50CHa that exposes a portion of the first lower contact electrode 25p and a second sub-contact hole 50CHb that exposes the second and third lower contact electrodes 35p and 45p. However, in some exemplary embodiments, a single first sub-contact hole CH may expose each of the first, second, and third lower contact electrodes 21p, 31p, and 41p.

[0080] 7A and 7B, the first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd are formed on a first insulating layer 81 in which the first, second, third and fourth contact holes 20CH, 30CH, 40CH and 50CH are formed. The first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd can be formed, for example, by forming a conductive layer on substantially the entire surface of the substrate 11 and patterning the conductive layer using a photolithography process or the like.

[0081] The first pad 20pd is formed so as to overlap the region where the first contact hole 20CH is formed, so that the first pad 20pd can be connected to the first upper contact electrode 21n of the first light-emitting stack 20 through the first contact hole 20CH. The second pad 30pd is formed so as to overlap the region where the second contact hole 30CH is formed, so that the second pad 30pd can be connected to the first-type semiconductor layer 31 of the second light-emitting stack 30 through the second contact hole 30CH. The third pad 40pd is formed so as to overlap the region where the third contact hole 40CH is formed, so that the third pad 40pd can be connected to the first-type semiconductor layer 41 of the third light-emitting stack 40 through the third contact hole 40CH. In addition, the fourth pad 50pd is formed so as to overlap the region in which the fourth contact hole 50CH is formed, more specifically, the region in which the first sub-contact hole 50CHa and the second sub-contact hole 50CHb are formed, and the fourth pad 50pd may be connected to the first, second and third lower contact electrodes 25p, 35p, 45p of the first, second and third light-emitting stacks 20, 30 and 40 via the first sub-contact hole 50CHa and the second sub-contact hole 50CHb.

[0082] 8A and 8B, a second insulating layer 83 may be formed on a first insulating layer 81. The second insulating layer 83 may be made of a material such as polyimide, SiO 2 , SiNx, Al 2 O 3It may contain various organic or inorganic insulating materials such as. For example, the second insulating layer 83 may contain a DBR (Distributed Bragg Reflector). As another example, the second insulating layer 83 may contain a black organic polymer. In some exemplary embodiments, an electrically floating metal reflective layer may be further disposed on the second insulating layer 83 to reflect the light emitted from the light-emitting laminates 20, 30, and 40 toward the substrate 11. In some exemplary embodiments, the second insulating layer 83 may have a single-layer structure or a multilayer structure formed of two or more insulating layers having different refractive indices from each other. Next, the second insulating layer 83 is patterned to form first, second, third, and fourth through-holes 20ct, 30ct, 40ct, and 50ct therein.

[0083] The first through-hole 20ct formed in the first pad 20pd exposes a part of the first pad 20pd. The second through-hole 30ct formed in the second pad 30pd exposes a part of the second pad 30pd. The third through-hole 40ct formed in the third pad 40pd exposes a part of the third pad 40pd. The fourth through-hole 50ct formed in the fourth pad 50pd exposes a part of the fourth pad 50pd. In the illustrated exemplary embodiment, the first, second, third, and fourth through-holes 20ct, 30ct, 40ct, and 50ct may be respectively defined in the regions where the first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are formed.

[0084] 9A and 9B, the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp are formed on the second insulating layer 83 in which the first, second, third and fourth through holes 20ct, 30ct, 40ct and 50ct are formed. The first bump electrode 20bp is formed so as to overlap the area in which the first through hole 20ct is formed, and the first bump electrode 20bp is connected to the first pad 20pd through the first through hole 20ct. The second bump electrode 30bp may be formed so as to overlap the area in which the second through hole 30ct is formed, and the second bump electrode 30bp may be connected to the second pad 30pd through the second through hole 30ct. In addition, the third bump electrode 40bp may be formed so as to overlap the area in which the third through hole 40ct is formed, and the third bump electrode 40bp may be connected to the third pad 40pd via the third through hole 40ct.

[0085] The fourth bump electrode 50bp is formed so as to overlap the region in which the fourth through hole 50ct is formed, and the fourth bump electrode 50bp is connected to the fourth pad 50pd through the fourth through hole 50ct. More specifically, the fourth pad 50pd is connected to the second-type semiconductor layers 25, 35, and 45 of the first, second, and third light-emitting stacks 20, 30, and 40 through the first sub-contact hole 50CHa and the second sub-contact hole 50CHb defined in the first, second, and third lower contact electrodes 25p, 35p, and 45p of the first, second, and third light-emitting stacks 20, 30, and 40. In particular, the fourth pad 50pd is connected to the first lower contact electrode 25p through the second sub-contact hole 50CHb, and is connected to the second and third lower contact electrodes 35p and 45p through the first sub-contact hole 50CHa. In this way, since the fourth pad 50pd is connected to the second and third lower contact electrodes 35p and 45p through one first sub-contact hole 50CHa, the manufacturing process of the light emitting chip 100 may be simplified and the area occupied by the contact holes of the light emitting chip 100 may be reduced. In addition, at least a part of the fourth bump electrode 50bp may overlap with the fourth pad 50pd. The fourth bump electrode 50bp is connected to the fourth pad 50pd through the fourth through hole 50ct in the overlapping portion between the fourth bump electrode 50bp and the fourth pad 50pd with the second insulating layer 83 interposed therebetween.

[0086] The first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp may be formed by, for example, depositing and patterning a conductive layer containing at least one of Ni, Ag, Au, Pt, Ti, Al, Cr, W, TiW, Mo, Cu, TiCu, etc. on the substrate 11. Hereinafter, the first pad 20pd and the first bump electrode 20bp may be collectively referred to as the first contact portion 20C, the second pad 30pd and the second bump electrode 30bp may be collectively referred to as the second contact portion 30C, the third pad 40pd and the third bump electrode 40bp may be collectively referred to as the third contact portion 40C, and the fourth pad 50pd and the fourth bump electrode 50bp may be collectively referred to as the fourth contact portion 50C.

[0087] According to an exemplary embodiment, the first, second, third and fourth contact parts 20C, 30C, 40C and 50C may be formed at various positions. For example, if the light emitting chip 100 has a substantially rectangular shape as shown in the drawings, the first, second, third and fourth contact parts 20C, 30C, 40C and 50C may be disposed around each corner of the substantially rectangular shape. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the light emitting chip 100 may be formed to have various shapes, and the first, second, third and fourth contact parts 20C, 30C, 40C and 50C may be formed at other positions depending on the shape of the light emitting device.

[0088] The first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd are insulated from each other by spacing them apart. Furthermore, the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp are insulated from each other by spacing them apart. According to an exemplary embodiment, the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp may cover at least a portion of the side surface of the first, second and third light emitting stacks 20, 30 and 40, respectively, which may promote the in situ dissipation of heat generated from the first, second and third light emitting stacks 20, 30 and 40.

[0089] The concept of the present invention is not limited to a specific structure of the contact portions 20C, 30C, 40C, and 50C. For example, in some exemplary embodiments, the bump electrodes 20bp, 30bp, 40bp, or 50bp may be omitted from at least one of the contact portions 20C, 30C, 40C, and 50C. In this case, the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C may be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce.

[0090] Figure 10A is a schematic plan view showing a manufacturing process of a light-emitting chip according to an exemplary embodiment, and Figures 10B and 10C are schematic cross-sectional views taken along lines A-A' and B-B', respectively, of Figure 10A.

[0091] 10A, 10B and 10C, the first, second, third and fourth connection electrodes 20ce, 30ce, 40ce and 50ce are formed on the light emitting stack structure with a space between them. The first, second, third and fourth connection electrodes 20ce, 30ce, 40ce and 50ce may be electrically connected to the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp, respectively, to transmit external signals to the light emitting stacks 20, 30 and 40, respectively. More specifically, according to the illustrated exemplary embodiment, the first connection electrode 20ce may be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n via the first pad 20pd, and electrically connected to the first type semiconductor layer 21 of the first light emitting stack 20. The second connection electrode 30ce may be connected to the second bump electrode 30bp via the second pad 30pd and electrically connected to the first-type semiconductor layer 31 of the second light-emitting stack 30. The third connection electrode 40ce may be connected to the third bump electrode 40bp connected to the third pad 40pd and electrically connected to the first-type semiconductor layer 41 of the third light-emitting stack 40. The fourth connection electrode 50ce may be connected to the fourth bump electrode 50bp connected to the fourth pad 50pd and electrically connected to the second-type semiconductor layers 25, 35 and 45 of the light-emitting stacks 20, 30 and 40 via the first, second and third lower contact electrodes 25p, 35p and 45p, respectively.

[0092] According to the illustrated exemplary embodiment, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially elongated shape that protrudes vertically from the substrate 11. The connection electrodes 20ce, 30ce, 40ce, and 50ce may include a metal such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof. For example, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may include two or more metals or multiple different metal layers to relieve stress thereon from the elongated shape of the connection electrodes 20ce, 30ce, 40ce, and 50ce. In another exemplary embodiment, if the connection electrodes 20ce, 30ce, 40ce, and 50ce include Cu, an additional metal may be deposited or plated thereon to inhibit oxidation of the Cu. In some exemplary embodiments, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include Cu / Ni / Sn, the Cu may prevent Sn from penetrating into the light emitting stack. In some exemplary embodiments, the connecting electrodes 20ce, 30ce, 40ce, and 50ce may include a seed layer for forming a metal layer during a plating process, which will be described in more detail below.

[0093] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially flat upper surface to facilitate electrical connection between the light emitting stack and external wiring or electrodes, which will be described later. According to an exemplary embodiment, when the light emitting chip includes a micro LED having a surface area of ​​less than about 10,000 μm2 as known in the art, or less than about 4,000 μm2 or 2,500 μm2 in other exemplary embodiments, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one portion of the first, second, and third light emitting stacks 20, 30, and 40, as shown in the drawings. More specifically, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on a side surface of the light emitting stack. In this way, a larger contact area can be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light emitting stack, since the area of ​​the lower surface of the connection electrodes is larger than that of the upper surface. Therefore, the connection electrodes 20ce, 30ce, 40ce, and 50ce can be formed more stably on the light-emitting stack structure. For example, the length (or height) of one side L of the connection electrodes 20ce, 30ce, 40ce, and 50ce facing the outside and the other side L' facing the center of the light-emitting chip 100 may be different. More specifically, the length of one side L of the connection electrodes facing the outside may be greater than the length of the other side L' facing the center of the light-emitting chip 100. For example, the difference in length between the two opposing sides L, L' of the connection electrodes may be greater than the thickness (or height) of one of the LED stacks 20, 30, and 40. In this way, the contact area between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting stack structure is increased, and the structure of the light-emitting chip is strengthened. Furthermore, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on the side surface of the light-emitting stacked structure, so that heat generated from the light-emitting stacked structure can be dissipated to the outside more efficiently.

[0094] According to an exemplary embodiment, the difference in length between the one surface L of the connection electrode facing the outside of the light emitting chip 100 and the other surface L' facing the center of the light emitting chip 100 may be about 3 μm. In this case, the light emitting stack structure may be formed thin, in particular, the first LED stack 20 may have a thickness of about 1 μm, the second LED stack 30 may have a thickness of about 0.7 μm, the third LED stack 40 may have a thickness of about 0.7 μm, and the first adhesive layer 61 and the second adhesive layer 63 may have a thickness of about 0.2 μm to about 0.3 μm, but are not limited thereto. According to another exemplary embodiment, the difference in length between the one surface L of the connection electrode facing the outside of the light emitting chip 100 and the other surface L' facing the center of the light emitting chip 100 may be about 10 μm to about 16 μm. In this case, the light emitting stack structure is formed relatively thick and can have a more stable structure, and in particular, the first LED stack 20 may have a thickness of about 4 μm to about 5 μm, the second LED stack 30 may have a thickness of about 3 μm, the third LED stack 40 may have a thickness of about 3 μm, and the first and second adhesive layers 61, 63 may each have a thickness of about 3 μm, but are not limited thereto. However, the concept of the present invention is not limited to a specific difference in length between the opposing surfaces of the connecting electrodes, and the difference in length between the opposing surfaces of the connecting electrodes may be changed.

[0095] In some exemplary embodiments, at least one of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may overlap with each side of the light-emitting stacks 20, 30, and 40, thereby balancing the temperature between the light-emitting stacks 20, 30, and 40, and efficiently dissipating heat generated inside to the outside. In addition, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include a reflective material such as a metal, the connecting electrodes 20ce, 30ce, 40ce, and 50ce can reflect light emitted from at least one or more of the light-emitting stacks 20, 30, and 40 to improve light efficiency.

[0096] The method of forming the first, second, third and fourth connecting electrodes 20ce, 30ce, 40ce and 50ce is not particularly limited. For example, according to an exemplary embodiment, a seed layer may be deposited as a conductive surface on the light emitting stack structure, and the seed layer may be patterned using photolithography or the like so that the seed layer is located at a desired location where the connecting electrodes are to be formed. The seed layer may then be plated with a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag or an alloy thereof, and the seed layer may be removed. In some exemplary embodiments, additional metal may be deposited or plated on the plated metal (e.g., the connecting electrodes) such as by electroless nickel immersion gold (ENIG) to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer may remain on each connecting electrode.

[0097] According to an exemplary embodiment, when the bump electrodes 20bp, 30bp, 40bp, and 50bp are omitted from the contact portions 20C, 30C, 40C, and 50C, the pads 20pd, 30pd, 40pd, and 50pd may be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce. For example, after forming the through holes 20ct, 30ct, 40ct, and 50ct that partially expose the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C, a seed layer may be formed as a conductive surface on the light-emitting stacked structure, and the seed layer may be patterned using photolithography or the like so that the seed layer is disposed at a desired position where the connection electrode is to be formed. In this case, the seed layer may overlap at least a portion of each of the pads 20pd, 30pd, 40pd, and 50pd. According to exemplary embodiments, the seed layer may be deposited to a thickness of about 1000 Å, and then the seed layer may be plated with a metal, such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof, and the seed layer may be removed. In some exemplary embodiments, additional metal may be deposited or plated onto the plated metal (e.g., the connection electrodes), such as with electroless nickel immersion gold (ENIG), to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer may remain on each connection electrode.

[0098] 11, 12, 13, 14, 15, 16, and 17 are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to exemplary embodiments.

[0099] Typically, during manufacturing, an array of multiple light-emitting chips is formed on a substrate. The substrate is then cut along scribe lines to singulate (separate) each light-emitting chip, and the light-emitting chips may be transferred to another substrate or tape using various transfer techniques for further processing of the light-emitting chips, such as packaging. In this case, if the light-emitting chip includes connection electrodes such as metal bumps or pillars that protrude from the light-emitting structure to the outside, various problems may occur in subsequent processes, such as the transfer step, due to the structure of the bare light-emitting chip exposing the connection electrodes to the outside. Furthermore, if the light-emitting chip includes a micro LED with a surface area of ​​less than about 10,000 square micrometers, less than about 4,000 square micrometers, or less than about 2,500 square micrometers depending on the application, the light-emitting chip may be difficult to handle due to its small form factor.

[0100] For example, when the connection electrode has a substantially elongated shape such as a rod shape, the protruding structure of the connection electrode may not ensure a sufficient adsorption area for the light emitting chip, making it difficult to transport the light emitting chip using a conventional vacuum method. Furthermore, the exposed connection electrode may directly receive various stresses in subsequent processes, such as when the connection electrode comes into contact with a manufacturing device, which may damage the structure of the light emitting chip. As another example, when the light emitting chip is transferred by attaching an adhesive tape to the upper surface (e.g., the surface facing the substrate) of the light emitting chip, the contact area between the light emitting chip and the adhesive tape may be limited to the upper surface of the connection electrode. In this case, unlike when the adhesive tape is attached to the lower surface of the chip (e.g., the substrate), the adhesive force between the light emitting chip and the adhesive tape may be weak, and the light emitting chip may peel off from the adhesive tape in an undesirable manner during transfer. As another example, when the light emitting chip is transported using a conventional pick-and-place method, the ejection pin may directly contact a part of the light emitting chip arranged between the connection electrodes, damaging the upper structure of the light emitting structure.

[0101] FIG. 11 shows an array of light-emitting stacked structures formed on a substrate 11. Referring to FIG. 11, a passivation layer 90 is disposed between the connection electrodes 20ce, 30ce, 40ce, and 50ce. The passivation layer 90 may be formed to be substantially flush with the upper surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce by a polishing process or the like. In this manner, the passivation layer 90 can protect the light-emitting structure from external impacts that may be applied in a subsequent process, and can provide a sufficient contact area for the light-emitting chip 100 to facilitate handling in a subsequent transfer process. Furthermore, the passivation layer 90 can prevent light from leaking toward the side surface of the light-emitting chip 100, and can prevent or at least suppress interference of light emitted from adjacent light-emitting chips 100.

[0102] 12, the substrate 11 (e.g., a growth substrate) on which the light-emitting chips 100 are formed may be mounted on a temporary substrate 95. The temporary substrate 95 is not particularly limited as long as it can support the arrangement of the light-emitting chips 100 in the subsequent process. For example, in some exemplary embodiments, the temporary substrate 95 may be a tape.

[0103] Referring to FIG. 13, the substrate 11 may be removed from the light-emitting chip 100 using various known methods in the art. For example, in some exemplary embodiments, a known laser lift-off (LLO) method or the like may be used to irradiate the substrate 11 with laser light to lift off the substrate 11 from the light-emitting chip 100. In this way, since the substrate 11 is removed from the light-emitting chip 100, the light emitted from the light-emitting chip 100 does not pass through the substrate 11, and the light efficiency and color purity of the light-emitting chip 100 can be improved. In this case, even if the substrate 11 is removed from the light-emitting chip 100, the light-emitting chip 100 configured according to the exemplary embodiments has a reinforcing structure formed at least in part by the substantially elongated connection electrodes 20ce, 30ce, 40ce, and 50ce and the passivation layer 90 surrounding at least the side surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce. Therefore, the light-emitting chip 100 can withstand various external stresses that may be applied during manufacturing or use.

[0104] In some exemplary embodiments, uneven portions may be formed on the surface of the third LED laminate 40 that is exposed by removing the substrate 11 to balance the visibility of the light emitted from each light-emitting laminate.

[0105] Referring to FIGS. 14 and 15, according to an exemplary embodiment, the laser L may be irradiated between the light-emitting chips 100 to individually separate (isolate) the light-emitting chips 100 from each other. However, the concept of the present invention is not limited to a specific method used to separate the light-emitting chips 100. For example, in some exemplary embodiments, the light-emitting chips 100 may be individually separated by mechanically cutting along the scribing line using a blade or the like.

[0106] Referring to FIG. 16, the light-emitting chip 100 may be transferred and mounted on the circuit board 11p. The temporary substrate 95 may be removed after or before the light-emitting chip 100 is mounted on the circuit board 11p.

[0107] In an exemplary embodiment, the circuit board 11p includes a lower circuit electrode 11pa, an upper circuit electrode 11pc, and a middle circuit electrode 11pb disposed therebetween, which may be electrically connected to each other. The lower circuit electrode 11pa may be connected to the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce, respectively. In some exemplary embodiments, the lower circuit electrode 11pa may be surface-treated with ENIG to facilitate electrical connection with the connection electrodes of the light-emitting chip 100 by being partially melted at high temperature.

[0108] According to an exemplary embodiment, the first, second, third and fourth connection electrodes 20ce, 30ce, 40ce and 50ce of the light emitting chip 100 may be respectively bonded to the lower circuit electrode 11pa of the circuit board 11p by, for example, anisotropic conductive film (ACF) bonding. When the light emitting chip 100 is bonded to the circuit board by ACF bonding, which can be performed at a lower temperature compared to other bonding methods, the light emitting chip 100 can be prevented from being exposed to high temperatures during bonding. However, the concept of the present invention is not limited to a specific bonding method. For example, in some exemplary embodiments, the light emitting chip 100 may be bonded to the circuit board 11p by using anisotropic conductive paste (ACP), solder, ball grid area (BGA), or microbumps including at least one of Cu and Sn. In this case, the upper surfaces of the connection electrodes 20ce, 30ce, 40ce and 50ce are made substantially flush with the passivation layer 90 by a polishing process or the like, thereby improving adhesion to the anisotropic conductive film of the light-emitting chip 100 and forming a more stable structure when bonded to the circuit board 11p.

[0109] According to an exemplary embodiment, the upper circuit electrodes 11pc may be spaced apart from each other at a predetermined pitch. For example, the pitch between the upper circuit electrodes 11pc may correspond to the pitch of the electrodes of a target substrate, such as a display device. In this way, the light emitting package 110 according to the exemplary embodiment may be mounted on a conventional display device without changing the configuration of the target substrate of the display device.

[0110] Referring to FIG. 17, after the passivation layer 90 is formed, a molding layer 91 may be formed on the light emitting chip 100 mounted on the circuit board 11p. The molding layer 91 may surround at least a side of the light emitting chip 100 and protect the light emitting chip 100 from external impact. According to the illustrated exemplary embodiment, the molding layer 91 may expose at least one side of the light emitting chip 100 to enhance light efficiency. In this case, since the light emitting chip 100 according to the illustrated exemplary embodiment does not include a growth substrate 11, the light emitted from the light emitting package 110 has increased brightness and purity. According to the exemplary embodiment, the molding layer 91 may include an organic or inorganic polymer. In some exemplary embodiments, the molding layer 91 may include substantially the same material as the passivation layer 90, but since the molding layer 91 is formed later, the two layers are distinguished even if they are formed of the same material. However, the inventive concept is not so limited and in some exemplary embodiments, molding layer 91 and passivation layer 90 may comprise different materials.

[0111] The light emitting chips 100 surrounded by the molding layer 91 may then be cut to provide the light emitting package 110 of FIG. 1. Although FIG. 17 shows the light emitting package 110 including one light emitting chip 100 therein, the concept of the present invention is not limited to a specific number of light emitting chips 100 in the light emitting package. For example, in some exemplary embodiments, the light emitting chips 100 surrounded by the molding layer 91 may be cut in a desired configuration, and such light emitting packages may include at least one or more light emitting chips 100 therein by various methods known in the art, taking into consideration the final device in which the light emitting package will be mounted, such as a display device. For example, the light emitting package 110 may include one or more light emitting chips 100 arranged in an n×m array, where n and m are natural numbers.

[0112] 18A to 18C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 2 according to another exemplary embodiment.

[0113] Referring to FIG. 18, according to another exemplary embodiment, the molding layer 91 may be formed to cover the top surface of the light emitting chip 100 (e.g., the third LED stack 40). As described above, in this case, the molding layer 91 may include a photosensitive organic polymer or an inorganic polymer to transmit light emitted from the light emitting chip 100. In this manner, the light emitting chip 100 of the light emitting package 120 may be protected from external stress and the like. Then, the light emitting chip 100 surrounded by the molding layer 91 may be cut to provide the light emitting package 120 of FIG. 2. Although FIG. 18 shows that the light emitting package 120 includes one light emitting chip 100 therein, the concept of the present invention is not limited to the number of light emitting chips 100 in the light emitting package being a specific number. For example, in some exemplary embodiments, the light emitting chip 100 surrounded by the molding layer 91 may be cut in a desired configuration, and such light emitting package may include at least one or more light emitting chips 100 therein by various methods known in the art.

[0114] As described above, in FIGS. 11 to 17, the step of forming the passivation layer 90 before the light emitting chips 100 are separated from each other (or singulated) is illustrated. However, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the light emitting chips 100 formed on the substrate 11 may be separated from each other before the step of forming the passivation layer 90 thereon. More specifically, returning to FIG. 11, before forming the passivation layer 90 on the light emitting chip 100, a separation step may be performed so that the third light emitting stack 40 formed substantially on the entire substrate 11 with the light emitting chip 100 sandwiched therebetween is separated from each other, thereby exposing at least a part of the substrate 11 between the light emitting chips 100. In this case, at least the side surface of the third light emitting stack 40 between the light emitting chips 100 may also be exposed from the separation step. In this way, when the passivation layer 90 is formed on each of the light-emitting chips 100 in a later process, the passivation layer 90 may cover the exposed side surface of the third light-emitting stack 40 in addition to the surface of the light-emitting chip 100 shown in FIG. 11. In this way, the passivation layer 90 may further improve the reliability of the light-emitting chip 100 from the external environment. In addition, the passivation layer 90 can substantially block light emitted from each light-emitting stack in its longitudinal direction, and improve the light efficiency of the light-emitting chip 100 in the vertical direction.

[0115] FIG. 19 is a schematic cross-sectional view of a luminescence package constructed in accordance with an exemplary embodiment of the present invention, and FIG. 20 is a schematic cross-sectional view of a luminescence package constructed in accordance with another exemplary embodiment of the present invention.

[0116] Referring to Figure 19, a light-emitting package 210 according to an exemplary embodiment includes a light-emitting chip 200, a circuit board 11p' including a lower circuit electrode 11pa', an intermediate circuit electrode 11pb' and an upper circuit electrode 11pc', and a molding layer 91' surrounding at least the sides of the light-emitting chip 200.

[0117] The molding layer 91' may surround at least a side of the light emitting chip 200 to protect the light emitting chip 200 from external impact. According to the illustrated exemplary embodiment, the molding layer 91' may expose at least one surface of the light emitting chip 200 to enhance light efficiency and color purity. In this case, the light emitting chip 200 according to the illustrated exemplary embodiment does not include a substrate on which the light emitting stack structure is grown, so that the light emitted from the light emitting package 210 is increased in brightness and purity. According to the exemplary embodiment, the molding layer 91' may include an organic or inorganic polymer. In some exemplary embodiments, the molding layer 91' may include substantially the same material as the passivation layer 290. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the molding layer 91' and the passivation layer 290 may include different materials from each other.

[0118] The light emitting package 210 according to the exemplary embodiment is substantially the same as the light emitting package 110 of FIG. 1, except for the shape of the connection electrodes and the fact that the light emitting chip 200 includes a passivation layer 290 formed between the connection electrodes, which will be described in detail below. Note that the circuit board 11p′ and its components are substantially the same as the circuit board 11p described above, and therefore, to avoid redundancy, repeated description thereof will be omitted.

[0119] According to an exemplary embodiment, the top electrodes 11pc′ of the light emitting package 210 may be spaced apart from each other at a predetermined pitch corresponding to the pitch of the electrodes of a final device, so that the light emitting package 210 can be easily mounted on a substrate of a final device, such as a display device, even if the layout of the electrodes of the final device is designed for a conventional light emitting device.

[0120] 20, the light emitting package 220 according to the exemplary embodiment is substantially the same as the light emitting package 210 of FIG. 19 except for the shape of the molding layer 91'. More specifically, the molding layer 91' according to the illustrated exemplary embodiment covers the upper surface of the light emitting chip 200. In this manner, the molding layer 91' can protect the light emitting chip 200 from external impact and from intrusion of external particles such as dust and moisture into the light emitting stack structure. In addition, as shown in FIG. 20, when the molding layer 91' covers the upper surface of the light emitting chip 200, the light transmittance can be controlled by adjusting the thickness of the molding layer 91' or forming the molding layer 91' from a material that can obtain a desired light transmittance. Note that the light emitting package 220 is substantially the same as the light emitting package 210 of FIG. 19 except for the shape of the molding layer 91', and therefore repeated description of the components thereof will be omitted to avoid redundancy.

[0121] 21A and 22A are plan views showing a manufacturing process of a light-emitting chip according to another exemplary embodiment, and FIGs. 21B and 22B are cross-sectional views taken along line A-A' of the corresponding plan views shown in FIGs. 21A and 22A according to another exemplary embodiment.

[0122] 21A and 21B, the light emitting chip 200 according to the exemplary embodiment includes a light emitting stack structure, connection electrodes 20ce', 30ce', 40ce' and 50ce', and a passivation layer 290 formed therebetween. The light emitting stack structure is substantially similar to the configuration shown in FIG. 9A and FIG. 9B. However, according to the illustrated exemplary embodiment, the passivation layer 290 may be formed to cover at least a portion of the upper surface of the light emitting stack structure shown in FIG. 9A and FIG. 9B. More specifically, the passivation layer 290 may cover at least a portion of the upper surface of the first light emitting stack 20 disposed on the upper portion of the stack structure, and protect the light emitting stack structure from external stress during manufacturing.

[0123] According to the illustrated exemplary embodiment, the passivation layer 290 may form an inclined angle with respect to the substrate 11. For example, the angles G and G' (see FIG. 22B) formed between the passivation layer 290 and the substrate 11 may be less than about 80°. If the inclination angle is greater than about 80°, the passivation layer 290 may not be able to sufficiently cover the step formed on the side of the light-emitting stack structure. In some exemplary embodiments, the inclination angle between the passivation layer 290 and the substrate 11 may be greater than about 60° and less than about 70°. In this manner, the connection electrodes 20ce', 30ce', 40ce', and 50ce' (see FIG. 22A and FIG. 22B) formed on the passivation layer 290 may also be stably formed on the light-emitting stack structure. In some exemplary embodiments, the edges formed between the top surface and the side surfaces of the passivation layer 290 may form a smooth angle such that the connecting electrodes 20ce', 30ce', 40ce', and 50ce' formed thereon have a substantially uniform thickness. However, the inventive concept is not limited in this respect, and in some exemplary embodiments, the edges formed between the top surface and the side surfaces of the passivation layer 290 may be substantially sharp.

[0124] 22A and 22B, according to the illustrated exemplary embodiment, the first, second, third and fourth connection electrodes 20ce', 30ce', 40ce' and 50ce' spaced apart from one another are formed on the passivation layer 290. As described above, the first, second, third and fourth connection electrodes 20ce', 30ce', 40ce' and 50ce' may be electrically connected to the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp, respectively, similar to the first, second, third and fourth connection electrodes 20ce, 30ce, 40ce and 50ce of the light emitting chip 100, to transmit external signals to the light emitting stacks 20, 30 and 40, respectively. More specifically, the first connection electrode 20ce' may be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n via the first pad 20pd, and electrically connected to the first-type semiconductor layer 21 of the first light-emitting stack 20. The second connection electrode 30ce' may be connected to the second bump electrode 30bp via the second pad 30pd, and electrically connected to the first-type semiconductor layer 31 of the second light-emitting stack 30. The third connection electrode 40ce' may be connected to the third bump electrode 40bp connected to the third pad 40pd, and electrically connected to the first-type semiconductor layer 41 of the third light-emitting stack 40. In addition, the fourth connection electrode 50ce' may be connected to the fourth bump electrode 50bp connected to the fourth pad 50bp, and electrically connected to the second-type semiconductor layers 25, 35, and 45 of the light-emitting stacks 20, 30, and 40, respectively, via the first, second, and third lower contact electrodes 25p, 35p, and 45p.

[0125] The method of forming the first, second, third and fourth connecting electrodes 20ce', 30ce', 40ce' and 50ce' is not particularly limited. For example, according to an exemplary embodiment, a conductive layer may be deposited on the passivation layer 290 and patterned using photolithography or the like so that each of the conductive layers overlaps a portion of the first bump electrode 20bp, the second bump electrode 30bp, the third bump electrode 40bp and the fourth bump electrode 50bp exposed by the passivation layer 290. The conductive layer (e.g., the connecting electrode) according to an exemplary embodiment may include a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag or an alloy thereof. In this case, a separate plating step may be omitted. In some exemplary embodiments, an additional metal may be deposited on the conductive layer, such as by electroless nickel immersion gold (ENIG), to prevent or at least inhibit oxidation of the connecting electrodes 20ce', 30ce', 40ce' and 50ce'.

[0126] According to the illustrated exemplary embodiment, each of the connecting electrodes 20ce', 30ce', 40ce', and 50ce' may have a curved or angular shape protruding away from the substrate 11 to substantially cover the light emitting stack structure and the passivation layer 290. As shown in the drawings, each of the connecting electrodes 20ce', 30ce', 40ce', and 50ce' may have a substantially flat upper surface to facilitate electrical connection between the light emitting stack structure and external wiring or electrodes, and to enhance adhesion between the light emitting chip 200 and other elements such as a PCB during subsequent bonding and transfer steps. The connecting electrodes 20ce', 30ce', 40ce', and 50ce' according to the illustrated exemplary embodiment may surround at least a portion of each light emitting stack 20, 30, and 40 to protect the light emitting stack structure, so that the light emitting chip 200, together with the passivation layer 290, has a more stable structure to withstand various subsequent processes. For example, the connection electrodes 20ce', 30ce', 40ce', and 50ce' surrounding at least the side surfaces of the light-emitting stack structure can absorb at least a part of the stress directly applied to the light-emitting stack structure, thereby protecting the light-emitting chip during manufacturing.

[0127] According to the illustrated exemplary embodiment, the third connection electrode 40ce' is shown as being asymmetric with respect to the first connection electrode 20ce'. More specifically, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' may have a portion that does not overlap with the passivation layer 290, for example, FIG. 22B shows that the portion of the third connection electrode 40ce' that does not overlap with the passivation layer 290 is larger in area than that of the first connection electrode 20ce' near two opposite ends of the substrate 11. However, the concept of the present invention is not limited in this respect, and in some exemplary embodiments, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' may be symmetric with respect to each other. For example, the portions of the connection electrodes 20ce', 30ce', 40ce', and 50ce' that do not overlap with the passivation layer 290 may have the same area as each other.

[0128] In the drawings, the passivation layer 290 is not formed between the portions of the connection electrodes 20ce', 30ce', 40ce', and 50ce' disposed on the upper surface of the passivation layer 290, but the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the passivation layer 290 may be formed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' so that the upper surface of the passivation layer 290 is substantially flush with the upper surfaces of the connection electrodes 20ce', 30ce', 40ce', and 50ce'. By doing so, the adhesion between the light emitting chip 200 and a printed circuit board or the like can be further strengthened in a later process. Note that the portions of the passivation layer 290 disposed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' may be formed before or after the connection electrodes 20ce', 30ce', 40ce', and 50ce' are formed. It should be noted that the components of the light-emitting chip 200 according to the illustrated exemplary embodiment are substantially the same as the components of the light-emitting chip 100 described above, and therefore repeated descriptions of the substantially same components are omitted to avoid redundancy.

[0129] 23 and 24 are schematic cross-sectional views illustrating the manufacturing process of a light emitting package according to an exemplary embodiment.

[0130] 22, the array of light emitting chips 200 formed on the growth substrate 11 may be separated from one another and transferred to be mounted on a circuit board 11p'. The circuit board 11p' according to the exemplary embodiment is substantially the same as the circuit board 11p described above, and therefore a repeated description thereof will be omitted to avoid redundancy. As described above, the upper circuit electrodes 11pc' of the circuit board 11p' may be spaced apart from one another at a desired pitch to match the pitch of electrodes of a final device such as a display device.

[0131] 24, when the light emitting chips 200 separated from each other are mounted on the circuit board 11p', the substrate 11 of the light emitting chip 200 may be removed by various known methods in the art, such as the LLO method. In this manner, since the substrate 11 is removed from the light emitting chip 200, the light emitted from the light emitting chip 200 does not pass through the substrate 11, and the light efficiency and color purity of the light emitting chip 200 can be improved. In this case, even if the substrate 11 is removed from the light emitting chip 200, the light emitting chip 200 configured according to the exemplary embodiment has a structure that is at least partially reinforced by the passivation layer 290 and the connection electrodes 20ce', 30ce', 40ce', and 50ce' having a curved shape, so that the light emitting chip 200 can withstand various external stresses applied thereto that may occur during manufacturing or use.

[0132] Note that, although Figures 23 and 24 show the growth substrate 11 being cut and then removed from the light-emitting chip 200 (e.g., the light-emitting chip 200 being separated into individual pieces), the concept of the present invention is not limited to this.

[0133] 25, 26, 27, 28 and 29 are schematic cross-sectional views illustrating manufacturing steps of the luminescent package of FIG. 19 according to an exemplary embodiment.

[0134] Referring to Figures 25 to 27, according to another exemplary embodiment, instead of the substrate 11 being removed from the light-emitting chip 200 after being cut, as shown in Figures 23 and 24, the growth substrate 11 is removed from the selected light-emitting chip 200.

[0135] More specifically, the array of the light emitting chips 200 formed on the substrate 11 may be separated through a separation process such that the third light emitting stacks 40 formed substantially on the entire substrate 11 with the light emitting chips 200 sandwiched therebetween are separated from each other. In this case, the separation process may be performed before or after forming the passivation layer 290 on the light emitting stack structure.

[0136] When the light emitting chips 200 are separated from each other so that at least a part of the substrate 11 arranged between the light emitting chips 200 is exposed, the light emitting chip 200 is mounted on the circuit substrate 11p'. In this case, the lower circuit electrode 11pa' may be formed to correspond to only a part of the light emitting chip 200 formed on the substrate 11. When the light emitting chip 200 is arranged on the circuit substrate 11p', the light emitting chip 200 to be transferred may be selectively irradiated with a laser L as shown in FIG. 26. In this case, according to an exemplary embodiment, the connection electrodes of the light emitting chip 200 may be bonded to the lower circuit electrodes 11pa' of the circuit substrate 11p', for example, by ACF (Anisotropic Conductive Film) bonding. When the light emitting chip 200 is bonded to the circuit substrate 11p' by ACF bonding, which can be performed at a lower temperature compared to other bonding methods, the light emitting chip 200 can be protected from being exposed to high temperatures during bonding. However, the concept of the present invention is not limited to a specific bonding method. For example, in some exemplary embodiments, the light emitting chip 200 may be bonded to the circuit board 11p' using anisotropic conductive paste (ACP), solder, ball grid area (BGA), or microbumps containing at least one of Cu and Sn. In this case, as shown in FIG. 22B, the portion of the connection electrode overlapping the passivation layer 290 of the light emitting chip 200 is substantially flat, so that the adhesion of the light emitting chip 200 to the anisotropic conductive film is enhanced, and a more stable structure can be formed when the light emitting chip 200 is bonded to the circuit board 11p'.

[0137] 27, the substrate 11 may then be lifted up, and the light-emitting chips 200 selectively irradiated with the laser L may be mounted on a circuit substrate 11p'. The remaining light-emitting chips 200 not irradiated with the laser L may be lifted up together with the substrate 11, and may be transferred to a desired different or same circuit substrate 11p' later.

[0138] In some exemplary embodiments, the surface of the top LED stack exposed by removing substrate 11 may be textured to balance the appearance of the light emitted by each light emitting stack.

[0139] 28, when the light emitting chip 200 is mounted on the circuit board 11p', a molding layer 91' may be formed to surround at least the side of the light emitting chip 200. According to an exemplary embodiment, the molding layer 91' may transmit a part of the light emitted from the light emitting chip 200, and may also reflect, diffract and / or absorb a part of the external light to prevent the external light from being reflected by the light emitting chip 200 toward a direction that may be visible to a user. The molding layer 91' may surround at least the side of the light emitting chip 200 to protect the light emitting chip 200 from external moisture and stress, and may also strengthen the structural configuration of the light emitting package to facilitate subsequent transfer and / or mounting processes.

[0140] According to the illustrated exemplary embodiment, the molding layer 91' may be formed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' of the light emitting chip 200, and may cover at least a part of the passivation layer 290. The molding layer 91' according to the exemplary embodiment may include an epoxy molding compound (EMC) and may be formed to have various colors, such as, but not limited to, black and transparent. For example, in some exemplary embodiments, the molding layer 91' may include a photosensitive polyimide dry film (PID). The molding layer 91' may be formed by various methods known in the art, such as a lamination method, a transfer molding method, and / or a printing method. For example, the molding layer 91' may be formed by a vacuum lamination process in which an organic polymer sheet is placed on the light emitting chip 200 and high temperature and high pressure are applied in a vacuum to improve light uniformity by providing a substantially planar top surface of the light emitting package. In some exemplary embodiments, molding layer 91' and passivation layer 290 may comprise substantially the same material or different materials.

[0141] 29, the circuit board 11p' may be cut in a desired configuration to provide light emitting packages, taking into consideration a final device in which the light emitting packages will be mounted, such as a display device. For example, the light emitting package 210 may include one or more light emitting chips 200 arranged in an n×m array, where n and m are natural numbers. Although FIG. 29 exemplarily illustrates a light emitting package including two light emitting chips 200 therein, the concept of the present invention is not limited to a specific number of light emitting chips 100 in the light emitting package.

[0142] According to the illustrated exemplary embodiment, the molding layer 91' may expose at least a portion of the light-emitting chip 200. For example, a portion of the light-emitting chip 200, such as the third light-emitting stack 40 in contact with the substrate 11, may be exposed from the molding layer 91' to further enhance the efficacy and color purity of the light emitted from the light-emitting chip 200. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the molding layer 91' may cover the portion of the light-emitting chip 200 in contact with the substrate 11.

[0143] 30 is a schematic cross-sectional view illustrating a manufacturing process of the light emitting package of FIG. 20 according to another exemplary embodiment.

[0144] Referring to FIG. 30, according to an exemplary embodiment, the molding layer 91' may be formed to cover the light emitting chip 200 mounted on the circuit board 11p' shown in FIG. 27. In this manner, the molding layer 91' may protect the light emitting chip 200 from external stress and the like, and may prevent external light from being reflected toward the user. In addition, the light transmittance may be controlled by adjusting the thickness of the molding layer 91' or forming the molding layer 91' from a material that provides a desired light transmittance. Thereafter, the circuit board 11p' may be cut into a desired shape in consideration of a final device in which the light emitting package is mounted, such as a display device, to provide a light emitting package such as the light emitting package 220 shown in FIG. 20. For example, the light emitting package 220 may include one or more light emitting chips 200 arranged in an n×m array, where n and m are natural numbers.

[0145] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description, and therefore, the inventive concept is not intended to be limited to such embodiments, but rather is intended to cover the broader scope of the appended claims and various obvious modifications and equivalents that will be apparent to those skilled in the art.

Claims

1. a first LED subunit having opposing first and second surfaces; a second LED subunit disposed on the second surface of the first LED subunit; a third LED subunit disposed on the second LED subunit; a plurality of connection electrodes having side surfaces and electrically connected to each of the first, second and third LED subunits, the plurality of connection electrodes covering at least one side surface of the first, second and third LED subunits; a first passivation layer surrounding at least side surfaces of the plurality of connection electrodes and having a portion covering at least a portion of the first surface of the first LED subunit; a substrate having opposing first and second surfaces, the first surface facing the first, second and third LED subunits; a plurality of first electrodes arranged on the first surface of the substrate corresponding to the plurality of connection electrodes and connected to the plurality of connection electrodes; Including, In a cross-sectional view, each of the plurality of connection electrodes has a first side surface facing a center of the first, second, and third LED subunits and a second side surface facing an opposite side to the first side surface; The first side and the second side have different lengths.

2. 10. The light emitting package of claim 1, wherein the portion of the first passivation layer covering the first surface of the first LED subunit has a thickness of less than about 100 μm.

3. The light emitting package of claim 1 , wherein the first passivation layer contacts the first surface of the first LED subunit.

4. a second electrode disposed on the second surface of the substrate and connected to the first electrode; 2. The light emitting package according to claim 1, wherein the second electrode includes a first portion overlapping at least one of the first, second and third LED subunits and having a first area, and a second portion not overlapping at least one of the first, second and third LED subunits and having a second area larger than the first area.

5. The light emitting package according to claim 1 , wherein at least one of the plurality of connecting electrodes has an angular shape.

6. The light emitting package according to claim 1 , wherein the first passivation layer is disposed between the plurality of connecting electrodes.

7. At least one of the plurality of connection electrodes has a first surface and a second surface facing each other, the first surface facing at least one of the first, second and third LED subunits; The light emitting package according to claim 1 , wherein the first surface of the connection electrode has an area larger than an area of ​​the second surface.

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