Solar Cells and Photovoltaic Systems

Abstract

To provide a solar cell causing less damage and recombination to a passivation structure, and having high photoelectric conversion efficiency while ensuring good electrical connection.SOLUTION: A solar cell includes: a substrate layer 10 including a first surface and a second surface arranged oppositely along a thickness direction thereof; a tunnel oxide layer 20, a first doped polysilicon layer 30, and a first passivation layer 40 sequentially arranged on the first surface of the substrate layer 10 in a direction gradually away from the substrate layer 10; and a first fine gate layer including a plurality of first fine gates 50 being sequentially arranged at intervals along a first direction x, at least one of the first fine gates 50 being arranged in first connection holes not shown, bottoms of the first connection holes being located in the first doped polysilicon layer 30, and the first fine gates 50 passing through the first connection holes corresponding thereto to be electrically connected to the first doped polysilicon layer 30.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the technical field of solar cells, and in particular to solar cells and Bright light Concerning electromotive force systems. [Background technology]

[0002] TOPCon cell (tunneling oxide layer passivation contact cell) is a solar cell that uses an ultra-thin oxide layer as the passivation layer structure. The ultra-thin tunneling oxide layer and one doped polysilicon thin layer jointly form a passivation contact structure, which can effectively reduce the surface recombination and metal contact recombination, provide good surface passivation for the back side of the silicon wafer, effectively reduce the back side recombination current density, and improve the photoelectric conversion efficiency of the cell.

[0003] Conventional TOPCon batteries expose some doped polysilicon layers by etching or laser ablation, and then fabricate electrodes to form ohmic contacts (or called electrical connections) with the doped polysilicon layers. However, the etching or laser ablation process causes relatively large damage to the passivation layer and anti-reflective layer, which significantly affects the performance improvement of TOPCon batteries. Summary of the Invention [Problem to be solved by the invention]

[0004] Based on this, the present application provides a solar cell and a solar cell having high photoelectric conversion efficiency by reducing damage and recombination to a passivation layer and an antireflection layer. Photovoltaic Systems to provide. [Means for solving the problem]

[0005] According to one aspect of the present application, there is provided a solar cell, comprising: a substrate layer including a first surface and a second surface disposed opposite to each other along a thickness direction of the substrate layer; a tunneling oxide layer, a first doped polysilicon layer, and a first passivation layer sequentially disposed on a first surface of the substrate layer in a direction gradually moving away from the substrate layer; a first fine gate layer including a plurality of first fine gates arranged sequentially at intervals along a first direction; At least one of the first micro-gates is provided in a first connection hole, a bottom of the first connection hole is located in the first doped polysilicon layer, each of the first micro-gates is electrically connected to the first doped polysilicon layer through a corresponding one of the first connection holes, and in the first direction, the width of each of the first connection holes is smaller than the width of the first micro-gate corresponding to the first connection hole.

[0007] In some embodiments thereof, the projected area of ​​each of the first contact holes on the first surface is independently 10 nm 2 ~10μm 2 It is.

[0008] In some embodiments thereof, the projected area on the first surface is less than 1 mm 2 The first fine gates per pixel are electrically connected to the first doped polysilicon layer via 10,000 to 100,000 of the first contact holes.

[0009] In some of the embodiments, the first passivation layer is provided with at least one second contact hole; each of the first fine gates is electrically connected to the first doped polysilicon layer through the corresponding second connection hole and the first connection hole, and in the first direction, the width of each of the second connection holes is equal to or smaller than the width of the first fine gate corresponding to the second connection hole; The projections of the first connection holes onto the first surface are all within the range of the projection of the second connection holes onto the first surface.

[0010] In some of the embodiments, the number of the second contact holes is smaller than the number of the first contact holes.

[0012] In some embodiments thereof, the projected area of ​​each of the second contact holes on the first surface is independently 10 nm 2 ~10μm 2 It is.

[0013] In some of the embodiments, the first passivation layer has a thickness of 40 nm to 100 nm.

[0014] In some of the embodiments, the first doped polysilicon layer has a thickness of 10 nm to 200 nm.

[0015] In some embodiments thereof, the solar cell further comprises a boron doped layer, a second passivation layer, and a second fine gate layer; The boron-doped layer and the second passivation layer are sequentially provided on a second surface of the substrate layer along a direction gradually moving away from the substrate layer, and the second fine gate layer includes a plurality of second fine gates sequentially arranged at intervals along a second direction; At least one of the second fine gates is provided in a third connection hole, the bottom of the third connection hole is located in the boron-doped layer, each second fine gate is electrically connected to the boron-doped layer through a corresponding one of the third connection holes, and in the second direction, the width of each of the third connection holes is smaller than the width of the second fine gate corresponding to the third connection hole.

[0017] In some embodiments thereof, the projected area of ​​each of the third contact holes on the second surface is independently 10 nm 2 ~10μm 2 It is.

[0018] In some embodiments, the projected area on the second surface is less than 1 mm 2The second fine gates per pixel are electrically connected to the boron-doped layer via 10,000 to 100,000 third contact holes.

[0019] In some of the embodiments, at least one fourth contact hole is provided in the second passivation layer, and each of the second fine gates is electrically connected to the boron-doped layer through the corresponding fourth contact hole and the third contact hole, and in the second direction, the width of each of the fourth contact holes is equal to or smaller than the width of the second fine gate corresponding to the third contact hole; The projections of the third contact holes onto the second surface are all within the range of the projection of the fourth contact hole onto the second surface.

[0020] In some of the embodiments, the number of the fourth contact holes is smaller than the number of the third contact holes.

[0022] In some embodiments thereof, the projected area of ​​each of the fourth contact holes on the second surface is independently 10 nm 2 ~10μm 2 It is.

[0023] In some of the embodiments, the second passivation layer has a thickness of 2 nm to 20 nm.

[0024] In some of these embodiments, the second fine gate and the substrate layer are separated by at least the boron doped layer.

[0025] In some of these embodiments, the solar cell further comprises an anti-reflective layer; The anti-reflection layer is provided on a side of the second passivation layer remote from the substrate layer.

[0026] In some of the embodiments, the antireflection layer has a thickness of 40 nm to 100 nm.

[0027] According to a second aspect, the present application further provides a method for manufacturing a solar cell, comprising: sequentially forming a tunneling oxide layer, a first doped polysilicon layer, and a first passivation layer on a first surface of a substrate layer; printing a first pattern on a surface of the first passivation layer remote from the substrate layer, the material of the first pattern including a first metal paste, the first pattern including a plurality of first gate stripes spaced apart from one another along a first direction; drying the first pattern; sintering the first pattern after drying to manufacture a first fine gate layer, the first fine gate layer including a plurality of first fine gates arranged in sequence at intervals along a first direction, each of the first fine gates corresponding to one of the first gate stripes; In the sintering process, the material of the first pattern corrodes the first passivation layer and the first doped polysilicon layer, and etches at least one first connection hole in the first passivation layer and the first doped polysilicon layer at a position corresponding to at least one first gate stripe, the bottom of the first connection hole is located in the first doped polysilicon layer, and each first fine gate among the manufactured first fine gates contacts the first doped polysilicon layer through its corresponding first connection hole.

[0028] In some of the embodiments, the peak temperature of the sintering process is 700°C to 900°C.

[0029] According to a third aspect, the present application further provides a photovoltaic system comprising a solar cell as described above or a solar cell manufactured by the method for manufacturing a solar cell as described above. Effect of the Invention

[0030] The present application has at least the following beneficial effects: In the solar cell provided in the embodiment of the present application, the first fine gate contacts the first doped polysilicon layer through a contact hole on the first passivation layer, and the dimensions of the first contact hole are both smaller than the first fine gate, so that damage to the passivation structure of the solar cell and recombination are small while ensuring good electrical contact, and compared with conventional solar cells, the solar cell provided in the embodiment of the present application has a high photoelectric conversion efficiency. [Brief description of the drawings]

[0031] [Figure 1] 1 is a structural schematic diagram of a solar cell according to an embodiment of the present application. [Diagram 2] 2 is a schematic plan view of the solar cell shown in FIG. 1 in a direction from a first surface to a second surface. [Diagram 3] 2 is a schematic plan view of the solar cell shown in FIG. 1 in a direction from the second surface to the first surface. [Figure 4] 1 is a structural schematic diagram of a solar cell according to an embodiment of the present application. [Diagram 5] 5(a) is a plan view of the lower part of the covered region of the second fine gate of the solar cell shown in FIG. 4, and (b) is a plan view of the lower part of the covered region of the first fine gate of the solar cell shown in FIG. [Figure 6] 1 is a structural schematic diagram of a solar cell according to an embodiment of the present application. [Figure 7] 7(a) is a plan view of the lower part of the covered region of the second fine gate of the solar cell shown in FIG. 6, and (b) is a plan view of the lower part of the covered region of the first fine gate of the solar cell shown in FIG. [Figure 8] 1 is a structural schematic diagram of a solar cell according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] In order to facilitate understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. However, the present application may be embodied in many different forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more complete understanding of the disclosure of the present application.

[0033] In the description of this application, the orientations or positional relationships indicated by terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, are based on the orientations or positional relationships shown in the drawings, are for convenience and simplification of the description of this application, and are not intended to indicate or imply that the devices or elements shown have a particular orientation or must be constructed and operated in a particular orientation, and therefore cannot be understood as limiting this application.

[0034] It should be noted that the terms "first" and "second" are merely for descriptive purposes and should not be understood to indicate or imply a relative importance or number of technical features shown. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the present description, "plurality" means at least two, e.g., two, three, etc., unless otherwise specified.

[0035] In this application, the terms "attached," "coupled," "connected," "fixed," and the like, unless otherwise expressly specified and limited, should be understood in a broad sense, and for example, unless otherwise expressly limited, may be fixed connection, detachable connection, or integral, may be mechanical connection or electrical connection, may be direct connection or indirect connection through an intervening medium, may be internal communication between two elements, or may be a relationship of interaction between two elements. The specific meaning of the above terms in this application can be understood by those skilled in the art according to the specific situation.

[0036] It should be noted that when an element is referred to as "anchored" to another element, it may be directly on the other element, or there may be intervening elements present. When an element is considered to be "connected" to another element, it may be directly connected to the other element, or there may be intervening elements present at the same time.

[0037] In this application, unless expressly specified and limited otherwise, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Furthermore, a first feature being "above," "above," and "on top of" a second feature indicates that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal height than the second feature. A first feature being "below," "below," and "on the bottom of" a second feature indicates that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal height than the second feature.

[0038] Furthermore, the drawings are not drawn to scale, and the relative dimensions of each element are merely illustrated in the drawings as examples to facilitate understanding of the present application, but are not necessarily drawn to true scale, and the scale of the drawings is not intended to be limiting of the present application.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the present application. The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0040] In this application, ohmic contact has the same meaning as electrical connection, and preferably the electrical connection is a physical contact, i.e., electrical connection refers to a circuit connection that is a physical contact, rather than a wireless communication signal connection.

[0041] 1 and 2, one embodiment of the present application provides a solar cell 1, which includes a substrate layer 10, a tunneling oxide layer 20, a first doped polysilicon layer 30, a first passivation layer 40 and a first fine gate layer 50; Here, the substrate layer 10 includes a first surface and a second surface that are provided opposite to each other along a thickness direction of the substrate layer 10, a tunneling oxide layer 20, a first doped polysilicon layer 30 and a first passivation layer 40 are successively provided on a first surface of the substrate layer 10 in a direction gradually moving away from the substrate layer 10; The first fine gate layer includes a plurality of first fine gates 50 arranged in sequence at intervals along a first direction x; At least one first fine gate 50 is provided in a first connection hole, the bottom of the first connection hole is located in the first doped polysilicon layer 30 (the first fine gate and the first connection hole form a damascene structure, so the first connection hole is not shown in Figures 1 to 3), each first fine gate 50 is electrically connected to the first doped polysilicon layer 30 through its corresponding first connection hole, and in the first direction x, the width W1 of each first connection hole is smaller than the width W2 of the first fine gate 50 corresponding to the first connection hole.

[0042] As can be understood, in the present application, the first contact hole penetrates the entire first passivation layer 40 and also penetrates a part of the first doped polysilicon layer 30 along the thickness direction.

[0043] In the above-mentioned solar cell 1, the first fine gate 50 is electrically connected to the first doped polysilicon layer 30 through the first connection hole, and the dimensions of the first connection hole are both smaller than the first fine gate 50. While ensuring good electrical connection, damage to and recombination of the passivation structure of the solar cell 1 is small, and the first fine gate 50 does not penetrate the first doped polysilicon layer 30 to connect to the tunneling oxide layer 20, which further reduces damage to the passivation structure of the solar cell 1 caused by the first fine gate layer, and further avoids damage and recombination of the passivation structure. Compared with the conventional solar cell 1, the solar cell 1 provided in the embodiment of the present application has a high photoelectric conversion efficiency.

[0044] In some of the embodiments, the projected areas of the first contact holes on the first surface of the substrate layer 10 are independent of each other. 1 0nm 2 ~10μm 2 The projected area of ​​the first contact hole on the first surface of the substrate layer 10 is Within this range By controlling the size of the first contact hole to be small, damage and recombination to the first passivation layer 40 can be further reduced while ensuring good ohmic contact / electrical connection between the first fine gate 50 and the first doped polysilicon layer 30, and photoelectric conversion efficiency can be improved compared to conventional solar cells. Optionally, the projected area of ​​each first contact hole on the first surface of the substrate layer 10 can be within 10 nm 2 , 50 nm 2 , 100 nm 2 , 500 nm 2 , 0.1 μm 2 , 1 μm 2 , 10μm 2 or within a range of any of the above values.

[0045] In some of the embodiments, the projected area of ​​the substrate layer 10 on the first surface is 1 mm 2 The first fine gate 50 per one of the first doped polysilicon layers 30 is electrically connected to the first doped polysilicon layer 30 via 10,000 to 100,000 first contact holes.2 The number of first contact holes electrically connecting the first fine gate 50 per one to the first doped polysilicon layer 30 is within a range of 1, 10, 100, 200, 500, 1,000, 2,000, 3,000, 5,000, 8,000, 10,000, 20,000, 30,000, 50,000, 80,000, 100,000 or any number greater than or equal to 1.

[0046] In some embodiments, the thickness of the first passivation layer 40 is between 40 nm and 100 nm. Optionally, the thickness of the first passivation layer 40 is within a range of 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any value greater than or equal to 40 nm.

[0047] In some embodiments, the thickness of the first doped polysilicon layer 30 is between 10 nm and 200 nm. Optionally, the thickness of the first doped polysilicon layer 30 is within a range of 10 nm, 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, or any value greater than or equal to 10 nm.

[0048] 1 and 3, in some embodiments thereof, the solar cell 1 further includes a boron doped layer 60, a second passivation layer 70, and a second fine gate layer.

[0049] The boron-doped layer 60 and the second passivation layer 70 are sequentially provided on the second surface of the substrate layer 10 along a direction gradually moving away from the substrate layer 10, and the second fine gate layer includes a plurality of second fine gates 80 sequentially arranged at intervals along the second direction y.

[0050] In some embodiments, the thickness of the second passivation layer 70 is between 2 nm and 20 nm. Optionally, the thickness of the second passivation layer 70 is within a range of 2 nm, 5 nm, 10 nm, 15 nm, 20 nm, or any value greater than or equal to 2 nm.

[0051] 4 to 8, in some embodiments, at least one second contact hole is provided in the first passivation layer 40 (the first fine gates 50 and the second contact holes form a damascene structure, so the second contact hole is not shown in FIGS. 4 to 8), and each first fine gate 50 is electrically connected to the first doped polysilicon layer 30 through its corresponding second contact hole and first contact hole, and in the first direction, the width W02 of each second contact hole is equal to or smaller than the width W2 of the first fine gates 50 corresponding to the second contact hole; The projections of each of the first contact holes onto the first surface are all within the range of the projection of the second contact hole onto the first surface.

[0052] As will be appreciated, along the thickness direction, the second connection hole penetrates some or all of the first passivation layer 40 but does not penetrate to the first doped polysilicon layer 30, i.e., once the first fine gate is removed, when viewed from the first direction to the second direction, the second connection hole includes at least one first connection hole, and preferably the second connection hole includes multiple first connection holes.

[0053] By providing the second connection hole, the first fine gate 50 is only partially embedded in the first passivation layer 40 or covers the surface of the first passivation layer 40, except for the portion electrically connected to the first doped polysilicon layer 30, so that damage to the first passivation layer 40 by the first fine gate 50 is small.

[0054] In some of the embodiments, the number of the second contact holes is smaller than the number of the first contact holes.

[0055] In some embodiments, the projected areas of the second contact holes on the first surface of the substrate layer 10 are independent of each other. 1 0nm 2 ~10μm 2 The projected area of ​​the second contact hole on the first surface of the substrate layer 10 is Within this rangeBy controlling the size of the second contact hole to be smaller (larger than the first contact hole), damage to and recombination in the first passivation layer 40 can be further reduced while still ensuring good ohmic contact / electrical connection between the first fine gate 50 and the first doped polysilicon layer 30, and photoelectric conversion efficiency can be improved compared to conventional solar cells. Optionally, the projected area of ​​each second contact hole on the first surface of the substrate layer 10 can be less than 10 nm 2 , 20nm 2 , 50 nm 2 , 100 nm 2 , 500 nm 2 , 0.1 μm 2 , 1 μm 2 , 2 μm 2 , 3 μm 2 , 10μm 2 or within a range of any of the above values.

[0056] In some of the embodiments, the projected area of ​​the substrate layer 10 on the first surface is 1 mm 2 The first fine gate 50 per one of the first doped polysilicon layers 30 is electrically connected to the first doped polysilicon layer 30 via 10,000 to 100,000 second contact holes. 2 The number of second contact holes electrically connecting the first fine gate 50 to the first doped polysilicon layer 30 per one is within a range of 1, 2, 10, 100, 200, 500, 1,000, 2,000, 3,000, 5,000, 8,000, 10,000, 20,000, 30,000, 50,000, 80,000, 100,000 or any number greater than or equal to 1.

[0057] 1 to 8, in some embodiments, for a solar cell 1 including a boron-doped layer 60, a second passivation layer 70, and a second fine gate layer, the boron-doped layer 60 and the second passivation layer 70 are sequentially provided on a second surface of the substrate layer 10 along a direction gradually moving away from the substrate layer 10, and the second fine gate layer includes a plurality of second fine gates 80 sequentially arranged at intervals along a second direction y; At least one second fine gate 80 is provided in a third contact hole, the bottom of the third contact hole is located in the boron-doped layer 60 (the second fine gate and the third contact hole form a damascene structure, so the third contact hole is not shown in Figs. 1 to 3), each second fine gate 80 is electrically connected to the boron-doped layer 60 through a corresponding third contact hole, and in the second direction y, the width W3 of each third contact hole is smaller than the width W4 of the second fine gate 80 corresponding to the third contact hole. In some embodiments shown in Fig. 1, the first direction x and the second direction y are the same. It will be understood that in some other embodiments, the first direction x and the second direction y may be different. As an example, the first direction x may be perpendicular to the second direction y.

[0058] As can be seen, the third contact hole penetrates the entire second passivation layer 70 and a portion of the boron-doped layer 60 along the thickness direction.

[0059] In some of the embodiments, the projected areas of the third contact holes on the second surface of the substrate layer 10 are independent of each other. 1 0nm 2 ~10μm 2 The projected area of ​​the third contact hole on the second surface of the substrate layer 10 is Within this range By controlling the size of the third contact hole to be small, damage to and recombination in the second passivation layer 70 can be further reduced while ensuring good ohmic contact / electrical connection between the second fine gate 80 and the boron-doped layer 60, and the photoelectric conversion efficiency can be improved compared to conventional solar cells. Optionally, the projected area of ​​each third contact hole on the second surface of the substrate layer 10 can be within 10 nm 2 , 50 nm 2 , 100 nm 2 , 500 nm 2 , 0.1 μm 2 , 1 μm 2 , 10μm 2 or within a range of any of the above values.

[0060] In some of the embodiments, the projected area of ​​the substrate layer 10 on the second surface is 1 mm 2 The second fine gate 80 per second is electrically connected to the boron-doped layer 60 via 10,000 to 100,000 third contact holes. 2 The number of third contact holes electrically connecting the second fine gate 80 to the boron-doped layer 60 per one is within a range of 1, 10, 100, 200, 500, 1,000, 2,000, 3,000, 5,000, 8,000, 10,000, 20,000, 30,000, 50,000, 80,000, 100,000 or any numerical value greater than or equal to 1.

[0061] 4 to 8, in some embodiments, at least one fourth contact hole is provided in the second passivation layer 70 (the second fine gates and the fourth contact hole form a damascene structure, so the fourth contact hole is not shown in FIGS. 4 to 8), and each second fine gate 80 is electrically connected to the boron-doped layer 60 through its corresponding fourth contact hole and third contact hole, and in the second direction y, the width W04 of each fourth contact hole is equal to or smaller than the width W4 of the second fine gate 80 corresponding to the third contact hole; The projections of the third contact holes onto the second surface of the substrate layer 10 are all within the range of the projection of the fourth contact hole onto the second surface of the substrate layer 10 .

[0062] As will be appreciated, along the thickness direction, the fourth connection hole penetrates some or all of the second passivation layer 70 but does not penetrate to the boron-doped layer 60, i.e., once the second fine gate is removed, when viewed from the second direction to the first direction, the fourth connection hole includes at least one third connection hole, and preferably the fourth connection hole includes multiple third connection holes.

[0063] By providing the fourth connection hole, the second fine gate 80, except for the portion electrically connected to the boron-doped layer 60, is only partially embedded in the second passivation layer 70 or is located on the surface side of the second passivation layer 70 away from the substrate layer 10, so that damage to the second passivation layer 70 by the second fine gate 80 is small.

[0064] In some of the embodiments, the projected areas of the fourth contact holes on the second surface of the substrate layer 10 are independent of each other. 1 0nm 2 ~10μm 2 The projected area of ​​the fourth contact hole on the second surface of the substrate layer 10 is Within this range By controlling the size of the fourth contact hole to be smaller (larger than the third contact hole), damage to and recombination in the second passivation layer 70 can be further reduced while still ensuring good ohmic contact / electrical connection between the second fine gate 80 and the boron-doped layer 60, thereby improving the photoelectric conversion efficiency compared to conventional solar cells. Optionally, the projected area of ​​each fourth contact hole on the second surface of the substrate layer 10 can be less than 10 nm 2 , 20nm 2 , 50 nm 2 , 100 nm 2 , 500 nm 2 , 0.1 μm 2 , 1 μm 2 , 2 μm 2 , 3 μm 2 , 10μm 2 or within a range of any of the above values.

[0065] In some of the embodiments, the projected area of ​​the substrate layer 10 on the second surface is 1 mm 2 The second fine gate 80 per second is electrically connected to the boron-doped layer 60 via 10,000 to 100,000 fourth contact holes. 2The number of third contact holes electrically connecting the second fine gate 80 to the boron-doped layer 60 per one is within a range of 1, 10, 100, 200, 500, 1,000, 2,000, 3,000, 5,000, 8,000, 10,000, 20,000, 30,000, 50,000, 80,000, 100,000 or any numerical value greater than or equal to 1.

[0066] In some embodiments, the thickness of the second passivation layer 70 is between 2 nm and 20 nm. Optionally, the thickness of the second passivation layer 70 is within a range of 2 nm, 5 nm, 10 nm, 15 nm, 20 nm, or any value greater than or equal to 2 nm.

[0067] 1 to 8, in some embodiments, the solar cell 1 further includes an anti-reflection layer 90, which is provided on the side of the second passivation layer 70 away from the substrate layer 10.

[0068] In some embodiments thereof, the thickness of the anti-reflective layer 90 is between 40 nm and 100 nm. Optionally, the thickness of the anti-reflective layer 90 is within a range of 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any value greater than or equal to 40 nm.

[0069] As will be understood, a solar cell including an anti-reflection layer 90 may or may not have a connection hole, and in an embodiment including a connection hole, the concept of providing the connection hole is similar to that of the fourth connection hole in the second passivation layer 70, and therefore is also called a fourth connection hole, and the fourth connection hole in the anti-reflection layer 90 penetrates part or all of the anti-reflection layer 90 along the thickness direction.

[0070] Referring to the above description of the fourth contact hole in the second passivation layer, at least one fourth contact hole is provided in the anti-reflection layer 90 (the second fine gates and the fourth contact hole form a damascene structure, so the fourth contact hole is not shown in FIGS. 4 to 8), and each second fine gate 80 is electrically connected to the boron-doped layer 60 through its corresponding fourth contact hole and third contact hole, and in the second direction y, the width W04 of the fourth contact hole in each anti-reflection layer 90 is equal to or smaller than the width W4 of the second fine gate 80 corresponding to the third contact hole. In this way, damage to the anti-reflection layer 90 caused by the second fine gate 80 is small, and damage to the passivation structure of the solar cell 1 and recombination can be further reduced.

[0071] 4 to 8, in some of the embodiments, the fourth contact hole penetrates through a part of the antireflection layer 90 and the entire second passivation layer 70 along the thickness direction.

[0072] Referring to Figures 4 to 8, in some embodiments, at least one fifth hole is provided in the first passivation layer 40, the bottom of the fifth hole is located in the first passivation layer 40, and the width W05 of each fifth hole is smaller than the width W2 of the first fine gate 50 corresponding to the first connection hole.

[0073] Referring to FIG. 4, in some embodiments, at least one sixth hole is provided in the second passivation layer 70, the bottom of the sixth hole is located in the second passivation layer 70, and the width W06 of each sixth hole is smaller than the width W4 of the second fine gate 80 corresponding to the third connection hole.

[0074] Referring to FIG. 6, in some embodiments, at least one sixth hole is provided in the anti-reflective layer 90, the bottom of the sixth hole is located in the anti-reflective layer 90, and the width W06 of each sixth hole is smaller than the width W4 of the second fine gate 80 corresponding to the third connection hole.

[0075] Referring to FIG. 8, in some embodiments, at least one sixth hole is provided in the second passivation layer 70 and the anti-reflective layer 90, the bottom of the sixth hole is located in the second passivation layer 70, and the width W06 of each sixth hole is smaller than the width W4 of the second fine gate 80 corresponding to the third connection hole.

[0076] In some of the embodiments, the solar cell 1 further includes at least one first main gate (not shown), which is connected to each of the first fine gates 50 in the first fine gate layer.

[0077] In some of the embodiments, the solar cell 1 further includes at least one second main gate (not shown), which is connected to each second fine gate 80 in the second fine gate layer.

[0078] In some of the embodiments, the solar cell 1 is a TOPCon cell.

[0079] In some of the embodiments, the substrate layer 10 is an N-type single crystal silicon wafer.

[0080] In some embodiments, the second surface of the substrate layer 10 has a textured structure. The textured second surface can improve the light utilization rate of the solar cell 1 and increase the photoelectric conversion efficiency.

[0081] In some of these embodiments, the tunneling oxide layer 20 is an ultra-thin silicon oxide film.

[0082] In some of these embodiments, the material of the first passivation layer 40 includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. In some of these embodiments, the material of the first passivation layer 40 is silicon nitride.

[0083] In some of the embodiments, the material of the first doped polysilicon layer 30 is phosphorus doped polysilicon.

[0084] In some of the embodiments, the second passivation layer 70 is an alumina passivation film.

[0085] In some of these embodiments, the material of the antireflective layer 90 includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. In some of these embodiments, the material of the antireflective layer 90 is silicon nitride.

[0086] In some of the embodiments, the first micro-gate 50 includes at least one of a metal element and a metal alloy. Optionally, the first micro-gate 50 includes one of a silver element, an aluminum element, and a silver-aluminum alloy. Further, the first main gate includes a silver element.

[0087] In some of the embodiments, the second micro-gate 80 includes at least one of a metal element and a metal alloy. Optionally, the second micro-gate 80 includes one of a silver element, an aluminum element, and a silver-aluminum alloy. Further, the second micro-gate 80 includes a silver-aluminum alloy.

[0088] According to a second aspect, the present application further provides a method for manufacturing a solar cell 1, comprising the following steps S110 to S140.

[0089] S110: Sequentially forming a tunneling oxide layer 20, a first doped polysilicon layer 30 and a first passivation layer 40 on a first surface of a substrate layer 10.

[0090] S120: Print a first pattern on a surface of the first passivation layer 40 facing away from the substrate layer 10, the material of the first pattern including a first metal paste, and the first pattern including a plurality of first gate stripes arranged sequentially at intervals along a first direction.

[0091] S130: The first pattern is dried.

[0092] S140: Sinter the first pattern after the drying process to produce a first fine gate layer, the first fine gate layer 50 including a plurality of first fine gates 50 arranged sequentially at intervals along a first direction, each first fine gate 50 corresponding to one first gate stripe.

[0093] Here, in the sintering process, the material of the first pattern corrodes the first passivation layer 40 and the first doped polysilicon layer 30, and etches at least one first connection hole in the first passivation layer 40 and the first doped polysilicon layer 30 at a position corresponding to at least one first gate stripe, the bottom of the first connection hole is located in the first doped polysilicon layer 30, and each first fine gate 50 among the manufactured first fine gates 50 contacts the first doped polysilicon layer 30 through its corresponding first connection hole.

[0094] In the manufacturing method of the above-mentioned solar cell 1, the manufacturing material of the fine gate is corroded into the first passivation layer 40 in a sintering process to form a first connection hole, so that the first fine gate 50 penetrates the first connection hole and contacts the first doped polysilicon layer 30. There is no need to remove the first passivation layer 40 by etching or laser ablation processing during the manufacturing process. Ohmic contact between the first fine gate 50 and the first doped polysilicon layer 30 can be achieved by sintering. Damage and recombination to the first passivation layer 40 during manufacturing is small, and the manufactured solar cell 1 has high photoelectric conversion efficiency.

[0095] In some embodiments, the peak sintering temperature is between 700° C. and 900° C. Optionally, the peak sintering temperature is 700° C., 750° C., 800° C., 850° C., 900° C., or any value in the range above.

[0096] In some of the embodiments, before step S120, Step S114: printing a first main gate pattern on the surface of the first passivation layer 40 away from the substrate layer 10; and Step S116 of drying the first main gate pattern.

[0097] In some of the embodiments, before step S120, The method includes a step S210 of sequentially forming a boron-doped layer 60 and a second passivation layer 70 on a second surface of the substrate layer 10.

[0098] In some of the embodiments, step S112 further includes forming an anti-reflection layer 90 on a surface of the second passivation layer 70.

[0099] In some of the embodiments, before step S140, Step S220 of printing a second pattern on a surface of the second passivation layer 70 or the anti-reflection layer 90 away from the substrate layer 10, the material of the second pattern including a second metal paste, the second pattern including a plurality of second gate stripes arranged sequentially at intervals along a second direction; and a step S230 of drying the second pattern.

[0100] In some of the embodiments, before step S220, Step S212: printing a second main gate pattern on the surface of the second passivation layer 70 or the anti-reflection layer 90 away from the substrate layer 10; and a step S214 of drying the second main gate pattern.

[0101] In some of the embodiments, in step S140, the first pattern after drying is sintered and the second pattern after drying is sintered at the same time to produce a second fine gate layer.

[0102] By way of example, the present application provides a method for manufacturing a TOPCon battery, (1) cleaning and texturing an N-type monocrystalline silicon wafer; (2) treating a front surface of an N-type monocrystalline silicon wafer with a boron diffusion process; (3) backside cleaning to remove the borosilicate glass (BSG) layer; (4) producing an ultra-thin silicon oxide layer by backside oxidation, depositing phosphorus-doped polysilicon, and forming an n+ polysilicon layer; (5) depositing, successively, a passivation layer and an anti-reflective layer on the front surface; (6) depositing a passivation layer on the back surface; (7) screen printing a rear main gate electrode and drying it, and then printing a rear fine gate electrode and drying it; (8) screen printing a front main gate electrode and drying, then printing a front fine gate electrode and drying; (9) sintering the silicon wafer on which the main gate and the fine gate electrode are printed, and controlling the peak temperature of the sintering process to 700°C to 900°C to manufacture a solar cell; The method includes test screening (10) the solar cells manufactured in step (9).

[0103] According to a third aspect, the present application further provides a photovoltaic system comprising the solar cell 1 described above or the solar cell 1 manufactured by the method for manufacturing the solar cell 1 described above.

[0104] The photovoltaic system can be applied to photovoltaic stations such as ground power stations, roof power stations, and water power stations, and can also be applied to equipment or devices that generate electricity using solar energy, such as consumer solar power sources, solar street lights, solar automobiles, and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited thereto, that is, the photovoltaic system can be applied to any field that requires photovoltaic power. Taking a photovoltaic system network as an example, the photovoltaic system can include a photovoltaic array, a convergence box, and an inverter, and the photovoltaic array can be a combination of an array of a plurality of solar cells 1, for example, a plurality of solar cells 1 can constitute a plurality of photovoltaic arrays, the photovoltaic arrays are connected to a convergence box, and the convergence box can combine the currents generated by the photovoltaic arrays, and the combined current is converted into an AC current required by the commercial power grid through an inverter, and then connected to the commercial power grid to realize the supply of solar energy.

[0105] The following is a specific example.

[0106] Example 1 This embodiment provides a solar cell 1, the structure of which is shown in Figures 1 to 3. The solar cell 1 includes a substrate layer 10 (N-type single crystal silicon wafer), a tunneling oxide layer 20, an n+ polysilicon layer, a first passivation layer 40 (silicon nitride), a boron-doped layer 60 (p-type emitter), a second passivation layer 70 (aluminum oxide) and an anti-reflection layer 90 (silicon nitride).

[0107] A tunneling oxide layer 20, an n+ polysilicon layer and a first passivation layer 40 (silicon nitride) are sequentially provided on a first surface of the substrate layer 10 in a direction gradually moving away from the substrate layer 10.

[0108] A boron doped layer 60 (p-type emitter), a second passivation layer 70 (aluminum oxide) and an anti-reflective layer 90 (silicon nitride) are sequentially provided on the second surface of the substrate layer 10 in a direction gradually moving away from the substrate layer 10.

[0109] A chip having the above structure is manufactured by sequentially subjecting the substrate layer 10 to processes such as cleaning and texturing, front boron diffusion, backside cleaning, backside deposition of silica and polysilicon, backside phosphorus diffusion, cleaning, frontside plating, and backside plating.

[0110] The solar cell 1 of this embodiment further includes a front main gate, a front fine gate, a back main gate, and a back fine gate. In the first direction x, a plurality of back fine gates are provided on the surface of the first passivation layer 40, which are arranged in sequence at intervals along the first direction x. In the second direction y, a plurality of front fine gates are provided on the surface of the anti-reflection layer 90, which are arranged in sequence at intervals along the first direction y.

[0111] The first passivation layer 40 is provided with at least one first contact hole at a position corresponding to the back surface fine gate, the back surface fine gate is electrically connected to the first doped polysilicon layer 30 through the first contact hole, and in the first direction x, the width W1 of the contact hole is smaller than the width W2 of the back surface fine gate. The back surface main gate is connected to the back surface fine gate. The projection area of ​​the first contact hole on the first surface of the substrate layer 10 is 10 nm 2 ~10μm 2 It is.

[0112] The anti-reflection layer 90 and the second passivation layer 70 are each provided with at least one third contact hole at a position corresponding to the front fine gate, the front fine gate is electrically connected to the boron-doped layer 60 through the third contact hole, and in the second direction y, the width W3 of the third contact hole is smaller than the width W4 of the front fine gate. The front main gate is connected to the front fine gate. The projection area of ​​the third contact hole on the second surface of the substrate layer 10 is 10 nm 2 ~10μm 2 It is.

[0113] Specifically, the manufacturing process of the front main gate, the front fine gate, the back main gate and the back fine gate in the above solar cell includes: (1) Screen-print a main gate silver paste on the back surface of a silicon wafer to produce a back main gate electrode and dry it. Then, print a fine gate silver paste on the back surface to produce a back fine gate electrode and dry it. (2) Screen-print the main gate paste on the front side of the silicon wafer to produce a front main gate electrode and dry it. Then, print the fine gate paste on the front side to produce a front fine gate electrode and dry it. (3) The battery with electrodes printed on both sides is sintered, and the temperature is increased to 700°C or higher at a rate of more than 50°C / min, and then decreased to room temperature at a rate of more than 50°C / min to obtain the solar cell of this embodiment.

[0114] Comparative Example 1 The solar cell provided in this Comparative Example has the same chip structure as that of Example 1. The difference from Example 1 is that the structures of the front fine gate and the back fine gate are different.

[0115] In the solar cell of this comparative example, The first passivation layer has connection grooves at positions corresponding to the backside fine gates, the backside fine gates are connected to the first doped polysilicon layer through the connection grooves, and the width of the connection grooves is equal to the width of the backside fine gates, that is, in the regions corresponding to the backside fine gates, the surface of the first doped polysilicon layer is not covered with the first passivation layer. The backside main gate is connected to the backside fine gates.

[0116] The anti-reflection layer and the second passivation layer are provided with a connecting groove at a position corresponding to the front fine gate, the front fine gate is connected to the boron-doped layer through the connecting groove, and the width of the connecting groove is equal to the width of the front fine gate, that is, in the region corresponding to the front fine gate, the surface of the boron-doped layer is not covered by the second passivation layer and the anti-reflection layer. The front main gate is connected to the front fine gate.

[0117] Specifically, the manufacturing process of the front main gate, the front fine gate, the back main gate and the back fine gate in the above solar cell includes: (1) A backside main gate electrode is formed by screen printing on the backside of a silicon wafer and dried. Then, a backside fine gate electrode is formed by screen printing on the backside and dried. (2) Screen print the paste on the front side of the chip to produce the front main gate electrode and dry it. Then, print the paste on the front side to produce the front fine gate electrode and dry it. (3) The chip with electrodes printed on both sides is sintered, heated to 800°C at 1500°C / min and held at that temperature for 1 minute, and then cooled to 25°C at 2500°C / min to obtain the solar cell of this embodiment.

[0118] Electrical performance tests of the solar cells of Example 1 and Comparative Example 1 showed that the mass production average efficiency of the solar cell of Example 1 was 25.5%, and that the solar cell of Example 1 had an open circuit voltage that was improved by 2 mV, a fill factor that was improved by 0.1%, and a cell photoelectric conversion efficiency that was improved by 0.1%, compared to the solar cell of Comparative Example 1.

[0119] The technical features of the above-described embodiments may be combined in any combination. For the sake of brevity, all possible combinations of the technical features in the above embodiments have not been described. However, as long as there is no contradiction in the combinations of these technical features, they should all be considered to be within the scope of the present specification.

[0120] The above-mentioned examples merely represent some embodiments of the present application, and are convenient for concretely and in detail understanding of the technical solution of the present application, but cannot be understood as limiting the scope of protection of the invention patent. It should be pointed out that those skilled in the art can make some modifications and improvements without departing from the concept of the present application, which are within the scope of protection of the present application. It should be understood that any technical solution obtained by those skilled in the art through logical analysis, reasoning or limited testing based on the technical solution provided in this application is within the scope of protection of the appended claims described in this application. Therefore, the scope of protection of the present patent should be based on the content of the appended claims, and the specification and the accompanying drawings can be used to interpret the content of the appended claims. [Explanation of symbols]

[0121] 1 solar cell, 10 substrate layer, 20 tunneling oxide layer, 30 first doped polysilicon layer, 40 first passivation layer, 50 first fine gate, 501 first fine gate corresponding to second contact hole, 502 first fine gate corresponding to fifth hole, 60 boron doped layer, 70 second passivation layer, 80 second fine gate, 801 second fine gate corresponding to fourth contact hole, 802 second fine gate corresponding to sixth hole, 90 anti-reflection layer

Claims

1. A solar cell comprising: a substrate layer including a first surface and a second surface disposed opposite to each other along a thickness direction of the substrate layer; a tunneling oxide layer, a first doped polysilicon layer, and a first passivation layer sequentially disposed on a first surface of the substrate layer in a direction gradually moving away from the substrate layer; a first fine gate layer including a plurality of first fine gates arranged sequentially at intervals along a first direction; at least one first connection hole is provided in the first passivation layer and the first doped polysilicon layer, the first connection hole penetrates the entire first passivation layer and penetrates a part of the first doped polysilicon layer along a thickness direction, the bottom of the first connection hole is located in the first doped polysilicon layer, each of the first fine gates is electrically connected to the first doped polysilicon layer through a corresponding one of the first connection holes, and in the first direction, the width of each of the first connection holes is smaller than the width of the first fine gate corresponding to the first connection hole; The projected area of ​​each of the first contact holes on the first surface is independently 10 nm 2 ~10μm 2 and at least one first auxiliary hole is provided in the first passivation layer, a bottom of the first auxiliary hole is located in the first passivation layer, and a width of each of the first auxiliary holes is smaller than a width of a first fine gate corresponding to the first connection hole; further comprising a boron doped layer, a second passivation layer, an anti-reflective layer and a second fine gate layer; the boron-doped layer and the second passivation layer are sequentially provided on a second surface of the substrate layer along a direction gradually moving away from the substrate layer, the anti-reflection layer is provided on a side of the second passivation layer moving away from the substrate layer, and the second fine gate layer includes a plurality of second fine gates sequentially arranged at intervals along a second direction; at least one third connection hole is provided in the second passivation layer and the boron-doped layer, the third connection hole penetrates the entire second passivation layer and penetrates a part of the boron-doped layer along a thickness direction, the bottom of the third connection hole is located in the boron-doped layer, each of the second fine gates is electrically connected to the boron-doped layer through the corresponding third connection hole, and in the second direction, the width of each of the third connection holes is smaller than the width of the second fine gate corresponding to the third connection hole; at least one second auxiliary hole is provided in the antireflection layer, a bottom of the second auxiliary hole is located in the antireflection layer, and a width of each of the second auxiliary holes is smaller than a width of a second fine gate corresponding to the third connection hole; A solar cell characterized by:

2. The projected area on the first surface is 1 mm 2 the first fine gate per one is electrically connected to the first doped polysilicon layer via 10,000 to 100,000 of the first contact holes; The solar cell according to claim 1 .

3. At least one second connection hole is provided in the first passivation layer, and each of the first fine gates is electrically connected to the first doped polysilicon layer through the corresponding second connection hole and the first connection hole, and in the first direction, the width of each of the second connection holes is equal to or smaller than the width of the first fine gate corresponding to the second connection hole; a projection of each of the first connection holes onto the first surface is within a projection range of the second connection hole onto the first surface; The solar cell according to claim 1 .

4. the number of the second connection holes is smaller than the number of the first connection holes; The solar cell according to claim 3 .

5. (1) the thickness of the first passivation layer is 40 nm to 100 nm; and (2) the thickness of the first doped polysilicon layer is 10 nm to 200 nm; The solar cell according to claim 1 .

6. The projected area of ​​each of the third contact holes on the second surface is independently 10 nm 2 ~10μm 2 That is, The solar cell according to claim 1 .

7. The projected area on the second surface is 1 mm 2 the second fine gate is electrically connected to the boron-doped layer via 10,000 to 100,000 third contact holes. The solar cell according to claim 1 .

8. at least one fourth connection hole is provided in the second passivation layer, each of the second fine gates is electrically connected to the boron-doped layer through the corresponding fourth connection hole and the third connection hole, and in the second direction, the width of each of the fourth connection holes is equal to or smaller than the width of the second fine gate corresponding to the third connection hole; a projection of each of the third connection holes onto the second surface is within a projection range of the fourth connection hole onto the second surface; The solar cell according to claim 1 .

9. The thickness of the second passivation layer is 2 nm to 20 nm. The solar cell according to claim 1 .

10. The thickness of the anti-reflection layer is 40 nm to 100 nm. The solar cell according to claim 1 .

11. The substrate layer is an N-type single crystal silicon wafer. The solar cell according to any one of claims 1 to 5.

12. 1. A photovoltaic system comprising: A photovoltaic system comprising a solar cell according to any one of claims 1 to 5.

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