Semiconductor Device

Abstract

A semiconductor device (90) comprises, in this order: first to third channel layers (41-43) comprising group III-V semiconductors containing Fe and C; and a barrier layer (50) comprising a group III-V semiconductor having a bandgap wider than the bandgap of the third channel layer (43). A concentration profile satisfies the following conditions: a) the Fe concentration of the second channel layer (42) and the third channel layer (43) gradually decreases toward the barrier layer (50); b) the maximum value of the C concentration of the third channel layer (43) is higher than the average value of the C concentration of the second channel layer (42); and c) the maximum value of the C concentration of the third channel layer (43) is lower than the maximum value of the sum of the Fe concentration and the C concentration of the first channel layer (41).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device using III-V group semiconductors. [Background technology]

[0002] III-V semiconductors such as GaN (gallium nitride) are sometimes used in semiconductor devices such as HEMTs (High Electron Mobility Transistors) for high frequency applications. HEMTs are required to have good pinch-off characteristics, i.e., low leakage current (hereinafter also simply referred to as "leakage current") between the source and drain in the gate-off state. In order to suppress the leakage current, it is necessary to increase the electrical resistance of the part through which the leakage current can flow in the off state.

[0003] For the above purpose, a technique is known in which Fe (iron) and C (carbon) are doped as acceptors to compensate for residual donors in semiconductors such as GaN. However, when electrons traveling through the channel are captured by traps caused by the dopants, a phenomenon in which the drain current fluctuates over time can occur, which is called current collapse. Therefore, it is not easy to suppress current collapse and obtain good pinch-off characteristics at the same time. Taking this into consideration, studies are being conducted to devise concentration profiles of Fe and C in the thickness direction of the semiconductor layer.

[0004] For example, JP2016-511545A (Patent Document 1) discloses a MOCVD (Metal Organic Chemical Vapor Deposition) technique for forming a semi-insulating GaN layer doped with Fe and C. This technique takes into consideration the fact that in MOCVD, it is difficult to suddenly stop Fe doping, and that while C doping can be suddenly stopped, it is prone to generating crystal defects. Specifically, in MOCVD, 18 / cm 3Growth with Fe doping at a concentration of about 5×10 is performed. After that, active Fe doping is stopped and C doping is started, which starts growth with C doping. Here, in MOCVD, even in the growth after active Fe doping is stopped, the Fe concentration does not decrease suddenly but decreases gradually with growth. C doping is about 5×10 16 / cm 3 and approximately 5 x 10 19 / cm 3 and then can be controlled to stop. C doping, unlike Fe doping, can be abruptly stopped. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2016-511545 Summary of the Invention [Problem to be solved by the invention]

[0006] According to the technique exemplified in the above publication, in MOCVD, first, a 5×10 18 / cm 3 In this growth, only Fe is added as a dopant, so the total dopant concentration is 5×10 18 / cm 3 After that, the active Fe doping is stopped and growth with C doping is performed. The C concentration at the time of stopping the C doping is 5×10 19 / cm 3 The final C doping concentration is 5×10 19 / cm 3 is the initial total dopant concentration of 5×10 18 / cm 3 It is higher than.

[0007] The inventors have focused on the fact that when the concentration of C doping is increased as described above, the recovery time constant, which is an index of the time required for electrons to recover from a state in which they are trapped in a level formed by C doping, becomes large. When the above-mentioned concentration profile is used, there is a problem that when current collapse occurs due to electrons being trapped, the time required for the semiconductor device to recover its original current characteristics by electrons being released from the traps becomes long due to the large recovery time constant described above.

[0008] The present disclosure has been made to solve the above problems, and its purpose is to provide a semiconductor device that can suppress current collapse and obtain good pinch-off characteristics while avoiding an excessively large recovery time constant. [Means for solving the problem]

[0009] The semiconductor device according to the present disclosure includes a substrate, a first channel layer made of a III-V group semiconductor containing Fe and C as impurities, a second channel layer made of a III-V group semiconductor containing Fe and C as impurities, a third channel layer made of a III-V group semiconductor containing Fe and C as impurities, and a barrier layer made of a III-V group semiconductor having a band gap wider than the band gap of the third channel layer, in that order in the thickness direction. The semiconductor channel layer including the first channel layer, the second channel layer, and the third channel layer has a concentration profile of Fe concentration and C concentration that depends on the thickness direction. The concentration profile satisfies the following conditions: a) the Fe concentration in the second channel layer and the third channel layer gradually decreases toward the barrier layer, b) the maximum value of the C concentration in the third channel layer is higher than the average value of the C concentration in the second channel layer, and c) the maximum value of the C concentration in the third channel layer is lower than the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer. Effect of the Invention

[0010] According to the present disclosure, it is possible to suppress current collapse and obtain good pinch-off characteristics while avoiding an excessively large recovery time constant.

[0011] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a cross-sectional view roughly illustrating a configuration of a semiconductor device according to each of first to third embodiments. [Diagram 2] 4 is a graph showing an example of concentration profiles depending on the thickness direction for Fe concentration and C concentration in the semiconductor channel layer of the semiconductor device according to the first embodiment. FIG. [Diagram 3] 11 is a graph illustrating a calculation result of the relationship between the C concentration in the third channel layer and the pinch-off voltage variation rate for the semiconductor device according to the first embodiment. FIG. [Figure 4] FIG. 11 is a graph illustrating calculation results of the relationship between the thickness of the third channel layer and the current reduction rate after application of a stress voltage, and the relationship between the thickness of the third channel layer and the pinch-off voltage variation rate for the semiconductor device of the first embodiment. [Diagram 5] FIG. 11 is a graph showing an example of concentration profiles depending on the thickness direction for Fe concentration and C concentration in a semiconductor channel layer of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a graph showing an example of concentration profiles depending on the thickness direction for Fe concentration and C concentration in a semiconductor channel layer included in a semiconductor device according to a modification of the second embodiment. [Figure 7] FIG. 11 is a graph showing an example of concentration profiles depending on the thickness direction for Fe concentration and C concentration in a semiconductor channel layer included in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0014] In this specification, a III-V semiconductor is a semiconductor using at least one type of group III element and at least one type of group V element. In this technical field, group III is also called group 13, and group V is also called group 15. Examples of group III elements are aluminum (Al), gallium (Ga), and indium (In). Examples of group V elements are nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb).

[0015] <Embodiment 1> 1 is a cross-sectional view that shows a schematic configuration of a semiconductor device 90 according to the first embodiment (and the second and third embodiments described later). As will be described in detail later, the impurity concentration profiles are different between the first to third embodiments. The semiconductor device 90 is a high electron mobility transistor (HEMT) that uses a two-dimensional electron gas (2DEG).

[0016] The semiconductor device 90 includes a substrate 10, a nucleation layer 11, a semiconductor channel layer 40, and a barrier layer 50 in this order in the thickness direction (upward in the drawing). The semiconductor channel layer 40 includes a first channel layer 41, a second channel layer 42, and a third channel layer 43 in this order in the thickness direction (upward in the drawing). The semiconductor device 90 further includes a source electrode 61, a drain electrode 62, a gate electrode 65, and a protective layer 70. The source electrode 61, the drain electrode 62, and the gate electrode 65 are disposed on the semiconductor layer including the barrier layer 50 and the semiconductor channel layer 40, and may be in contact with the surface (upper surface) of the barrier layer 50 as shown. The portions of the semiconductor layer that are in contact with the source electrode 61 and the drain electrode 62 (portions directly below these electrodes in the drawing) may be doped to have a locally high impurity concentration in order to reduce the contact resistance with these electrodes.

[0017] The substrate 10 may be a single crystal substrate made of SiC, Si, sapphire, or GaN, for example, a SiC single crystal substrate. The nucleation layer 11 may be made of a III-V group semiconductor, for example, an AlN (aluminum nitride) layer. The thickness of the nucleation layer 11 is, for example, 10 nm.

[0018] The semiconductor channel layer 40 (specifically, each of the first channel layer 41, the second channel layer 42, and the third channel layer 43) is made of a III-V group semiconductor containing Fe and C as impurities, and the III-V group semiconductor is, for example, GaN. Fe and C have a function as an acceptor. The thickness of the semiconductor channel layer 40 is, for example, 300 nm or more and 1200 nm or less. The thickness of the third channel layer 43 is preferably 20 nm or more and 400 nm or less, and more preferably 100 nm or more and 300 nm or less. The barrier layer 50 is made of a III-V group semiconductor having a band gap wider than that of the third channel layer 43, and the III-V group semiconductor is, for example, AlGaN (aluminum gallium nitride). The thickness of the barrier layer 50 is, for example, 20 nm. The semiconductor channel layer 40 and the barrier layer 50 form a heterojunction. At the heterojunction interface, electrons accumulate due to the polarization effect, forming a 2DEG with high concentration and high mobility.

[0019] The semiconductor device 90 may have a spacer layer (not shown) between the semiconductor channel layer 40 and the barrier layer 50. The spacer layer is made of a III-V group semiconductor having a band gap wider than that of the barrier layer 50, and the III-V group semiconductor is, for example, AlN. The thickness of the spacer layer is, for example, 0.5 nm to 3 nm. When the spacer layer is provided, alloy scattering can be reduced, and thus 2DEG mobility can be improved. In addition, since the conduction band offset is increased, the 2DEG density can be increased and the forward gate leakage can be reduced.

[0020] The semiconductor device 90 may have a cap layer (not shown) between the barrier layer 50 and each of the source electrode 61, the gate electrode 65, and the drain electrode 62. The cap layer is made of, for example, a III-V group semiconductor such as GaN. The cap layer has a thickness of, for example, 2 nm. The protective layer 70 is an insulating layer provided to reduce surface defects in the semiconductor layer located at the top surface (the uppermost part in the figure), and is made of, for example, SiN (silicon nitride).

[0021] The semiconductor channel layer 40 has a concentration profile of Fe and C depending on the thickness direction. Fig. 2 is a graph showing an example of the concentration profile in the present embodiment 1. The horizontal axis of the graph, "depth", corresponds to the arrow D (Fig. 1) from the upper surface FB (surface facing the barrier layer 50) of the semiconductor channel layer 40 toward the lower surface FS (surface facing the substrate 10) along the thickness direction.

[0022] The concentration profile (Figure 2) is shown under the following conditions: a) the Fe concentration in the second channel layer 42 and the third channel layer 43 gradually decreases toward the barrier layer 50; b) the maximum value of the C concentration in the third channel layer 43 is higher than the average value of the C concentration in the second channel layer 42; and c) the maximum value of the C concentration in the third channel layer 43 is lower than the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer 41; It should be noted that the above-mentioned “maximum value of the sum of the Fe concentration and the C concentration in the first channel layer 41” means the maximum value in the profile of the total concentration of Fe and C in the first channel layer 41.

[0023] The concentration profile in the first embodiment will be described in detail below.

[0024] The conduction band energy is increased by the first channel layer 41 having a sufficiently high acceptor concentration, which improves the confinement effect of the 2DEG, thereby suppressing the leakage current and improving the pinch-off characteristics.

[0025] As mentioned above, due to the constraints of the film formation technology (typically MOCVD) in this technical field, it is impossible to suddenly stop the doping of Fe. Even if Fe is intentionally doped during the formation of the first channel layer 41, and the active doping of Fe is stopped at the point when the formation of the first channel layer 41 is completed and the formation of the second channel layer 42 is started, the concentration of Fe actually doped does not suddenly decrease due to the upward diffusion of Fe, but gradually decreases during the formation of the second channel layer 42 and the third channel layer 43. Therefore, Fe remains in the second channel layer 42 and the third channel layer 43. Specifically, the Fe concentration in the second channel layer 42 and the third channel layer 43 gradually decreases from the first channel layer 41 toward the barrier layer 50 (in other words, toward the upper surface FB of the semiconductor channel layer 40).

[0026] On the other hand, a certain amount of C (carbon) is unintentionally doped by being mixed in from the atmosphere during the manufacturing process. Therefore, the first channel layer 41, the second channel layer 42, and the third channel layer 43 all have at least a small C concentration. The C concentration due to this unintentional doping is relatively low, approximately 3×10 16 atoms / cm 3 . If we ignore this low concentration, it can be said that unlike Fe doping, C doping can be stopped abruptly. Therefore, the concentration can be intentionally changed abruptly in the depth direction in FIG. 2. Here, the main level formed by C doping becomes deeper when the C concentration is high, which leads to an increase in the recovery time constant. Therefore, in the first channel layer 41, it is desirable to suppress the leakage current mainly by doping Fe, not C, at a high concentration.

[0027] From the above viewpoint, it is desirable that the maximum value of the Fe concentration in the first channel layer 41 is higher than the maximum value of the C concentration in the first channel layer 41. The maximum value of the Fe concentration in the first channel layer 41 is 1×10 17 atoms / cm 3 That's it, 1×10 19atoms / cm 3 It is desirable that the following conditions are met. If the Fe concentration is lower than this range, the effect of preventing leakage current will be reduced. Also, if the Fe concentration is higher than this range, for the reasons described above, the Fe concentration in the second channel layer 42 will also undesirably become unnecessarily high, and as a result, current collapse may deteriorate. In the concentration profile illustrated in FIG. 2, at any depth position (in other words, thickness position) in the first channel layer 41, the Fe concentration is higher than the C concentration.

[0028] The concentrations of Fe and C contained in the second channel layer 42, in other words, the acceptor concentration, are desirably as low as possible. This is because if the concentration of acceptors contained in the second channel layer 42 is high, the trap density increases, and thereby current collapse may deteriorate. On the other hand, the Fe concentration in the first channel layer 41 is relatively high as described above, and as a result, for the reasons described above, it becomes difficult to reduce the Fe concentration in the second channel layer 42. Therefore, the maximum value of the Fe concentration in the second channel layer 42 is higher than the average value of the C concentration in the second channel layer 42. Also, in the concentration profile illustrated in FIG. 2, at any depth position in the second channel layer 42, the Fe concentration is higher than the C concentration. Also, in the concentration profile illustrated in FIG. 2, the minimum value of the Fe concentration in the second channel layer 42 is higher than the maximum value of the C concentration in the second channel layer 42. In the second channel layer, desirably the average value of the C concentration is 3×10 16 atoms / cm 3 or less, and more desirably the maximum value of the C concentration is 3×10 16 atoms / cm 3 or less.

[0029] The maximum value of the C concentration in the third channel layer is higher than the average value of the C concentration in the second channel layer 42. This increases the conduction band energy in the region near the 2DEG, improving the confinement effect of the 2DEG. This reduces the leakage current, suppresses the DIBL (Drain Induced Barrier Lowering) effect when a high drain voltage is applied, and improves the pinch-off characteristics. Furthermore, the higher conduction band barrier can suppress the electrons in the 2DEG from being trapped on the second channel layer 42 side. From the above, it is possible to both suppress the current collapse and obtain good pinch-off characteristics. Therefore, it is desirable to keep the C concentration low in the second channel layer 42 and to increase the C concentration in the third channel layer 43. To this end, it is desirable that the C concentration at the interface between the second channel layer 42 and the third channel layer 43 has a step-like change as shown in FIG. 2.

[0030] Here, when the C concentration in the third channel layer 43 becomes high, the trap density also becomes high. On the other hand, in the vicinity of the electron transit region, since the trap level and the Fermi level are close to each other, electrons are already trapped in many of the trap levels without applying a stress voltage. Therefore, the change in ionization trap density before and after stress is small. Therefore, an increase in the C concentration is unlikely to lead to a deterioration in the current collapse up to a certain extent. Therefore, it is preferable to increase the maximum value of the C concentration to a sufficient degree to suppress the leakage current. However, an excessively large C concentration forms an excessively deep trap level, which results in a substantial deterioration in the current collapse and a substantial increase in the recovery time constant. According to the study by the present inventors, in order to avoid a substantial deterioration in the current collapse and a substantial increase in the recovery time constant, it is desirable for the maximum value of the C concentration in the third channel layer 43 to be lower than the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer 41, and more desirably, to be less than half of the sum.

[0031] 3 is a graph illustrating a calculation result of the relationship between the C concentration in the third channel layer 43 and the pinch-off voltage variation rate when the drain voltage is changed from 5V to 50V for the semiconductor device 90 according to the first embodiment. When the drain voltage is increased, the pinch-off voltage shifts in the negative direction due to the DIBL effect. The value obtained by dividing this shift amount by the pinch-off voltage when the drain voltage is low is defined as the pinch-off voltage variation rate. Therefore, the pinch-off voltage variation rate shown in FIG. 3 is the value obtained by dividing the shift amount of the pinch-off voltage when the drain voltage is changed from 5V to 50V by the pinch-off voltage when the drain voltage is 5V.

[0032] 3, it can be seen that increasing the C concentration in the third channel layer 43 to a certain degree leads to an improvement in the pinch-off characteristics. In normal practical use of the semiconductor device 90, it is desirable for the pinch-off voltage fluctuation rate to be approximately 8% or less (see the dashed line in FIG. 3). To achieve this, the maximum value of the C concentration in the third channel layer 43 should be 5×10 16 atoms / cm 3 It is preferable that the value is equal to or greater than 1×10 17 atoms / cm 3 It is more preferable that the C concentration in the third channel layer 43 is 5×10 or more. However, if the C concentration in the third channel layer 43 is too high, the recovery time constant becomes too large due to the main trap level derived from C becoming deeper, as described above. From this point of view, the maximum value of the C concentration in the third channel layer 43 is 5×10 17 atoms / cm 3 It is desirable that the following:

[0033] 4 is a graph illustrating the results of calculations of the relationship between the thickness of the third channel layer 43 and the current reduction rate after application of a stress voltage, and the relationship between the thickness of the third channel layer 43 and the pinch-off voltage variation rate, for the semiconductor device 90 according to the first embodiment. The definition of the pinch-off voltage variation rate is the same as in FIG. 3.

[0034] From the graph of FIG. 4, it can be seen that increasing the thickness of the third channel layer 43 to a certain degree or more leads to an improvement in the pinch-off characteristics. On the other hand, it can be seen that decreasing the thickness of the third channel layer 43 to a certain degree or more leads to a suppression of the current drop rate after the stress voltage is applied, in other words, a suppression of the current collapse. Therefore, with respect to the thickness of the third channel layer 43, there is a trade-off relationship between the improvement of the pinch-off characteristics and the suppression of the current collapse. Here, as described above, it is desirable that the pinch-off voltage fluctuation rate is approximately 8% or less (see the lower broken line in FIG. 4). Also, it is desirable that the current drop rate after the stress voltage is applied is approximately 40% or less (see the upper broken line in FIG. 4) in normal practical use of the semiconductor device 90. Therefore, in order to achieve both the improvement of the pinch-off characteristics and the suppression of the current collapse, it is desirable that the thickness of the third channel layer 43 is 100 nm or more and 300 nm or less. The optimum value of the thickness of the third channel layer 43 depends on the C concentration of the third channel layer 43 and the Fe concentration of the first channel layer 41.

[0035] According to the first embodiment (see FIG. 2), firstly, the Fe concentration in the second channel layer 42 and the third channel layer 43 gradually decreases toward the barrier layer 50. This makes it possible to ensure a high Fe concentration in the first channel layer 41 while suppressing the Fe concentration at the upper surface FB of the semiconductor channel layer 40. Therefore, in the first channel layer 41, Fe can be mainly used as an acceptor for ensuring good pinch-off characteristics. Therefore, it is not necessary to increase the C concentration in the first channel layer 41. This contributes to preventing the recovery time constant from becoming excessively large.

[0036] Secondly, the Fe concentration in the third channel layer 43 is lowered by the gradual decrease in the Fe concentration described above, and the maximum value of the C concentration in the third channel layer 43 is higher than the average value of the C concentration in the second channel layer 42. By increasing the C concentration in the third channel layer 43, the effect of narrowly confining the two-dimensional electron gas (2DEG) in the vicinity of the barrier layer 50 is improved. This effect contributes to both improvement of the pinch-off characteristics and reduction of current collapse. In other words, the above characteristic regarding the C concentration is that the average value of the C concentration in the second channel layer 42 is lower than the maximum value of the C concentration in the third channel layer 43. This allows the acceptor concentration in the second channel layer 42 to be lowered. Therefore, it is possible to suppress current collapse caused by electrons in the 2DEG being trapped in the second channel layer 42.

[0037] Thirdly, the maximum value of the C concentration in the third channel layer 43 is set higher than the average value of the C concentration in the second channel layer 42 as described above, but is set lower than the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer 41. This prevents electrons that have spread from the 2DEG to the third channel layer 43 from spreading further to the first channel layer 41. This contributes to good pinch-off characteristics.

[0038] From the above, it is possible to simultaneously suppress current collapse and obtain good pinch-off characteristics while avoiding an excessively large recovery time constant.

[0039] The maximum value of the C concentration in the third channel layer 43 is 5×10 16 atoms / cm 3 That's it, 5 x 10 17 atoms / cm 3 This makes it possible to more sufficiently suppress the current collapse and obtain good pinch-off characteristics at the same time.

[0040] The maximum Fe concentration in the first channel layer 41 is 1×10 17 atoms / cm3 That's it, 1×10 19 atoms / cm 3 This makes it possible to more reliably suppress current collapse and obtain good pinch-off characteristics while avoiding an excessively large recovery time constant.

[0041] The maximum value of the C concentration in the third channel layer 43 may be equal to or less than half the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer 41. This makes it possible to more reliably suppress the current collapse and obtain good pinch-off characteristics while avoiding an excessively large recovery time constant.

[0042] The maximum value of the Fe concentration in the second channel layer 42 may be higher than the average value of the C concentration in the second channel layer 42. This makes it possible to more reliably achieve both suppression of current collapse and obtaining good pinch-off characteristics while avoiding an excessively large recovery time constant.

[0043] The maximum value of the Fe concentration in the first channel layer 41 may be higher than the maximum value of the C concentration in the first channel layer 41. This makes it possible to more sufficiently avoid an excessively large recovery time constant and obtain good pinch-off characteristics at the same time.

[0044] The C concentration may have a step-like change at the interface between the second channel layer 42 and the third channel layer 43. This makes it possible to more sufficiently suppress the current collapse and obtain good pinch-off characteristics at the same time.

[0045] The third channel layer 43 has a thickness of 100 nm or more and 300 nm or less, which makes it possible to more sufficiently suppress the current collapse and obtain good pinch-off characteristics at the same time.

[0046] <Embodiment 2> 5 is a graph showing an example of concentration profiles depending on the thickness direction for Fe concentration and C concentration in the semiconductor channel layer 40 of the semiconductor device 90 (FIG. 1) according to the second embodiment. In this embodiment, the C concentration at the interface between the third channel layer 43 and the layer including the barrier layer 50 on the third channel layer 43 is lower than the C concentration at the interface between the third channel layer 43 and the second channel layer 42, and is 3×10 16 atoms / cm 3 The above-mentioned "layer including the barrier layer 50 on the third channel layer 43" corresponds to the barrier layer 50 when the third channel layer 43 and the barrier layer 50 are in direct contact with each other as shown in Fig. 1, and corresponds to a stack of the spacer layer and the barrier layer 50 when the above-mentioned spacer layer is provided between the third channel layer 43 and the barrier layer 50. In other words, the above-mentioned condition is that the C concentration at the upper surface FB of the semiconductor channel layer 40 is lower than the C concentration at the interface between the third channel layer 43 and the second channel layer 42 and is less than 3 x 10 16 atoms / cm 3 The following is the result.

[0047] In order to obtain the above-described C concentration profile, it is necessary that the C concentration decreases toward the upper surface FB (in other words, toward a layer including the barrier layer 50 on the third channel layer 43) in at least a part of the third channel layer 43. This decrease may be a step-like decrease as shown in FIG. 5, or may be a gradual decrease as in the modified example shown in FIG. 6.

[0048] The configuration other than the above is almost the same as that of the above-mentioned embodiment 1. Therefore, in this embodiment as well, it is possible to simultaneously suppress the current collapse and obtain good pinch-off characteristics while avoiding an excessively large recovery time constant.

[0049] If the impurity concentration in the electron transport region is too high, the mobility will be excessively reduced due to ionized impurity scattering. In particular, if the acceptor concentration is too high, the 2DEG density will be excessively reduced due to an increase in the conduction band energy. Therefore, by using the concentration profile as described above in this embodiment, it is possible to suppress the reduction in mobility in the electron transport region and also the reduction in 2DEG density. Therefore, the current characteristics of the semiconductor device 90 in the on-state can be improved.

[0050] <Embodiment 3> FIG. 7 is a graph showing an example of concentration profiles of the Fe concentration and the C concentration in the semiconductor channel layer 40 of the semiconductor device 90 (FIG. 1) according to the third embodiment, depending on the thickness direction.

[0051] In the third embodiment, the maximum value of the Fe concentration in the first channel layer 41 is lower than the maximum value of the C concentration in the first channel layer 41. By not making the maximum value of the Fe concentration in the first channel layer 41 too high, it is possible to reduce the concentration of Fe that is unintentionally doped in the second channel layer 42 and the third channel layer 43. This makes it possible to reduce current collapse.

[0052] In the first channel layer 41, while the maximum value of the Fe concentration is lowered as described above, in order to avoid a situation in which a sufficiently good pinch-off characteristic cannot be obtained due to the lowering of the maximum value of the Fe concentration, the acceptor concentration in the first channel layer 41 may be ensured by increasing the maximum value of the C concentration in the first channel layer 41. However, the maximum value of the C concentration is set to 5×10 in order to prevent the level of the main trap formed due to the C doping from becoming excessively deep. 17 atoms / cm 3 It is desirable that:

[0053] In the concentration profile illustrated in FIG. 7, the Fe concentration is lower than the C concentration at any depth position (in other words, thickness position) in the first channel layer 41.

[0054] Other configurations of the third embodiment than those described above are substantially the same as those of the first embodiment, and therefore description thereof will not be repeated.

[0055] In addition, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted. Although the present disclosure has been described in detail, the above description is illustrative in all aspects and is not intended to be limiting. It is understood that countless modified examples not illustrated can be envisioned from the present disclosure. [Explanation of symbols]

[0056] 10 substrate, 11 nucleation layer, 40 semiconductor channel layer, 41 first channel layer, 42 second channel layer, 43 third channel layer, 50 barrier layer, 61 source electrode, 62 drain electrode, 65 gate electrode, 70 protective layer, 90 semiconductor device.

Claims

1. A substrate; a first channel layer made of a III-V group semiconductor containing Fe and C as impurities; a second channel layer made of a III-V group semiconductor containing Fe and C as impurities; a third channel layer made of a III-V group semiconductor containing Fe and C as impurities; a barrier layer made of a III-V group semiconductor having a band gap wider than the band gap of the third channel layer; in that order in the thickness direction, The semiconductor channel layer including the first channel layer, the second channel layer, and the third channel layer has a concentration profile depending on the thickness direction for Fe concentration and C concentration, and the concentration profile is determined under the following conditions: a) the Fe concentration in the second channel layer and the third channel layer gradually decreases toward the barrier layer; b) the maximum value of the C concentration in the third channel layer is higher than the average value of the C concentration in the second channel layer; and c) the maximum value of the C concentration in the third channel layer is lower than the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer; It satisfies the maximum value of the C concentration in the third channel layer is 5×10 16 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less; Semiconductor device.

2. The maximum value of the Fe concentration in the first channel layer is 1×10 １７ atoms / cm ３ That's it, 1 x 10 １９ atoms / cm ３ 2. The semiconductor device according to claim 1, wherein:

3. 3. The semiconductor device according to claim 1, wherein the maximum value of the C concentration in the third channel layer is equal to or less than half the maximum value of the sum of the Fe concentration and the C concentration in the first channel layer.

4. 3. The semiconductor device according to claim 1, wherein the maximum value of the Fe concentration in the second channel layer is higher than the average value of the C concentration in the second channel layer.

5. 3. The semiconductor device according to claim 1, wherein the maximum value of the Fe concentration in the first channel layer is higher than the maximum value of the C concentration in the first channel layer.

6. 3. The semiconductor device according to claim 1, wherein the C concentration has a stepwise change at an interface between the second channel layer and the third channel layer.

7. 3. The semiconductor device according to claim 1, wherein the third channel layer has a thickness of 100 nm or more and 300 nm or less.

8. The C concentration at the interface between the third channel layer and a layer including the barrier layer on the third channel layer is lower than the C concentration at the interface between the third channel layer and the second channel layer, and is 3×10 １６ atoms / cm ３ 3. The semiconductor device according to claim 1, wherein:

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