Semiconductor light-emitting device and photocoupler

Abstract

To provide a semiconductor light-emitting device and photocoupler, having high reliability even in a high-temperature action environment.SOLUTION: A semiconductor light-emitting device comprises: a gallium arsenic (GaAs) substrate of cubic crystal; a light-emitting layer provided on the GaAs substrate, and containing indium gallium arsenic (InGaAs) represented by the compositional formula, InxGa1-xAs (0<x<1); and a semiconductor multilayer film provided on a surface of the GaAs substrate, inclined to (100) plane of the cubic crystal, between the GaAs substrate and the light-emitting layer. The semiconductor multilayer film includes first and second layers which are alternately laminated in a direction perpendicular to the surface of the GaAs substrate; the first layer has a composition different from that of the second layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to a semiconductor light-emitting device and a photocoupler.

Background Art

[0002] High reliability is required for semiconductor light-emitting devices. In in-vehicle applications and the like, it is important to operate stably and have a long life in a high-temperature operating environment, for example, at 105°C.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor light-emitting device and a photocoupler having high reliability in a high-temperature operating environment.

Means for Solving the Problems

[0005] The semiconductor light-emitting device according to an embodiment includes a cubic gallium arsenide (GaAs) substrate, a light-emitting layer provided on the GaAs substrate and containing indium gallium arsenide (InGaAs) represented by the composition formula In x Ga 1-x As (0 < x < 1), and a semiconductor multilayer film provided on the surface of the GaAs substrate inclined with respect to the (100) plane of the cubic crystal between the GaAs substrate and the light-emitting layer. The semiconductor multilayer film includes a first layer and a second layer alternately laminated in a direction perpendicular to the surface of the GaAs substrate, and the first layer has a composition different from that of the second layer.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

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Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, the dimensions and ratios thereof may be represented differently in the drawings.

[0008] FIGS. 1(a) and (b) are schematic cross-sectional views showing a semiconductor light-emitting device 1 according to an embodiment. FIG. 1(a) is a chip cross-sectional view. FIG. 1(b) is a partial cross-sectional view showing the region surrounded by the dashed line in FIG. 1(a).

[0009] The semiconductor light-emitting device 1 is, for example, a light-emitting diode that emits near-infrared light. The semiconductor light-emitting device 1 includes a cubic gallium arsenide (GaAs) substrate 10, an epitaxial growth layer 20, a first electrode 30, and a second electrode 40.

[0010] The GaAs substrate 10 has, for example, n-type conductivity. The GaAs substrate 10 has a surface 10F that is inclined, for example, in the (011) plane direction with respect to the cubic (100) plane. The epitaxial growth layer 20 is provided on the surface 10F of the GaAs substrate 10.

[0011] As shown in FIG. 1(a), the side surface 10S connecting the surface 10F and the back surface 10B of the GaAs substrate 10 is, for example, the (011) plane. The cross-sectional shape of the semiconductor light-emitting device 1 is, for example, a parallelogram in a cross-section parallel to the (0-11) plane. Also, if the inclination angle of the surface 10F in the (011) plane direction is θ, the cubic (1-1-1) plane has an inclination of θ + approximately 55° with respect to the back surface 10B.

[0012] The first electrode 30 is provided on the back surface 10B of the GaAs substrate 10. The first electrode 30 is, for example, an n-side electrode. The back surface 10B of the GaAs substrate 10 is located on the opposite side of the surface 10F and is inclined with respect to the (100) plane.

[0013] The second electrode 40 is provided on the epitaxial growth layer 20. The second electrode 40 is, for example, a p-side electrode. The second electrode 40 is partially provided on the epitaxial growth layer 20.

[0014] As shown in FIG. 1(b), the epitaxial growth layer 20 includes a light-emitting layer 21, a semiconductor multilayer film 23, an n-type cladding layer 25, a p-type cladding layer 27, and a p-type contact layer 29.

[0015] The light-emitting layer 21 has the composition formula In x Ga 1-xIt contains indium gallium arsenide (hereinafter referred to as InGaAs) represented by As(0 < x < 1). InGaAs has lower rigidity (hardness) and a smaller Young's modulus than the GaAs substrate 10. Also, InGaAs has a larger lattice constant than the GaAs substrate 10 and constitutes, for example, a strained quantum well structure. The semiconductor multilayer film 23 is provided on the surface 10F of the GaAs substrate 10 between the GaAs substrate 10 and the light-emitting layer 21.

[0016] The semiconductor multilayer film 23 is provided on the surface 10F of the GaAs substrate 10. The semiconductor multilayer film 23 has, for example, n-type conductivity. Also, the semiconductor multilayer film 23 includes at least one first layer 23a and at least one second layer 23b that are alternately laminated in a direction perpendicular to the surface 10F of the GaAs substrate 10. The first layer 23a has a composition different from that of the second layer 23b. The first layer 23a has a rigidity (hardness) different from that of the second layer 23b.

[0017] The n-type cladding layer 25 is provided between the light-emitting layer 21 and the semiconductor multilayer film 23. The n-type cladding layer 25 contains, for example, aluminum gallium arsenide (hereinafter referred to as AlGaAs) represented by Al z Ga 1-z As(0 < z < 1).

[0018] The p-type cladding layer 27 is provided on the light-emitting layer 21. The p-type cladding layer 27 contains, for example, AlGaAs. The light-emitting layer 21 is provided between the n-type cladding layer 25 and the p-type cladding layer 27.

[0019] The p-type contact layer 29 is provided on the p-type cladding layer 27. The p-type contact layer 29 contains, for example, GaAs. The second electrode 40 is provided on the p-type contact layer 29 and is, for example, ohmically connected to the p-type contact layer 29.

[0020] FIG. 2 is a schematic cross-sectional view showing the light-emitting layer 21 of the semiconductor light-emitting device 1 according to the embodiment. The light-emitting layer 21 includes a quantum well layer 21w and a barrier layer 21b. The quantum well layer 21w and the barrier layer 21b are alternately stacked in the direction from the n-type clad layer 25 toward the p-type clad layer 27, that is, in the direction perpendicular to the surface 10F of the GaAs substrate 10 (see FIG. 1(b)). The quantum well layer 21w is provided, for example, between adjacent barrier layers 21b. The quantum well layer 21w contains InGaAs. The barrier layer 21b contains, for example, AlGaAs. The quantum well structure composed of InGaAs / AlGaAs is a strained quantum well structure caused by lattice mismatch with respect to the GaAs substrate 10, and the emission wavelength is, for example, 950 nm.

[0021] FIGS. 3(a) to (d) are schematic cross-sectional views showing the manufacturing process of the semiconductor light-emitting device 1 according to the embodiment. FIGS. 3(a) to (d) represent the process of chip-forming the semiconductor light-emitting device 1.

[0022] As shown in FIG. 3(a), a first electrode 30 is formed on the back surface 10B of the GaAs substrate 10. The first electrode 30 is provided, for example, over the entire surface of the back surface 10B. The first electrode 30 is ohmically connected to the GaAs substrate 10. The first electrode 30 contains, for example, gold (Au) or silver (Ag) and functions as a reflection film for light emitted from the light-emitting layer 21.

[0023] A plurality of second electrodes 40 are formed on the surface 10F side of the GaAs substrate 10. The second electrodes 40 are provided on the epitaxial growth layer 20 (see FIG. 1(a)) and are electrically connected to the p-type contact layer 29.

[0024] As shown in FIG. 3(b), a scribe line SL is formed on the back surface 10B side of the GaAs substrate 10 using a scribe needle ST. The scribe needle ST has a diamond blade at its tip and can form a groove-shaped scribe line SL that divides the first electrode 30 and reaches the GaAs substrate 10 on the back surface 10B side of the GaAs substrate 10. The scribe line SL is formed so as to be located between adjacent second electrodes 40 when viewed in the direction perpendicular to the back surface 10B.

[0025] As shown in FIG. 3(c), on the surface 10F side of the GaAs substrate 10, the GaAs substrate 10 is cleaved using a breaking blade BE. The breaking blade BE is pressed against a position on the opposite side of the scribe line SL. The GaAs substrate 10 is pressed by the breaking blade BE and cleaved starting from the scribe line SL.

[0026] As shown in FIG. 3(d), the GaAs substrate 10 is divided into a plurality of chips (semiconductor light-emitting devices 1). The chip size CS of the semiconductor light-emitting device is, for example, 200 micrometers (μm). Also, the chip thickness CT is, for example, 150 μm.

[0027] In such a chip dividing method, since mechanical damage such as minute defects or a crushed layer existing at the bottom of the scribe line SL formed on the back surface 10B of the GaAs substrate 10 serves as a starting point for cleavage, mechanical damage remains in the divided chips. For example, it is possible to remove such mechanical damage by etching the GaAs substrate 10 after chip division, but it is difficult to remove all of the minute defects, for example.

[0028] FIGS. 4(a) to (d) are cathode luminescence (CL) images of the semiconductor light-emitting device 1 according to the embodiment. The chips used for the CL measurement are those in which the operating voltage at a predetermined light output changed by more than 10% in an accelerated reliability test (ambient temperature 125° C., operating current 120 mA, 500 hours) under high temperature and high current.

[0029] FIGS. 4(a) to (d) show CL images on the chip side surface (see FIG. 1(a)). The CL measurement observes a light emission phenomenon caused by the recombination of carriers (electrons and holes) excited by an electron beam. When the excited carriers are trapped by defects, non-radiative recombination occurs. Therefore, the regions where defects exist in the crystal do not emit light.

[0030] As can be seen from Fig. 4(a), a dark line DL extending from the corner where the cleavage plane (011) of the chip is connected to the back surface 10B of the GaAs substrate 10 (i.e., the scribe line SL) to the surface of the epitaxial growth layer 20 can be seen (see Fig. 1(a)). This dark line extends, for example, along the (1-1-1) plane.

[0031] Fig. 4(b) is a CL image observed after the chip side surface is etched by 30 μm. Also in this case, a dark line DL extending from the corner where the (011) plane is connected to the back surface 10B of the GaAs substrate 10 to the surface of the epitaxial growth layer 20 can be seen.

[0032] Fig. 4(c) is a CL image observed after the chip side surface is further etched by 30 μm (total 60 μm). The dark line DL extends from the corner where the (011) plane is connected to the back surface 10B of the GaAs substrate 10 to the surface of the epitaxial growth layer 20.

[0033] Fig. 4(d) is a CL image observed after the chip side surface is further etched by 30 μm (total 90 μm). The dark line DL extends from the corner where the (011) plane is connected to the back surface 10B of the GaAs substrate 10 to the center of the GaAs substrate 10.

[0034] These CL images show that crystal defects spread planar in the GaAs substrate 10 from the corner where the cleavage plane of the GaAs substrate 10 is connected to the back surface 10B. That is, it can be seen that the crystal defects are planar dislocations along the (1-1-1) plane. Also, in the CL image shown in Fig. 4(d), the dark line DL has not reached the epitaxial growth layer 20, and the dislocation seems to extend starting from the corner where the back surface 10B is connected to the cleavage plane. In other words, it can be seen that the dislocation extends in the GaAs substrate 10 starting from the scribe line SL (see Fig. 3(c)). Such dislocations gradually extend, for example, due to temperature changes in the operating environment. Also, when the chip is resin-sealed, the extension of the dislocation is accelerated by the resin stress.

[0035] Thus, in the acceleration test under high temperature and high current, the crystal defects remaining in the scribe line SL may spread over time and reach the epitaxial growth layer 20. As a result, the light-emitting characteristics deteriorate. The above test conditions assume a severe usage environment, for example, in-vehicle applications, and dislocation propagation that does not occur in normal applications is observed.

[0036] For example, a normal reliability test is carried out at room temperature under the conditions of an operating current of 20 mA and a conduction time of 10,000 h. Under such conditions, for example, luminance degradation of 10% or more does not occur. On the other hand, when the chip is sealed with an epoxy resin and a conduction test is carried out at a high temperature, luminance degradation may occur due to resin stress. Such luminance degradation due to resin stress can be suppressed by using a double-sealing structure (see FIG. 8) in which the chip is first sealed with a silicone resin, which is a non-elastic resin (with little plastic deformation), and then sealed with an epoxy resin. However, in the above-described acceleration reliability test under high temperature and high current, luminance degradation may also occur even in the double-resin sealing structure.

[0037] In the semiconductor multilayer film 23 in the epitaxial growth layer 20, by combining a first layer 23a and a second layer 23b having different rigidities, the propagation of such dislocations to the light-emitting layer 21 is suppressed, and the reliability of the semiconductor light-emitting device 1 is improved. The semiconductor multilayer film 23, for example, changes the propagation direction of dislocations at each interface between the first layer 23a and the second layer 23b so that they do not reach the light-emitting layer 21. Alternatively, it has the effect of combining dislocations with each other to cause them to disappear. However, under severe acceleration conditions, this dislocation suppression effect may not be sufficient in some cases.

[0038] (Example 1) In the semiconductor multilayer film 23 (see FIG. 1(b)), for example, indium aluminum phosphide represented by the composition formula In z Al 1-z P (0 < z < 1) (hereinafter referred to as InAlP), and the composition formula Al v Ga 1-vEither GaAs or AlGaAs represented by As(0 ≦ v < 1) can be used. For example, the first layer 23a of the semiconductor multilayer film 23 is made of InAlP, and the second layer 23b is made of GaAs (v = 0). The film thicknesses of the first layer 23a and the second layer 23b are each 50 nanometers (nm). The semiconductor multilayer film 23 includes 10 pairs of the first layer 23a / second layer 23b. The same effect can be obtained even if the second layer 23b is AlGaAs (0 < v < 1).

[0039] The semiconductor multilayer film 23 is configured to transmit the light emitted from the light-emitting layer 21. The emitted light passes through the semiconductor multilayer film 23 and propagates in the GaAs substrate 10. Thereby, the entire chip can be made to emit light. As seen in the prior art, if the semiconductor multilayer film 23 is configured to reflect (Bragg reflection) the emitted light of the light-emitting layer 21, a light-emitting device with high directivity in which light is emitted in the direction from the semiconductor multilayer film 23 toward the second electrode 40 is obtained. For applications where a light-emitting device with low directivity is suitable, such as a photocoupler, etc., it is preferable that the semiconductor multilayer film 23 is configured to transmit the emitted light of the light-emitting layer 21. That is, it is preferable that the light of the light-emitting layer 21 is emitted not only from the upper surface of the chip but also from the side surface so that the entire chip emits light.

[0040] (Example 2) For the semiconductor multilayer film 23 (see FIG. 1(b)), for example, InGaAs and gallium arsenide phosphide represented by the composition formula GaAs w P 1-w (0 < w < 1) (hereinafter referred to as GaAsP) can be used. The first layer 23a is made of In 0.1 Ga 0.9 As, and the second layer 23b is made of GaAs 0.9 P 0.1 . The film thicknesses of the first layer 23a and the second layer 23b are each 10 nm. The semiconductor multilayer film 23 includes 10 pairs of the first layer 23a / second layer 23b.

[0041] The lattice constants of InGaAs and GaAsP are opposite in their magnitude relationship with respect to the lattice constant of GaAs. Also, the linear expansion coefficients of InGaAs and GaAsP are different. For this reason, in the semiconductor multilayer film 23, the difference in lattice constants is compensated by the lattice strain within the elastic limit, and crystal defects due to lattice mismatch do not occur. In this example, due to the elastic strain in the semiconductor multilayer film 23, the effect of changing the propagation direction of dislocations at the InGaAs / GaAsP interface becomes larger. As a result, the effect of suppressing the propagation of dislocations is larger compared to the semiconductor multilayer film 23 of Example 1, and the occurrence rate of characteristic degradation chips in the accelerated reliability test can be reduced.

[0042] FIG. 5 is a graph showing the characteristics of the semiconductor light-emitting device 1 according to the embodiment. The horizontal axis is the tilt angle θ (see FIG. 1(a)) of the GaAs substrate 10. The vertical axis is the occurrence rate of characteristic degradation chips in the accelerated reliability test. The graph indicated by "A" in the figure represents the characteristics when the semiconductor multilayer film 23 of Example 1 is used. Also, the graph indicated by "B" represents the characteristics when the semiconductor multilayer film 23 of Example 2 is used.

[0043] In the semiconductor multilayer film 23 including InAlP / AlGaAs of Example 1, when the tilt angle θ is zero, the occurrence rate of characteristic degradation chips is about 15%, and when the tilt angle θ becomes 10° or more, the occurrence rate of characteristic degradation chips becomes 0%.

[0044] Note that Al v Ga 1-v Even when the Al composition v of AlGaAs is changed from 0 to 0.2, similar results are obtained, and it can be seen that there is freedom in the Al composition of AlGaAs combined with InAlP. This is presumably because the rigidity of AlGaAs does not change significantly due to the difference in the Al composition v.

[0045] In the semiconductor multilayer film 23 including InGaAs / GaAsP of Example 2, when the tilt angle θ is zero, the occurrence rate of characteristic degradation chips is about 10%, and when the tilt angle θ becomes 8° or more, the occurrence rate of characteristic degradation chips becomes 0%.

[0046] The propagation plane (1-1-1) of dislocations with respect to the back surface 10B of the GaAs substrate 10 is θ + approximately 55° (see Fig. 1(a)). As the inclination angle θ increases, the intrusion angle of dislocations into the semiconductor multilayer film 23 increases. That is, as the intrusion angle into the semiconductor multilayer film 23 increases, the change in the propagation direction of dislocations increases, and it is considered that the influence on the light-emitting layer 21 is suppressed. This is because as the inclination of the surface 10F of the GaAs substrate 10 with respect to the (100) plane increases, the surface morphology of the epitaxial growth layer 20 improves, such as being better, and it is considered that these factors combined suppress the propagation of dislocations.

[0047] Thus, by inclining the surface 10F of the GaAs substrate 10 with respect to the (100) plane, the reliability of the semiconductor light-emitting device 1 can be improved. Also, by setting the inclination angle θ of the GaAs substrate 10 to preferably 8° or more, more preferably 10° or more, the reliability in a more severe usage environment can be ensured. On the other hand, when the inclination angle θ becomes 25° or more, it becomes difficult to obtain an epitaxial growth layer with low dislocations. Therefore, the inclination angle θ is preferably 8° or more and 25° or less. More preferably, it is 10° or more and 25° or less.

[0048] Figs. 6(a) and (b) are schematic diagrams illustrating the semiconductor light-emitting device 1 according to the embodiment. Fig. 6(a) is a chip cross-sectional view, and Fig. 6(b) is a plan view showing the chip surface.

[0049] As shown in Fig. 6(a), in the semiconductor light-emitting device 1, cracks CP are likely to occur at the end of the upper surface of the epitaxial growth layer 20. This is due to the fact that when using the GaAs substrate 10 inclined with respect to the (100) plane, the inner angle of the angle where the upper surface of the epitaxial growth layer 20 intersects with the side surface 10S, which is the cleavage plane, is an acute angle. Also, the fact that the semiconductor multilayer film 23 includes the first layer 23a and the second layer 23b with different rigidities is also one of the factors for the occurrence of such cracks CP.

[0050] As shown in Fig. 6(b), the crack CP is confirmed as a recess on one side of the upper surface of the chip. In the process of chip formation shown in Fig. 3, the GaAs substrate 10 is divided along the cleavage plane from the scribe line SL to the position of the semiconductor multilayer film 23. However, in the semiconductor multilayer film 23, the continuity of the cleavage plane is inhibited. Therefore, it is considered that a partially chipped outer edge is formed on the upper surface of the epitaxial growth layer 20.

[0051] Fig. 7 is a schematic cross-sectional view showing a semiconductor light-emitting device 2 according to a modified example of the embodiment. The semiconductor light-emitting device 2 includes a GaAs substrate 10, a light-emitting layer 21, a semiconductor multilayer film 23, a first electrode 50, and a second electrode 60.

[0052] As shown in Fig. 7, the epitaxial layer 20 including the light-emitting layer 21, the semiconductor multilayer film 23, the n-type clad layer 25, the p-type clad layer 27, and the p-type contact layer 29 has a mesa structure. The first electrode 50 is provided on the surface 10F of the GaAs substrate 10 exposed by mesa processing to a depth reaching the GaAs substrate 10. The first electrode 50 is an n-side electrode. Also, by mesa processing to a depth reaching the n-type clad layer 25, the n-type clad layer 25 may be exposed and the first electrode 50 may be provided on the n-type clad layer 25.

[0053] The second electrode 60 is provided on the p-type contact layer 29. The second electrode 60 is a p-side electrode. The second electrode 60 contains, for example, gold (Au) or silver (Ag), and is configured to reflect the light radiated from the light-emitting layer 21 toward the second electrode 60 and emit it from the back surface 10B of the GaAs substrate 10.

[0054] In the semiconductor light-emitting device 2, the light LO radiated in the vertical direction from the light-emitting layer 21 propagates through the semiconductor multilayer film 23 and the GaAs substrate 10, and is emitted to the outside from the back surface 10B of the GaAs substrate 10. Also in this example, the semiconductor multilayer film 23 is provided so as to transmit the light LO radiated from the light-emitting layer 21.

[0055] FIG. 8 is a schematic cross-sectional view showing a photocoupler 70 using the semiconductor light-emitting device 1 according to the embodiment. The photocoupler 70 includes the semiconductor light-emitting device 1 and the light-receiving device 5. The semiconductor light-emitting device 1 and the light-receiving device 5 are arranged to face each other and are optically coupled. That is, the light-receiving device 5 detects the light emitted from the semiconductor light-emitting device 1.

[0056] As shown in FIG. 8, the semiconductor light-emitting device 1 is mounted on the input-side lead 71 and is electrically connected. The light-receiving device 5 is mounted on the output-side lead 73 and is electrically connected. Note that the photocoupler 70 includes a plurality of input-side leads 71 and a plurality of output-side leads 73. The photocoupler 70 includes, for example, an input-side lead 71 electrically connected to the first electrode 30 (see FIG. 1) of the semiconductor light-emitting device, and another input-side lead 71 electrically connected to the second electrode 40 (see FIG. 1) via a metal wire. The plurality of output-side leads 73 include leads connected to the anode and cathode of the light-receiving device, respectively.

[0057] The semiconductor light-emitting device 1 is encapsulated in the first resin 75. The first resin 75 is, for example, a silicone resin. The first resin 75 transmits the light emitted from the semiconductor light-emitting device 1.

[0058] The input-side lead 71 and the output-side lead 73 are arranged such that the semiconductor light-emitting device 1 and the light-receiving element 5 face each other. Subsequently, a second resin 77 is molded to cover the portion of the input-side lead 71 where the semiconductor light-emitting device 1 is mounted and the portion of the output-side lead 73 where the light-receiving device 5 is mounted. The second resin 77 is provided to cover the semiconductor light-emitting device 1 and the light-receiving device 5 via the first resin 75. The second resin 77 transmits the light emitted from the semiconductor light-emitting device 1. The second resin 77 is, for example, an epoxy resin.

[0059] Furthermore, a third resin 79 that covers the second resin 77 is molded. The third resin 79 shields the light emitted from the semiconductor light-emitting device. The third resin 79 is, for example, an epoxy resin containing carbon.

[0060] In the photocoupler 70, the semiconductor light-emitting device 1 is encapsulated with a first resin 75 which is an inelastic resin. Further, the semiconductor light-emitting device 1 is encapsulated via the first resin 75 with a resin 77 having a higher hardness than the first resin 75. By using such a double encapsulation structure, the resin stress applied to the semiconductor light-emitting device 1 can be suppressed, and its reliability can be improved.

[0061] As described above, in the semiconductor light-emitting devices 1 and 2, by providing the semiconductor multilayer film 23 between the GaAs substrate 10 and the light-emitting layer 21 and inclining the surface 10F of the GaAs substrate 10 with respect to the (100) plane, it becomes possible to prevent crystal defects generated in the process of chip formation from affecting its reliability. For example, when the light-emitting layer 21 has lower rigidity (hardness) than the GaAs substrate 10 and the semiconductor multilayer film 23 includes a plurality of layers having different rigidities or linear expansion coefficients from each other, such an effect is more remarkable.

[0062] That is, the semiconductor multilayer film 23 suppresses the propagation of dislocations from the GaAs substrate 10 to the light-emitting layer 21. Further, by inclining the crystal growth surface of the GaAs substrate 10 with respect to the (100) plane, the effect of suppressing the propagation of dislocations in the semiconductor multilayer film 23 can be enhanced. Since the light-emitting layer 21 of the semiconductor light-emitting device 1 has a strained quantum well in which deterioration of the light-emitting characteristics due to the propagation of dislocations is likely to occur, the above-described effect of suppressing dislocations becomes more remarkable.

[0063] Note that the embodiments are not limited to those exemplified above. For example, instead of the scribing method, a dicing method can be used for the chip. Even in cutting with a dicing blade, since defects occur on the cut surface, it is considered that the extension of dislocations along a crystal plane equivalent to the (111) plane occurs. Therefore, the configuration of combining the inclination of the semiconductor multilayer film 23 and the surface 10F of the GaAs substrate 10 is also effective when using the dicing method.

[0064] Also, the logarithm of the first layer 23a and the second layer 23b in the semiconductor multilayer film 23 is not limited to 10, and at least two pairs or more are sufficient. Also, the suppression of dislocation propagation occurs at the interface between the first layer 23a and the second layer 23b. Therefore, the film thicknesses of the first layer 23a and the second layer 23b may be variously deformed.

[0065] Also, although the (011) plane is exemplified as the side surface 10S of the GaAs substrate 10, it is not limited thereto. For example, the crystal planes of (01-1), (0-1-1), and (0-11) equivalent to the (011) plane may be used. That is, when the surface 10F of the GaAs substrate 10 is inclined with respect to the (01-1) plane, dislocations propagate along the (1-11) plane. When inclined in the (0-1-1) plane direction, it propagates along the (111) plane, and when inclined in the (0-11) plane direction, it propagates along the (11-1) plane.

[0066] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0067] 1, 2... semiconductor light-emitting device, 10... GaAs substrate, 10B... back surface, 10F... front surface, 10S... side surface, 20... epitaxial growth layer, 21... light-emitting layer, 21b... barrier layer, 21w... quantum well layer, 23... semiconductor multilayer film, 23a... first layer, 23b... second layer, 25... n-type clad layer, 27... p-type clad layer, 29... p-type contact layer, 30, 50... first electrode, 40, 60... second electrode, 70... photocoupler, 71... input-side lead, 73... output-side lead, 75... first resin, 77... second resin, 79... third resin, θ... tilt angle, BE... braking blade, CP... crack, CS... chip size, CT... chip thickness, DL... dark line, SL... scribe line, ST... scribe needle

Claims

1. A cubic gallium arsenide (GaAs) substrate, Provided on the GaAs substrate, an emission layer containing indium gallium arsenide (InGaAs) represented by the composition formula In ｘ Ga １－ｘ As (0 < x < 1), and A semiconductor multilayer film provided on the surface of the GaAs substrate inclined with respect to the (100) plane of the cubic crystal between the GaAs substrate and the light-emitting layer, Comprising, The semiconductor multilayer film includes a first layer and a second layer alternately laminated in a direction perpendicular to the surface of the GaAs substrate, and the first layer has a composition different from that of the second layer, The GaAs substrate has a back surface opposite to the surface, and side surfaces connecting the surface and the back surface, At least one of the side surface of the GaAs substrate and the corner where the side surface and the back surface are connected includes a crystal dislocation extending in a direction toward the semiconductor multilayer film, a semiconductor light-emitting device.

2. A cubic gallium arsenide (GaAs) substrate, Provided on the GaAs substrate, a light-emitting layer containing indium gallium arsenide (InGaAs) represented by the composition formula In ｘ Ga １－ｘ As (0 < x < 1), and A semiconductor multilayer film provided on the surface of the GaAs substrate inclined with respect to the (100) plane of the cubic crystal between the GaAs substrate and the light-emitting layer, Comprising, The semiconductor multilayer film includes a first layer and a second layer alternately laminated in a direction perpendicular to the surface of the GaAs substrate, and the first layer has a composition different from that of the second layer, The semiconductor multilayer film transmits light emitted from the light-emitting layer, a semiconductor light-emitting device.

3. A cubic gallium arsenide (GaAs) substrate, Provided on the GaAs substrate, a light-emitting layer containing indium gallium arsenide (InGaAs) represented by the composition formula In ｘ Ga １－ｘ As (0 < x < 1), and A semiconductor multilayer film provided on the surface of the GaAs substrate inclined with respect to the (100) plane of the cubic crystal between the GaAs substrate and the light-emitting layer, Comprising, The semiconductor multilayer film includes a first layer and a second layer alternately laminated in a direction perpendicular to the surface of the GaAs substrate, and the first layer has a composition different from that of the second layer, The first layer of the semiconductor multilayer film is an indium aluminum phosphide (InAlP) layer represented by the composition formula In ｙ Al １－ｙ P (0 < y < 1), and the second layer is gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) represented by the composition formula Al ｖ Ga １－ｖ As (0 ≤ v < 1), a semiconductor light-emitting device.

4. A cubic gallium arsenide (GaAs) substrate, Provided on the GaAs substrate, a light-emitting layer containing indium gallium arsenide (InGaAs) represented by the composition formula In ｘ Ga １－ｘ As (0 < x < 1), and A semiconductor multilayer film provided on the surface of the GaAs substrate inclined with respect to the (100) plane of the cubic crystal between the GaAs substrate and the light-emitting layer, Comprising, The semiconductor multilayer film includes a first layer and a second layer alternately laminated in a direction perpendicular to the surface of the GaAs substrate, and the first layer has a composition different from that of the second layer, The first layer of the semiconductor multilayer film is an InGaAs layer, and the second layer is a gallium arsenide phosphide (GaAsP) layer represented by the composition formula GaAs ｗ P １－ｗ (0 < w < 1), which is a semiconductor light-emitting device.

5. A cubic gallium arsenide (GaAs) substrate, Provided on the GaAs substrate, a light-emitting layer containing indium gallium arsenide (InGaAs) represented by the composition formula In ｘ Ga １－ｘ As (0 < x < 1), and A semiconductor multilayer film provided on the surface of the GaAs substrate inclined with respect to the (100) plane of the cubic crystal between the GaAs substrate and the light-emitting layer, Comprising, The semiconductor multilayer film includes a first layer and a second layer that are alternately stacked in a direction perpendicular to the surface of the GaAs substrate, and the first layer seals a semiconductor light-emitting device having a composition different from that of the second layer with a first resin. A photocoupler having a sealing structure that covers the semiconductor light-emitting device with a second resin via the first resin, wherein the second resin has a higher hardness than the first resin. **Claim 6** The photocoupler according to claim 5, wherein the surface of the GaAs substrate is inclined at an angle between 8° and 25° with respect to the (100) plane of the cubic crystal. **Claim 7** The GaAs substrate has a back surface opposite to the surface, and side surfaces connecting the surface and the back surface. At least one of the side surfaces of the GaAs substrate and the corners where the side surfaces and the back surface are connected includes a crystal dislocation extending in a direction toward the semiconductor multilayer film. The semiconductor light-emitting device according to any one of claims 2 to 4, wherein the side surface of the GaAs substrate is a (011) plane of the cubic crystal or a crystal plane equivalent to the (011) plane. **Claim 8** The GaAs substrate has a back surface opposite to the surface, and side surfaces connecting the surface and the back surface. At least one of the side surfaces of the GaAs substrate and the corners where the side surfaces and the back surface are connected includes a crystal dislocation extending in a direction toward the semiconductor multilayer film. The photocoupler according to claim 5 or 6, wherein the side surface of the GaAs substrate is a (011) plane of the cubic crystal or a crystal plane equivalent to the (011) plane. **Claim 9** The semiconductor light-emitting device according to claim 1 or 7, wherein the crystal dislocation of the GaAs substrate extends along a crystal plane equivalent to the (111) plane of the cubic crystal. **Claim 10** The photocoupler according to claim 8, wherein the crystal dislocation of the GaAs substrate extends along a crystal plane equivalent to the (111) plane of the cubic crystal.

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