Semiconductor device

Abstract

To provide a semiconductor device which can improve a tolerance dose while suppressing an increase in on-resistance.SOLUTION: A plurality of gate electrodes include a first gate electrode 17a and a second gate electrode 17b. In a cell region 7 of a semiconductor element 4, a region where current flows between a front surface electrode and a back surface electrode by applying voltage to the first gate electrode 17a is a first cell region 7a, and a region where current flows between the front surface electrode and the back surface electrode by applying voltage to the second gate electrode 17b is a second cell region 7b. The semiconductor element 4 and a control circuit are structured such that a time difference of a current interruption occurs between the first cell region 7a and the second cell region 7b when interrupting the current flowing through the first cell region 7a and the second cell region 7b.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which an electrical connection member is connected to a surface electrode of a semiconductor substrate.

Background Art

[0002] This electrical connection member connects the surface electrode of the semiconductor element to an external circuit and plays a role of reducing the temperature rise of the semiconductor element by heat dissipation.

[0003] In a semiconductor device provided with such an electrical connection member, a thermal resistance difference occurs between a portion of the semiconductor element connected to the electrical connection member and an outer portion thereof. Then, this thermal resistance difference promotes current positive feedback, resulting in a decrease in withstand voltage and a risk of element breakdown. Regarding this, a technique of alleviating heat concentration by thinning out cells outside the electrical connection member has been proposed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when thinning out the cells in this way, the on-resistance during normal operation increases and the power loss becomes large.

[0006] In view of the above points, an object of the present invention is to provide a semiconductor device capable of improving the withstand voltage while suppressing an increase in on-resistance.

Means for Solving the Problems

[0007] In order to achieve the above object, in the invention according to claim 1, there is provided a semiconductor device including a substrate (11), a surface electrode (19) formed on the front surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate. By applying a voltage to the plurality of gate electrodes, a semiconductor element (4) that controls conduction and interruption between the surface electrode and the back surface electrode, a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes, and a control circuit (24) having a connection circuit (27) that connects the plurality of gate electrodes, and an electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the surface electrode. The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b). Among the cell regions (7) of the semiconductor element, a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b). The semiconductor element and the control circuit are configured such that a time difference in current interruption occurs between the first cell region and the second cell region when interrupting the current flowing through the first cell region and the second cell region. The first gate electrode and the second gate electrode are each formed in a stripe shape. , complex Lumps of a plurality of first gate electrodes and lumps of one or a plurality of second gate electrodes are arranged alternately.

[0008] According to this, during normal operation, both the first and second cell regions are operated, and when interrupting the current, the current can be interrupted first in one cell region to pseudo-reduce the number of cells. Therefore, it is possible to suppress an increase in on-resistance during normal operation, reduce a temperature rise due to current positive feedback during interruption, and improve the withstand capacity of the semiconductor element.

[0009] Note that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0012] (First Embodiment) The first embodiment will be described. The semiconductor device 1 of the present embodiment shown in FIG. 1 is used in a load driving circuit that supplies power to an electrical load such as a vehicle ECU. ECU is an abbreviation for Electronic Control Unit. The semiconductor device 1 includes a lead frame 2, solder 3, a semiconductor element 4, solder 5, and an electrical connection member 6.

[0013] The lead frame 2 is a plate-like member that supports the semiconductor element 4 and is made of a conductive material such as copper. The back surface of the semiconductor element 4 is joined to the surface of the lead frame 2 by the solder 3.

[0014] The semiconductor element 4 is a switching element such as a MOSFET or an IGBT that controls the energized and cut-off states by applying a voltage. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0015] In the present embodiment, a case where the semiconductor element 4 is a trench gate type DMOS element in which a source electrode and a gate electrode are formed on the front surface side and a drain electrode is formed on the back surface will be described. DMOS is an abbreviation for Double-Diffused MOSFET. The back surface of the electrical connection member 6 is joined to the surface of the semiconductor element 4 by the solder 5.

[0016] The electrical connection member 6 connects the source electrode of the semiconductor element 4 to a lead portion (not shown) of the lead frame 2 and is made of a conductive material such as copper. Further, the electrical connection member 6 also serves to dissipate the heat of the semiconductor element 4 and suppress the temperature rise of the semiconductor element 4. The electrical connection member 6 of the present embodiment is what is called a heat sink, a heat spreader, a clip, etc., and a rectangular plate-shaped end portion is placed on the surface side of the semiconductor element 4.

[0017] A detailed configuration of the semiconductor element 4 will be described. As shown in FIG. 2, the semiconductor element 4 has a structure in which an outer peripheral region 8 is arranged so as to surround a square cell region 7. A large number of trench gate type DMOSs shown in FIG. 3 are formed in the cell region 7, and gate pads 9 connected to a gate electrode 17 described later are formed in the outer peripheral region 8.

[0018] The solder 5 and the electrical connection member 6 are arranged so as to cover a part of the cell region 7, and heat dissipation is mainly performed in this region, that is, in the portion of the semiconductor element 4 located below the electrical connection member 6. The region where this heat dissipation is performed is defined as a heat dissipation region 10. In the present embodiment, the heat dissipation region 10 is a rectangular region in the inner peripheral portion of the cell region 7.

[0019] As shown in FIG. 3, the semiconductor element 4 includes a substrate 11, an n-type epitaxial layer 12, a p-type high impurity layer 13, an n + -type source region 14, a trench 15, a gate insulating film 16, a gate electrode 17, an interlayer insulating film 18, a source electrode 19, and a drain electrode 20.

[0020] The substrate 11 is made of, for example, silicon. An n-type epitaxial layer 12 is formed on the surface of the substrate 11. In the semiconductor element 4, each part constituting DMOS etc. is formed on the n-type epitaxial layer 12.

[0021] A p-type highly doped layer 13 is formed on the surface layer of the n-type epitaxial layer 12. The p-type highly doped layer 13 is formed by ion-implanting p-type impurities to a predetermined depth from the surface of the n-type epitaxial layer 12. The p-type highly doped layer 13 functions as a p-type body layer and also functions as a p-type channel layer that forms a channel of the MOSFET.

[0022] A part of the surface layer of the p-type highly doped layer 13 has an n + -type source region 14 formed therein. + The n-type source region 14 is formed by ion-implanting n-type impurities to a predetermined depth from the surface of the p-type highly doped layer 13. + A plurality of n-type source regions 14 are formed, and the plurality of n + -type source regions 14 are formed in a stripe shape with one direction parallel to the surface of the substrate 11 as the longitudinal direction.

[0023] In the portion of the semiconductor element 4 where the n + -type source region 14 is formed, a trench 15 is formed. The trench 15 is formed so as to penetrate the n-type source region 14 and the p-type highly doped layer 13 and reach the n-type epitaxial layer 12. + The trench 15 is formed so as to penetrate the n-type source region 14 and the p-type highly doped layer 13 and reach the n-type epitaxial layer 12. A plurality of trenches 15 are formed corresponding to the n + -type source region 14, and the plurality of trenches 15 are formed in a stripe shape with the same direction as the n + -type source region 14 as the longitudinal direction.

[0024] A gate insulating film 16 is formed on the inner wall surface of the trench 15 by an oxide film or the like. On the surface side of the substrate 11, a gate electrode 17 is formed so as to fill the trench 15 on the surface of the gate insulating film 16. The gate electrode 17 is connected to the gate pad 9 by a gate wiring layer (not shown).

[0025] As described later, a source electrode 19 and a drain electrode 20 are formed on the front and back surfaces of the semiconductor element 4. When a gate voltage is applied to the gate electrode 17 via the gate pad 9 and a gate wiring layer (not shown), a channel is formed in a portion of the p-type high impurity layer 13 that contacts the side surface of the trench 15, and a drain current flows between the source electrode 19 and the drain electrode 20.

[0026] The gate electrode 17 is n + type source regions 14 and a plurality of trenches 15 are formed corresponding thereto, and the plurality of gate electrodes 17 include a first gate electrode 17a and a second gate electrode 17b. Among the cell regions 7, a region where a current flows between the source electrode 19 and the drain electrode 20 by applying a voltage to the first gate electrode 17a is defined as a first cell region 7a. Also, among the cell regions 7, a region where a current flows between the source electrode 19 and the drain electrode 20 by applying a voltage to the second gate electrode 17b is defined as a second cell region 7b.

[0027] As shown in FIG. 2, the first gate electrode 17a and the second gate electrode 17b are formed in a stripe shape so as to be arranged alternately. And the first cell region 7a and the second cell region 7b are formed in a stripe shape so as to be arranged alternately along the extending direction of the first gate electrode 17a and the second gate electrode 17b.

[0028] A plurality of gate pads 9 are formed in the outer peripheral region 8. The first gate electrode 17a and the second gate electrode 17b are connected to different gate pads 9, and it is possible to connect the first gate electrode 17a and the second gate electrode 17b to a drive circuit 26 described later through different paths.

[0029] An interlayer insulating film 18 is formed on the gate electrode 17. In the interlayer insulating film 18, contact holes are provided so as to cover the gate electrode 17 and expose the surfaces of the p-type high impurity layer 13 and the n + type source region 14. The source electrode 19 covers the interlayer insulating film 18 and is connected to the p-type high impurity layer 13 and the n through the contact holes in the interlayer insulating film 18.+ It is formed on the surface side of the substrate 11 so as to be in contact with the type source region 14. The source electrode 19 corresponds to the surface electrode.

[0030] The source electrode 19 is formed over the entire cell region 7, and its outer edge is covered by a protective film (not shown). The region inside the outer edge is exposed from the protective film, and this region serves as a source pad for external connection. The semiconductor element 4 is electrically connected to the electrical connection member 6 via the solder 5 at this source pad. Then, heat moves from the source electrode 19 to the electrical connection member 6 via the solder 5, thereby suppressing the temperature rise of the semiconductor element 4.

[0031] A drain electrode 20 is formed on the back side of the substrate 11, that is, on the surface opposite to the n-type epitaxial layer 12. The drain electrode 20 corresponds to the back surface electrode. With such a structure, a MOSFET in the cell region 7 is configured, and by applying a voltage to the gate electrode 17, the conduction and interruption between the source electrode 19 and the drain electrode 20 are controlled.

[0032] A load driving circuit using the semiconductor device 1 will be described. The load driving circuit shown in FIG. 4 is configured to switch on and off the current supplied from the power source to the electrical load by the semiconductor element 4. The load driving circuit includes the semiconductor element 4, a power source 21, a wiring 22, a load 23, and a control circuit 24.

[0033] The power source 21 is connected to the drain electrode 20 of the semiconductor element 4 by the wiring 22. A load 23 is connected to the source electrode 19 of the semiconductor element 4. The diode 25 shown in FIG. 4 is a parasitic diode composed of the n-type epitaxial layer 12 and the p-type high impurity layer 13 of the semiconductor element 4. The gate electrode 17 of the semiconductor element 4 is connected to the control circuit 24.

[0034] The control circuit 24 applies a voltage to a plurality of gate electrodes 17, and is composed of a drive circuit 26 and a connection circuit 27. The drive circuit 26 outputs a voltage to be applied to the plurality of gate electrodes 17. The drive circuit 26 is connected to the plurality of gate electrodes 17 via the connection circuit 27. The semiconductor device 1 includes the connection circuit 27 of the control circuit 24. The drive circuit 26 may be provided in the semiconductor device 1 or may be provided outside the semiconductor device 1.

[0035] When the semiconductor element 4 and the control circuit 24 cut off the current flowing through the first cell region 7a and the second cell region 7b, a time difference in current interruption occurs between the first cell region 7a and the second cell region 7b.

[0036] Specifically, when the semiconductor element 4 and the control circuit 24 cut off the current flowing through the first cell region 7a and the second cell region 7b, the drain current is cut off in the first cell region 7a earlier than in the second cell region 7b. The first cell region 7a is formed to include the outside of the portion of the semiconductor element 4 located below the electrical connection member 6, and the second cell region 7b is formed to include the portion of the semiconductor element 4 located below the electrical connection member 6.

[0037] As shown in FIG. 2, in the present embodiment, both the first cell region 7a and the second cell region 7b are formed in the portion of the semiconductor element 4 located below the electrical connection member 6, that is, the heat dissipation region 10, and outside the heat dissipation region 10.

[0038] In the present embodiment, the connection circuit 27 is configured such that a difference in conduction resistance occurs between the first cell region 7a and the second cell region 7b, thereby causing a time difference in current interruption. Specifically, the first gate electrode 17a and the second gate electrode 17b are connected to the drive circuit 26 through different paths by the connection circuit 27. A difference in resistance value is provided between the portion of the connection circuit 27 connecting the first gate electrode 17a and the drive circuit 26 and the portion connecting the second gate electrode 17b and the drive circuit 26.

[0039] For example, as shown in FIG. 4, the connection circuit 27 includes a circuit that short - circuits the first gate electrode 17a and the drive circuit 26, and a circuit that connects the second gate electrode 17b and the drive circuit 26 via a resistor 28.

[0040] Alternatively, as shown in FIG. 5, the first gate electrode 17a and the drive circuit 26 are connected via a resistor 29, and the second gate electrode 17b and the drive circuit 26 are connected via a resistor 30. Let the resistance values of the resistor 29 and the resistor 30 be R1 and R2 respectively, and R1 < R2. The resistor 29 and the resistor 30 correspond to the first resistor and the second resistor respectively.

[0041] In this way, by making the gate resistance value of the second gate electrode 17b larger than that of the first gate electrode 17a, when the voltage applied from the drive circuit 26 to the plurality of gate electrodes 17 is turned off, the drain current of the first cell region 7a is cut off earlier than that of the second cell region 7b. That is, the cells on the semiconductor element 4 are in a state of being pseudo - thinned.

[0042] FIG. 6 shows the relationship between the gate voltage and the drain current when only the first cell region 7a is operated and when both the first cell region 7a and the second cell region 7b are operated. In FIG. 6, the solid line and the broken line respectively show the relationship between the gate voltage and the drain current at room temperature and at high temperature when only the first cell region 7a is operated. The one - dot chain line and the two - dot chain line respectively show the relationship between the gate voltage and the drain current at room temperature and at high temperature when both the first cell region 7a and the second cell region 7b are operated.

[0043] As shown by the arrow in FIG. 6, when only the first cell region 7a is operated, that is, when the cells are pseudo - thinned, in the operating region at the time of cut - off, the difference in drain current between room temperature and high temperature is smaller than when both the first cell region 7a and the second cell region 7b are operated. In this way, by thinning the cells, the difference in drain current between room temperature and high temperature becomes smaller, and the temperature rise due to current positive feedback can be reduced.

[0044] When a ground fault occurs between the semiconductor element 4 and the load 23, the drive circuit 26 sends a control signal to the semiconductor element 4 and reduces the voltage of the gate electrode 17 to cut off the current supplied to the load 23. At this time, in the semiconductor element 4, since there is a thermal resistance difference between the inside and the outside of the heat dissipation region 10, this thermal resistance difference promotes the current positive feedback, resulting in a decrease in the withstand voltage and a possibility of element breakdown. Regarding this, there is a method of reducing the number of cells on the outside of the heat dissipation region 10 to alleviate the heat concentration and reduce the temperature rise due to the current positive feedback. However, when thinning out the cells in this way, the on-resistance during normal operation increases and the power loss becomes large.

[0045]

[0046] On the other hand, in this embodiment, both the first cell region 7a and the second cell region 7b are operated during normal operation. And when the drain current is cut off, one of the cell regions is cut off first, so that the number of cells is virtually reduced. Therefore, it is possible to suppress an increase in the on-resistance during normal operation, reduce the temperature rise due to the current positive feedback during cut-off, and improve the withstand voltage of the semiconductor element 4.

[0047] (1) When the semiconductor element 4 and the control circuit 24 cut off the current flowing through the first cell region 7a and the second cell region 7b, due to the difference in the conduction resistance between the first and second cell regions 7a and 7b, the current is cut off in the first cell region 7a before the second cell region 7b.

[0048] And the electrical connection member 6 is placed so as to cover a part of the surface side of the substrate 11, and the first cell region 7a is formed to include the outside of the portion of the semiconductor element 4 located below the electrical connection member 6. Also, the second cell region 7b is formed to include the portion of the semiconductor element 4 located below the electrical connection member 6.

[0049] By arranging the first cell region 7a where the drain current is cut off first outside the heat dissipation region 10 in this way, the temperature rise due to current positive feedback can be further reduced.

[0050] (Second Embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the arrangements of the first cell region 7a and the second cell region 7b are changed, and the rest is the same as the first embodiment. Therefore, only the parts different from the first embodiment will be described.

[0051] In this embodiment, only the second cell region 7b out of the first cell region 7a and the second cell region 7b is formed in the portion of the semiconductor element 4 located below the electrical connection member 6. Both the first cell region 7a and the second cell region 7b are formed outside the portion of the semiconductor element 4 located below the electrical connection member 6.

[0052] Specifically, as shown in FIG. 7, in the heat dissipation region 10, the second cell region 7b is formed in a stripe shape, and outside the heat dissipation region 10, the first cell region 7a and the second cell region 7b are alternately formed in a stripe shape.

[0053] This embodiment can obtain the same effects as the first embodiment from the same configuration and operation as the first embodiment.

[0054] Also, according to the above embodiment, the following effects can be obtained.

[0055] (1) Only the second cell region 7b out of the first cell region 7a and the second cell region 7b is formed in the portion of the semiconductor element 4 located below the electrical connection member 6. Also, the first cell region 7a and the second cell region 7b are formed outside the portion of the semiconductor element 4 located below the electrical connection member 6. Thereby, since the number of cells is pseudo-reduced only at the time of interruption outside the heat dissipation region 10, the temperature rise due to current positive feedback can be efficiently reduced.

[0056] (Third Embodiment) The third embodiment will be described. This embodiment is different from the second embodiment in that the numbers of the first cell regions 7a and the second cell regions 7b are changed, and since the other aspects are the same as those of the second embodiment, only the parts different from the second embodiment will be described.

[0057] In this embodiment, a plurality of first cell regions 7a and one second cell region 7b are alternately formed in a stripe shape. Specifically, as shown in FIG. 8, outside the heat dissipation region 10, clusters of three first cell regions 7a and one second cell region 7b are arranged alternately.

[0058] This embodiment can obtain the same effects as those of the first and second embodiments from the same configuration and operation as those of the first and second embodiments.

[0059] Also, according to the above embodiment, the following effects can be obtained.

[0060] (1) A plurality of first cell regions 7a and one second cell region 7b are arranged alternately. In such a configuration, when the semiconductor element 4 has a fine structure, the manufacturing of the semiconductor element 4 becomes easier compared to a configuration in which one first cell region 7a and one second cell region 7b are arranged alternately.

[0061] (Fourth Embodiment) The fourth embodiment will be described. This embodiment is different from the first embodiment in that the arrangement of the connection circuit 27 is changed, and since the other aspects are the same as those of the first embodiment, only the parts different from the first embodiment will be described.

[0062] In this embodiment, the connection circuit 27 is formed in a region of the semiconductor element 4 where no cells are arranged. Specifically, as shown in FIG. 9, the connection circuit 27 is arranged in a location away from the cell region 7 and the gate pad 9 in the outer peripheral region 8.

[0063] This embodiment can obtain the same effects as the first embodiment from the same configuration and operation as the first embodiment.

[0064] Also, according to the above embodiment, the following effects can be obtained.

[0065] (1) The connection circuit 27 is formed in a region of the semiconductor element 4 where cells are not arranged. In this way, by forming the cells of the semiconductor element 4 and the connection circuit 27 on the same substrate, the configuration of the circuit using the semiconductor device 1 is simplified.

[0066] (Fifth Embodiment) The fifth embodiment will be described. This embodiment is different from the first embodiment in the configuration of the connection circuit 27, and the rest is the same as the first embodiment. Therefore, only the parts different from the first embodiment will be described.

[0067] In this embodiment, a Zener diode is used to create a time difference in current interruption between the first cell region 7a and the second cell region 7b.

[0068] For example, as shown in FIG. 10, the connection circuit 27 includes a bidirectional Zener diode 31 in addition to resistors 29 and 30. R1 and R2 have the same value as each other. Note that the fact that R1 and R2 are equal to each other includes not only the case where they are exactly equal but also the case where they are approximately equal.

[0069] The second gate electrode 17b and the drain electrode 20 are connected via the Zener diode 31. The breakdown voltage of the Zener diode 31 when viewing the potential from the second gate electrode 17b to the drain electrode 20 is made larger than the voltage applied to the second gate electrode 17b during the normal operation of the semiconductor element 4.

[0070] In such a configuration, when blocking, the gate voltage decreases in the first cell region 7a, while in the second cell region 7b, a voltage is applied by the Zener diode 31. Therefore, the blocking in the second cell region 7b is slower than that in the first cell region 7a.

[0071] Alternatively, as shown in FIG. 11, the connection circuit 27 includes bidirectional Zener diodes 32 and 33 in addition to resistors 29 and 30. R1 and R2 have equal values. The first gate electrode 17a and the drain electrode 20 are connected via the Zener diode 32, and the second gate electrode 17b and the drain electrode 20 are connected via the Zener diode 33.

[0072] The breakdown voltage of the Zener diode 32 when viewing the potential of the drain electrode 20 from the first gate electrode 17a is greater than the voltage applied to the first gate electrode 17a during normal operation of the semiconductor element 4. Also, the breakdown voltage of the Zener diode 33 when viewing the potential of the drain electrode 20 from the second gate electrode 17b is greater than the voltage applied to the second gate electrode 17b during normal operation of the semiconductor element 4.

[0073] The breakdown voltage of the Zener diode 33 as viewed from the drain electrode 20 side is smaller than the breakdown voltage of the Zener diode 32 as viewed from the drain electrode 20 side. The Zener diode 32 and the Zener diode 33 correspond to the first Zener diode and the second Zener diode.

[0074] With such a configuration, voltages are applied to both the first cell region 7a and the second cell region 7b by the Zener diodes 32 and 33 during cutoff. However, since the breakdown voltage of the Zener diode 33 is smaller than that of the Zener diode 32, the cutoff in the second cell region 7b is slower than that in the first cell region 7a.

[0075] This embodiment can obtain the same effects as the first embodiment from the same configuration and operation as the first embodiment.

[0076] (Sixth Embodiment) A sixth embodiment will be described. This embodiment is different from the first embodiment in the configuration of the connection circuit 27, and is the same as the first embodiment in other respects. Therefore, only the differences from the first embodiment will be described.

[0077] In this embodiment, a delay circuit is used to create a time difference in current interruption between the first cell region 7a and the second cell region 7b.

[0078] For example, as shown in FIG. 12, the connection circuit 27 includes resistors 34 and a capacitor 35 in addition to resistors 29 and 30. R1 and R2 have equal values. The second gate electrode 17b and the source electrode 19 are connected via a circuit in which the resistor 34 and the capacitor 35 are connected in series. The resistor 34 corresponds to the third resistor.

[0079] In such a configuration, when interrupted, the gate voltage drops in the first cell region 7a, while in the second cell region 7b, the voltage drop is delayed by the delay circuit composed of the resistor 34 and the capacitor 35. Therefore, in the second cell region 7b, the interruption is slower than in the first cell region 7a.

[0080] Alternatively, as shown in FIG. 13, the connection circuit 27 includes resistors 36 and 38, capacitors 37 and 39 in addition to resistors 29 and 30. R1 and R2 have equal values. The first gate electrode 17a and the source electrode 19 are connected via a circuit in which the resistor 36 and the capacitor 37 are connected in series, and the second gate electrode 17b and the source electrode 19 are connected via a circuit in which the resistor 38 and the capacitor 39 are connected in series.

[0081] The capacitance of the capacitor 39 is made larger than the capacitance of the capacitor 37. The resistors 36 and 38 correspond to the fourth resistor and the fifth resistor, respectively, and the capacitors 37 and 39 correspond to the first capacitor and the second capacitor, respectively.

[0082] In such a configuration, during interruption, the voltage drop is delayed in both the first cell region 7a and the second cell region 7b by the delay circuits composed of the resistor 36 and the capacitor 37, and the delay circuit composed of the resistor 38 and the capacitor 39. However, since the capacitance of the capacitor 39 is larger than that of the capacitor 37, the interruption in the second cell region 7b is slower than that in the first cell region 7a.

[0083] This embodiment can obtain the same effects as the first embodiment from the same configuration and operation as the first embodiment.

[0084] (Seventh Embodiment) The seventh embodiment will be described. This embodiment is obtained by changing the configurations of the semiconductor element 4 and the connection circuit 27 with respect to the first embodiment, and since the other aspects are the same as those of the first embodiment, only the parts different from the first embodiment will be described.

[0085] In this embodiment, by providing a difference in threshold voltage between the first gate electrode 17a and the second gate electrode 17b, a time difference in current interruption is created between the first cell region 7a and the second cell region 7b.

[0086] The threshold voltage can be adjusted by the thickness of the gate insulating film 16. That is, as shown in FIG. 14, the gate insulating film 16 in the trench 15 where the first gate electrode 17a is formed is formed thicker than the gate insulating film 16 in the trench 15 where the second gate electrode 17b is formed. Thereby, the threshold voltage of the first cell region 7a becomes larger than that of the second cell region 7b.

[0087] In such a configuration, the first cell region 7a and the second cell region 7b can be connected to the drive circuit 26 by circuits having the same configuration. For example, as shown in FIG. 15, the connection circuit 27 is configured to short-circuit the first gate electrode 17a and the second gate electrode 17b to the drive circuit 26.

[0088] Alternatively, the connection circuit 27 is configured as shown in FIG. 5, and R1 = R2. Alternatively, the connection circuit 27 is configured as shown in FIG. 11. With the breakdown voltages of the Zener diodes 32 and 33 being Vz1 and Vz2 respectively, R1 = R2 and Vz1 = Vz2. Note that the equality of Vz1 and Vz2 includes not only the case where they are exactly equal but also the case where they are approximately equal.

[0089] This embodiment can achieve the same effects as the first embodiment from the same configuration and operation as the first embodiment.

[0090] (Eighth Embodiment) The eighth embodiment will be described. This embodiment is obtained by changing the configuration of the control circuit 24 with respect to the first embodiment, and since the other aspects are the same as those of the first embodiment, only the differences from the first embodiment will be described.

[0091] In this embodiment, due to the driving capabilities of the drive circuits 26, a time difference in current interruption is generated between the first cell region 7a and the second cell region 7b. As shown in FIG. 16, two drive circuits 26 are arranged in this embodiment. The two drive circuits 26 are respectively referred to as a first drive circuit 26a and a second drive circuit 26b.

[0092] The first drive circuit 26a is short-circuited to the first gate electrode 17a by the connection circuit 27, and the second drive circuit 26b is short-circuited to the second gate electrode 17b by the connection circuit 27. The first drive circuit 26a has a higher driving capability than the second drive circuit 26b.

[0093] By making the driving capability of the first drive circuit 26a higher than that of the second drive circuit 26b, when the first drive circuit 26a and the second drive circuit 26b output an off signal simultaneously, the gate voltage in the first cell region 7a drops faster than in the second cell region 7b, and the drain current is interrupted. Note that if the drain current in the first cell region 7a is interrupted earlier than in the second cell region 7b, the second drive circuit 26b may output an off signal earlier than the first drive circuit 26a.

[0094] This embodiment can obtain the same effects as the first embodiment from the same configuration and operation as the first embodiment.

[0095] (Other Embodiments) Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified within the scope described in the claims. Also, the above embodiments are not unrelated to each other, and can be appropriately combined except in cases where the combination is clearly impossible. Further, in each of the above embodiments, it goes without saying that the elements constituting the embodiment are not necessarily essential except in cases where it is explicitly stated that they are essential and cases where they are considered to be clearly essential in principle.

[0096] In each of the above embodiments, the case where the semiconductor element 4 is a DMOS element has been described, but the semiconductor element 4 may be another semiconductor element. For example, the semiconductor element 4 may be an IGBT element.

[0097] In the first embodiment, the number of the first cell regions 7a and the second cell regions 7b may be set as in the third embodiment. In the second and third embodiments, the connection circuit 27 may be formed on the semiconductor element 4 as in the fourth embodiment. In the second to fourth embodiments, the connection circuit 27 may be configured as in the fifth and sixth embodiments. In the second to fourth embodiments, the semiconductor element 4 may be configured as in the seventh embodiment. In the second and third embodiments, the drive circuit 26 may be configured as in the eighth embodiment.

[0098] In the third embodiment, two first cell regions 7a and one second cell region 7b may be arranged alternately. Also, four or more first cell regions 7a and one second cell region 7b may be arranged alternately. Also, one first cell region 7a and a plurality of second cell regions 7b may be arranged alternately. Also, a plurality of first cell regions 7a and a plurality of second cell regions 7b may be arranged alternately.

[0099] As shown in FIGS. 17 and 18, the electrical connection member 6 may be arranged such that the heat dissipation region 10 includes a part of the outer peripheral portion of the cell region 7. As shown in FIG. 17, only the second cell region 7b among the first cell region 7a and the second cell region 7b may be formed inside the heat dissipation region 10, and only the first cell region 7a may be formed outside the heat dissipation region 10. In each of the above embodiments, the cells are pseudo-thinned during interruption. However, as shown in FIG. 17, by limiting the region to be interrupted first, it is possible to suppress an increase in on-resistance during normal operation and reduce the temperature rise due to current positive feedback during interruption. Further, when the heat dissipation region 10 includes a part of the outer peripheral portion of the cell region 7, as shown in FIG. 18, only the second cell region 7b among the first cell region 7a and the second cell region 7b may be formed inside the heat dissipation region 10, and both of them may be formed outside the heat dissipation region 10.

[0100] As shown in FIG. 19, the electrical connection member 6 may be constituted by a bonding wire. In this case, two electrical connection members 6 may be connected to the source electrode 19 to form two heat dissipation regions 10 as shown in FIG. 20.

[0101] In FIGS. 2, 7 to 9, 17, and 18, the first cell region 7a, the second cell region 7b, the first gate electrode 17a, and the second gate electrode 17b extend in the left-right direction of the drawing, but they may extend in the up-down direction of the drawing.

Explanation of Reference Numerals

[0102] 4 Semiconductor element 6 Electrical connection member 7a First cell region 7b Second cell region 17a First gate electrode 17b Second gate electrode 24 Control circuit

Claims

1. A semiconductor device, comprising: a substrate (11), a surface electrode (19) formed on the surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the surface side of the substrate, wherein a semiconductor element (4) controls conduction and interruption between the surface electrode and the back surface electrode by applying a voltage to the plurality of gate electrodes; a control circuit (24) having a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes and a connection circuit (27) that connects the drive circuit to the plurality of gate electrodes; an electrical connection member (6) placed on the surface side of the semiconductor element and electrically connected to the surface electrode; the plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b); in a cell region (7) of the semiconductor element, a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b); the semiconductor element and the control circuit are configured such that a time difference in current interruption occurs between the first cell region and the second cell region when interrupting the current flowing through the first cell region and the second cell region; the first gate electrode and the second gate electrode are each formed in a stripe shape; A semiconductor device in which clusters of a plurality of the first gate electrodes and clusters of one or more of the second gate electrodes are arranged alternately.

2. The semiconductor device according to claim 1, wherein the number of the first gate electrodes is equal to or greater than the number of the second gate electrodes outside a portion of the semiconductor element located below the electrical connection member.

3. the electrical connection member is placed so as to cover a part of the surface side of the substrate; the first cell region is formed to include an outside of a portion of the semiconductor element located below the electrical connection member; The semiconductor device according to claim 1 or 2, wherein the second cell region is formed to include a portion of the semiconductor element located below the electrical connection member.

4. Only the second cell region of the first cell region and the second cell region is formed in a portion of the semiconductor element located below the electrical connection member. The semiconductor device according to claim 3, wherein the first cell region and the second cell region are formed outside a portion of the semiconductor element that is located below the electrical connection member.

5. A semiconductor device, comprising a substrate (11), a surface electrode (19) formed on the front surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate, wherein a semiconductor element (4) controls conduction and interruption between the surface electrode and the back surface electrode by applying a voltage to the plurality of gate electrodes; a control circuit (24) having a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes and a connection circuit (27) that connects the drive circuit to the plurality of gate electrodes; and an electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the surface electrode. The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b). Of the cell region (7) of the semiconductor element, a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b). The semiconductor element and the control circuit are configured such that a time difference in current interruption occurs between the first cell region and the second cell region when interrupting the current flowing through the first cell region and the second cell region. The electrical connection member is placed so as to cover a part of the front surface side of the substrate. The first cell region is formed to include the outside of a portion of the semiconductor element that is located below the electrical connection member. The second cell region is formed to include a portion of the semiconductor element that is located below the electrical connection member. Only the second cell region of the first cell region and the second cell region is formed in a portion of the semiconductor element that is located below the electrical connection member. A semiconductor device in which the first cell region and the second cell region are formed outside a portion of the semiconductor element that is located below the electrical connection member.

6. The drive circuit and the first gate electrode are short-circuited. The semiconductor device according to any one of claims 1 to 5, wherein the drive circuit and the second gate electrode are connected via a resistor (28).

7. The drive circuit and the first gate electrode are connected via a first resistor (29), The semiconductor device according to any one of claims 1 to 5, wherein the drive circuit and the second gate electrode are connected via a second resistor (30) having a resistance value larger than that of the first resistor.

8. The drive circuit and the first gate electrode are connected via a first resistor (29), The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor, The second gate electrode and the back surface electrode are connected via a bidirectional Zener diode (31), The semiconductor device according to any one of claims 1 to 5, wherein the breakdown voltage of the Zener diode as viewed from the side of the second gate electrode is larger than the voltage applied to the second gate electrode during normal operation of the semiconductor element.

9. The drive circuit and the first gate electrode are connected via a first resistor (29), The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor, The first gate electrode and the back surface electrode are connected via a bidirectional first Zener diode (32), The second gate electrode and the back surface electrode are connected via a bidirectional second Zener diode (33), The breakdown voltage of the first Zener diode as viewed from the side of the first gate electrode is larger than the voltage applied to the first gate electrode during normal operation of the semiconductor element, The breakdown voltage of the second Zener diode as viewed from the side of the second gate electrode is larger than the voltage applied to the second gate electrode during normal operation of the semiconductor element, The semiconductor device according to any one of claims 1 to 5, wherein the breakdown voltage of the second Zener diode as viewed from the side of the back surface electrode is smaller than the breakdown voltage of the first Zener diode as viewed from the side of the back surface electrode.

10. The drive circuit and the first gate electrode are connected via a first resistor (29), The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor, The semiconductor device according to any one of claims 1 to 5, wherein the second gate electrode and the surface electrode are connected via a circuit in which a third resistor (34) and a capacitor (35) are connected in series.

11. The drive circuit and the first gate electrode are connected via a first resistor (29), The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor, The first gate electrode and the surface electrode are connected via a circuit in which a fourth resistor (36) and a first capacitor (37) are connected in series, The semiconductor device according to any one of claims 1 to 5, wherein the second gate electrode and the surface electrode are connected via a circuit in which a fifth resistor (38) and a second capacitor (39) having a capacitance larger than that of the first capacitor are connected in series.

12. The first gate electrode is connected to a first drive circuit (26a), The second gate electrode is connected to a second drive circuit (26b), The semiconductor device according to any one of claims 1 to 5, wherein the driving ability of the first drive circuit is higher than that of the second drive circuit.

13. The drive circuit is short-circuited with the first gate electrode and the second gate electrode, The semiconductor device according to any one of claims 1 to 5, wherein the threshold voltage of the first cell region is larger than the threshold voltage of the second cell region.

14. The drive circuit and the first gate electrode are connected via a first resistor (29), The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor, The semiconductor device according to any one of claims 1 to 5, wherein the threshold voltage of the first cell region is larger than the threshold voltage of the second cell region.

15. The drive circuit and the first gate electrode are connected via a first resistor (29), The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor, The first gate electrode and the back electrode are connected via a bidirectional first Zener diode (32), The second gate electrode and the back electrode are connected via a bidirectional second Zener diode (33). The breakdown voltage of the first Zener diode as viewed from the side of the first gate electrode is greater than the voltage applied to the first gate electrode during normal operation of the semiconductor element. The breakdown voltage of the second Zener diode as viewed from the side of the second gate electrode is greater than the voltage applied to the second gate electrode during normal operation of the semiconductor element. The breakdown voltages of the first Zener diode and the second Zener diode as viewed from the side of the back electrode are equal to each other. The semiconductor device according to any one of claims 1 to 5, wherein the threshold voltage of the first cell region is greater than the threshold voltage of the second cell region.

16. A semiconductor device, comprising a substrate (11), a surface electrode (19) formed on the front surface side of the substrate, a back electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate, wherein energization and interruption between the surface electrode and the back electrode are controlled by applying a voltage to the plurality of gate electrodes. A semiconductor element (4); A control circuit (24) having a drive circuit (26) for outputting a voltage to be applied to the plurality of gate electrodes and a connection circuit (27) for connecting the drive circuit and the plurality of gate electrodes; An electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the surface electrode. The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b). Of the cell regions (7) of the semiconductor element, a region where a current flows between the surface electrode and the back electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the surface electrode and the back electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b). The semiconductor element and the control circuit are configured such that a time difference in current interruption occurs between the first cell region and the second cell region when interrupting the current flowing through the first cell region and the second cell region. The drive circuit and the first gate electrode are connected via a first resistor (29). The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor. The first gate electrode and the back electrode are connected via a bidirectional first Zener diode (32). The second gate electrode and the back surface electrode are connected via a bidirectional second Zener diode (33). The breakdown voltage of the first Zener diode as viewed from the side of the first gate electrode is larger than the voltage applied to the first gate electrode during normal operation of the semiconductor element. The breakdown voltage of the second Zener diode as viewed from the side of the second gate electrode is larger than the voltage applied to the second gate electrode during normal operation of the semiconductor element. A semiconductor device in which the breakdown voltage of the second Zener diode as viewed from the side of the back surface electrode is smaller than the breakdown voltage of the first Zener diode as viewed from the side of the back surface electrode.

17. A semiconductor device comprising: a substrate (11), a surface electrode (19) formed on the front surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate, and a semiconductor element (4) that controls conduction and interruption between the surface electrode and the back surface electrode by applying a voltage to the plurality of gate electrodes; a control circuit (24) having a connection circuit (27) that connects a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes and the plurality of gate electrodes; an electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the surface electrode. The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b). In the cell region (7) of the semiconductor element, a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b). The semiconductor element and the control circuit are configured such that a time difference in current interruption occurs between the first cell region and the second cell region when interrupting the current flowing through the first cell region and the second cell region. The first gate electrode is connected to a first drive circuit (26a). The second gate electrode is connected to a second drive circuit (26b). A semiconductor device in which the driving ability of the first drive circuit is higher than the driving ability of the second drive circuit.

18. A semiconductor device comprising: A semiconductor device having a substrate (11), a surface electrode (19) formed on the front surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate, wherein energization and interruption between the surface electrode and the back surface electrode are controlled by applying a voltage to the plurality of gate electrodes (4); A control circuit (24) having a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes and a connection circuit (27) that connects the drive circuit to the plurality of gate electrodes; An electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the surface electrode; The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b); In a cell region (7) of the semiconductor element, a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b); The semiconductor element and the control circuit are configured such that a time difference in current interruption occurs between the first cell region and the second cell region when interrupting the current flowing through the first cell region and the second cell region; The drive circuit is short-circuited with the first gate electrode and the second gate electrode; A semiconductor device in which the threshold voltage of the first cell region is higher than the threshold voltage of the second cell region.

19. A semiconductor device, comprising: A semiconductor element (4) having a substrate (11), a surface electrode (19) formed on the front surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate, wherein energization and interruption between the surface electrode and the back surface electrode are controlled by applying a voltage to the plurality of gate electrodes; A control circuit (24) having a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes and a connection circuit (27) that connects the drive circuit to the plurality of gate electrodes; An electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the surface electrode; The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b); Of the cell region (7) of the semiconductor element, a region where a current flows between the front surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the front surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b). The semiconductor element and the control circuit are configured such that when cutting off the current flowing through the first cell region and the second cell region, a time difference in current cutoff occurs between the first cell region and the second cell region. The drive circuit and the first gate electrode are connected via a first resistor (29). The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor. A semiconductor device in which the threshold voltage of the first cell region is higher than the threshold voltage of the second cell region.

20. A semiconductor device, having a substrate (11), a front surface electrode (19) formed on the front surface side of the substrate, a back surface electrode (20) formed on the back surface side of the substrate, and a plurality of gate electrodes (17) formed on the front surface side of the substrate, and a semiconductor element (4) in which energization and interruption between the front surface electrode and the back surface electrode are controlled by applying a voltage to the plurality of gate electrodes; a control circuit (24) having a connection circuit (27) connecting a drive circuit (26) that outputs a voltage to be applied to the plurality of gate electrodes and the plurality of gate electrodes; and an electrical connection member (6) placed on the front surface side of the semiconductor element and electrically connected to the front surface electrode. The plurality of gate electrodes include a first gate electrode (17a) and a second gate electrode (17b). Of the cell region (7) of the semiconductor element, a region where a current flows between the front surface electrode and the back surface electrode when a voltage is applied to the first gate electrode is defined as a first cell region (7a), and a region where a current flows between the front surface electrode and the back surface electrode when a voltage is applied to the second gate electrode is defined as a second cell region (7b). The semiconductor element and the control circuit are configured such that when cutting off the current flowing through the first cell region and the second cell region, a time difference in current cutoff occurs between the first cell region and the second cell region. The drive circuit and the first gate electrode are connected via a first resistor (29). The drive circuit and the second gate electrode are connected via a second resistor (30) having the same resistance value as the first resistor. The first gate electrode and the back surface electrode are connected via a bidirectional first Zener diode (32). The second gate electrode and the back surface electrode are connected via a bidirectional second Zener diode (33). The breakdown voltage of the first Zener diode as viewed from the side of the first gate electrode is greater than the voltage applied to the first gate electrode during normal operation of the semiconductor element. The breakdown voltage of the second Zener diode as viewed from the side of the second gate electrode is greater than the voltage applied to the second gate electrode during normal operation of the semiconductor element. The breakdown voltages of the first Zener diode and the second Zener diode as viewed from the side of the back surface electrode are equal to each other. A semiconductor device in which the threshold voltage of the first cell region is greater than the threshold voltage of the second cell region.

21. The semiconductor device according to any one of claims 1 to 20, wherein when the semiconductor element and the control circuit cut off the current flowing through the first cell region and the second cell region, the current is cut off in the first cell region before the second cell region.

22. The semiconductor device according to any one of claims 1 to 21, wherein the connection circuit is formed in a region of the semiconductor element where no cells are arranged.

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