Semiconductor device

Abstract

Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided in contact with the emitter region; a collector region of a second conductivity type provided between the drift region and the lower surface of the semiconductor substrate; and a floating region of a first conductivity type provided in contact with the upper surface of the collector region and having a doping concentration higher than the collector region. The collector region has a first region not covered with the floating region and a second region covered with the floating region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, semiconductor devices including IGBTs and the like are known (see, for example, Patent Documents 1 and 2). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-023118 [Patent Document 2] Japanese Patent Application Laid-Open No. 2018-049866 Problems to be Solved

[0003] In a semiconductor device, it is preferable to suppress switching loss. General Disclosure

[0004] In order to solve the above problems, in a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type provided therein. The semiconductor device may include an emitter region of the first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a higher doping concentration than the drift region. Any of the above semiconductor devices may include a base region of a second conductivity type provided in contact with the emitter region. Any of the above semiconductor devices may include a collector region of the second conductivity type provided between the drift region and the lower surface of the semiconductor substrate. Any of the above semiconductor devices may include a floating region of the first conductivity type provided in contact with the upper surface of the collector region and having a higher doping concentration than the collector region. In any of the above semiconductor devices, the collector region may have a first region not covered by the floating region and a second region covered by the floating region.

[0005] In any of the above semiconductor devices, the doping concentration of the floating region may be 10 times or more the doping concentration of the collector region.

[0006] In any of the above semiconductor devices, the thickness of the floating region in the depth direction may be 0.5 times or more the thickness of the collector region in the depth direction.

[0007] In any of the above semiconductor devices, the product of the doping concentration and the thickness in the depth direction of the floating region may be 10 times or more the product of the doping concentration and the thickness in the depth direction of the collector region.

[0008] In any of the above semiconductor devices, let the area of the first region occupying the unit area of the collector region in a top view be S 1 , the area of the second region be S 2 , the injection efficiency of the first region be η 1 , and the injection efficiency of the second region be η 2 . When the average injection efficiency η C given by the following formula may be 0.1 or more and 0.4 or less. η C =(S 1 ×η 1 +S 2 ×η 2 ) / (S 1 +S 2 )

[0009] Any of the above semiconductor devices may include a buffer region formed between the collector region and the drift region and having a higher doping concentration than the drift region. In any of the above semiconductor devices, the floating region may be disposed between the buffer region and the collector region. In any of the above semiconductor devices, the doping concentration of the floating region may be higher than the doping concentration of the buffer region.

[0010] Any of the above semiconductor devices may include a transistor section. In any of the above semiconductor devices of the transistor section before In a top view wherein the collector region , let the area of the first region occupying 1 be S 2 , and the area of the second region be S Cis the doping concentration N of the collector region in the first region A may be given by the following formula. D C =S 1 ×N A / (S 1 +S 2 ) In any of the semiconductor devices described above, the doping concentration N of the collector region in the first region A may be higher than the average doping concentration D C . In any of the semiconductor devices described above, the ratio α of the area S2 of the second region to the area S1 of the first region may be given by the following formula. α=S 2 / S 1 In any of the semiconductor devices described above, the ratio β may be given by the following formula including the doping concentration N D of the floating region. β=(N A / D C -1)×N D / (N D ―N A ) In any of the semiconductor devices described above, The doping concentration N of the collector region in the first region A is the doping concentration N of the floating region D 10 -5 times or more and 0.6 times or less .

[0011] In any of the semiconductor devices described above, a plurality of gate trench portions provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region may be arranged along the arrangement direction. In any of the semiconductor devices described above, the first region and the second region may be alternately arranged along the arrangement direction.

[0012] Any of the above semiconductor devices may include an active portion including the emitter region and the base region. Any of the above semiconductor devices may include a well region of a second conductivity type that surrounds the active portion in a top view and is provided in contact with the top surface of the semiconductor substrate. Any of the above semiconductor devices may include an edge termination structure portion disposed between the well region and an edge of the semiconductor substrate. In any of the above semiconductor devices, both the first region and the second region may be provided in the active portion. In any of the above semiconductor devices, the second region may be provided in the edge termination structure portion, and the first region may not be provided.

[0013] In any of the above semiconductor devices, the second region may be provided at a position overlapping the well region, and the first region may not be provided.

[0014] In any of the above semiconductor devices, the second region of the edge termination structure portion may extend to a position overlapping the emitter region of the active portion.

[0015] Any of the above semiconductor devices may include a gate trench portion provided from the top surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region. In any of the above semiconductor devices, the first region may be provided at a position overlapping the gate trench portion.

[0016] Any of the above semiconductor devices may include a contact region provided in contact with the top surface of the semiconductor substrate and having a doping concentration higher than that of the base region. In any of the above semiconductor devices, the contact area ratio of the first region may be higher than the contact area ratio of the second region. In any of the above semiconductor devices, the contact area ratio may be a ratio of the area of the contact region exposed on the top surface of the semiconductor substrate to a unit area.

[0017] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups may also be inventions.

Brief Description of the Drawings

[0018]

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Embodiments for Carrying Out the Invention

[0019] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0020] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0021] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without specifying positive or negative, it means the directions parallel to the +Z-axis and -Z-axis.

[0022] In this specification, orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Also, in this specification, the directions parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction.

[0023] The region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate may sometimes be referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate may sometimes be referred to as the lower surface side.

[0024] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0025] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to obtain a semiconductor showing an N-type conductivity type or a semiconductor showing a P-type conductivity type.

[0026] In this specification, doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of charges. As an example, if the donor concentration is N D , and the acceptor concentration is N A , then the net doping concentration at any position is N D - N A . In this specification, the net doping concentration may sometimes be simply referred to as the doping concentration.

[0027] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, VOH defects formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor function as donors that supply electrons. In this specification, VOH defects may sometimes be referred to as hydrogen donors.

[0028] In this specification, in the semiconductor substrate, N-type bulk donors are distributed throughout. The bulk donors are donors by dopants that were contained substantially uniformly in the ingot when the ingot that is the source of the semiconductor substrate was manufactured. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donors in this example are phosphorus. The bulk donors are also contained in P-type regions. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 . A higher oxygen concentration tends to be more likely to generate hydrogen donors. The bulk donor concentration may use the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Further, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or less. Note that each concentration in the present invention may be a value at room temperature. As an example, the value at room temperature may use the value at 300 K (Kelvin) (about 26.9 °C).

[0029] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. Although the unit of length may be expressed in cm, various calculations may be performed after converting to meters (m).

[0030] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the electrically activated state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by the voltage-capacitance measurement method (CV method). Also, the carrier concentration measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration. The carrier concentration measured by the CV method or SR method may be taken as the value in the thermal equilibrium state. Also, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in the region may be taken as the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be taken as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0031] When the concentration distribution of donors, acceptors, or net doping has a peak, the peak value may be taken as the concentration of donors, acceptors, or net doping in the region. In cases where the concentration of donors, acceptors, or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors, or net doping in the region may be taken as the concentration of donors, acceptors, or net doping. In this specification, for the concentration per unit volume, the notation atoms / cm 3 , or, / cm 3It is used. This unit is used for the donor or acceptor concentration in the semiconductor substrate, or the chemical concentration. The "atoms" notation may be omitted.

[0032] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility is caused by the scattering of carriers due to the disorder of the crystal structure (disorder) such as lattice defects.

[0033] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic that serves as a donor, or the acceptor concentration of boron (boron) that serves as an acceptor is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen that serves as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0034] FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 1, the positions where each member is projected onto the upper surface of the semiconductor substrate 10 are shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.

[0035] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has side edges 162 in a top view. When simply referred to as a top view in this specification, it means looking from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of side edges 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to any of the side edges 162. Also, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0036] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1. The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. Also, a region sandwiched by the active portion 160 in a top view may be included in the active portion 160.

[0037] A transistor portion 70 including transistor elements such as IGBTs (Insulated Gate Bipolar Transistors) is provided in the active portion 160. A diode portion 80 including diode elements such as a freewheeling diode (FWD) may be further provided in the active portion 160. In the example of FIG. 1, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0038] In FIG. 1, a symbol "I" is attached to the region where the transistor portion 70 is arranged, and a symbol "F" is attached to the region where the diode portion 80 is arranged. In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extending direction (the Y-axis direction in FIG. 1). The transistor portion 70 and the diode portion 80 may each have a longitudinal dimension in the extending direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.

[0039] The diode section 80 has an N+-type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is a region that overlaps with the cathode region in a top view. On the lower surface of the semiconductor substrate 10, a P+-type collector region may be provided in a region other than the cathode region. In this specification, the extended region 81 obtained by extending the diode section 80 in the Y-axis direction up to the gate wiring described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extended region 81.

[0040] The transistor section 70 has a P+-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor section 70, a gate structure including an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10.

[0041] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged in the vicinity of the end side 162. The vicinity of the end side 162 refers to the region between the end side 162 in a top view and the emitter electrode. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

[0042] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0043] The gate wiring in this example has an outer peripheral gate wiring 130 and an active side gate wiring 131. The outer peripheral gate wiring 130 is arranged between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 of this example surrounds the active portion 160 in a top view. The region surrounded by the outer peripheral gate wiring 130 in a top view may be regarded as the active portion 160. Also, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be regarded as the active portion 160.

[0044] The outer peripheral gate wiring 130 is connected to the gate pad 164. The outer peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0045] The active side gate wiring 131 is provided in the active portion 160. By providing the active side gate wiring 131 in the active portion 160, for each region of the semiconductor substrate 10, the variation in the wiring length from the gate pad 164 can be reduced.

[0046] The outer peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The outer peripheral gate wiring 130 and the active side gate wiring 131 may be wirings formed of a semiconductor such as impurity-doped polysilicon.

[0047] The active-side gate wiring 131 may be connected to the outer peripheral gate wiring 130. The active-side gate wiring 131 in this example is provided to extend in the X-axis direction so as to cross the active portion 160 at substantially the center in the Y-axis direction from one outer peripheral gate wiring 130 sandwiching the active portion 160 to the other outer peripheral gate wiring 130. When the active portion 160 is divided by the active-side gate wiring 131, in each divided region, the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction.

[0048] The semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) that simulates the operation of the transistor portion provided in the active portion 160.

[0049] The semiconductor device 100 in this example includes an edge termination structure portion 90 between the active portion 160 and the end side 162 in a top view. The edge termination structure portion 90 in this example is arranged between the outer peripheral gate wiring 130 and the end side 162. The edge termination structure portion 90 relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and a RESURF provided annularly surrounding the active portion 160.

[0050] FIG. 2 is an enlarged view of region D in FIG. 1. Region D is a region including the transistor portion 70, the diode portion 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Further, the semiconductor device 100 in this example includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0051] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG. 2. Contact holes 54 are provided through the interlayer insulating film of this example. In FIG. 2, each contact hole 54 is hatched with oblique lines.

[0052] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not have to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0053] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0054] The emitter electrode 52 is formed of a material containing metal. In FIG. 2, the range where the emitter electrode 52 is provided is shown. For example, at least a part of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy like AlSi, AlSiCu, etc. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, etc. under the region formed of aluminum or the like. Further, in the contact hole, a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like may be provided.

[0055] The well region 11 is provided overlapping the active side gate wiring 131. The well region 11 is also provided extending with a predetermined width in a range where it does not overlap the active side gate wiring 131. The well region 11 in this example is provided away from the active side gate wiring 131 side from the Y-axis direction end of the contact hole 54. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. The base region 14 in this example is P-type, and the well region 11 is P+-type.

[0056] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the array direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the array direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the array direction. The diode section 80 of this example is not provided with a gate trench section 40.

[0057] The gate trench section 40 of this example may have two straight portions 39 (portions of the trench that are linear along the extending direction) extending along the extending direction perpendicular to the array direction, and a tip portion 41 connecting the two straight portions 39. The extending direction in FIG. 2 is the Y-axis direction.

[0058] At least a part of the tip portion 41 is preferably provided in a curved shape in a top view. By connecting the ends of the two linear portions 39 in the Y-axis direction with the tip portion 41, the electric field concentration at the ends of the linear portions 39 can be alleviated.

[0059] In the transistor portion 70, the dummy trench portion 30 is provided between the respective linear portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the respective linear portions 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a linear portion 29 and a tip portion 31 similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 2 includes both a linear dummy trench portion 30 without a tip portion 31 and a dummy trench portion 30 having a tip portion 31.

[0060] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a top view. That is, at the ends of each trench portion in the Y-axis direction, the bottom in the depth direction of each trench portion is covered by the well region 11. Thereby, the electric field concentration at the bottom of each trench portion can be alleviated.

[0061] A mesa portion is provided between the respective trench portions in the array direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided to extend in the extending direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10. In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. When simply referred to as a mesa portion in this specification, it refers to each of the mesa portion 60 and the mesa portion 61.

[0062] A base region 14 is provided in each mesa portion. Among the portions of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is defined as the base region 14-e. In FIG. 2, the base region 14-e disposed at one end in the extending direction of each mesa portion is shown, but the base region 14-e is also disposed at the other end of each mesa portion. In each mesa portion, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided in a region sandwiched by the base regions 14-e in a top view. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0063] The mesa portion 60 of the transistor portion 70 has an emitter region 12 in contact with (i.e., exposed on) the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 to may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0064] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the extending direction (Y-axis direction) of the trench portion.

[0065] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched by the emitter regions 12.

[0066] The mesa portion 61 of the diode section 80 is not provided with an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, contact regions 15 may be provided in contact with the respective base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed over the entire region sandwiched between the contact regions 15.

[0067] A contact hole 54 is provided above each mesa portion. The contact hole 54 is disposed in the region sandwiched between the base regions 14-e. The contact hole 54 of this example is provided above each of the regions of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be disposed at the center in the arrangement direction (X-axis direction) of the mesa portions 60.

[0068] In the diode section 80, an N+-type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. On the lower surface of the semiconductor substrate 10, a P+-type collector region 22 may be provided in the region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0069] The cathode region 82 is arranged away from the well region 11 in the Y-axis direction. Thereby, a distance between the P-type region (well region 11) that has a relatively high doping concentration and is formed to a deep position, and the cathode region 82 can be ensured, and the breakdown voltage can be improved. An end portion of the cathode region 82 in the Y-axis direction in this example is arranged away from the well region 11 more than an end portion of the contact hole 54 in the Y-axis direction. In other examples, the end portion of the cathode region 82 in the Y-axis direction may be arranged between the well region 11 and the contact hole 54.

[0070] FIG. 3 is a diagram showing an example of an e-e cross section in FIG. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 in this example has, in this cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0071] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as a silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The contact hole 54 described in FIG. 2 is provided in the interlayer insulating film 38.

[0072] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0073] The semiconductor substrate 10 has an N-type or N−-type drift region 18. The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.

[0074] In the mesa portion 60 of the transistor portion 70, an N+-type emitter region 12 and a P-type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+-type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18. The accumulation region 16 is an N+-type region having a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. The accumulation region 16 may also be provided in each mesa portion 61 of the diode portion 80, or may not be provided.

[0075] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0076] The base region 14 is provided below the emitter region 12. The base region 14 in this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0077] In the mesa portion 61 of the diode portion 80, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The base region 14 of the diode portion 80 may be referred to as an anode region.

[0078] In each of the transistor section 70 and the diode section 80, an N+-type buffer region 20 may be provided under the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Also, the doping concentration of the drift region 18 may be the average value of the doping concentrations in a region where the doping concentration distribution is substantially flat.

[0079] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be provided at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+-type collector region 22 and the N+-type cathode region 82.

[0080] In the transistor section 70, a P+-type collector region 22 is provided under the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0081] In the diode section 80, an N+-type cathode region 82 is provided under the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements serving as donors and acceptors in each region are not limited to the above-described examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0082] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14 to below the base region 14. In a region where at least any one of the emitter region 12, the contact region 15, and the accumulation region is provided, each trench portion also penetrates these doping regions. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed in the order of forming the doping region and then the trench portion. Those in which the doping region is formed between the trench portions after the trench portions are formed are also included in those in which the trench portion penetrates the doping region.

[0083] As described above, the transistor portion 70 is provided with a gate trench portion 40 and a dummy trench portion 30. The diode portion 80 is provided with a dummy trench portion 30 and is not provided with a gate trench portion 40. In this example, the boundary in the X-axis direction between the diode portion 80 and the transistor portion 70 is the boundary between the cathode region 82 and the collector region 22.

[0084] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0085] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.

[0086] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0087] The gate trench portion 40 and the dummy trench portion 30 in this example are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved surfaces convex downward (curved in the cross section). In this specification, the depth position of the lower end of the gate trench portion 40 is defined as Zt.

[0088] In the semiconductor device 100, it is preferable that the switching loss is low. In particular, when the semiconductor device 100 is used for a product with a high-speed operation having an operating frequency of 20 kHz or higher, the switching loss of the semiconductor device 100 may become a dominant loss in the product. Therefore, for example, if the turn-off loss Eoff of the semiconductor device 100 is low, the product loss can be reduced.

[0089] If the injection efficiency of carriers in the collector region 22 is lowered, the turn-off loss Eoff can be reduced. On the other hand, when the injection efficiency of the collector region 22 is lowered, the ratio of variation with respect to the designed value of the injection efficiency of the collector region 22 increases, and the characteristic variation between individual semiconductor devices 100 or between lots becomes large.

[0090] For example, the injection efficiency can be lowered by reducing the doping concentration of the collector region 22, but the ratio of variation with respect to the designed value of the doping concentration of the collector region 22 increases. In such a case, the variation in the sheet resistance of the collector region 22 becomes large. When the variation in the sheet resistance of the collector region 22 becomes large, variations in the on-voltage and latch-up tolerance of the semiconductor device 100 increase. Also, in a circuit in which a plurality of semiconductor devices 100 are used in parallel, if the on-voltages of the semiconductor devices 100 vary, current may concentrate on a specific device and the tolerance of the circuit may decrease.

[0091] The semiconductor device 100 of this example includes an N+-type floating region 71 provided in contact with the upper surface of the collector region 22 and having a higher doping concentration than the collector region 22. A PN junction is formed between the floating region 71 and the collector region 22. A buffer region 20 may be provided on the floating region 71. The floating region 71 may or may not be provided above the cathode region 82.

[0092] The floating region 71 is partially provided on the upper surface of the collector region 22. The collector region 22 has a first region 26 not covered by the floating region 71 and a second region 28 covered by the floating region 71. The first region 26 and the second region 28 in this example are arranged alternately side by side in the XY plane. In one transistor section 70, two or more of the first region 26 and the second region 28 may be included. The first region 26 may be provided at the end of the transistor section 70 in the X-axis direction, and the second region 28 may also be provided. In this example, the upper surfaces of the first region 26 and the second region 28 are in contact with the buffer region 20, but may also be in contact with the drift region 18.

[0093] By covering a part of the collector region 22 with the floating region 71, the injection efficiency of carriers (holes in this example) into the drift region 18 can be reduced without lowering the doping concentration of the collector region 22. Therefore, the turn-off loss Eoff can be reduced while suppressing variations in the doping concentration of the collector region 22. The injection efficiency is as follows. For example, let the hole current density be J p , and the electron current density be J n . The injection efficiency of the collector region 22 is the ratio of the current density of minority carriers to the total current density. In this example, since the conductivity type of the drift region 18 is N-type and the conductivity type of the collector region 22 is P-type, the minority carriers in the drift region 18 are holes. In this case, the injection efficiency in the collector region 22 can be defined by the following formula. J p / (J p +J n )

[0094] When the injection efficiency η 1 of the first region 26 is taken as 1, the injection efficiency η 2 of the second region 28 can be defined by Equation (1). η 1 =1 η 2 =(N A / (N A +N D ))×(W P / (W N+W P )) ··· Formula (1) However, N A is the doping concentration of the collector region 22, N D is the doping concentration of the floating region 71, W P is the thickness of the collector region 22 in the Z-axis direction, W N is the thickness of the floating region 71 in the Z-axis direction. The doping concentration of each region may use the peak value in the region, or the average value. When the doping concentration in each region has a peak, the thickness of each region may use the thickness of the region of the full width at half maximum of the peak.

[0095] By providing the second region 28 with a relatively low injection efficiency, the overall injection efficiency of the collector region 22 can be reduced. Thereby, the turn-off loss Eoff of the semiconductor device 100 can be reduced. Also, since the injection efficiency of the first region 26 is relatively large, the variation in the injection efficiency of the first region 26 can be made small. In the injection efficiency of the collector region 22, since the injection efficiency of the first region 26 is dominant, by making the variation in the injection efficiency of the first region 26 small, the variation in the overall injection efficiency of the collector region 22 can be suppressed.

[0096] The doping concentration N D (net doping concentration) of the floating region 71 may be 1.5 times or more, 2 times or more, 5 times or more, 10 times or more, or 20 times or more of the doping concentration N A (net doping concentration) of the collector region 22. The higher the doping concentration N D of the floating region 71, the smaller the injection efficiency of the second region 28 can be made. As an example, the doping concentration N D may be 1×10 17 / cm 3 or more, and may be 1×10 18 / cm 3 or more. The doping concentration N D may be 1×10 20 / cm 3 or less, and may be 1×10 19 / cm3 may be as follows. The doping concentration N A is 1×10 16 / cm 3 or more, and may be 1×10 17 / cm 3 or more. The doping concentration N A is 1×10 19 / cm 3 or less, and may be 1×10 18 / cm 3 or less.

[0097] The thickness W in the depth direction (Z-axis direction) of the floating region 71 N may be 0.1 times or more, 0.5 times or more, greater than 1 time, or 2 times or more of the thickness W in the depth direction of the collector region 22. The thicker the floating region 71, the smaller the implantation efficiency of the second region 28 can be. As an example, the thickness W P may be 0.1 μm or more, and may be 0.3 μm or more. The thickness W N may be 1.0 μm or less, and may be 0.5 μm or less. The thickness W N may be 0.1 μm or more, and may be 0.2 μm or more. The thickness W P may be 1.0 μm or less, and may be 0.5 μm or less. P The product N

[0098] of the doping concentration N of the floating region 71 D and the thickness W N N D ×W N may be 1.5 times or more, 2 times or more, 5 times or more, 10 times or more, or 20 times or more of the product N A of the doping concentration N of the collector region 22 P and the thickness W A N P ×W D ×W N

[0099] The larger the product N D ×W N is, the smaller the implantation efficiency of the second region 28 can be.FIG. 4A is a diagram showing an arrangement example of the first region 26 and the second region 28 in a top view. In FIG. 4A, a part of the transistor portion 70 is shown. Let the area of the first region 26 in the unit area of the collector region 22 be S1, and the area of the second region 28 be S2. The unit area in FIG. 4A is a part of the collector region 22, but the unit area may be the entire collector region 22. In this case, the total area of the first region 26 in the semiconductor device 100 may be S1, and the total area of the second region 28 may be S2.

[0100] Let the injection efficiency of the first region 26 be η 1 , and the injection efficiency of the second region 28 be η 2 (η 1 >η 2 ), and the average injection efficiency η C is defined by Equation (2). η C =(S 1 ×η 1 +S 2 ×η 2 ) / (S 1 +S 2 ) ··· Equation (2) The average injection efficiency η C is 0.1 or more and 0.4 or less. Thereby, the average injection efficiency η C of the semiconductor device 100 can be made sufficiently low to reduce the turn-off loss. The average injection efficiency η C may be 0.15 or more, or may be 0.2 or more. The average injection efficiency η C may be 0.35 or less, or may be 0.3 or less. The injection efficiency is the current density of the minority carriers with respect to the total current density as described above ratio , and in this example with respect to the total current density it is the current density of holes ratio . During conduction, excess minority carriers and majority carriers are accumulated in the drift region 18, and conductivity modulation occurs. When the ratio of the current density of the minority carriers is in the above range, the concentration of the minority carriers on the collector region 22 side accumulated in the drift region 18 becomes low, and the concentration of the minority carriers on the emitter region 12 side can be relatively increased. Thereby, the turn-off loss can be reduced. The average injection efficiency η CWhen it is 0.5 or more, the turn-off loss increases relatively. Therefore, the average injection efficiency η C may be at least 0.5 less than or more.

[0101] The injection efficiency η 2 may be 0.3 or less. Thereby, the average injection efficiency η C is reduced, and the switching loss of the semiconductor device 100 can be reduced. The injection efficiency η 2 may be 0.5 times or less of the injection efficiency η 1 or less.

[0102] The area S1 of the first region 26 may be the same as or different from the area S2 of the second region 28. The area S1 may be smaller than the area S2. Thereby, the average injection efficiency η C and described later the average doping concentration D C are reduced, and it becomes easier to reduce the turn-off loss. The area S1 may be 80% or less of the area S2, or may be 50% or less. Here, the average injection efficiency η C may be obtained from Equation (2) per unit area as shown in FIG. 4A. When the first region 26 and the second region 28 are distributed in a stripe shape, the unit length L1 of the first region 26 in the distribution direction (the X-axis direction in FIG. 4A) is replaced with S1 in Equation (2), and the unit length L2 of the second region 28 is replaced with S2 in Equation (2) for calculation.

[0103] As shown in FIG. 4A, each of the first region 26 and the second region 28 may have a stripe shape with a longitudinal direction in the Y-axis direction. The lengths of the first region 26 and the second region 28 in the Y-axis direction may be the same or different. In this example, the first region 26 and the second region 28 are alternately arranged in the X-axis direction. The width W1 of the first region 26 in the X-axis direction may be the same as or different from the width W2 of the second region 28 in the X-axis direction. The width W1 may be smaller than the width W2. Thereby, the average injection efficiency η C is reduced, and it becomes easier to reduce the turn-off loss. The width W1 may be 80% or less of the width W2, or may be 50% or less.

[0104] FIG. 4B is a diagram showing characteristics for determining the area S2 of the second region 28 with respect to the area S1 of the first region 26. The horizontal axis represents the doping concentration N of the collector region 22 with respect to the doping concentration N of the floating region 71 D of the ratio, and the vertical axis is the ratio β described later. In FIG. 4B, the ratio (N of the doping concentration N of the collector region 22 with respect to the average doping concentration D described later A / D C of ) shows the following characteristics when it is 30, 20, 10, 8, 5, 3, or 2 A A / D C ). 7 FIG. 4B shows the characteristics as follows.

[0105] The effective doping concentration of the collector region 22 in the second region 28 is defined by Equation (3A) as D 2 and the average doping concentration D C . D C =(S 1 ×N A +S 2 ×D 2 ) / (S 1 +S 2 ) ··· Equation (3A) Here, the effective doping concentration of the collector region 22 in the second region 28 is not the actual doping concentration of the collector region 22, but is assumed to be a doping concentration that does not substantially function as the collector region 22 due to the floating region 71. That is, since the effective doping concentration D of the collector region 22 in the second region 28 is substantially 0, D can be set to 0 in Equation (3A). That is, 2 2 = 0, so D C = S 1 ×N A / (S 1 +S 2 ) ··· Equation (3B) is obtained.

[0106] The doping concentration D of the collector region 22 in the first region 26 is the average doping concentration D 1 ​​​C It may be higher. Let α be the ratio of the area S2 of the second region 28 to the area S1 of the first region 26 in the collector region 22. The ratio α is given by the following formula. α = S 2 / S 1 ··· Equation (4) Here, the ratio β is defined by the following formula. β = (N A / D C - 1) × N D / (N D ― N A ) ··· Equation (5) The ratio β is an index for estimating how many times or more the area S2 of the second region 28 is larger than the area S1 of the first region 26 when the doping concentration of the collector region 22 in the first region 26 is N A and the doping concentration of the floating region 71 in the second region 28 is N D so that the desired average doping concentration D C can be obtained. The ratio α is the ratio β smaller than .

[0107] The first term on the right side of Equation (5) indicates how many times at least the area S2 of the second region 28 should be the area S1 of the first region 26. The second term on the right side is a correction term according to the doping concentration N A of the collector region 22 in the first region 26 and the doping concentration N D of the floating region 71 in the second region 28. When the doping concentration N D of the floating region 71 is sufficiently larger than the doping concentration N A of the collector region 22, the second term becomes substantially 1. The closer the doping concentration N D of the floating region 71 is to the doping concentration N A of the collector region 22, the larger the area S2 of the second region 28 must be in order to obtain the target average doping concentration D C .

[0108] As shown in FIG. 4B, when the doping concentration N D of the floating region 71 is the doping concentration N of the collector region 22A If it is sufficiently larger than, the doping concentration D of the average doping concentration C The doping concentration N of the collector region 22 with respect to A The ratio β stabilizes regardless of substantially depending on the ratio of. By stabilizing the ratio β, the average doping concentration D C The fluctuations and variations of are suppressed, and the on-voltage stabilizes. The doping concentration N of the collector region 22 A May be 0.1 times or less of the doping concentration N of the floating region 71 D May be 0.6 times or less, may be 0.4 times or less, may be 0.2 times or less, may be 0.01 times or less. The doping concentration N of the collector region 22 A May be 0.1 times or less of the doping concentration N of the floating region 71 D Of 10 -5 May be more than times, may be more than 10 -4 May be more than times, may be 0.001 times or more, may be 0.01 times or more.

[0109] The doping concentration N of the collector region 22 A May be higher than the average doping concentration D C May be 1.5 times or more of the average doping concentration D, may be 2 times or more, may be 3 times or more, may be 5 times or more. The doping concentration N of the collector region 22 C May be 1.5 times or more of the average doping concentration D, may be 2 times or more, may be 3 times or more, may be 5 times or more. The doping concentration N of the collector region 22 A May be 30 times or less of the average doping concentration D C May be 20 times or less, may be 10 times or less.

[0110] Here, the average doping concentration D C As shown in FIG. 4A, it may be obtained from Equation (3B) per unit area. When the first region 26 and the second region 28 are distributed in a stripe shape, the unit length L1 of the first region 26 in the distribution direction (the X-axis direction in FIG. 4A) is replaced with S1 in Equation (3B), and the unit length L2 of the second region 28 is replaced with S2 in Equation (3B) for calculation.

[0111] FIG. 5 is a diagram showing an example of the arrangement of the first region 26 and the second region 28 in a top view. In this example, the first region 26 is discretely arranged also in the Y-axis direction, which is different from the example of FIG. 4A. Other structures are the same as those in the example of FIG. 4A. The first region 26 and the second region 28 in this example are configured such that unit cells (or unit lattices) indicated by dotted lines are regularly tiled on the collector region 22. The average doping concentration D C in this example may be obtained from Equation (3A) or (3B). Let s1 be the area of the first region 26 in the unit cell and s2 be the area of the second region 28 in the unit cell. The area S1 of the first region 26 in Equation (3A) or (3B) may be replaced with s1, and the area S2 of the second region 28 may be replaced with s2 for calculation.

[0112] FIG. 6 is a diagram showing an example of the a-a cross section of FIG. 1. The a-a cross section is an XZ plane passing through the transistor portion 70. FIG. 6 shows an example of the arrangement of the first region 26 and the second region 28 in the X-axis direction. Structures other than the first region 26 and the second region 28 are the same as those in the examples described in FIGS. 1 to 5.

[0113] In this example, at least one first region 26 is provided at a position overlapping with the gate trench portion 40. All the first regions 26 may be provided at positions overlapping with the gate trench portion 40. The overlap between the first region 26 and the gate trench portion 40 means that at least one gate trench portion 40 is arranged within the range in the X-axis direction where the first region 26 is provided. The first region 26 may also overlap with the dummy trench portion 30. By arranging the first region 26 below the gate trench portion 40, the carrier density below the gate structure can be increased, and the on-voltage can be reduced. The number of gate trench portions 40 arranged above one first region 26 may be more than the number of gate trench portions 40 arranged above one second region 28. Thereby, the overall on-voltage of the transistor portion 70 can be reduced. The number of gate trench portions 40 arranged above one first region 26 may be the same as or less than the number of gate trench portions 40 arranged above one second region 28.

[0114] As shown in FIG. 6, a second region 28 may be provided below at least one gate trench portion 40. A second region 28 may be provided below each dummy trench portion 30. A second region 28 may be provided below all the dummy trench portions 30, and a first region 26 may be provided below at least one dummy trench portion 30.

[0115] FIG. 7 is a diagram showing another example of the a-a cross section. In this example, the arrangement of the contact regions 15 on the upper surface 21 of the semiconductor substrate 10 is different from that of the example in FIG. 6. Other structures are the same as those of the example in FIG. 6. The contact region 15 is a P+-type region having a higher doping concentration than the base region 14, which is provided in contact with the upper surface 21 of the semiconductor substrate 10.

[0116] Either the emitter region 12 or the contact region 15 is exposed on the upper surface of the mesa portion 60 in this example. In this example, more contact regions 15 are arranged in the first region 26 than in the second region 28. Thereby, holes injected from the first region 26 can be easily extracted through the contact region 15, and a decrease in the latch-up tolerance can be suppressed.

[0117] FIG. 8 is a diagram showing an arrangement example of the emitter region 12 and the contact region 15 in a top view. In FIG. 8, the contact region 15 is hatched with oblique lines. On the upper surface of each mesa portion 60 in this example, the emitter region 12 and the contact region 15 are alternately arranged in the Y-axis direction. The area S of the contact region 15 exposed on the upper surface 21 of the semiconductor substrate 10 C of the unit area S R to the ratio S C / S R is defined as the contact area ratio. The unit area S Rmay be the area of the entire upper surface of one mesa portion 60. The contact area ratio R1 of the first region 26 may be higher than the contact area ratio R2 of the second region 28. The contact area ratio of each region may be the contact area ratio of the region overlapping each region in a top view. Thereby, the path for extracting holes injected from the first region 26 to the emitter electrode 52 can be made to have a low resistance, and latch-up can be suppressed. The contact area ratio R1 may be 1.2 times or more, 1.5 times or more, or even 2 times or more the contact area ratio R2.

[0118] In this example, the length in the Y-axis direction of one contact region 15 in the first region 26 is larger than the length in the Y-axis direction of one contact region 15 in the second region 28. The length in the Y-axis direction of the emitter region 12 may be the same in the first region 26 and the second region 28, or may be different. In other examples, the length in the Y-axis direction of one emitter region 12 in the first region 26 may be smaller than the length in the Y-axis direction of one emitter region 12 in the second region 28. In this case, the length in the Y-axis direction of the contact region 15 may be the same in the first region 26 and the second region 28, or may be different.

[0119] In this example, the mesa portion 60 overlapping the first region 26 is defined as mesa portion 60-a, and the mesa portion 60 not overlapping the first region 26 is defined as mesa portion 60-b. The mesa portion 60 overlapping both the first region 26 and the second region 28 may also be defined as mesa portion 60-a. The contact area ratio in the mesa portion 60-a may be used as the contact area ratio of the first region 26. The contact area ratio in the mesa portion 60-b may be used as the contact area ratio of the second region 28.

[0120] FIG. 9 is a diagram showing another example of the a-a cross section. In this example, the arrangement of the contact regions 15 on the upper surface 21 of the semiconductor substrate 10 is different from the example of FIG. 7. Other structures are the same as the example of FIG. 7. The contact regions 15 in this example are arranged side by side with the emitter region 12 in the X-axis direction.

[0121] FIG. 10 is a diagram showing an arrangement example of the emitter region 12 and the contact region 15 in a top view. In FIG. 10, the contact region 15 is hatched with oblique lines. On the upper surface of each mesa portion 60 in this example, the contact region 15 adjacent to the emitter region 12 in the X-axis direction is arranged connected to the contact region 15 adjacent to the emitter region 12 in the Y-axis direction. Also in this example, the contact area ratio R1 of the first region 26 is higher than the contact area ratio R2 of the second region 28. Further, by arranging the contact region 15 adjacent to the emitter region 12, a path for extracting holes injected from the first region 26 to the emitter electrode 52 can be formed adjacent to the emitter region 12, so that the resistance of the path can be reduced and latch-up can be suppressed. The contact area ratio R1 may be 1.2 times or more, 1.5 times or more, or 2 times or more of the contact area ratio R2. The contact region 15 and the contact regions 15-1 and 15-2 with oblique hatching may have the same doping concentration distribution.

[0122] The semiconductor device 100 may have a contact region 15-2 in contact with the gate trench portion 40 and a contact region 15-1 in contact with the dummy trench portion 30. In this example, for each dummy trench portion 30, the contact regions 15-1 are arranged on both sides in the X-axis direction.

[0123] The area ratio of the contact region 15-2 provided in the first region 26 (the area of the contact region 15-2 with respect to the area of the first region 26) is higher than the area ratio of the contact region 15-2 provided in the second region 28. In this example, one contact region 15-2 is provided for at least one gate trench portion 40 in the first region 26, and no contact region 15-2 is provided in the second region 28.

[0124] FIG. 11 is a diagram showing an example of the b-b cross-section of FIG. 1. The b-b cross-section is an XZ plane that passes through the edge termination structure portion 90 and a part of the active portion 160 (transistor portion 70). The edge termination structure portion 90 may include one or more guard rings 92. The edge termination structure portion 90 may include one or more field plates 93. The guard ring 92 is a P+-type region provided in contact with the upper surface 21 of the semiconductor substrate 10. The guard ring 92 surrounds the active portion 160. The field plate 93 is a metal member disposed above the upper surface 21 of the semiconductor substrate 10. An interlayer insulating film 38 may be provided between the field plate 93 and the semiconductor substrate 10. The field plate 93 and the guard ring 92 may be electrically connected or may not be connected. In this example, the field plate 93 and the guard ring 92 are connected via a polysilicon wiring 94 provided on the upper surface of the semiconductor substrate 10.

[0125] Outside the guard ring 92 and the field plate 93, a channel stopper 95 and an electrode 96 may be provided. The channel stopper 95 prevents the depletion layer extending from the active portion 160 from reaching the edge 162 of the semiconductor substrate 10. The channel stopper 95 is a P-type or N-type region having a higher concentration than the drift region 18. The electrode 96 is connected to the channel stopper 95. The same potential as the collector electrode 24 may be applied to the electrode 96.

[0126] An outer peripheral gate wiring 130 is provided between the active portion 160 and the edge termination structure portion 90. A polysilicon gate runner 132 may be provided between the outer peripheral gate wiring 130 and the semiconductor substrate 10. A well region 11 is provided below the outer peripheral gate wiring 130 and the gate runner 132. The well region 11 may be connected to the emitter electrode 52. The well region 11 may be in contact with the base region 14.

[0127] Both the first region 26 and the second region 28 are provided in the active portion 160. The second region 28 is provided in the edge termination structure portion 90, and the first region 26 does not have to be provided. By providing the second region 28 throughout the edge termination structure portion 90, the injection efficiency of holes into the edge termination structure portion 90 can be reduced, and the dynamic breakdown voltage of the edge termination structure portion 90 can be improved. Thereby, the overvoltage withstand capacity (clamp withstand capacity) of the semiconductor device 100 can be improved.

[0128] The second region 28-1 of the edge termination structure portion 90 may extend below the well region 11. The second region 28-1 may overlap the entire well region 11. That is, the second region 28-1 is provided at a position overlapping the well region 11, and the first region 26 does not have to be provided. The second region 28-1 may extend to a position overlapping the emitter electrode 52. The second region 28-1 may extend to the active portion 160. In this example, semiconductor substrate 10 The end portion on the side opposite to the side edge 162 of is taken as the end portion of the active portion 160. By extending the second region 28-1, it becomes easier to improve the breakdown voltage in the edge termination structure portion 90.

[0129] FIG. 12 is a diagram showing an arrangement example of the second region 28-1 in the active portion 160. FIG. 12 enlarges the vicinity of the end portion of the second region 28-1 on the active portion 160 side. The second region 28-1 in this example is provided so as to extend to a position overlapping the emitter region 12-1 of the active portion 160. The emitter region 12-1 in this example is the emitter region 12 closest to the edge termination structure portion 90 in the X-axis direction. The end portion of the second region 28-1 in the X-axis direction may overlap the emitter region 12-1. The end portion of the second region 28-1 in the X-axis direction may be provided at a position overlapping the contact hole 54 of the mesa portion 60 where the emitter region 12-1 is provided. A boundary between the first region 26 and the second region 28-1 may be provided below the mesa portion 60. With the configurations as shown in FIGS. 11 and 12, while improving the breakdown voltage of the edge termination structure portion 90, variations in the characteristics of the transistor portion 70 can be suppressed, and turn-off loss can be reduced.

[0130] FIG. 13 is a diagram showing an example of the net doping concentration distribution along the c-c line in FIG. 3. The c-c line passes through a part of the floating region 71, the buffer region 20, and the drift region 18 in the second region 28. collector region 22 The doping concentration of the buffer region 20 is higher than the doping concentration D d of the drift region 18. The buffer region 20 in this example has one or more doping concentration peaks 27 arranged at different positions in the depth direction. The doping concentration N D of the floating region 71 may be higher than the doping concentration of the buffer region 20. The doping concentration N D of the floating region 71 may be higher than any of the doping concentration peaks 27 of the buffer region 20. The doping concentration N D of the floating region 71 may be 10 times or more, 50 times or more, or even 100 times or more the maximum value of the doping concentration in the buffer region 20.

[0131] Let the lower end position of the floating region 71 be Z 1 and the upper end position be Z 2 . The lower end position Z 1 may be the depth position of the PN junction between the collector region 22 and the buffer region 20. The upper end position Z 2 may be the position where the doping concentration first becomes a minimum value above the position where the doping concentration becomes the peak value N D . In another example, above the position where the doping concentration becomes the peak value N D , the position where the doping concentration first becomes α×N D may be set as the upper end position Z 2 . α is a real number from 0 to 1. α may be, for example, 0.5, 0.1, or even 0.01. Also, below the position where the doping concentration becomes the peak value N D , the position where the doping concentration first becomes α×N D may be set as the lower end position Z 1 .

[0132] FIG. 14 is a diagram showing the relationship between the set value of the dose amount of the P-type impurity to be implanted into the collector region 22 and the variation in the doping concentration of the collector region 22. The doping concentration of the collector region 22 is the value after implanting the P-type impurity and annealing. The variation in the doping concentration may be the standard deviation of the doping concentrations in a plurality of semiconductor devices 100. Although the variation in the doping concentration is shown in the example of FIG. 14, the on-voltage of the semiconductor device 100 also varies similarly.

[0133] Even when a certain dose amount is set, variations in the dose amount, variations in the annealing conditions, etc. cause variations in the doping concentration. When the set value of the dose amount becomes smaller, the proportion of the variation becomes larger. Therefore, as shown in FIG. 14, the smaller the set value of the dose amount, the greater the tendency for the variation in the doping concentration to be larger. In the example of FIG. 14, when the set value of the dose amount exceeds 1×10 12 / cm 2 , the variation in the doping concentration becomes almost constant.

[0134] The dose amount for the collector region 22 may be 1×10 12 / cm 2 or more. The value obtained by integrating the peak waveform of the doping concentration of the collector region 22 within the range of the full width at half maximum in the depth direction may be used as the dose amount of the collector region 22. The dose amount for the collector region 22 may be 1×10 13 / cm 2 or more, and may also be 1×10 14 / cm 2 or more.

[0135] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0136] In the claims, the description, and the drawings, the execution order of each process such as the operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "earlier" or "preceding" etc. in particular. It should be noted that, unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flow in the claims, the description, and the drawings, even if it is described for convenience using "first," "next," etc., it does not mean that it is essential to implement in this order.

Explanation of Reference Numerals

[0137] 10 ··· semiconductor substrate, 11 ··· well region, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· storage region, 18 ··· drift region, 20 ··· buffer region, 21 ··· upper surface, 22 ··· collector region, 23 ··· lower surface, 24 ··· collector electrode, 26 ··· first region, 27 ··· peak doping concentration, 28 ··· second region, 29 ··· straight portion, 30 ··· dummy trench portion, 31 ··· tip portion, 32 ··· dummy insulating film, 34 ··· dummy conductive portion, 38 ··· interlayer insulating film, 39 ··· straight portion, 40 ··· gate trench portion, 41 ··· tip portion, 42 ··· gate insulating film, 44 ··· gate conductive portion, 52 ··· emitter electrode, 54 ··· contact hole, 60, 61 ··· mesa portion, 70 ··· transistor portion, 71 ··· floating region, 80 ··· diode portion, 81 ··· extension region, 82 ··· cathode region, 90 ··· edge termination structure portion, 92 ··· guard ring, 93 ··· field plate, 94 ··· wiring, 95 ··· channel stopper, 96 ··· electrode, 100 ··· semiconductor device, 130 ··· outer peripheral gate wiring, 131 ··· active side gate wiring, 132 ··· gate runner, 160 ··· active portion, 162 ··· end side, 164 ··· gate pad

Claims

1. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type; An emitter region of the first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; A base region of the second conductivity type provided in contact with the emitter region; A collector region of the second conductivity type provided between the drift region and the lower surface of the semiconductor substrate; A floating region of the first conductivity type provided in contact with the upper surface of the collector region and having a doping concentration higher than that of the collector region and comprising; The collector region has a first region not covered by the floating region and a second region covered by the floating region; The value NA / ND obtained by dividing the doping concentration NA of the collector region by the doping concentration ND of the floating region is 0.1 or less; The thickness WP in the depth direction of the collector region is smaller than the thickness WN in the depth direction of the floating region semiconductor device.

2. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of the first conductivity type; A transistor portion provided on the semiconductor substrate; An emitter region of the first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; A base region of the second conductivity type provided in contact with the emitter region; A collector region of the second conductivity type provided between the drift region and the lower surface of the semiconductor substrate; A floating region of the first conductivity type provided in contact with the upper surface of the collector region and having a doping concentration higher than that of the collector region and comprising; The collector region has a first region not covered by the floating region and a second region covered by the floating region; Let the area of the first region in the collector region in a top view of the transistor portion be S 1 and the area of the second region be S 2 and The average doping concentration D of the collector region Ｃ is given by the following equation using the doping concentration N of the collector region in the first region Ａ as follows D Ｃ = S １ × N Ａ / (S １ + S ２ ) The doping concentration N of the collector region in the first region Ａ is higher than the average doping concentration D Ｃ and The ratio α of the area S2 of the second region to the area S1 of the first region is given by the following formula, α = S ２ / S １ The ratio β is given by the following formula including the doping concentration N of the floating region Ｄ and is given by the following formula β = (N Ａ / D Ｃ - 1) × N Ｄ / (N Ｄ ― N Ａ ) The doping concentration N of the collector region in the first region Ａ is 10 Ｄ times or more and 0.1 times or less of the doping concentration N －５ of the floating region semiconductor device.

3. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of the first conductivity type; A transistor portion provided on the semiconductor substrate; An emitter region of the first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; A base region of the second conductivity type provided in contact with the emitter region; A collector region of the second conductivity type provided between the drift region and the lower surface of the semiconductor substrate; A floating region of a first conductivity type that is provided in contact with the upper surface of the collector region and has a doping concentration higher than that of the collector region, and comprises the collector region has a first region not covered by the floating region and a second region covered by the floating region, In a top view of the transistor portion, let the area of the first region in the collector region be S 1 , and the area of the second region be S 2 . Let the injection efficiency of the first region be η 1 , and the injection efficiency of the second region be η 2 . When this is the case, the average injection efficiency η Ｃ given by the following formula is 0.1 or more and 0.4 or less η Ｃ = (S １ × η １ + S ２ × η ２ ) / (S １ + S ２ ) a semiconductor device. **Claim 4**: A semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, an emitter region of a first conductivity type that is provided in contact with the upper surface of the semiconductor substrate and has a doping concentration higher than that of the drift region, a base region of a second conductivity type that is provided in contact with the emitter region, a collector region of a second conductivity type that is provided between the drift region and the lower surface of the semiconductor substrate, a floating region of a first conductivity type that is provided in contact with the upper surface of the collector region and has a doping concentration higher than that of the collector region, and comprises the collector region has a first region not covered by the floating region and a second region covered by the floating region, an active portion including the emitter region and the base region, a well region of a second conductivity type that surrounds the active portion in a top view and is provided in contact with the upper surface of the semiconductor substrate, and an edge termination structure portion disposed between the well region and the edge of the semiconductor substrate comprises both the first region and the second region are provided in the active portion, the second region is provided in the edge termination structure portion, and the first region is not provided a semiconductor device. **Claim 5**: A semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, an emitter region of a first conductivity type that is provided in contact with the upper surface of the semiconductor substrate and has a doping concentration higher than that of the drift region, a base region of a second conductivity type that is provided in contact with the emitter region, a collector region of a second conductivity type that is provided between the drift region and the lower surface of the semiconductor substrate, a floating region of a first conductivity type that is provided in contact with the upper surface of the collector region and has a doping concentration higher than that of the collector region, and comprises the collector region has a first region not covered by the floating region and a second region covered by the floating region, trench portions that are provided from the upper surface of the semiconductor substrate to the drift region, are in contact with the emitter region and the base region, and are arranged in a plurality along the arrangement direction Inside the semiconductor substrate, there is a mesa portion which is a region sandwiched by the trench portions in the arrangement direction, a contact region which is provided in contact with the upper surface of the semiconductor substrate and has a higher doping concentration than the base region, and further includes, the contact area ratio of the first region is higher than the contact area ratio of the second region, the contact area ratio is the ratio of the area of the contact region exposed on the upper surface of one mesa portion to the area of one mesa portion, a semiconductor device.

6. The doping concentration of the floating region is 10 times or more the doping concentration of the collector region. The semiconductor device according to any one of claims 3 to 5.

7. The thickness of the floating region in the depth direction is 0.5 times or more the thickness of the collector region in the depth direction. The semiconductor device according to any one of claims 2 to 5.

8. The product of the doping concentration and the thickness in the depth direction of the floating region is 10 times or more the product of the doping concentration and the thickness in the depth direction of the collector region. The semiconductor device according to any one of claims 2 to 5.

9. further includes a buffer region formed between the collector region and the drift region and having a higher doping concentration than the drift region, the floating region is disposed between the buffer region and the collector region, the doping concentration of the floating region is higher than the doping concentration of the buffer region. The semiconductor device according to any one of claims 1 to 5.

10. A plurality of gate trench portions provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region are arranged along the arrangement direction, the first region and the second region are alternately arranged along the arrangement direction. The semiconductor device according to any one of claims 1 to 5.

11. The second region is provided at a position overlapping the well region, and the first region is not provided. The semiconductor device according to claim 4.

12. The second region of the edge termination structure portion extends to a position overlapping the emitter region of the active portion. The semiconductor device according to claim 4.

13. further includes a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region. The first region is provided at a position overlapping the gate trench portion. The semiconductor device according to any one of claims 1 to 5.

14. Comprising a plurality of the gate trench portions, The first region is arranged at a position overlapping the plurality of gate trench portions. The semiconductor device according to claim 13.

15. An emitter electrode provided above the upper surface of the semiconductor substrate, A dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, in contact with the emitter region and the base region, and electrically connected to the emitter electrode And further comprising, The second region is provided at a position overlapping the dummy trench portion. The semiconductor device according to claim 13.

16. The collector region has a plurality of the first regions, All of the first regions are arranged at positions overlapping the gate trench portion. The semiconductor device according to claim 13.

17. The injection efficiency η of the first region １ and the injection efficiency η of the second region ２ are the ratios of the current density of minority carriers to the total current density The semiconductor device according to claim 3.

18. The transistor portion is, At least one of the first region and the second region is repeatedly arranged along the repetition direction, and the width in the repetition direction is equal to the period of the repetition. The semiconductor device according to claim 2 or 3.

19. The ratio β is 1.5 times or less of the ratio α. The semiconductor device according to claim 2.

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