Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

Improve the reliability of the semiconductor light-emitting device. 【Solution means】The semiconductor light-emitting device 10 includes a laminated film in which a first TiN layer and a Rh layer are alternately laminated, and a second TiN layer provided on the laminated film, and is provided on the p-side contact electrode 30. The p-side current diffusion layer 34 having a p-side connection opening 34a through which the second TiN layer exposes the Rh layer, a pad opening provided in the p-side connection opening, and covering the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, and the p-side current diffusion layer 34 at a location different from the pad opening, a protective layer made of a dielectric material, a p-side pad electrode 42 that contacts the Rh layer of the p-side current diffusion layer 34 at the p-side connection opening and is provided on the protective layer outside the pad opening, and a p-side bonding layer 46 provided on the p-side pad electrode 42 and containing AuSn.

Description

Technical Field

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the semiconductor light-emitting device.

Background Art

[0002] A semiconductor light-emitting device has an n-type semiconductor layer, an active layer, and a p-type semiconductor layer laminated on a substrate. The semiconductor light-emitting device is joined to a submount substrate via, for example, an AuSn layer (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When AuSn used for joining to the submount substrate diffuses into the semiconductor layer, it may lead to a decrease in luminous efficiency.

[0005] The present invention has been made in view of such problems, and an object thereof is to provide a technique for improving the reliability of a semiconductor light-emitting device.

Means for Solving the Problems

[0006] A semiconductor light-emitting device according to an aspect of the present invention includes an n-type semiconductor layer, an active layer provided on a first upper surface of the n-type semiconductor layer, a p-type semiconductor layer provided on the active layer, a contact electrode that contacts a second upper surface different from the first upper surface of the n-type semiconductor layer or contacts the upper surface of the p-type semiconductor layer, a laminated film provided on the contact electrode and having a first TiN layer and a Rh layer laminated alternately, a second TiN layer provided on the laminated film, a current diffusion layer having a connection opening through which the second TiN layer exposes the Rh layer, a protection layer that has a pad opening provided in the connection opening and covers the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer at a location different from the pad opening and is made of a dielectric material, a pad electrode that contacts the Rh layer of the current diffusion layer at the connection opening and is provided on the protection layer outside the pad opening, and a bonding layer provided on the pad electrode and containing AuSn.

[0007] Another aspect of the present invention is a method for manufacturing a semiconductor light-emitting device. The method includes a step of forming an active layer on an n-type semiconductor layer, a step of forming a p-type semiconductor layer on the active layer, a step of removing a part of each of the p-type semiconductor layer and the active layer to expose the upper surface of the n-type semiconductor layer, a step of forming a contact electrode that contacts the upper surface of the p-type semiconductor layer or contacts the upper surface of the n-type semiconductor layer, a step of forming a current diffusion layer provided on the contact electrode and including a laminated film in which a first TiN layer and a Rh layer are laminated alternately and a second TiN layer provided on the laminated film, a step of forming a protection layer that covers the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer and is made of a dielectric material, a step of removing the protection layer on the current diffusion layer to form a pad opening, a step of removing the second TiN layer at the pad opening to form a connection opening through which the Rh layer of the current diffusion layer is exposed, a step of forming a pad electrode that contacts the Rh layer of the current diffusion layer at the connection opening and is provided on the protection layer outside the pad opening, and a step of forming a bonding layer provided on the pad electrode and containing AuSn.

Advantages of the Invention

[0008] According to the present invention, the reliability of the semiconductor light-emitting device can be improved.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate. Also, for the purpose of assisting the understanding of the description, the dimensional ratios of the respective components in each drawing do not necessarily match the dimensional ratios of the actual light-emitting device.

[0011] The semiconductor light-emitting device according to this embodiment is configured to emit "deep ultraviolet light" with a central wavelength λ of about 360 nm or less, and is a so-called DUV-LED (Deep UltraViolet-Light Emitting Diode) chip. In order to output deep ultraviolet light of such a wavelength, an aluminum gallium nitride (AlGaN)-based semiconductor material with a bandgap of about 3.4 eV or more is used. In this embodiment, in particular, the case of emitting deep ultraviolet light with a central wavelength λ of about 240 nm to 320 nm is shown.

[0012] In this specification, the "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and includes semiconductor materials containing other materials such as indium nitride (InN). Therefore, the "AlGaN-based semiconductor material" referred to in this specification can be represented by the composition of In 1-x-y Al x Ga y N (0 < x + y ≤ 1, 0 < x < 1, 0 < y < 1), and includes AlGaN or InAlGaN. The "AlGaN-based semiconductor material" in this specification has, for example, a molar fraction of each of AlN and GaN of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

[0013] In addition, in order to distinguish materials that do not contain AlN, they may be referred to as "GaN-based semiconductor materials". "GaN-based semiconductor materials" include GaN and InGaN. Similarly, in order to distinguish materials that do not contain GaN, they may be referred to as "AlN-based semiconductor materials". "AlN-based semiconductor materials" include AlN and InAlN.

[0014] FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor light-emitting element 10 according to an embodiment. The semiconductor light-emitting element 10 includes a substrate 20, a base layer 22, an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a p-side contact electrode 30, an n-side contact electrode 32, a p-side current diffusion layer 34, an n-side current diffusion layer 36, a first protective layer 38, a second protective layer 40, a p-side pad electrode 42, an n-side pad electrode 44, a p-side bonding layer 46, and an n-side bonding layer 48.

[0015] In FIG. 1, the direction indicated by arrow A may be referred to as the "vertical direction" or the "thickness direction". Also, when viewed from the substrate 20, the direction away from the substrate 20 may be referred to as the upper side, and the direction toward the substrate 20 may be referred to as the lower side.

[0016] The substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a is a crystal growth surface for growing each layer from the base layer 22 to the p-type semiconductor layer 28. The substrate 20 is made of a material having translucency with respect to the deep ultraviolet light emitted by the semiconductor light-emitting element 10, and is, for example, made of sapphire (Al 2 O 3 ). A fine concavo-convex pattern having a depth and pitch of submicron (1 μm or less) is formed on the first main surface 20a. Such a substrate 20 is also called a patterned sapphire substrate (PSS). The second main surface 20b is a light extraction surface for extracting the deep ultraviolet light emitted by the active layer 26 to the outside. The substrate 20 may be made of AlN or may be made of AlGaN. The substrate 20 may be a normal substrate constituted by a flat surface on which the first main surface 20a is not patterned.

[0017] The base layer 22 is provided on the first main surface 20a of the substrate 20. The base layer 22 is an underlying layer (template layer) for forming the n-type semiconductor layer 24. The base layer 22 is, for example, an undoped AlN layer, specifically, an AlN layer grown at high temperature (HT-AlN; High Temperature - AlN). The base layer 22 may include an undoped AlGaN layer formed on the AlN layer. When the substrate 20 is an AlN substrate or an AlGaN substrate, the base layer 22 may be composed of only an undoped AlGaN layer. That is, the base layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

[0018] The n-type semiconductor layer 24 is provided on the upper surface 22a of the base layer 22. The n-type semiconductor layer 24 is composed of an n-type AlGaN-based semiconductor material and is doped with, for example, Si as an n-type impurity. The composition ratio of the n-type semiconductor layer 24 is selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The n-type semiconductor layer 24 has a bandgap larger than the wavelength of the deep ultraviolet light emitted by the active layer 26. For example, it is configured so that the bandgap is 4.3 eV or more. The n-type semiconductor layer 24 is preferably configured so that the molar fraction of AlN is 80% or less, that is, the bandgap is 5.5 eV or less, and more preferably configured so that the molar fraction of AlN is 70% or less (that is, the bandgap is 5.2 eV or less). The n-type semiconductor layer 24 has a thickness of 1 μm or more and 3 μm or less, for example, a thickness of about 2 μm.

[0019] The n-type semiconductor layer 24 has a Si impurity concentration of 1×10 18 / cm 3 or more and 5×10 19 / cm 3 or less. The n-type semiconductor layer 24 is preferably configured so that the Si concentration is 5×10 18 / cm 3 or more and 3×10 19 / cm 3 or less, and more preferably 7×10 18 / cm3 Above 2×10 19 / cm 3 It is more preferably configured to be below. In one embodiment, the Si concentration of the n-type semiconductor layer 24 is 1×10 19 / cm 3 Before and after, specifically 8×10 18 / cm 3 Above 1.5×10 19 / cm 3 In the following range.

[0020] The n-type semiconductor layer 24 has a first upper surface 24a and a second upper surface 24b. The first upper surface 24a is a portion where the active layer 26 is formed, and the second upper surface 24b is a portion where the active layer 26 is not formed.

[0021] The active layer 26 is provided on the first upper surface 24a of the n-type semiconductor layer 24. The active layer 26 is composed of an AlGaN-based semiconductor material and is sandwiched between the n-type semiconductor layer 24 and the p-type semiconductor layer 28 to form a double heterostructure. The active layer 26 is configured to have a bandgap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less. For example, the AlN composition ratio is selected so that deep ultraviolet light with a wavelength of 320 nm or less can be output.

[0022] The active layer 26 has, for example, a single-layer or multi-layer quantum well structure and includes a barrier layer composed of an undoped AlGaN-based semiconductor material and a well layer composed of an undoped AlGaN-based semiconductor material. The active layer 26 includes, for example, a first barrier layer in direct contact with the n-type semiconductor layer 24 and a first well layer provided on the first barrier layer. One or more pairs of barrier layers and well layers may be additionally provided between the first well layer and the p-type semiconductor layer 28. Each of the barrier layer and the well layer has a thickness of 1 nm or more and 20 nm or less, and for example, has a thickness of 2 nm or more and 10 nm or less.

[0023] An electron blocking layer may be further provided between the active layer 26 and the p-type semiconductor layer 28. The electron blocking layer is composed of an undoped AlGaN-based semiconductor material, and is configured such that, for example, the molar fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer may be configured such that the molar fraction of AlN is 80% or more, or may be composed of an AlN-based semiconductor material that does not contain GaN. The electron blocking layer has a thickness of 1 nm or more and 10 nm or less, and for example, has a thickness of 2 nm or more and 5 nm or less.

[0024] The p-type semiconductor layer 28 is formed on the active layer 26. The p-type semiconductor layer 28 is a p-type AlGaN-based semiconductor material layer or a p-type GaN-based semiconductor material layer, and is, for example, an AlGaN layer or a GaN layer doped with magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 28 has a thickness of, for example, 20 nm or more and 400 nm or less.

[0025] The p-type semiconductor layer 28 may be composed of a plurality of layers. The p-type semiconductor layer 28 may have, for example, a p-type cladding layer and a p-type contact layer. The p-type cladding layer is a p-type AlGaN layer with a higher AlN ratio compared to the p-type contact layer, and is provided so as to be in direct contact with the active layer 26. The p-type contact layer is a p-type AlGaN layer or a p-type GaN layer with a lower AlN ratio compared to the p-type cladding layer. The p-type contact layer is provided on the p-type cladding layer and is provided so as to be in direct contact with the p-side contact electrode 30. The p-type cladding layer may have a p-type first cladding layer and a p-side second cladding layer.

[0026] The composition ratio of the p-type first cladding layer is selected so as to transmit the deep ultraviolet light emitted by the active layer 26. The p-type first cladding layer is configured such that, for example, the molar fraction of AlN is 25% or more, preferably 40% or more, or 50% or more. The AlN ratio of the p-type first cladding layer is, for example, about the same as the AlN ratio of the n-type semiconductor layer 24, or larger than the AlN ratio of the n-type semiconductor layer 24. The AlN ratio of the p-type cladding layer may be 70% or more, or 80% or more. The p-type first cladding layer has a thickness of 10 nm or more and 100 nm or less, and for example, has a thickness of 15 nm or more and 70 nm or less.

[0027] The p-type second cladding layer is provided on the p-type first cladding layer. The p-type second cladding layer is a p-type AlGaN layer with a medium AlN ratio, having an AlN ratio lower than that of the p-type first cladding layer and higher than that of the p-type contact layer. The p-type second cladding layer is formed such that, for example, the molar fraction of AlN is 25% or more, preferably 40% or more, or 50% or more. The AlN ratio of the p-type second cladding layer is formed such that, for example, it is about ±10% of the AlN ratio of the n-type semiconductor layer 24. The p-type second cladding layer has a thickness of 5 nm or more and 250 nm or less, and for example, has a thickness of 10 nm or more and 150 nm or less. Note that the p-type second cladding layer may not be provided, and the p-type cladding layer may be composed of only the p-type first cladding layer.

[0028] The p-type contact layer is a p-type AlGaN layer or a p-type GaN layer with a relatively low AlN ratio. The p-type contact layer is configured such that the AlN ratio is 20% or less, preferably formed such that the AlN ratio is 10% or less, 5% or less, or 0%, in order to obtain a good ohmic contact with the p-side contact electrode 30. That is, the p-type contact layer can be formed of a p-type GaN-based semiconductor material substantially free of AlN. As a result, the p-type contact layer can absorb the deep ultraviolet light emitted by the active layer 26. The p-type contact layer is preferably formed thin in order to reduce the absorption amount of the deep ultraviolet light emitted by the active layer 26. The p-type contact layer has a thickness of 5 nm or more and 30 nm or less, and for example, has a thickness of 10 nm or more and 20 nm or less.

[0029] The p-side contact electrode 30 is provided on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is capable of making ohmic contact with the p-type semiconductor layer 28 (for example, a p-type contact layer), and is made of a material having a high reflectivity with respect to the deep ultraviolet light emitted by the active layer 26. The p-side contact electrode 30 includes an Rh layer that directly contacts the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 consists of, for example, only the Rh layer. The thickness of the Rh layer included in the p-side contact electrode 30 is 50 nm or more and 200 nm or less, and for example, 70 nm or more and 150 nm or less.

[0030] The n-side contact electrode 32 is provided on the second upper surface 24b of the n-type semiconductor layer 24. The n-side contact electrode 32 includes a first Ti layer, an Al layer, a second Ti layer, and a TiN layer that are laminated in order. The details of the configuration of the n-side contact electrode 32 will be described separately later with reference to FIG. 3.

[0031] The p-side current diffusion layer 34 is provided on the p-side contact electrode 30. The p-side current diffusion layer 34 is in contact with the p-side contact electrode 30 and may cover the entire p-side contact electrode 30. The p-side current diffusion layer 34 includes a laminated film in which a first TiN layer and an Rh layer are alternately laminated, and a second TiN layer provided on the laminated film. The p-side current diffusion layer 34 has a p-side connection opening 34a in which the second TiN layer is partially removed and the Rh layer is exposed. The details of the configuration of the p-side current diffusion layer 34 will be described separately later with reference to FIG. 2.

[0032] The n-side current diffusion layer 36 is provided on the n-side contact electrode 32. The n-side current diffusion layer 36 is in contact with the n-side contact electrode 32 and may cover the entire n-side contact electrode 32. The n-side current diffusion layer 36 can have the same configuration as the p-side current diffusion layer 34, and includes a laminated film in which a first TiN layer and an Rh layer are alternately laminated, and a second TiN layer provided on the laminated film. The n-side current diffusion layer 36 has an n-side connection opening 36a in which the second TiN layer is partially removed and the Rh layer is exposed. The details of the configuration of the n-side current diffusion layer 36 will be described separately later with reference to FIG. 3.

[0033] The first protective layer 38 is provided so as to cover the entire upper part of the element. The first protective layer 38 covers the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36. The first protective layer 38 has a first p-side pad opening 38p provided on the p-side current diffusion layer 34 and a first n-side pad opening 38n provided on the n-side current diffusion layer 36. The first protective layer 38 covers the p-side current diffusion layer 34 at a location different from the first p-side pad opening 38p and covers the n-side current diffusion layer 36 at a location different from the first n-side pad opening 38n. The first protective layer 38 contacts the base layer 22 at the outer periphery of the n-type semiconductor layer 24. The first protective layer 38 contacts the upper surface 22a of the base layer 22, contacts the second upper surface 24b and the side surface 24c of the n-type semiconductor layer 24, contacts the side surface 26b of the active layer 26, contacts the upper surface 28a and the side surface 28b of the p-type semiconductor layer 28, contacts the p-side current diffusion layer 34, and contacts the n-side current diffusion layer 36.

[0034] The first protective layer 38 is composed of an oxide dielectric material such as silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ). The first protective layer 38 is preferably composed of SiO 2 . The thickness of the first protective layer 38 is 300 nm or more and 1500 nm or less, for example, 600 nm or more and 1000 nm or less.

[0035] The second protective layer 40 is provided so as to cover the entire upper part of the element and so as to cover the entire surface of the first protective layer 38. The second protective layer 40 has a second p-side pad opening 40p provided on the p-side current diffusion layer 34 and a second n-side pad opening 40n provided on the n-side current diffusion layer 36. The second protective layer 40 covers the first protective layer 38 at a location different from the second p-side pad opening 40p and the second n-side pad opening 40n. The second protective layer 40 is also provided inside each of the first p-side pad opening 38p and the first n-side pad opening 38n. The second protective layer 40 covers the inner peripheral surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p and covers the inner peripheral surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 contacts the base layer 22 at the outer periphery of the first protective layer 38. The second protective layer 40 contacts the upper surface 22a of the base layer 22, contacts the inner peripheral surfaces 38a, 38b of the first protective layer 38, contacts the upper surface 34b of the p-side current diffusion layer 34, and contacts the upper surface 36b of the n-side current diffusion layer 36.

[0036] The second protective layer 40 is made of silicon nitride (SiN x ) which is a dielectric material excellent in moisture resistance. The thickness of the second protective layer 40 is 50 nm or more and 500 nm or less, for example, 100 nm or more and 400 nm or less.

[0037] The p-side pad electrode 42 and the n-side pad electrode 44 are portions to be joined when mounting the semiconductor light-emitting element 10 on a submount or the like. The p-side pad electrode 42 and the n-side pad electrode 44 include, for example, a stacked structure of Ni / Au or Ti / Au. The p-side pad electrode 42 and the n-side pad electrode 44 may be configured not to contain platinum group elements such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt). The thickness of each of the p-side pad electrode 42 and the n-side pad electrode 44 is 100 nm or more, for example, 200 nm or more and 1000 nm or less.

[0038] The p-side pad electrode 42 is provided on the p-side current diffusion layer 34 and contacts the upper surface 34b of the p-side current diffusion layer 34 at the second p-side pad opening 40p. The p-side pad electrode 42 contacts the Rh layer of the p-side current diffusion layer 34 at the p-side connection opening 34a. The p-side pad electrode 42 is electrically connected to the p-side contact electrode 30 through the p-side current diffusion layer 34. The p-side pad electrode 42 is provided so as to close the second p-side pad opening 40p and is provided on the second protective layer 40 outside the second p-side pad opening 40p.

[0039] The n-side pad electrode 44 is provided on the n-side current diffusion layer 36 and contacts the upper surface 36b of the n-side current diffusion layer 36 at the second n-side pad opening 40n. The n-side pad electrode 44 contacts the Rh layer of the n-side current diffusion layer 36 at the n-side connection opening 36a. The n-side pad electrode 44 is electrically connected to the n-side contact electrode 32 through the n-side current diffusion layer 36. The n-side pad electrode 44 is provided so as to close the second n-side pad opening 40n and is provided on the second protective layer 40 outside the second n-side pad opening 40n.

[0040] The p-side bonding layer 46 and the n-side bonding layer 48 are bonding layers for bonding the semiconductor light-emitting element 10 to the submount. The p-side bonding layer 46 and the n-side bonding layer 48 contain, for example, Au and Sn. The p-side bonding layer 46 and the n-side bonding layer 48 may contain AuSn, which is a mixed crystal of Au and Sn, or may have a laminated structure of an Au layer and an Sn layer.

[0041] FIG. 2 schematically shows the configuration of the p-side contact electrode 30, the p-side current diffusion layer 34, and the p-side pad electrode 42. The p-side current diffusion layer 34 includes a Ti layer 50, a laminated film 56 in which the first TiN layer 52 and the Rh layer 54 are alternately laminated, and a second TiN layer 58. The p-side pad electrode 42 includes an adhesive layer 42a made of Ni or Ti and an Au layer 42b.

[0042] The Ti layer 50 of the p-side current diffusion layer 34 is in contact with the p-side contact electrode 30. The thickness of the Ti layer 50 of the p-side current diffusion layer 34 is 10 nm or more and 200 nm or less, for example, 20 nm or more and 150 nm or less. The p-side current diffusion layer 34 may not include the Ti layer 50, and the stacked film 56 (for example, the first TiN layer 52) of the p-side current diffusion layer 34 may be in contact with the p-side contact electrode 30.

[0043] The stacked film 56 of the p-side current diffusion layer 34 is provided on the Ti layer 50. The stacked film 56 of the p-side current diffusion layer 34 includes the first TiN layer 52 and the Rh layer 54. The stacked film 56 may have a plurality of first TiN layers 52 and a plurality of Rh layers 54 that are alternately stacked. The first TiN layer 52 is composed of conductive TiN. The thickness of the first TiN layer 52 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The thickness of the Rh layer 54 is 10 nm or more and 200 nm or less, for example, 20 nm or more and 150 nm or less.

[0044] The second TiN layer 58 of the p-side current diffusion layer 34 is provided on the stacked film 56. The second TiN layer 58 is in contact with the Rh layer 54 that constitutes the uppermost layer of the stacked film 56. The second TiN layer 58 is composed of conductive TiN. The thickness of the second TiN layer 58 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The second TiN layer 58 has a p-side connection opening 34a that exposes the Rh layer 54 that constitutes the uppermost layer of the stacked film 56. The p-side connection opening 34a is provided at a position communicating with the first p-side pad opening 38p.

[0045] The first protective layer 38 is provided on the p-side current diffusion layer 34 outside the p-side connection opening 34a. The first protective layer 38 is in contact with the second TiN layer 58 of the p-side current diffusion layer 34. The first protective layer 38 is not provided inside the p-side connection opening 34a and does not contact the upper surface 34b (that is, the uppermost Rh layer 54) of the p-side current diffusion layer 34 exposed at the p-side connection opening 34a.

[0046] The second protective layer 40 contacts the inner peripheral surface 38a that defines the first p-side pad opening 38p of the first protective layer 38. The second protective layer 40 contacts the inner peripheral surface 34c that defines the p-side connection opening 34a of the p-side current diffusion layer 34. The second protective layer 40 contacts the upper surface 34b (i.e., the uppermost Rh layer 54) of the p-side current diffusion layer 34 that is exposed inside the p-side connection opening 34a.

[0047] The adhesive layer 42a of the p-side pad electrode 42 contacts the p-side current diffusion layer 34 inside the second p-side pad opening 40p. The adhesive layer 42a of the p-side pad electrode 42 contacts the Rh layer 54 that constitutes the uppermost layer of the laminated film 56. The adhesive layer 42a of the p-side pad electrode 42 does not contact the second TiN layer 58 of the p-side current diffusion layer 34. The adhesive layer 42a of the p-side pad electrode 42 does not contact the first protective layer 38. The Au layer 42b of the p-side pad electrode 42 is provided on the adhesive layer 42a. The p-side bonding layer 46 (not shown in FIG. 2) is provided on the Au layer 42b of the p-side pad electrode 42.

[0048] FIG. 3 schematically shows the configurations of the n-side contact electrode 32, the n-side current diffusion layer 36, and the n-side pad electrode 44. The n-side contact electrode 32 includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66. The n-side current diffusion layer 36 includes a Ti layer 70, a laminated film 76 in which a first TiN layer 72 and a Rh layer 74 are alternately laminated, and a second TiN layer 78. The n-side pad electrode 44 includes an adhesive layer 44a made of Ni or Ti and an Au layer 44b.

[0049] The Ti layer 70 of the n-side current diffusion layer 36 contacts the TiN layer 66 of the n-side contact electrode 32. The thickness of the Ti layer 70 of the n-side current diffusion layer 36 is 10 nm or more and 200 nm or less, for example, 20 nm or more and 150 nm or less. The n-side current diffusion layer 36 may not include the Ti layer 70, and the laminated film 76 (for example, the first TiN layer 72) of the n-side current diffusion layer 36 may contact the n-side contact electrode 32.

[0050] The laminated film 76 of the n-side current diffusion layer 36 is provided on the Ti layer 70. The laminated film 76 of the n-side current diffusion layer 36 includes a first TiN layer 72 and a Rh layer 74. The laminated film 76 may have a plurality of first TiN layers 72 and a plurality of Rh layers 74 laminated alternately. The first TiN layer 72 is composed of conductive TiN. The thickness of the first TiN layer 72 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The thickness of the Rh layer 74 is 10 nm or more and 200 nm or less, for example, 20 nm or more and 150 nm or less.

[0051] The second TiN layer 78 of the n-side current diffusion layer 36 is provided on the laminated film 76. The second TiN layer 78 is composed of conductive TiN. The thickness of the second TiN layer 78 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The second TiN layer 78 has an n-side connection opening 36a that exposes the Rh layer 74 constituting the uppermost layer of the laminated film 76. The n-side connection opening 36a is provided at a position communicating with the first n-side pad opening 38n.

[0052] The first protective layer 38 is provided on the n-side current diffusion layer 36 outside the n-side connection opening 36a. The first protective layer 38 contacts the second TiN layer 78 of the n-side current diffusion layer 36. The first protective layer 38 is not provided inside the n-side connection opening 36a and does not contact the upper surface 36b (that is, the uppermost Rh layer 74) of the n-side current diffusion layer 36 exposed at the n-side connection opening 36a.

[0053] The second protective layer 40 contacts the inner peripheral surface 38b that defines the first n-side pad opening 38n of the first protective layer 38. The second protective layer 40 contacts the inner peripheral surface 36c that defines the n-side connection opening 36a of the n-side current diffusion layer 36. The second protective layer 40 contacts the upper surface 36b (that is, the uppermost Rh layer 74) of the n-side current diffusion layer 36 exposed inside the n-side connection opening 36a.

[0054] The adhesive layer 44a of the n-side pad electrode 44 contacts the n-side current diffusion layer 36 inside the second n-side pad opening 40n. The adhesive layer 44a of the n-side pad electrode 44 contacts the Rh layer 74 that constitutes the uppermost layer of the laminated film 76. The adhesive layer 44a of the n-side pad electrode 44 does not contact the second TiN layer 78 of the n-side current diffusion layer 36. The adhesive layer 44a of the n-side pad electrode 44 does not contact the first protective layer 38. The Au layer 44b of the n-side pad electrode 44 is provided on the adhesive layer 44a. The n-side bonding layer 48 (not shown in FIG. 3) is provided on the Au layer 44b of the n-side pad electrode 44.

[0055] Next, a method for manufacturing the semiconductor light-emitting element 10 will be described. FIGS. 4 to 11 are diagrams schematically showing the manufacturing process of the semiconductor light-emitting element 10. First, in FIG. 4, a base layer 22, an n-type semiconductor layer 24, an active layer 26, and a p-type semiconductor layer 28 are sequentially formed on the first main surface 20a of the substrate 20.

[0056] The substrate 20 is, for example, a patterned sapphire substrate. The base layer 22 includes, for example, an HT-AlN layer and an undoped AlGaN layer. The n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are semiconductor layers composed of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and can be formed using a well-known epitaxial growth method such as metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

[0057] Next, as shown in FIG. 4, for example, using a known lithography technique, a mask 80 is formed on the upper surface 28a of the p-type semiconductor layer 28. In a state where the mask 80 is formed, the p-type semiconductor layer 28 and the active layer 26 in a region that does not overlap with the mask 80 are removed by dry etching or the like to expose the second upper surface 24b of the n-type semiconductor layer 24. By this etching process, side surfaces 28b of the p-type semiconductor layer 28, side surfaces 26b of the active layer 26, and the second upper surface 24b of the n-type semiconductor layer 24 are formed. Then, the mask 80 is removed.

[0058] Next, as shown in FIG. 5, for example, using a known lithography technique, a p-side contact electrode 30 is formed on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 includes a Rh layer that directly contacts the upper surface 28a of the p-type semiconductor layer 28. The Rh layer of the p-side contact electrode 30 is formed by a vapor deposition method. By forming the Rh layer by the vapor deposition method, damage to the upper surface 28a of the p-type semiconductor layer 28 can be suppressed compared to the case of using a sputtering method, and the contact resistance of the p-side contact electrode 30 can be improved.

[0059] After the formation of the p-side contact electrode 30, the p-side contact electrode 30 is annealed. The p-side contact electrode 30 is annealed at a temperature of 500°C or higher and 650°C or lower, for example, using a RTA (Rapid Thermal Annealing) method. By the annealing treatment of the p-side contact electrode 30, the contact resistance of the p-side contact electrode 30 is reduced. By the annealing treatment of the p-side contact electrode 30, the film density of the p-side contact electrode 30 increases, and the reflectance of the p-side contact electrode 30 is improved.

[0060] Next, as shown in FIG. 5, for example, using a known lithography technique, an n-side contact electrode 32 is formed on the second upper surface 24b of the n-type semiconductor layer 24. The n-side contact electrode 32 contacts the second upper surface 24b of the n-type semiconductor layer 24 and includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66 (see FIG. 3) that are sequentially stacked. The first Ti layer 60, the Al layer 62, the second Ti layer 64, and the TiN layer 66 that constitute the n-side contact electrode 32 are formed by sputtering.

[0061] After the formation of the n-side contact electrode 32, the n-side contact electrode 32 is annealed. The n-side contact electrode 32 is annealed at a temperature of 500°C or higher and 650°C or lower, for example, using a RTA method. By the annealing treatment of the n-side contact electrode 32, the contact resistance of the n-side contact electrode 32 is reduced.

[0062] Next, as shown in FIG. 6, for example, using a known lithography technique, a p-side current diffusion layer 34 is formed on the p-side contact electrode 30, and an n-side current diffusion layer 36 is formed on the n-side contact electrode 32. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 include a Ti layer, a laminated film in which a first TiN layer and a Rh layer are alternately laminated, and a second TiN layer. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 can be formed by sputtering. Note that the p-side current diffusion layer 34 and the n-side current diffusion layer 36 may be formed separately.

[0063] Next, as shown in FIG. 7, for example, using a known lithography technique, a mask 82 is formed on the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36. In a state where the mask 82 is formed, the n-type semiconductor layer 24 in a region that does not overlap with the mask 82 is removed by dry etching or the like to expose the upper surface 22a of the base layer 22. By this etching process, a side surface 24c of the n-type semiconductor layer 24 is formed. Then, the mask 82 is removed.

[0064] Next, as shown in FIG. 8, a first protective layer 38 is formed so as to cover the entire upper part of the element. The first protective layer 38 2 can be composed of and can be formed using a plasma-enhanced chemical vapor deposition (PECVD) method. The first protective layer 38 is formed so as to be in contact with the upper surface 22a of the base layer 22, the second upper surface 24b and the side surface 24c of the n-type semiconductor layer 24, the side surface 26c of the active layer 26, the upper surface 28a and the side surface 28c of the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36.

[0065] Next, as shown in FIG. 9, a mask 84 is formed on the first protective layer 38 using, for example, a known lithography technique. The mask 84 is formed excluding the formation range W1p of the first p-side pad opening 38p, the formation range W1n of the first n-side pad opening 38n, and the first outer peripheral range W1a for exposing the upper surface 22a of the base layer 22. In a state where the mask 84 is formed, the first protective layer 38 in a region not overlapping with the mask 84 is removed by dry etching. By removing the first protective layer 38 on the p-side current diffusion layer 34, a first p-side pad opening 38p where the p-side current diffusion layer 34 is exposed is formed. By removing the first protective layer 38 on the n-side current diffusion layer 36, a first n-side pad opening 38n where the n-side current diffusion layer 36 is exposed is formed. Further, by removing the outer peripheral portion of the first protective layer 38 in the first outer peripheral range W1a, the upper surface 22a of the base layer 22 is exposed.

[0066] As shown in FIG. 9, in the formation range W1p of the first p-side pad opening 38p, by dry etching the p-side current diffusion layer 34, the second TiN layer 58 of the p-side current diffusion layer 34 is removed, and a p-side connection opening 34a where the uppermost Rh layer 54 is exposed is formed. Also, in the formation range W1n of the first n-side pad opening 38n, by dry etching the n-side current diffusion layer 36, the second TiN layer 78 of the n-side current diffusion layer 36 is removed, and an n-side connection opening 36a where the uppermost Rh layer 74 is exposed is formed. Thereafter, the mask 84 is removed.

[0067] Next, as shown in FIG. 10, a second protective layer 40 is formed so as to cover the entire upper part of the element. The second protective layer 40 is SiN xIt can be composed of and can be formed using the PECVD method. The second protective layer 40 is formed so as to contact the upper surface 22a of the base layer 22 and the surface of the first protective layer 38. The second protective layer 40 contacts the inner peripheral surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p at the first p-side pad opening 38p. The second protective layer 40 contacts the inner peripheral surface 34c of the p-side current diffusion layer 34 (i.e., the second TiN layer 58) that defines the p-side connection opening 34a and contacts the upper surface 34b of the p-side current diffusion layer 34 at the p-side connection opening 34a. The second protective layer 40 contacts the inner peripheral surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n at the first n-side pad opening 38n. The second protective layer 40 contacts the inner peripheral surface 36c of the n-side current diffusion layer 36 (i.e., the second TiN layer 78) that defines the n-side connection opening 36a and contacts the upper surface 36b of the n-side current diffusion layer 36 at the n-side connection opening 36a.

[0068] Next, as shown in FIG. 11, for example, using a known lithography technique, a mask 86 is formed on the second protective layer 40. The mask 86 is formed excluding the formation range W2p of the second p-side pad opening 40p, the formation range W2n of the second n-side pad opening 40n, and the second outer peripheral range W2a that exposes the upper surface 22a of the base layer 22. In a state where the mask 86 is formed, the second protective layer 40 in a region that does not overlap the mask 86 is removed by dry etching or the like. By removing the second protective layer 40 on the p-side current diffusion layer 34, a second p-side pad opening 40p is formed in which the upper surface 34b of the p-side current diffusion layer 34 is exposed. By removing the second protective layer 40 on the n-side current diffusion layer 36, a second n-side pad opening 40n is formed in which the upper surface 36b of the n-side current diffusion layer 36 is exposed. Further, by removing the outer peripheral portion of the second protective layer 40 in the second outer peripheral range W2a, the upper surface 22a of the base layer 22 is exposed. The second outer peripheral range W2a becomes an element separation region for cutting the substrate 20 and the base layer 22 to individualize the elements. Thereafter, the mask 86 is removed.

[0069] Next, as shown in FIG. 1, for example, using a known lithography technique, a p-side pad electrode 42 connected to the p-side current diffusion layer 34 is formed at the second p-side pad opening 40p, and an n-side pad electrode 44 connected to the n-side current diffusion layer 36 is formed at the second n-side pad opening 40n. The p-side pad electrode 42 is formed so as to overlap the second protective layer 40 outside the second p-side pad opening 40p. The n-side pad electrode 44 is formed so as to overlap the second protective layer 40 outside the second n-side pad opening 40n. The p-side pad electrode 42 and the n-side pad electrode 44 can be formed simultaneously, but may also be formed separately. Next, for example, using a known lithography technique, a p-side bonding layer 46 is formed on the p-side pad electrode 42, and an n-side bonding layer 48 is formed on the n-side pad electrode 44. The p-side bonding layer 46 and the n-side bonding layer 48 can be formed simultaneously, but may also be formed separately.

[0070] Through the above steps, the semiconductor light-emitting element 10 shown in FIG. 1 is completed.

[0071] FIG. 12 is a cross-sectional view schematically showing the configuration of the semiconductor light-emitting device 100 according to the embodiment. The semiconductor light-emitting device 100 includes a semiconductor light-emitting element 10 and a submount 90. In FIG. 12, the semiconductor light-emitting element 10 shown in FIG. 1 is turned upside down.

[0072] The submount 90 includes a submount substrate 92, a first mount electrode 94, and a second mount electrode 96. The first mount electrode 94 and the second mount electrode 96 are provided on the surface of the submount substrate 92. The first mount electrode 94 is connected to the p-side pad electrode 42 via the p-side bonding layer 46. The second mount electrode 96 is connected to the n-side pad electrode 44 via the n-side bonding layer 48.

[0073] According to the present embodiment, since the semiconductor light-emitting element 10 is connected to the submount 90 via the p-side bonding layer 46 and the n-side bonding layer 48 containing AuSn, the driving heat of the semiconductor light-emitting element 10 can be efficiently transmitted to the submount 90. Thereby, the semiconductor light-emitting element 10 can be efficiently cooled, and the reliability of the semiconductor light-emitting element 10 can be improved.

[0074] According to this embodiment, the diffusion of AuSn contained in the p-side bonding layer 46 toward the p-type semiconductor layer 28 can be prevented or blocked by the Rh layer 54 contained in the p-side current diffusion layer 34. In particular, the diffusion prevention effect can be improved by bringing the Rh layer 54 of the p-side current diffusion layer 34, which has a diffusion prevention effect on AuSn, into direct contact with the p-side pad electrode 42.

[0075] According to this embodiment, since the second protective layer 40 is in a structure that directly contacts the Rh layers 54 and 74 of the p-side current diffusion layer 34 and the n-side current diffusion layer 36, the sealing property by the first protective layer 38 and the second protective layer 40 can be improved.

[0076] As described above, the present invention has been described based on the embodiments. It is understood by those skilled in the art that the present invention is not limited to the above-described embodiments, various design changes are possible, various modifications are possible, and such modifications are also within the scope of the present invention.

[0077] Hereinafter, some aspects of the present invention will be described.

[0078] A first aspect of the present invention includes an n-type semiconductor layer, an active layer provided on a first upper surface of the n-type semiconductor layer, a p-type semiconductor layer provided on the active layer, a contact electrode that contacts a second upper surface different from the first upper surface of the n-type semiconductor layer or contacts an upper surface of the p-type semiconductor layer, a stacked film provided on the contact electrode and having a first TiN layer and a Rh layer stacked alternately, a second TiN layer provided on the stacked film, a current diffusion layer having a connection opening through which the second TiN layer exposes the Rh layer, a protection layer having a pad opening provided in the connection opening and covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer at a location different from the pad opening and being composed of a dielectric material, a pad electrode that contacts the Rh layer of the current diffusion layer in the connection opening and is provided on the protection layer outside the pad opening, and a bonding layer provided on the pad electrode and containing AuSn. According to the first aspect, by providing a bonding layer containing AuSn on the pad electrode, the heat dissipation performance can be improved. Further, by bringing the pad electrode into contact with the Rh layer, the diffusion of AuSn contained in the bonding layer toward the semiconductor layer can be suitably prevented by the Rh layer, and a decrease in the light emission efficiency can be suppressed. Thereby, a highly reliable semiconductor light-emitting device can be provided.

[0079] A second aspect of the present invention is the semiconductor light-emitting device according to the first aspect, wherein the protection layer includes a first protection layer having a first pad opening provided in the connection opening and covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer at a location different from the first pad opening and being composed of silicon oxide, and a second protection layer having a second pad opening provided in the connection opening and covering the first protection layer at a location different from the second pad opening and being composed of silicon nitride. According to the second aspect, by combining the first protection layer and the second protection layer, the sealing performance of the semiconductor light-emitting device can be improved.

[0080] A third aspect of the present invention is the semiconductor light-emitting device according to the second aspect, wherein the second protective layer contacts the inner peripheral surfaces of the connection opening and the first pad opening and contacts the Rh layer at the connection opening. According to the third aspect, by adopting a structure in which the second protective layer contacts the Rh layer of the current diffusion layer, the sealing performance by the first protective layer and the second protective layer can be improved.

[0081] A fourth aspect of the present invention is the semiconductor light-emitting device according to the second or third aspect, wherein the second protective layer contacts the second TiN layer at the connection opening. According to the fourth aspect, by adopting a structure in which the second protective layer contacts the second TiN layer of the current diffusion layer, the sealing performance by the first protective layer and the second protective layer can be improved.

[0082] The fifth aspect of the present invention includes a step of forming an active layer on an n-type semiconductor layer, a step of forming a p-type semiconductor layer on the active layer, a step of removing a part of each of the p-type semiconductor layer and the active layer to expose the upper surface of the n-type semiconductor layer, a step of forming a contact electrode that contacts the upper surface of the p-type semiconductor layer or contacts the upper surface of the n-type semiconductor layer, a step of forming a current diffusion layer including a laminated film provided on the contact electrode and having a first TiN layer and a Rh layer laminated alternately, and a second TiN layer provided on the laminated film, a step of forming a protective layer covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer and composed of a dielectric material, a step of removing the protective layer on the current diffusion layer to form a pad opening, a step of removing the second TiN layer of the current diffusion layer in the pad opening to form a connection opening where the Rh layer is exposed, a step of forming a pad electrode that contacts the Rh layer of the current diffusion layer in the connection opening and is provided on the protective layer outside the pad opening, and a step of forming a bonding layer containing AuSn on the pad electrode. According to the fifth aspect, by removing the second TiN layer of the current diffusion layer and bringing the pad electrode into contact with the Rh layer of the current diffusion layer, diffusion of AuSn contained in the bonding layer toward the semiconductor layer can be suitably prevented by the Rh layer, and a decrease in luminous efficiency can be suppressed.

[0083] The sixth aspect of the present invention further includes a step of forming a mask having an opening on the protective layer, the step of forming the pad opening includes a step of dry-etching the protective layer through the opening of the mask, and the step of forming the connection opening includes a step of dry-etching the second TiN layer of the current diffusion layer through the opening of the mask, which is the method for manufacturing a semiconductor light-emitting device according to the fifth aspect. According to the sixth aspect, by forming the pad opening and the connection opening by dry-etching using a common mask, the pad electrode can be brought into contact with the Rh layer of the current diffusion layer, and the effect of preventing diffusion of AuSn by the Rh layer can be improved.

Description of Reference Numerals

[0084] 10…semiconductor light-emitting element, 24…n-type semiconductor layer, 24a…first upper surface, 24b…second upper surface, 26…active layer, 28…p-type semiconductor layer, 30…p-side contact electrode, 32…n-side contact electrode, 34…p-side current diffusion layer, 34a…p-side connection opening, 36…n-side current diffusion layer, 36a…n-side connection opening, 38…first protective layer, 38a…inner peripheral surface, 38p…first p-side pad opening, 38n…first n-side pad opening, 40…second protective layer, 40p…second p-side pad opening, 40n…second n-side pad opening, 42…p-side pad electrode, 44…n-side pad electrode, 52, 72…first TiN layer, 54, 74…Rh layer, 58, 78…second TiN layer.

Claims

1. An n-type semiconductor layer; an active layer provided on a first upper surface of the n-type semiconductor layer; a p-type semiconductor layer provided on the active layer; a contact electrode in contact with a second upper surface different from the first upper surface of the n-type semiconductor layer or in contact with an upper surface of the p-type semiconductor layer; a current spreading layer provided on the contact electrode, the current spreading layer including a laminate film in which a first TiN layer and a Rh layer are alternately laminated, and a second TiN layer provided on the laminate film, the second TiN layer having a connection opening exposing the Rh layer; a protective layer having a pad opening provided in the connection opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current spreading layer at a location different from the pad opening, and made of a dielectric material; a pad electrode in contact with the Rh layer of the current spreading layer in the connection opening and provided on the protective layer outside the pad opening; a bonding layer provided on the pad electrode and containing AuSn; Semiconductor light emitting element.

2. The protective layer is a first protective layer made of silicon oxide, the first protective layer having a first pad opening provided in the connection opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current spreading layer at a location different from the first pad opening; a second protective layer having a second pad opening provided in the connection opening, covering the first protective layer at a location different from the second pad opening, and made of silicon nitride; The semiconductor light emitting device according to claim 1 .

3. the second protective layer is in contact with inner circumferential surfaces of the connection opening and the first pad opening, and is in contact with the Rh layer at the connection opening; The semiconductor light emitting device according to claim 2 .

4. the second protective layer contacts the second TiN layer at the contact opening; The semiconductor light emitting device according to claim 2 .

5. forming an active layer on the n-type semiconductor layer; forming a p-type semiconductor layer on the active layer; removing a portion of each of the p-type semiconductor layer and the active layer to expose an upper surface of the n-type semiconductor layer; forming a contact electrode in contact with a top surface of the p-type semiconductor layer or in contact with the top surface of the n-type semiconductor layer; forming a current spreading layer including a laminated film provided on the contact electrode, the laminated film being formed by alternately laminating a first TiN layer and a Rh layer, and a second TiN layer provided on the laminated film; forming a protective layer made of a dielectric material to cover the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current spreading layer; removing the protective layer on the current spreading layer to form a pad opening; removing the second TiN layer in the pad opening to form a contact opening in which the Rh layer of the current spreading layer is exposed; forming a pad electrode in contact with the Rh layer of the current spreading layer in the connection opening and provided on the protective layer outside the pad opening; forming a bonding layer containing AuSn on the pad electrode; A method for manufacturing a semiconductor light emitting device.

6. forming a mask having an opening on the protective layer; forming the pad opening includes dry etching the protective layer through the opening of the mask; The step of forming the connection opening includes the step of dry etching the second TiN layer of the current spreading layer through the opening of the mask. The method for manufacturing a semiconductor light emitting device according to claim 5 .

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