Semiconductor device and power conversion device

Abstract

The present invention increases maximum unipolar current density while relaxing the electric field that acts on a body diode when a transistor is in an off state. A semiconductor device according to the present invention comprises a first separation region and a second separation region. The first separation region extends in a first direction and a second direction as seen in plan view and has at least one first turn region that turns back in the second direction. The second separation region extends in at least the first direction as seen in plan view, and the width of the second separation region in the second direction is at least the width of the first separation region in the first direction or the second direction.

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] A vertical metal-oxide-semiconductor field-effect transistor (MOSFET) using silicon carbide may incorporate a unipolar diode as a freewheeling diode.

[0003] For example, Patent Document 1 proposes a method of incorporating a Schottky barrier diode (SBD) as a unipolar diode within a unit cell of a MOSFET and using it.

[0004] In such a unipolar transistor that has a built-in unipolar diode in the active region, i.e., a diode that conducts electricity only with majority carriers, the diffusion potential of the unipolar diode, i.e., the voltage at which electricity begins to flow, can be designed to be lower than the voltage at which electricity begins to flow in a PN junction (hereinafter sometimes referred to as the body diode) in a MOS structure, thereby suppressing the forward current and defect expansion in the body diode. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-049951 A Summary of the Invention [Problem to be solved by the invention]

[0006] In a MOSFET with a built-in SBD, when a current with a specific current density flows through the SBD, conduction of the body diode starts. This specific current density is defined as the maximum unipolar current density.

[0007] If the width or length of the SBD, that is, the area, is designed to be large, the maximum unipolar current density increases and the current flowing through the body diode can be suppressed. On the other hand, when the transistor is in the off state, the electric field tends to concentrate on the PN diode formed around the SBD, and leakage current may flow, generating heat and possibly damaging the device or circuit.

[0008] From the above, there is a situation where it is desired to design a large SBD area to increase the maximum unipolar current density, and conversely, there is a situation where it is desired to design a narrow SBD area to prevent device breakdown when the transistor is in the off state.

[0009] The technology disclosed in the present specification has been made in view of the problems described above, and is a technology for increasing the maximum unipolar current density while relaxing the electric field applied to the body diode in the off state of the transistor.

Means for Solving the Problem

[0010] A semiconductor device, which is a first aspect of the technology disclosed in the present specification, includes a first-conductivity-type drift layer provided on the upper surface of a first-conductivity-type semiconductor substrate, a plurality of second-conductivity-type well regions provided separately from each other on the surface layer of the drift layer, a first-conductivity-type source region provided on the surface layer of the well region, a first-conductivity-type first separation region which is a region between the plurality of well regions on the surface layer of the drift layer, a first-conductivity-type second separation region which is a region between the plurality of well regions on the surface layer of the drift layer and is different from the first separation region, a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer, a gate electrode provided in contact with the gate insulating film, a Schottky electrode provided on the upper surface of the first separation region and forming a Schottky junction with the first separation region, an ohmic electrode provided on the upper surface of the source region, and a source electrode provided in contact with the Schottky electrode and the ohmic electrode. The first separation region extends in a first direction and a second direction different from the first direction in a plan view, the first separation region has at least one first folding region that folds back in the second direction, the second separation region extends at least in the first direction in a plan view, and the width of the second separation region in the second direction is equal to or greater than the width of the first separation region in the first direction or the second direction.

Effect of the Invention

[0011] According to at least the first aspect of the technology disclosed in the present specification, by providing the first folding region in the first separation region, the maximum unipolar current density can be increased. On the other hand, by making the width of the first separation region narrower than the width of the second separation region, the electric field applied to the PN junction formed by the first separation region and the well region can be reduced.

[0012] Also, the objects, features, aspects, and advantages related to the technology disclosed in the present specification will become more apparent from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features and the like are also shown for the purpose of explaining the technology, but these are examples, and not all of them are necessarily essential features for the embodiments to be practicable.

[0015] Note that the drawings are shown schematically, and for convenience of explanation, omissions or simplifications of configurations are made in the drawings as appropriate. Also, the mutual relationships of the sizes and positions of the configurations shown in different drawings are not necessarily accurately described and can be changed as appropriate. Further, in drawings such as a plan view that is not a cross-sectional view, hatching may be added to facilitate understanding of the content of the embodiment.

[0016] Also, in the explanations shown below, the same reference numerals are used to illustrate the same components, and their names and functions are also assumed to be the same. Therefore, detailed explanations thereof may be omitted to avoid duplication.

[0017] Also, in the explanations described in the present specification, when a component is described as "including", "comprising", or "having", etc., it is not an exclusive expression that excludes the existence of other components, unless otherwise specified.

[0018] Also, in the explanations described in the present specification, even when ordinal numbers such as "first" or "second" are used, these terms are used for convenience to facilitate understanding of the content of the embodiment, and the content of the embodiment is not limited to the order that may be generated by these ordinal numbers.

[0019] In addition, in the description given in the specification of the present application, even when terms such as "upper", "lower", "left", "right", "side", "bottom", "front" or "back" that mean specific positions or directions are used, these terms are used for convenience in order to facilitate understanding of the content of the embodiment, and have no relation to the position or direction when the embodiment is actually implemented.

[0020] In addition, in the description given in the specification of the present application, when described as "the upper surface of..." or "the lower surface of...", in addition to the upper surface itself or the lower surface itself of the target component, a state in which other components are formed on the upper surface or the lower surface of the target component is also included. That is, for example, when described as "B provided on the upper surface of A", it does not prevent another component "C" from intervening between A and B.

[0021] <First Embodiment> Hereinafter, a semiconductor device according to the present embodiment will be described.

[0022] In this specification, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. Also, n - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0023] <Regarding the Configuration of the Semiconductor Device> FIG. 1 is a plan view of an SBD-integrated MOSFET which is a semiconductor device according to the present embodiment. The plan view is a view of the semiconductor substrate in a plan view from above, omitting the source electrode, the gate wiring layer, the insulating film, etc. FIG. 2 is a schematic cross-sectional view taken along the cross-section A-A' in FIG. 1.

[0024] In FIG. 1, a separation region 21 is provided that extends in the X direction and the Y direction and has a folding region 221 that folds back in the Y direction. In FIG. 1, a plurality of folding regions 221 are provided, but even if only one folding region 221 is provided, it may be the case.

[0025] In FIG. 2, an n-type drift layer 20 is formed on the upper surface of a low-resistance n-type semiconductor substrate 10. Further, a plurality of p-type well regions 30 are provided in the surface layer portion of the drift layer 20.

[0026] In the surface layer portion of each well region 30, an n-type source region 40 is formed at a position that enters inward from the outer periphery of the well region 30 by a predetermined interval.

[0027] On the side of the source region 40 in the surface layer portion of each well region 30, a low-resistance p-type contact region 35 is formed. Further, an n-type separation region 21 is formed between the well regions 30 that are separated from each other in the surface layer portion of the drift layer 20.

[0028] The n-type impurity concentration of the separation region 21 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0029] On the upper surface of the separation region 21, a Schottky electrode 71 that makes a Schottky connection with the separation region 21 is formed. Here, the Schottky electrode 71 is formed so as to cover at least the separation region 21 in a plan view, that is, it is desirable that the area of the Schottky electrode 71 is larger than the area of the separation region 21.

[0030] The region between the well regions 30 that are separated from each other in the surface layer portion of the drift layer 20 and are different from the separation region 21 is an n-type separation region 22. The separation region 22 has the same width as the width of the separation region 21 or a width wider than the width of the separation region 21. In other words, the separation region 21 has the same width as the width of the separation region 22 or a width narrower than the width of the separation region 22.

[0031] The n-type impurity concentration in the separation region 22 may be the same as that in the drift layer 20, or may be higher or lower than that in the drift layer 20.

[0032] A gate insulating film 50 is formed on the upper surface of the well region 30, the upper surface of the separation region 22 between the well regions 30, and the upper surface of the source region 40 in each well region 30. The gate insulating film 50 is provided in contact with the well region 30 sandwiched between the source region 40 and the drift layer 20.

[0033] A gate electrode 60 is formed in a range overlapping the source region 40 and the well region 30 in a plan view on the upper surface of the gate insulating film 50. The surface layer portion of the well region 30 facing through the gate insulating film 50 below the location where the gate electrode 60 is formed is called the channel region.

[0034] An ohmic electrode 70 is formed on a part of the upper surface of the source region 40 and a part of the upper surface of the contact region 35. And a source electrode 80 is formed covering the ohmic electrode 70 and the Schottky electrode 71.

[0035] The source region 40 can easily transfer electrons through the ohmic electrode 70. The well region 30 can easily transfer holes through the low-resistance contact region 35 and the ohmic electrode 70.

[0036] However, the ohmic electrode 70 is not in contact with the separation region 21. This is to prevent the Schottky junction formed between the separation region 21 and the source electrode 80 from being bypassed by an ohmic contact. Specifically, the separation region 21 and the ohmic electrode 70 are electrically separated by the contact region 35 and the well region 30.

[0037] The interlayer insulating film 55 is formed to cover the gate electrode 60. Then, via the contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50, the source electrode 80 is in contact with the upper surfaces of the ohmic electrode 70, the Schottky electrode 71, and the contact region 35.

[0038] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10.

[0039] As shown in FIG. 1, the well region 30, the contact region 35, and the separation region 22 extend along the direction X and are formed in a stripe shape. Also, the gate electrode 60 in FIG. 2 is formed to extend along the direction X.

[0040] The separation region 21 extends along the direction X and the direction Y which is a direction different from the direction X, and is arranged while repeatedly folding back between the well regions 30 (the folding occurs in the folding region 221). This is defined as being arranged in a meandering shape (zigzag shape).

[0041] When arranging the separation region 21 in a meandering shape, the width of the separation region 21 is made the same as the width of the separation region 22 or narrower than the width of the separation region 22.

[0042] In FIG. 1, the direction X is a direction parallel to the direction in which the well region 30, the contact region 35, and the separation region 22 extend, and the direction Y is a direction orthogonal to the direction X.

[0043] <Regarding the operation of the semiconductor device> Next, the operation of the SBD - embedded MOSFET which is a semiconductor device according to the present embodiment will be described. Hereinafter, a silicon carbide semiconductor device in which the semiconductor material is 4H - type silicon carbide will be described as an example. In this case, the diffusion potential of the pn junction is approximately 2V.

[0044] First, the case of the reflux operation will be described.

[0045] In the reverse flow operation, current tries to flow from the source electrode 80 to the drain electrode 84. Particularly when an off voltage is applied to the gate electrode 60, there is no current path through the channel.

[0046] At this time, since an SBD is formed between the separation region 21 and the Schottky electrode 71, which turns on at a lower voltage than the body diode composed of the well region 30 and the drift layer 20, when the current density is low, all of the reverse flow current flows through the SBD and does not flow through the body diode.

[0047] However, when the current density increases, a voltage exceeding about 2V is generated as the voltage drop occurring at the Schottky interface and the separation region 21, which is applied to the parallel PN junction, and the current conduction of the body diode starts.

[0048] To increase the current density at this time, that is, the maximum unipolar current density, it is effective to increase the n-type concentration of the separation region 21 or widen the width of the separation region 21 in order to reduce the resistance of the separation region 21. However, in either method, the electric field strength applied to the Schottky interface or the PN junction in the off state of the transistor increases.

[0049] Here, when the separation region 21 is arranged in a meandering shape as in the present embodiment, the amount of electrons flowing through the SBD can be increased without increasing the n-type concentration of the separation region 21 and without widening the width of the separation region 21, and the maximum unipolar current density can be increased.

[0050] Also, the smaller the period of the meandering of the separation region 21, the more the amount of electrons flowing through the SBD can be increased, so that the maximum unipolar current density can be further increased.

[0051] Next, the case where the transistor is off will be described.

[0052] When the transistor is in the off state, an electric field tends to concentrate on the PN junction formed by the separation region 21 and the well region 30 and the PN junction formed by the separation region 22 and the well region 30.

[0053] As a method for alleviating the electric field concentration at the PN junction formed by the separation region 21 and the well region 30 and the PN junction formed by the separation region 22 and the well region 30, it is conceivable to narrow the width of the separation region 21 and the width of the separation region 22, respectively. When the width of the separation region 21 and the width of the separation region 22 are narrowed, the potential fluctuations in the separation region 21 and the separation region 22 in the off state of the transistor become smaller respectively. Therefore, the electric field concentration on the PN junction formed by the separation region 21 and the well region 30 and the PN junction formed by the separation region 22 and the well region 30 can be alleviated respectively.

[0054] As shown in FIG. 2, a gate insulating film 50 is formed on the upper surface of the separation region 22, and the gate insulating film 50 shares the voltage applied to the entire device by applying a reverse voltage in the off state of the transistor. By doing so, the electric field applied to the PN junction formed by the separation region 22 and the well region 30 is reduced. For this reason, in the PN junction formed by the separation region 21 and the well region 30 where there is no layer that shares the electric field on the upper surface, a strong electric field tends to concentrate.

[0055] Therefore, if the width of the separation region 21 is made narrower than the width of the separation region 22, the electric field applied to the PN junction formed by the separation region 21 and the well region 30 can be reduced. Therefore, the breakdown of the element in the off state of the transistor can be suppressed.

[0056] For the above reasons, when arranging the separation region 21 in a meandering manner, by making the width of the separation region 21 the same as or narrower than the width of the separation region 22, the electric field concentration on the body diode formed by the separation region 21 and the well region 30 in the off state of the transistor can be suppressed, and the breakdown of the element can be prevented.

[0057] As described above, according to the semiconductor device related to the present embodiment, by suppressing the operation of the body diode during the reflux operation, the maximum unipolar current density can be increased, and the destruction of the element when the transistor is in the off state can be suppressed, and the trade-off relationship between the two can be improved.

[0058] <Regarding the manufacturing method of the semiconductor device> Next, a method for manufacturing an SBD-integrated MOSFET, which is a semiconductor device related to the present embodiment, will be described. Hereinafter, a silicon carbide semiconductor device in which the semiconductor material is 4H-type silicon carbide will be described as an example.

[0059] First, on the upper surface of a semiconductor substrate 10 made of n-type, low-resistance silicon carbide having a (0001) plane with an off-angle on the first main surface and having a 4H polytype, by chemical vapor deposition (CVD method), for example, 1×10 15 cm -3 or more, and 1×10 17 cm -3 or less of impurity concentration, an n-type drift layer 20 made of silicon carbide with a thickness of, for example, 5 μm or more and 50 μm or less is epitaxially grown.

[0060] Next, an implantation mask is formed in a predetermined region on the upper surface of the drift layer 20 using a photoresist or the like, and further, Al (aluminum), which is a p-type impurity, is ion-implanted. At this time, the depth of the Al ion implantation does not exceed the thickness of the drift layer 20, for example, 0.5 μm or more and 3 μm or less. Also, the impurity concentration of the ion-implanted Al has a maximum value at a depth away from the upper surface of the drift layer 20, and the concentration is, for example, 1×10 17 cm -3 or more, and 1×10 19 cm -3 or less, and is higher than the impurity concentration of the drift layer 20. On the other hand, on the upper surface of the drift layer 20, the impurity concentration of the implanted Al is thin, and the concentration is, for example, 1×10 15 cm -3 or more, and 1×1018 cm -3 The following steps are then carried out. Subsequently, the implantation mask is removed. In this step, the region implanted with Al ions becomes the well region 30.

[0061] Next, an implantation mask is formed on the upper surface of the drift layer 20 using a photoresist or the like, and Al with a p-type impurity concentration is ion-implanted. At this time, the depth of Al ion implantation does not exceed the thickness of the drift layer 20, for example, it is 0.5 μm or more and 3 μm or less. Desirably, the implantation depth of Al ion implantation is shallower than that of the well region 30 so that high-concentration implantation defects remain inside the well region 30. Also, the impurity concentration of the implanted Al is, for example, 1×10 19 cm -3 or more and 1×10 21 cm -3 or less, higher than the impurity concentration of the drift layer 20, and lower than the impurity concentration of the well region 30. Subsequently, the implantation mask is removed. By this step, the region implanted with Al ions becomes the contact region 35.

[0062] Next, an implantation mask is formed on the upper surface of the drift layer 20 using a photoresist or the like so that a predetermined location inside the well region 30 is open in plan view. Then, N (nitrogen), which is an n-type impurity, is ion-implanted. The implantation depth of N is shallower than the thickness of the well region 30. Also, the impurity concentration of the implanted N is 1×10 18 cm -3 or more and 1×10 21 cm -3 or less, and exceeds the p-type impurity concentration of the well region 30. In order to reduce the sheet resistance or the contact resistance with the ohmic electrode 70, the impurity concentration of N is preferably higher than 1×10 19 cm -3 . Among the regions implanted with N in this step, the region showing an n-type conductivity type becomes the source region 40.

[0063] Next, an annealing treatment is performed by a heat treatment apparatus (not shown here) in an inert gas atmosphere such as argon (Ar) gas at a temperature of, for example, 1300 °C or higher and 1900 °C or lower for a time of, for example, 30 seconds or longer and 1 hour or shorter. By this annealing treatment, the ion-implanted N and Al are electrically activated.

[0064] Next, using a CVD method, photolithography technology, or the like, a field insulating film (not shown here) made of silicon oxide having a thickness thicker than that of the gate insulating film, for example, 0.5 μm or more and 2 μm or less, is formed on the upper surface of the drift layer 20 in a region other than the active region (that is, a region substantially corresponding to the region where the well region 30 is formed).

[0065] Next, the upper surface of the drift layer 20 not covered by the field insulating film is thermally oxidized to form a silicon oxide film that is the desired gate insulating film 50. Subsequently, a polycrystalline silicon film having conductivity is formed on the upper surface of the gate insulating film 50 and the upper surface of the field insulating film by a reduced-pressure CVD method, and further, a gate electrode 60 is formed by patterning this.

[0066] Next, an interlayer insulating film 55 made of silicon oxide is formed by a reduced-pressure CVD method. Subsequently, a contact hole 90 that penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the contact region 35 and the source region 40 in the active region is formed.

[0067] Next, after forming a metal film mainly composed of Ni by a sputtering method or the like, heat treatment is performed at a temperature of, for example, 600 °C or higher and 1100 °C or lower, and the metal film mainly composed of Ni is reacted with the silicon carbide layer in the contact hole 90 to form a silicide between the silicon carbide layer and the metal film.

[0068] Subsequently, the remaining metal film other than the silicide formed by the above reaction is removed by wet etching. Thereby, an ohmic electrode 70 is formed.

[0069] Subsequently, a metal film mainly composed of Ni is formed on the lower surface (second main surface) of the semiconductor substrate 10, and further heat treatment is performed to form a back surface ohmic electrode (not shown here) on the lower surface side of the semiconductor substrate 10.

[0070] Next, using patterning with a photoresist or the like, the interlayer insulating film 55 and the gate insulating film 50 on the upper surface of the separation region 21 are removed. As a removal method, wet etching that does not damage the surface of the silicon carbide layer serving as the Schottky interface is used. After the wet etching, if a photoresist is used, it is removed.

[0071] Subsequently, a metal film serving as a Schottky electrode is deposited by a sputtering method or the like, and using patterning with a photoresist or the like, a Schottky electrode 71 is formed on the upper surface of the separation region 21 in the contact hole 90. The material of the Schottky electrode 71 may be, for example, Ti, Mo, or the like.

[0072] Next, a wiring metal such as Al is formed on the upper surface of the drift layer 20 on which the above Schottky electrode 71 is formed by a sputtering method or an evaporation method. Then, by processing into a predetermined shape by photolithography technology, an ohmic electrode 70 on the source side, a source electrode 80 in contact with the Schottky electrode 71, a gate pad (not shown here) in contact with the gate electrode 60, and a gate wiring (not shown here) are formed.

[0073] Furthermore, if a drain electrode 84, which is a metal film, is formed on the lower surface of the back surface ohmic electrode (not shown here) formed on the lower surface of the semiconductor substrate 10, the semiconductor device shown in FIGS. 1 and 2 is completed.

[0074] In addition, in the present embodiment, an example in which each ion implantation is performed in a predetermined order is shown, but the order of ion implantation may be appropriately changed. Also, the formation order of the back surface ohmic electrode on the lower surface of the semiconductor substrate 10, the ohmic electrode 70 on the upper surface of the semiconductor substrate 10, and the Schottky electrode 71 may be appropriately changed.

[0075] In addition, in this embodiment, an example in which the Schottky electrode 71 is formed only on the upper surface of the separation region 21 and the upper surface of the well region 30 has been shown. However, the Schottky electrode 71 may be formed on the upper surface of the ohmic electrode 70 or the upper surface of the interlayer insulating film 55.

[0076] In addition, in this embodiment, a planar type in which the channel or the Schottky electrode 71 is formed parallel to the main surface of the semiconductor substrate 10 has been assumed. However, a trench type in which the channel or the Schottky electrode 71 is formed obliquely or perpendicularly to the main surface of the semiconductor substrate 10 may be used. That is, a trench that penetrates the well region 30 and reaches the drift layer 20 may be provided, and a trench gate having a gate insulating film 50 and a gate electrode 60 formed inside the trench may be provided.

[0077] FIG. 12 is a plan view showing an example of the configuration of an active region of a trench-type SBD-integrated SiC-MOSFET, which is a semiconductor device according to this embodiment. FIG. 13 is a schematic cross-sectional view taken along the line A-A' in FIG. 12.

[0078] In FIGS. 12 and 13, a drift layer 20 made of n-type low-resistance silicon carbide is formed on the upper surface of a semiconductor substrate 10 made of n-type silicon carbide. A well region 30 made of p-type silicon carbide is formed in the surface layer portion of the drift layer 20.

[0079] A source region 40 made of n-type silicon carbide is formed in a part of the surface layer portion of the well region 30. A low-resistance p-type contact region 35 is formed in a region adjacent to the source region 40 in the surface layer portion of the well region 30.

[0080] In addition, in the active region, a gate trench 302 is formed that penetrates the source region 40 and the well region 30 and reaches the drift layer 20.

[0081] Also, a Schottky trench 303 is formed that penetrates the source region 40 and the well region 30 and reaches the drift layer 20 at a location different from the location where the gate trench 302 is formed.

[0082] The gate trench 302 and the Schottky trench 303 are arranged to extend alternately and parallel to each other. Also, the gate trench 302 and the Schottky trench 303 may be formed with the same width, or their widths may be different.

[0083] In the gate trench 302, a gate electrode 60A is formed surrounded by a gate insulating film 50A made of silicon oxide. The gate electrode 60A is composed of low-resistance polycrystalline silicon with a high impurity concentration. An interlayer insulating film 55 made of silicon oxide is formed on the upper surface of the gate electrode 60A.

[0084] In the Schottky trench 303, a source electrode 80 is formed surrounded by a Schottky electrode 71A. The Schottky electrode 71A is formed in contact with the drift layer 20 and makes a Schottky connection with the drift layer 20. Also, a p-type protection region 32 is formed in the drift layer 20 in contact with the bottom surface of the gate trench 302. Also, a p-type protection region 33 is formed in the drift layer 20 in contact with the bottom surface of the Schottky trench 303. The depths of the protection region 32 and the protection region 33 may be the same or different. Also, the impurity concentrations of the protection region 32 and the protection region 33 may be the same or different.

[0085] An ohmic electrode 70 is formed on a part of the upper surface of the source region 40 and a part of the upper surface of the contact region 35. Then, a source electrode 80 is formed covering the ohmic electrode 70 and the Schottky electrode 71A.

[0086] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10.

[0087] The operation of a trench-type SBD-integrated SiC-MOSFET, which is a semiconductor device according to this embodiment, will be described below.

[0088] First, the case of the reflux operation will be described.

[0089] In the reflux operation, similar to the case of a planar-type SBD-integrated SiC-MOSFET, when the current density is low, all of the reflux current flows through the SBD and does not flow through the body current. On the other hand, when the current density is high, a voltage exceeding about 2V is generated as a voltage drop occurring in the separation region 34, which is the region sandwiched between the Schottky interface and the Schottky trench 303 and the gate trench 302, and this is applied to the PN junction connected in parallel, and the conduction of the body diode is started.

[0090] In order to increase the current density in this case, that is, the maximum unipolar current density, in order to reduce the resistance of the separation region 34, it is effective to increase the n-type concentration of the separation region 34 or deepen the depth of the separation region 34 (that is, deepen the depth of the gate trench 302 and the Schottky trench 303).

[0091] However, in any method, the electric field strength applied to the Schottky interface or the PN junction in the off state of the transistor increases.

[0092] Here, when the Schottky trench 303 is arranged in a meandering manner as in this embodiment, the separation region 34 is also arranged in a meandering manner accordingly. Here, the region where the meandering Schottky trench 303 in a zigzag shape turns back in the direction Y is defined as the turning-back region 304. In FIG. 12, a plurality of turning-back regions 304 are provided at regular intervals, but the intervals at which the turning-back regions 304 are provided do not have to be constant.

[0093] In such a case, without increasing the n-type concentration of the separation region 34 and without increasing the depth of the separation region 34 (i.e., without increasing the depths of the gate trench 302 and the Schottky trench 303), the amount of electrons flowing through the SBD can be increased, and the maximum unipolar current density can be increased.

[0094] Next, the case where the transistor is off will be described.

[0095] In the off state of the transistor, an electric field is likely to concentrate on the PN junction formed by the protection region 32 and the drift layer 20 and the PN junction formed by the protection region 33 and the drift layer 20.

[0096] As a method for alleviating the electric field concentration at the PN junction formed by the protection region 32 and the drift layer 20 and the PN junction formed by the protection region 33 and the drift layer 20, it is conceivable to make the depth of the separation region 34 shallow (i.e., make the depths of the gate trench 302 and the Schottky trench 303 shallow respectively). When the depths of the gate trench 302 and the Schottky trench 303 are made shallow, the potential fluctuation in the separation region 34 in the off state of the transistor becomes small. Therefore, the electric field concentration on the PN junction formed by the protection region 32 and the drift layer 20 and the PN junction formed by the protection region 33 and the drift layer 20 can be alleviated respectively.

[0097] As shown in FIG. 13, a gate insulating film 50A is formed on the upper part of the protection region 32, and the gate insulating film 50A shares the voltage applied to the entire device by applying a reverse voltage in the off state of the transistor. By doing so, the electric field applied to the PN junction formed by the protection region 32 and the drift layer 20 is reduced. For this reason, in the PN junction formed by the protection region 33 and the drift layer 20 where there is no layer for sharing the electric field in the upper part, a strong electric field is likely to concentrate.

[0098] Therefore, by making the depth of the Schottky trench 303 the same as or shallower than the depth of the gate trench 302, the electric field applied to the PN junction formed by the protection region 33 and the drift layer 20 can be reduced. Therefore, destruction of the element in the off state of the transistor can be suppressed.

[0099] In addition, when the depth of the Schottky trench 303 is made the same as or shallower than the depth of the gate trench 302, the electric field applied to the Schottky electrode 71 can also be reduced. Therefore, the leakage current in the off state of the transistor can be reduced.

[0100] For the above reasons, when arranging the Schottky trench 303 in a meandering manner, by forming the depth of the Schottky trench 303 to be the same as or shallower than the depth of the gate trench 302, the electric field concentration on the body diode formed by the protection region 33 and the drift layer 20 in the off state of the transistor can be suppressed, and destruction of the element can be prevented. In addition, the electric field applied to the Schottky electrode 71 can be reduced to suppress the leakage current.

[0101] As described above, according to the semiconductor device according to the present embodiment, by suppressing the operation of the body diode during the reflux operation, the maximum unipolar current density can be increased, and destruction of the element in the off state of the transistor can be suppressed. Furthermore, the leakage current can be reduced, and the trade-off relationship between the two can be improved.

[0102] Note that when forming the well region 30 by implanting Al ions, the portion of the separation region 21 is covered with a photoresist or the like for ion implantation. However, the photoresist may fall down at this time. As the width of the separation region 21 becomes narrower, the dimensions of the photoresist used also become thinner, so the photoresist is more likely to fall down.

[0103] On the other hand, in the present embodiment, since the separation region 21 is arranged in a meandering shape, the photoresist used during Al ion implantation is also formed in a meandering shape. In this case, the photoresist is less likely to fall over than when the photoresist is formed linearly, and the occurrence of pattern defects can be suppressed.

[0104] FIG. 3 is a schematic diagram showing the structure when the plan view shown in FIG. 1 is continuously arranged repeatedly in the X direction and the Y direction. In FIG. 3, for convenience, only the separation region 21, the well region 30, and the separation region 22 are shown. In the following, the structure of a planar SBD-embedded SiC-MOSFET is mainly assumed, but it can be appropriately applied by replacing it with the trench-type SBD-embedded SiC-MOSFET shown in FIGS. 12 and 13 above. In that case, the meandering separation region 21 is appropriately read as the Schottky trench 303.

[0105] In FIG. 3, a p-type well region 30 that substantially corresponds to the MOSFET in plan view is formed while sandwiching an n-type separation region 21 that substantially corresponds to the SBD in plan view in the Y direction. Then, the bands extending in the X direction of the well region 30 sandwiching the separation region 21 are repeatedly arranged in a stripe shape in the Y direction. Such an arrangement is called a "stripe type".

[0106] In the above stripe type, when the plane orientation of the upper surface (the first main surface) of the semiconductor substrate 10 is a (0001) plane having an off-angle in the <11-20> direction, the stripe-shaped well region 30 extending in the X direction may be formed parallel to the <11-20> direction (that is, the off direction), or may be formed parallel to the direction orthogonal to the off direction.

[0107] Also, if the region where the SBD-integrated MOSFET as shown in FIG. 3 is formed is called the active region, when the period in which the separation region 21 extends in the X direction and the Y direction is constant, that is, when the period of the meandering is constant, the maximum unipolar current density in the active region within the semiconductor chip becomes uniform, and the performance of the device can be improved. However, the period of the meandering may be appropriately changed depending on the formation position of the active region within the semiconductor chip.

[0108] FIG. 4 is a plan view of the end portion of the active region of a Schottky diode (SBD)-integrated MOSFET, which is a semiconductor device according to the present embodiment. In FIG. 4, an active region C where the period in which the separation region 21 meanders is constant, a vicinity region D of the active region end where the period in which the separation region 21 meanders is not constant, and an end portion B (active region end) of the active region are shown. The vicinity region D of the active region end is arranged so as to surround the active region C. Further, the end portion B of the active region is arranged so as to surround the vicinity region D of the active region end.

[0109] At the end portion B of the active region, the current density of the SBD tends to decrease. For this reason, as shown in FIG. 4, although the period in which the separation region 21 meanders is constant in the active region C, by increasing the number of meanders of the separation region 21 (that is, shortening the period of meandering) in the vicinity region D of the active region end, the current density of the SBD in the vicinity region D of the active region end can be increased. Therefore, it is possible to suppress a decrease in the maximum unipolar current that may occur at the end portion B of the active region during the reflux operation, and improve the performance of the device.

[0110] In FIG. 1, the separation region 21 is shown as meandering by including a folded-back region 221 having a portion extending along the X direction and a portion extending along the Y direction orthogonal thereto. However, the separation region 21 only needs to have a component extending along the X direction and a component extending along the Y direction, respectively.

[0111] That is, as shown in FIG. 5, the separation region 21A includes a folded region 221A having portions extending in two directions inclined with respect to the direction X, and thus may be arranged while being repeatedly bent. Further, there is no limitation on the direction in which the separation region extends, and it may extend in three or more directions. Note that FIG. 5 is a plan view showing a modified example of an SBD-embedded MOSFET, which is a semiconductor device according to the present embodiment.

[0112] <Regarding the modified example> FIG. 6 is a plan view showing a modified example of an SBD-embedded MOSFET, which is a semiconductor device according to the present embodiment. When the separation region 21B is bent, it may be bent in a curved shape in the folded region 221B as shown in FIG. 6. When the separation region 21B is curved in a plan view, the change in the width of the separation region 21B when it is bent (that is, the width in the direction Y, the width in the direction inclined with respect to the directions X and Y, and the change in the width in the direction X) becomes small. Therefore, the electric field concentration at the PN junction formed by the separation region 21B and the well region 30 in the off state of the transistor is likely to be alleviated.

[0113] Further, when the separation region 21B is curved, there is no limitation on its curvature, and as long as its width is equal to or less than the width of the separation region 22, its width does not have to be constant. When the width of the separation region 21B is constant, local electric field concentration in the off state of the transistor is less likely to occur, so the element is less likely to be destroyed.

[0114] Further, when the region where the separation region 21B is bent is formed in a curved shape, the corner portions become curved portions, and the electric field concentration in the region is alleviated.

[0115] <Second Embodiment> A semiconductor device according to the present embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiment and illustrated, and detailed descriptions thereof will be omitted as appropriate.

[0116] <Regarding the configuration of the semiconductor device> FIG. 7 is a plan view of a MOSFET with a built-in Schottky diode (SBD), which is a semiconductor device according to the present embodiment.

[0117] The separation region 21C includes a folded-back region 221C having portions extending in two directions (directions inclined with respect to the direction Y) inclined with respect to the direction X, and is arranged while repeatedly bending in a zigzag manner between the well regions 30. Note that, unlike the separation region 21A, in the separation region 21C, there is no portion that is only a component in the direction Y (that is, the portion between the folded-back regions 221A).

[0118] Since the pattern of the separation region 21C in the present embodiment is simple, pattern collapse is less likely to occur when forming the pattern with a resist.

[0119] In addition, as the period in which the separation region 21C bends in a zigzag shape becomes smaller, the area of the SBD increases, so the current conduction ability of the SBD improves and the maximum unipolar current density increases.

[0120] In addition, the period in which the separation region 21C bends in a zigzag shape or the width of the separation region 21 does not necessarily have to be constant, and it can be applied to a stripe type or a lattice type (an arrangement in which the separation regions 22 are arranged in a lattice shape in a plan view).

[0121] Note that when the separation region 21C bends, it may bend in a curved manner. Also, there is no limit to the number of times the separation region 21C bends.

[0122] <Regarding a modification example> FIG. 8 is a plan view of a modification example of a MOSFET with a built-in Schottky diode (SBD), which is a semiconductor device according to the present embodiment.

[0123] In FIG. 8, the separation region 22C includes a folded-back region 222C having portions extending in two directions inclined with respect to the direction X with the same period as the period in which the separation region 21C zigzags (i.e., the period in which the folded-back region 221C is provided), and is arranged while being repeatedly folded. In accordance with these, the shapes of the well region 30C, the contact region 35C, and the source region 40C in plan view are also changed.

[0124] By zigzagging and arranging the separation region 22C so that the folding period of the separation region 22C (i.e., the period in which the folded-back region 222C is provided) coincides with the folding period of the separation region 21C (i.e., the period in which the folded-back region 221C is provided), the separation region 21C and the separation region 22C extend in parallel in the direction X, and the cell pitch in the direction Y in FIG. 8 can be narrowed. Therefore, miniaturization of the semiconductor chip becomes possible.

[0125] Note that the period or the width in which the separation region 22C zigzags does not have to be constant. Also, when the separation region 21C and the separation region 22C are folded, they may be folded in a curved manner. Also, there is no limit to the number of times the separation region 21C is folded.

[0126] <Third Embodiment> A semiconductor device according to this embodiment will be described. In the following description, the same reference numerals are given to and illustrated for the components similar to those described in the above-described embodiments, and the detailed description thereof will be omitted as appropriate.

[0127] <Regarding the Configuration of the Semiconductor Device> The cell structure is not limited to the stripe type, and may be, for example, a lattice type. FIG. 9 is a plan view of a MOSFET incorporating a Schottky diode (SBD), which is a semiconductor device according to the present embodiment. In the first and second embodiments, the spaced-apart regions 21 arranged to be bent are repeatedly arranged side by side in one direction (direction Y) in a plan view. In the present embodiment, lattice-shaped cells including the spaced-apart regions 21 are repeatedly arranged while being spaced apart from each other in the directions X and Y, respectively. Such a structure is called a "lattice type".

[0128] In FIG. 9, the spaced-apart region 21D arranged to be bent is provided with a folded-back region 221D having a portion extending along the direction X and a portion extending along the direction Y orthogonal thereto, and is repeatedly arranged while being spaced apart from each other in the directions X and Y. The well region 30D is repeatedly arranged while being spaced apart from each other in the directions X and Y while sandwiching the spaced-apart region 21D. Further, the contact region 35D is repeatedly arranged while being spaced apart from each other in the directions X and Y while surrounding the well region 30D. Further, the source region 40D is repeatedly arranged while being spaced apart from each other in the directions X and Y while surrounding the contact region 35D. Further, the well region 30D is repeatedly arranged while being spaced apart from each other in the directions X and Y while surrounding the source region 40D. Further, the spaced-apart region 22D is arranged to extend in the directions X and Y while partitioning the well region 30D in a lattice shape.

[0129] FIG. 10 is a schematic diagram showing an example of the arrangement of cells in the lattice type. In FIG. 10, only the spaced-apart region 21D, the well region 30D, and the spaced-apart region 22D are shown.

[0130] In the lattice type, a unit cell region composed of an n-type spaced-apart region 21D substantially corresponding to the SBD and a p-type well region 30D substantially corresponding to the MOSFET is partitioned by the spaced-apart region 22D and repeatedly arranged in the directions X and Y in a plan view.

[0131] The separation region 21D is repeatedly folded and arranged as in the first and second embodiments. And the well region 30D is arranged so as to surround the separation region 21D. There is no limit to the number of bends of the separation region 21D in the unit cell region, and it may be bent any number of times. Also, depending on the formation position within the semiconductor chip, the bending period or number of times of the separation region 21D in each unit cell region may be appropriately changed.

[0132] <Fourth Embodiment> The power conversion device according to the present embodiment will be described. In the following description, components similar to those described in the above-described embodiments will be denoted by the same reference numerals and illustrated, and detailed descriptions thereof will be omitted as appropriate.

[0133] <Regarding the Configuration of the Power Conversion Device> This embodiment applies the semiconductor device according to the first, second, and third embodiments to a power conversion device. Although the present technology is not limited to a specific power conversion device, hereinafter, as a fourth embodiment, a case where the present technology is applied to a three-phase inverter will be described.

[0134] FIG. 11 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

[0135] The power conversion system illustrated in FIG. 11 includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be configured by various things. For example, it can be configured by a DC system, a solar cell, or a storage battery, or it may be configured by a rectifier circuit or an AC / DC converter connected to an AC system. Also, the power source 100 may be configured by a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0136] The power conversion device 200 is a three-phase inverter connected between a power source 100 and a load 300. It converts the DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in FIG. 11 for example, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals for driving the respective switching elements of the main conversion circuit 201, and a control circuit 203 that outputs control signals for controlling the drive circuit 202 to the drive circuit 202.

[0137] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application and is a motor mounted on various electrical devices. For example, it is used as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

[0138] Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown here). By switching the switching elements, the DC power supplied from the power source 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201. The main conversion circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to the respective switching elements. A semiconductor device according to any one of the first embodiment, the second embodiment, and the third embodiment is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs of two to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0139] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with the control signals from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements. When maintaining the switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0140] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired amount of power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (on-time) during which each switching element of the main conversion circuit 201 should be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each point in time. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with this control signal.

[0141] In the power conversion device 200 according to the present embodiment, by applying the semiconductor devices according to the first embodiment, the second embodiment, and the third embodiment as the switching elements of the main conversion circuit 201, a power conversion device 200 with low loss and enhanced high-speed switching reliability can be realized.

[0142] In this embodiment, an example of applying this technology to a two-level three-phase inverter has been described. However, this technology is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device 200 is used, but it may also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, this technology may be applied to a single-phase inverter. Also, when supplying power to a DC load or the like, this technology can also be applied to a DC / DC converter or an AC / DC converter.

[0143] Furthermore, the power conversion device to which this technology is applied is not limited to the case where the above load is an electric motor. For example, it can also be used as a power supply device for a discharge machining machine, a laser processing machine, an induction heating cooker, or a non-contact power feeding system. Moreover, it can also be used as a power conditioner for a solar power generation system or a power storage system.

[0144] <Regarding the effects caused by the multiple embodiments described above> Next, examples of the effects caused by the multiple embodiments described above are shown. In the following description, the effects are described based on the specific configurations exemplified in the multiple embodiments described above. However, within the range where the same effects occur, they may be replaced with other specific configurations exemplified in this specification. That is, hereinafter, for convenience, only one of the corresponding specific configurations may be described representatively, but the specifically described representative configuration may be replaced with other corresponding specific configurations.

[0145] Also, such replacement may be made across multiple embodiments. That is, even when the respective configurations exemplified in different embodiments are combined to produce the same effects, it may be the case.

[0146] According to the embodiment described above, the semiconductor device includes an n-type drift layer 20, a plurality of p-type well regions 30 (or well regions 30C, 30D), an n-type source region 40 (or source regions 40, 40D), an n-type first separation region, an n-type second separation region, a gate insulating film 50, a gate electrode 60, a Schottky electrode 71, an ohmic electrode 70, and a source electrode 80. Here, the first separation region corresponds to at least one of, for example, separation regions 21, 21A, 21B, 21C, 21D, etc. Also, the second separation region corresponds to at least one of, for example, separation regions 22, 22C, 22D, etc. The drift layer 20 is provided on the upper surface of an n-type semiconductor substrate 10. The well regions 30 are provided separately from each other on the surface layer of the drift layer 20. The source region 40 is provided on the surface layer of the well region 30. The separation region 21 is a region between a plurality of well regions in the surface layer of the drift layer 20. The separation region 22 is a region between a plurality of well regions in the surface layer of the drift layer 20 and is a region different from the separation region 21. The gate insulating film 50 is provided in contact with the well region 30 sandwiched between the source region 40 and the drift layer 20. The gate electrode 60 is provided in contact with the gate insulating film 50. The Schottky electrode 71 is provided on the upper surface of the separation region 21 and forms a Schottky junction with the separation region 21. The ohmic electrode 70 is provided on the upper surface of the source region 40. The source electrode 80 is provided in contact with the Schottky electrode 71 and the ohmic electrode 70. And the separation region 21 extends in a first direction and a second direction different from the first direction in a plan view. Here, the first direction corresponds to, for example, direction X, etc. Also, the second direction corresponds to, for example, direction Y, etc. Also, the separation region 21 has at least one first folding region that folds back in the direction Y. Here, the first folding region corresponds to at least one of, for example, folding regions 221, 221A, 221B, 221C, 221D, etc.Further, the separation region 22 extends at least in the X direction in a plan view. Also, the width of the separation region 22 in the Y direction is equal to or greater than the width of the separation region 21 in the X direction or the Y direction.

[0147] According to such a configuration, by providing the folding region 221 in the separation region 21, it is possible to increase the amount of electrons flowing through the SBD without increasing the n-type concentration of the separation region 21 and without widening the width of the separation region 21, and to increase the maximum unipolar current density. On the other hand, by making the width of the separation region 21 narrower than the width of the separation region 22, the electric field applied to the PN junction formed between the separation region 21 and the well region 30 can be reduced. Therefore, while relaxing the electric field applied to the body diode in the off state of the transistor, the maximum unipolar current density can be increased.

[0148] In addition, when other configurations exemplified in the present specification are appropriately added to the above configuration, that is, even when other configurations in the present specification not mentioned as the above configuration are appropriately added, the same effects can be obtained.

[0149] Also, according to the embodiment described above, a plurality of folding regions 221 of the separation region 21 are provided. According to such a configuration, the separation region 21 can be formed in a meandering shape by repeatedly providing the folding region 221. Therefore, it is possible to increase the amount of electrons flowing through the SBD without increasing the n-type concentration of the separation region 21 and without widening the width of the separation region 21, and to increase the maximum unipolar current density.

[0150] Also, according to the embodiment described above, the folding regions 221 of the separation region 21 are provided at regular distance intervals. According to such a configuration, by making the period (distance interval) constant when the separation region 21 meanders, the maximum unipolar current density in the active region within the semiconductor chip becomes uniform, and the performance of the element can be improved. Also, through various calculations, the effect of improving the maximum unipolar current density by this structure was confirmed.

[0151] Further, according to the embodiment described above, the separation region 21 is zigzag-shaped in plan view. With such a configuration, the separation region 21 can be made zigzag-shaped by the repeatedly provided folding regions 221. Therefore, the amount of electrons flowing through the SBD can be increased without increasing the n-type concentration of the separation region 21 and without widening the width of the separation region 21, and the maximum unipolar current density can be increased. Further, since the separation region 21 is arranged in a meandering zigzag shape, the photoresist used during Al ion implantation is also formed in a meandering shape. In this case, the photoresist is less likely to fall over than when the photoresist is formed linearly, and the occurrence of pattern defects can be suppressed.

[0152] Further, according to the embodiment described above, the separation region 22C extends in the direction Y in plan view. And the separation region 22C has at least one second folding region that folds in the direction Y. Here, the second folding region corresponds to, for example, the folding region 222C or the like. By providing the folding region 221C and the folding region 222C corresponding to each other, the separation region 21C and the separation region 22C extend in parallel in the direction X. With such a configuration, the separation region 21C and the separation region 22C extend in parallel in the direction X, and the cell pitch in the direction Y in FIG. 8 can be narrowed. Therefore, miniaturization of the semiconductor chip becomes possible.

[0153] Further, according to the embodiment described above, the direction X is orthogonal to the direction Y. And the well region 30 (or the well region 30C) and the gate electrode 60 are stripe-shaped extending in the direction X in plan view. With such a configuration, since the meandering separation regions 21 can be arranged continuously in the direction X, it is easier to equalize the SBD current density in the semiconductor chip than when arranged intermittently in the direction X. Further, with such a configuration, since the meandering shapes extend in directions orthogonal to each other, the layout is easy.

[0154] Further, according to the embodiment described above, the folded-back region 221B has a curved shape in plan view. With such a configuration, the change in the width of the separated region 21B when the separated region 21B bends is reduced. Therefore, the electric field concentration at the PN junction formed between the separated region 21B and the well region 30 when the transistor is in the off state is likely to be alleviated.

[0155] Further, according to the embodiment described above, the semiconductor device includes a trench that penetrates the well region 30 and reaches the drift layer 20. And the gate insulating film 50 is formed to cover the side surface of the well region 30 sandwiched between the source region 40 and the drift layer 20 in the trench. Also, the gate electrode 60 is formed surrounded by the gate insulating film 50 in the trench. With such a configuration, the technology described in the above embodiment can be applied not only to planar gate type MOSFETs but also to trench gate type MOSFETs.

[0156] Further, according to the embodiment described above, the power conversion device has the above semiconductor device, and a main conversion circuit 201 that converts the input power and outputs it, a drive circuit 202 that outputs a drive signal for driving the semiconductor device to the semiconductor device, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202. With such a configuration, by using the above semiconductor device, it is possible to increase the maximum unipolar current density while alleviating the electric field applied to the body diode in the off state of the transistor.

[0157] <Regarding the modifications of the above-described multiple embodiments> In the multiple embodiments described above, the material, material, dimensions, shape, relative arrangement relationship, or implementation conditions of each component may be described, but these are all examples in all aspects and are not limiting.

[0158] Therefore, numerous variations and equivalents that are not illustrated by examples are envisioned within the scope of the technology disclosed in the present specification. For example, when modifying, adding, or omitting at least one component, or even when extracting at least one component in at least one embodiment and combining it with components in other embodiments, it shall be included.

[0159] Also, in at least one of the embodiments described above, when a material name or the like is described without specific designation, as long as there is no contradiction, it shall be assumed that other additives are included in the material, for example, alloys and the like are included.

[0160] Also, as long as there is no contradiction, when it is described in the embodiments described above that "one" component is provided, the component may be provided with "one or more".

[0161] Furthermore, each component in the embodiments described above is a conceptual unit, and within the scope of the technology disclosed in the present specification, it shall include cases where one component consists of multiple structures, cases where one component corresponds to a part of a certain structure, and even cases where multiple components are provided in one structure.

[0162] Also, each component in the embodiments described above shall include structures having other structures or shapes as long as they perform the same function.

[0163] Also, the descriptions in the present specification are referenced for all purposes related to this technology, and none of them are recognized as prior art.

Explanation of Reference Signs

[0164] 10 Semiconductor substrate, 20 Drift layer, 21 Spacing region, 21A Spacing region, 21B Spacing region, 21C Spacing region, 21D Spacing region, 22 Spacing region, 22C Spacing region, 22D Spacing region, 30 Well region, 30C Well region, 30D Well region, 32 Protection region, 33 Protection region, 34 Spacing region, 40 Source region, 40C Source region, 40D Source region, 50 Gate insulating film, 50A Gate insulating film, 60 Gate electrode, 60A Gate electrode, 70 Ohmic electrode, 71 Schottky electrode, 71A Schottky electrode, 80 Source electrode, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 221 Folding region, 221A Folding region, 221B Folding region, 221C Folding region, 221D Folding region, 222C Folding region, 302 Gate trench, 303 Schottky trench, 304 Folding region.

Claims

1. A first conductivity type drift layer provided on the upper surface of a semiconductor substrate of a first conductivity type, a plurality of second conductivity type well regions provided separately from each other on the surface layer of the drift layer, a first conductivity type source region provided on the surface layer of the well region, a first conductivity type first separation region which is a region between the plurality of well regions on the surface layer of the drift layer, a first conductivity type second separation region which is a region between the plurality of well regions on the surface layer of the drift layer and is a region different from the first separation region, a gate insulating film provided in contact with the well region sandwiched between the source region and the drift layer, a gate electrode provided in contact with the gate insulating film, a Schottky electrode provided on the upper surface of the first separation region and forming a Schottky junction with the first separation region, an ohmic electrode provided on the upper surface of the source region, and a source electrode provided in contact with the Schottky electrode and the ohmic electrode, wherein the first separation region extends in a first direction and a second direction different from the first direction in a plan view, the first separation region has at least one first folding region that folds back in the second direction, the second separation region extends at least in the first direction in a plan view, and the width of the second separation region in the second direction is equal to or greater than the width of the first separation region in the first direction or the second direction, a semiconductor device.

2. The semiconductor device according to claim 1, wherein a plurality of the first folding regions of the first separation region are provided, a semiconductor device.

3. The semiconductor device according to claim 2, wherein the first folding regions of the first separation region are provided at regular intervals, a semiconductor device.

4. The semiconductor device according to claim 2 or 3, wherein the first separation region has a zigzag shape in a plan view, a semiconductor device.

5. The semiconductor device according to any one of claims 1 to 3, wherein the second separation region extends in the second direction in a plan view, the second separation region has at least one second folding region that folds back in the second direction, and by providing the first folding region and the second folding region corresponding to each other, the first separation region and the second separation region extend in parallel in the first direction, a semiconductor device.

6. A first conductivity type drift layer provided on the upper surface of a semiconductor substrate of the first conductivity type, a plurality of second conductivity type well regions provided separately from each other on the surface layer of the drift layer, a first conductivity type source region provided on the surface layer of the well region, a first trench provided to reach from the upper surface of the well region into the drift layer, a second trench provided to reach from the upper surface of the well region into the drift layer and at a position different from that of the first trench, a separation region sandwiched between the first trench and the second trench, a gate insulating film covering the side surface of the well region sandwiched between the source region and the drift layer in the second trench, a gate electrode formed surrounded by the gate insulating film in the second trench, a Schottky electrode that forms a Schottky junction with the separation region in the first trench, an ohmic electrode provided on the upper surface of the source region, and a source electrode provided in contact with the Schottky electrode and the ohmic electrode. The first trench extends in a first direction and a second direction different from the first direction in a plan view, the first trench has at least one first folding region that folds back in the second direction, the second trench extends at least in the first direction in a plan view, a depth of the second trench from the upper surface of the well region is equal to or greater than a depth of the first trench from the upper surface of the well region, a semiconductor device.

7. The semiconductor device according to claim 6, wherein a plurality of the first folding regions of the first trench are provided. a semiconductor device.

8. The semiconductor device according to claim 7, wherein the first folding regions of the first trench are provided at regular intervals. a semiconductor device.

9. The semiconductor device according to claim 7 or 8, wherein the first trench has a zigzag shape in a plan view. a semiconductor device.

10. The semiconductor device according to any one of claims 6 to 8, wherein the second trench extends in the second direction in a plan view, the second trench has at least one second folding region that folds back in the second direction, and the first trench and the second trench extend in parallel in the first direction by providing the first folding region and the second folding region corresponding to each other. Semiconductor device.

11. The semiconductor device according to any one of Claims 1 to 3 and 6 to 8, wherein the first direction is orthogonal to the second direction, and the well region and the gate electrode are in a stripe shape extending in the first direction in a plan view. Semiconductor device.

12. The semiconductor device according to any one of Claims 1 to 3 and 6 to 8, wherein the first folded-back region is in a curved shape in a plan view. Semiconductor device.

13. having the semiconductor device according to any one of Claims 1 to 3 and 6 to 8, and a main conversion circuit that converts and outputs input power, a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device, and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. Power conversion device.

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