Method of manufacturing a semiconductor device

Abstract

Provided is a semiconductor device having a large storage capacity. The semiconductor device comprises: an oxide disposed on a substrate; a plurality of first electrical conductors on the oxide; a first insulator which is disposed on the plurality of first electrical conductors and has a plurality of openings formed overlapping a region between the plurality of first electrical conductors; a plurality of second insulators respectively disposed in the plurality of openings; a plurality of charge holding layers respectively disposed on the plurality of second insulators; a plurality of third insulators respectively disposed on the plurality of charge holding layers; and a plurality of second electrical conductors respectively disposed on the plurality of third insulators.

Description

Semiconductor device and method for fabricating a semiconductor device.

[0001] One aspect of the present invention relates to transistors, semiconductor devices, and electronic devices. Alternatively, one aspect of the present invention relates to a method for manufacturing semiconductor devices. Alternatively, one aspect of the present invention relates to semiconductor wafers and modules.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0004] In recent years, the development of semiconductor devices has progressed significantly, with particularly remarkable advancements in LSIs, CPUs, and memory. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) separated from a semiconductor wafer, and on which electrodes, which are connection terminals, are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, a low-power CPU that takes advantage of the low leakage current characteristic of oxide semiconductor transistors has been disclosed (see Patent Document 1). Also, for example, a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of oxide semiconductor transistors has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits.

[0009] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0010] One aspect of the present invention aims to provide a semiconductor device with a large memory capacity. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with little variation in transistor characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large field-effect mobility. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a small off-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Alternatively, one embodiment of the present invention aims to provide a novel semiconductor device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a semiconductor device comprising: an oxide disposed on a substrate; a plurality of first conductors disposed on the oxide; a first insulator disposed on the plurality of first conductors, with a plurality of openings formed on each of the first conductors superimposed in the regions between the plurality of first conductors; a plurality of second insulators disposed in each of the plurality of openings; a plurality of charge-holding layers disposed on each of the plurality of second insulators; a plurality of third insulators disposed on each of the plurality of charge-holding layers; and a plurality of second conductors disposed on each of the plurality of third insulators.

[0013] In the above, it is preferable that the plurality of first conductors are arranged linearly parallel to the upper surface of the oxide.

[0014] Furthermore, in the above configuration, the plurality of second insulators and the plurality of third insulators may be silicon-containing oxides, and the plurality of charge-holding layers may be silicon-containing nitrides. Furthermore, in the above configuration, the plurality of charge-holding layers may be conductors.

[0015] Furthermore, in the above configuration, it is preferable that the second insulator is in contact with the upper surface of the oxide and the side surface of the first insulator.

[0016] Furthermore, in the above configuration, it is preferable that multiple third conductors are arranged below the oxide, superimposed on multiple second conductors.

[0017] Another aspect of the present invention involves forming an oxide film on a substrate, forming a first conductive film on the oxide film, processing the oxide film and the first conductive film into island shapes to form an oxide and a first conductor, covering the oxide and the first conductor to form a first insulator, removing a portion of the first insulator and superimposing it on the first conductor to form a plurality of openings, removing a portion of the first conductor superimposed on the plurality of openings to form a plurality of second conductors arranged in a straight line, exposing the oxide in the region between the plurality of second conductors, and contacting the upper surface of the oxide, the first This is a method for manufacturing a semiconductor device, comprising: forming an insulating film; performing microwave processing in an oxygen-containing atmosphere; forming a second insulating film on the first insulating film; forming a third insulating film on the second insulating film; forming a second conductive film on the third insulating film; and performing CMP processing on the first insulating film, the second insulating film, the third insulating film, and the second conductive film until the upper surface of the first insulator is exposed, thereby forming a plurality of second insulators, a plurality of third insulators, a plurality of fourth insulators, and a plurality of third conductors, which are respectively arranged in the regions between a plurality of second conductors.

[0018] Furthermore, in the above, it is preferable that the first insulating film and the third insulating film are silicon-containing oxide films, and the second insulating film is a silicon-containing nitride film.

[0019] According to one aspect of the present invention, a semiconductor device with a large memory capacity can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims.

[0021] Figures 1A, 1B, and 1C are a top view, cross-sectional view, and circuit diagram of a semiconductor device according to one embodiment of the present invention. Figures 2A and 2B are schematic diagrams showing the electrical characteristics and charge transfer of a semiconductor device according to one embodiment of the present invention. Figures 3A, 3B, and 3C are circuit diagrams of a semiconductor device according to one embodiment of the present invention. Figures 4A and 4B are cross-sectional views and circuit diagrams of a semiconductor device according to one embodiment of the present invention. Figures 5A, 5B, 5C, and 5D are a top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 7A is a diagram illustrating the classification of IGZO crystal structures. Figure 7B is a diagram illustrating the XRD spectrum of a CAAC-IGZO film. Figure 7C is a diagram illustrating the micro-electron diffraction pattern of a CAAC-IGZO film. Figures 8A, 8B, 8C, and 8D are a top view and cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 9A, 9B, 9C, and 9D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 10A, 10B, 10C, and 10D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 11A, 11B, 11C, and 11D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 12A, 12B, 12C, and 12D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 13A, 13B, 13C, and 13D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 14A, 14B, 14C, and 14D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 15A, 15B, 15C, and 15D are top views and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 16 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 17 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 18 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 19 is a cross-sectional view showing the configuration of a semiconductor device according to one aspect of the present invention. Figure 20 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. Figure 21A is a block diagram showing an example of the configuration of a semiconductor device according to one aspect of the present invention.Figure 21B is a perspective view of a semiconductor device according to one aspect of the present invention. Figure 22 is a circuit diagram showing an example configuration of a semiconductor device according to one aspect of the present invention. Figures 23A and 23B are schematic diagrams of a semiconductor device according to one aspect of the present invention. Figures 24A, 24B, 24C, 24D, and 24E are schematic diagrams of a storage device according to one aspect of the present invention. Figures 25A, 25B, 25C, 25D, 25E, 25F, and 25G are schematic diagrams showing an electronic device according to one aspect of the present invention.

[0022] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0023] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. In addition, in drawings, the same reference numerals may be used in common across different drawings for the same part or parts with similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatch pattern may be the same, and no specific reference numeral may be assigned.

[0024] Furthermore, in particular, in top views (also called "plan views") and perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted.

[0025] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0026] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0027] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0029] Furthermore, the functions of the source and drain may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0030] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0031] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0032] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0033] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0034] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, and apparent channel width can be determined by analyzing cross-sectional TEM images, etc.

[0035] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. Ｏ Oxygen vacancy may form.

[0036] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0037] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0038] Furthermore, in this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0039] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0040] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. −２０ Below A, at 85°C, 1 × 10 −１８ A or less, or 1 × 10 at 125°C −１６ This means being A or less.

[0041] (Embodiment 1) In this embodiment, an example of the configuration of a semiconductor device that functions as a storage device according to one aspect of the present invention will be described with reference to Figures 1 to 4.

[0042] <Example of Semiconductor Device Configuration> The configuration of a semiconductor device having transistors 10, 12, and 14 will be explained using Figure 1. Figure 1A is a top view of the semiconductor device. Figure 1B is a cross-sectional view of the semiconductor device, specifically the section indicated by the dashed line A1-A2 in Figure 1A, and also a cross-sectional view of transistors 10, 12, and 14 in the channel length direction. Figure 1C is a circuit diagram corresponding to the cross-sectional view shown in Figure 1B. Note that some elements have been omitted from the top view of Figure 1A for clarity. In the following explanation, each transistor is assumed to be an n-channel type transistor. However, terms and symbols may be appropriately replaced to apply to p-channel type transistors.

[0043] The semiconductor device shown in Figures 1A and 1B has a structure in which multiple transistors 10 are provided between transistor 12 and transistor 14 (hereinafter sometimes referred to as a string). The string is provided extending in the A1-A2 direction, in other words, in the channel length direction of transistors 10, 12, and 14. Furthermore, multiple strings are arranged in a direction perpendicular to the A1-A2 direction, in other words, in the channel width direction of transistors 10, 12, and 14. Although three strings are shown in Figure 1A, the present invention is not limited to this, and the number of strings can be appropriately set according to the memory design. Also, there is no limit to the number of transistors 10 provided in the string, but for example, the number can be 2, 4, 8, 16, 32, 64, 128, etc.

[0044] The string comprises an oxide 20 on a substrate (not shown), a plurality of conductors 22 arranged on the oxide 20, an insulator 24 arranged on the plurality of conductors 22 and superimposed in the regions between the plurality of conductors 22, each having a plurality of openings, a plurality of insulators 26a arranged in each of the plurality of openings, a plurality of charge-holding layers 28 arranged on each of the plurality of insulators 26a, a plurality of insulators 26b arranged on each of the plurality of charge-holding layers 28, and a plurality of conductors 30 arranged on each of the plurality of insulators 26b.

[0045] As shown in Figure 1B, transistor 10 comprises an oxide 20, a conductor 22, an insulator 24, an insulator 26a, a charge retention layer 28, an insulator 26b, and a conductor 30. Transistors 12 and 14 have almost the same structure as transistor 10, but instead of insulators 26a, charge retention layer 28, and insulator 26b, an insulator 26 is provided. Here, the oxide 20 is provided extending in the A1-A2 direction. The multiple conductors 22 are arranged linearly parallel to the upper surface of the oxide 20, and the rows of multiple conductors 22 extend in the A1-A2 direction. The insulators 26a, charge retention layer 28, insulator 26b, insulator 26, and conductor 30 are provided extending in a direction perpendicular to the A1-A2 direction. Therefore, it can be said that transistors 10, 12, and 14 are provided in the region where the oxide 20 and the conductor 30 intersect.

[0046] In transistor 10, the conductor 30 functions as a gate electrode, the insulator 26a, charge retention layer 28, and insulator 26b function as gate insulators, and the conductor 22 functions as a source electrode or drain electrode. Similarly, in transistors 12 and 14, the conductor 30 functions as a gate electrode, the insulator 26 functions as a gate insulator, and the conductor 22 functions as a source electrode or drain electrode. As shown in Figure 1B, the conductor 30 is positioned in an opening provided between multiple conductors 22, and the conductors 30 and 22 are arranged alternately. In other words, in each string, the source electrodes and drain electrodes of adjacent transistors are not separated. That is, the conductor 22 can be said to be the drain electrode of the transistor located on the A1 side and the source electrode of the transistor located on the A2 side at the same time. Thus, transistors 10, 12, and 14 provided in the string are configured so that their source electrodes and drain electrodes are connected in series.

[0047] The transistor 10 has a charge-retaining layer 28 between the conductor 30 and the oxide 20. Therefore, the transistor 10 has a threshold voltage corresponding to the polarity and amount of charge in the charge-retaining layer 28. Because the transistor 10 can control the threshold voltage with the charge-retaining layer 28, it functions as a memory cell (also called a memory element) that stores data corresponding to the threshold voltage.

[0048] Here, Figure 2A schematically shows the Id-Vg curves for transistor 10 when charge is accumulated and when no charge is accumulated. Figure 2B shows a schematic cross-sectional view when charge is accumulated in the charge retention layer 28.

[0049] As shown on the left side of Figure 2A, for example, when no electrons are accumulated in the charge-holding layer 28, the threshold voltage of transistor 10 is a negative value. Then, as shown in Figure 2B, when electrons accumulate in the charge-holding layer 28, the threshold voltage fluctuates to cancel out the electric field generated by the electrons, and the threshold voltage becomes a positive value, as shown on the right side of Figure 2A. That is, transistor 10 conducts when no electrons are accumulated in the charge-holding layer 28, so it takes data "1", and does not conduct when electrons are accumulated, so it takes data "0". Note that Figure 2A describes an example where the threshold voltage of transistor 10 is negative at data "1" and positive at data "0", but it is not limited to this, and it is sufficient that the threshold voltage of transistor 10 at data "1" is smaller than the threshold voltage of transistor 10 at data "0". Also, although the case of a binary memory cell has been described, a multi-level memory cell with three or more levels (for example, quadrivalent, octave, 16-level, and 32-level) may also be used. The injection of electrons into the charge-holding layer 28 will be described later.

[0050] Furthermore, transistors 12 and 14 do not have a charge retention layer 28 and therefore do not have a function to store charge, and thus function as switching transistors. By making transistors 12 and 14 conductive or non-conductive, it is possible to select the string to be used in the writing, erasing, and reading operations of data in the semiconductor device. For this reason, transistors 12 and 14 can be called selection transistors.

[0051] In the above transistors, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) in the oxide 20 including the channel formation region. It is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of transistors 10, 12, and 14 can be reduced. By reducing the off-current of transistors 10, 12, and 14 in this way, it is possible to suppress the generation of leakage current between transistors 12 and 14 in the string. As a result, the power consumption of the memory device using the string can be reduced.

[0052] As oxide 20, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. For example, In-Ga-Zn oxide may be used as oxide 20, or an oxide obtained by adding tin to In-Ga-Zn oxide may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 20.

[0053] The above-mentioned metal oxide can be deposited on a substrate using methods such as sputtering. Therefore, a memory cell array can be provided on top of peripheral circuits such as drive circuits formed on a silicon substrate. This reduces the area occupied by peripheral circuits on a single chip and increases the area occupied by the memory cell array, thereby increasing the storage capacity of the semiconductor device. Furthermore, by depositing multiple layers of the above-mentioned metal oxide film, a stacked memory cell array can be provided. This allows cells to be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a stacked structure of memory cell arrays (hereinafter sometimes referred to as a 3D cell array) can be constructed. As a result, it is possible to achieve high integration of memory cells and provide a semiconductor device with a large storage capacity.

[0054] Furthermore, semiconductor devices using the above-mentioned metal oxides, particularly In-Ga-Zn oxide, exhibit excellent heat resistance, with a temperature range of -40°C to 190°C during which the semiconductor device can operate normally. This is superior heat resistance compared to that of phase-change memory (PCM) (-40°C to 150°C), resistive random access memory (ReRAM) (-40°C to 125°C), and magnetoresistive random access memory (MRAM) (-40°C to 105°C).

[0055] As shown in Figure 1B, the oxide 20 has a region 20a and a region 20b that is provided so as to sandwich region 20a. Region 20a functions as the channel forming region of each transistor, and region 20b functions as the source region or drain region of each transistor. At least a portion of region 20a is superimposed on the conductor 30. In other words, region 20a is provided in the region between the conductors 22. Region 20b is provided superimposed on the conductor 22.

[0056] Region 20a, which functions as a channel-forming region, has fewer oxygen vacancies or lower impurity concentrations than region 20b, resulting in a high-resistance region with a low carrier concentration. Therefore, region 20a can be said to be i-type (intrinsic) or substantially i-type. Region 20b, which functions as a source or drain region, has many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, or metal elements, resulting in an increased carrier concentration and low resistance. In other words, region 20b is an n-type region with a higher carrier concentration and lower resistance compared to region 20a. The method for selectively forming regions 20a and 20b will be described in a later embodiment.

[0057] In the string, as shown in Figure 1C, the sources and drains of multiple transistors 10 are connected in series, and the gates of multiple transistors 10 are connected to multiple wirings WL, respectively. The drain of transistor 10 located at one end of the series-connected transistors 10 is connected to the source of transistor 12, and the source of transistor 10 located at the other end of the series-connected transistors 10 is connected to the drain of transistor 14. The drain of transistor 12 is connected to wiring BL, and the gate of transistor 12 is connected to wiring SGB. The source of transistor 14 is connected to wiring SL, and the gate of transistor 14 is connected to wiring SGS.

[0058] Wiring WL functions as a word line for selecting memory cells. Wiring SGB and SGS functions as selection lines for selecting strings. Wiring BL functions as a bit line, and wiring SL functions as a source line.

[0059] Here, the conductor 30 of transistor 10 functions as wiring WL, the conductor 30 of transistor 12 functions as wiring SGB, and the conductor 30 of transistor 14 functions as wiring SGS. In other words, wiring WL, wiring SGB, and wiring SGS are connected to the other strings of transistors 10, 12, and 14, respectively, as shown in Figure 1A.

[0060] In the semiconductor device shown in this embodiment, as shown in Figure 1A, the string and the wiring WL, wiring SGB, and wiring SGS are arranged orthogonally to each other. In addition, the transistors 10 are arranged in a matrix, and transistors 12 and 14 are arranged in a direction perpendicular to A1-A2. However, the string and the wiring WL, wiring SGB, and wiring SGS do not necessarily have to be arranged orthogonally. For example, the extension directions of the wiring WL, wiring SGB, and wiring SGS may be inclined with respect to the extension direction of the string.

[0061] A group of memory cells connected to the same wiring WL is called a page. Data writing and reading are performed on a page-by-page basis. A group of strings connected to the same wiring SGB and wiring SGS is called a block. Therefore, one block can contain multiple pages. Data erasure is performed on a block-by-block basis. Furthermore, it is preferable that multiple strings contained within the same block are electrically connected to the same wiring SL.

[0062] Next, an example of data writing, erasing, and reading operations of the semiconductor device shown in Figure 1 will be explained using Figures 3A to 3C.

[0063] <Writing Operation> First, the operation of writing data to a selected memory cell will be explained using Figure 3A. In Figure 3A, the wiring WL for the page to be written to is denoted as wiring SWL, and the wiring WL for the page not to be written to is denoted as wiring NWL. Below, we will explain the operation of writing data "0" to the memory cell of data "1" connected to wiring SWL.

[0064] The data writing operation can be performed for each page as described above. First, the writing potential V is set to the wiring SWL connected to the page to be written to. ＷＷ Apply a voltage V to the wiring NWL connected to the page that will not be written to. ＯＰ A potential (the potential at which transistor 10 conducts regardless of the retained data) is applied. Note that the writing potential V ＷＷ The potential V ＯＰis significantly larger. Here, a potential that turns on the transistor 12 is applied to the wiring SGB, and a potential that turns off the transistor 14 is applied to the wiring SGS. Here, a potential V ＷＤ０ (write potential V ＷＷ significantly smaller than) is applied. As a result, the potential V of the wiring BL can be applied to the memory cells of the page to be written. ＷＤ０ In the transistor 10 of the memory cell where writing is performed, a tunnel current is induced between the conductor 22 and the region 20a and the charge holding layer 28 due to the potential difference between the potential V ＷＤ０ and the write potential V ＷＷ , and electrons are injected into the charge holding layer 28. In this way, data "0" is written into the memory cell connected to the wiring SWL.

[0065] Also, since data writing is performed page by page, writing is also simultaneously performed on other strings in the same block in the above writing. Here, when maintaining data "1" in the memory cells of other strings, a potential V ＷＤ１ (a potential of the same magnitude as the write potential V ＷＷ ) is applied to the wiring BL connected to the string. Since the potential difference between the potential V ＷＤ１ and the write potential V ＷＷ is small, electrons are not injected into the charge holding layer 28 of the transistor 10 of the above string connected to the wiring SWL. Therefore, data "1" in the above memory cell can be maintained.

[0066] Next, using the same method, other pages can be sequentially written. In this way, data can be written to all pages included in the block.

[0067] Note that data other than data "0" and data "1" can also be written to the memory cell. For example, the amount of electrons injected into the charge holding layer 28 can be controlled by adjusting the potential of the wiring BL or the like and the time for applying the potential.

[0068] <Erase Operation> Next, the operation of erasing all data in the selected block at once (writing data "1") will be explained using Figure 3B. In Figure 3B, the wiring WL of the page on which data "0" was written is defined as wiring SWL, and the wiring WL of the page on which data "1" was written is defined as wiring NWL.

[0069] The data erasure operation is performed block by block. For example, a potential is applied to the wiring SGS connected to the block whose data to be erased, causing transistor 14 to turn on, and an erasure potential V is applied to the wiring SL. Ｅ (Writing potential V) ＷＷ It is sufficient to apply a potential of a similar magnitude to that. This will erase the wiring SL V of the memory cell of the selected block. Ｅ The following is given: Elimination potential V Ｅ This causes electrons to be extracted from the charge retention layer 28 of the transistor 10 in the selected block. In this way, the data in the memory cell of the selected block is erased. Additionally, a potential is applied to the wiring SGB that turns on the transistor 12, and an erase potential V is applied to the wiring BL. Ｅ By applying a potential V, electrons may be extracted from the charge retention layer 28 of transistor 10, erasing the data of the memory cell in the selected block. Alternatively, an erase potential V may be applied to both wiring SL and wiring BL. Ｅ You may also erase the data in the memory cells of the selected block by providing a value.

[0070] Furthermore, it is preferable to erase the data before the above writing operation to set the memory cell of the block to be written to data "1". This operation of erasing data is also called a reset operation.

[0071] Furthermore, it is preferable to store data in memory cells that will not be rewritten in a separate area before the block reset operation.

[0072] <Read Operation> Next, the read operation of the selected memory cell will be explained using Figure 3C. In Figure 3C, the wiring WL for the page to be read is denoted as wiring SWL, and the wiring WL for the page not to be read is denoted as wiring NWL. The following describes the operation of reading data "0" from the memory cell connected to wiring SWL.

[0073] Data retrieval can also be performed page by page. First, the read potential V is connected to the wiring SWL connected to the page from which data is to be read. ＲＷ Apply a voltage V to the wiring NWL connected to the page that is not being read. ＯＰ Apply the voltage. Note that the readout potential V ＲＷ This is the potential at which transistor 10 is turned off if data "0", and turned on if data "1". Here, a potential is applied to wiring SGB to turn on transistor 12, and a potential is applied to wiring SGS to turn on transistor 14. Here, a potential V is applied to wiring BL. Ｒ Provides a potential V to the wiring SL. Ｓ (Potential V Ｒ A smaller potential is applied. This brings the potential V of the wiring BL across the memory cell of the page being read. Ｒ and the potential V of the wiring SL Ｓ Given the data, the memory cell is data "0", so the connection between wiring SL and wiring BL remains non-conductive, and the amount of current flowing between wiring SL and wiring BL is approximately 0. If the memory cell were data "1", the connection between wiring SL and wiring BL would be conductive, and current would flow between wiring SL and wiring BL. Therefore, the data of the memory cell can be read by measuring the current flowing between wiring SL and wiring BL.

[0074] Also, for example, if there is a potential V in the wiring BL Ｒ Precharge it, and then read the potential V to the wiring SWL. ＲＷ Apply a voltage V to the wiring NWL. ＯＰThe data in the memory cell may be read by applying a voltage. In this case, for example, when the memory cell is data "0", the connection between wiring SL and wiring BL remains non-conductive, and therefore the potential V of wiring BL Ｒ This is maintained. On the other hand, if the memory cell is data "1", wiring SL and wiring BL become conductive, and the potential of wiring BL becomes potential V Ｒ It descends from there. In other words, by measuring the potential of wiring BL, the data of the memory cell can be read.

[0075] Furthermore, since data is read page by page, the above read operation can simultaneously read data from other strings within the same block. The same method can then be used to read other pages sequentially. In this way, data from all pages contained within a block can be read.

[0076] The above data writing, erasing, and reading operations are merely examples of the driving method for the semiconductor device according to the present invention, and the driving method for the semiconductor device according to the present invention is not limited to these examples. The potentials applied to various wires can be set as appropriate to match the circuit configuration of the memory device.

[0077] <Modifications of the semiconductor device> The semiconductor device according to one aspect of the present invention is not limited to the structure shown in Figures 1A to 1C. Modifications of the semiconductor device according to one aspect of the present invention will be described below with reference to Figures 4A and 4B.

[0078] <Modification 1> In one aspect of the present invention, the semiconductor device may be configured such that the transistor 10 has an insulator 26, a conductor 30a, and a conductor 30b, as shown in Figure 4A. The string shown in Figure 4A differs from the string shown in Figure 1B in that it has an insulator 26, a conductor 30a, and a conductor 30b, but does not have a charge-holding layer 28, an insulator 26a, and an insulator 26b. The other configurations are the same as those of the string shown in Figure 1B, so the above description can be taken into consideration.

[0079] In the transistor 10 shown in Figure 4B, an insulator 26 is positioned in contact with the side and bottom surfaces of the opening formed by the conductor 22 and the insulator 24. The conductor 30a is positioned so as to be enclosed by the insulator 26, and a conductor 30b is positioned on top of the insulator 26 and the conductor 30a. Here, the conductor 30a is insulated from the conductor 30b, the conductor 22, the oxide 20, etc., by the insulator 26. The conductor 30a is also enclosed by the insulator 26 in the channel width direction of the transistor 10 and is provided individually for each transistor 10. In contrast, the conductor 30b functions as wiring WL and is therefore provided extending in the channel width direction of the transistor 10.

[0080] The semiconductor device shown in Figure 4B is a floating-gate type memory device, in which the conductor 30a functions as a floating gate and the conductor 30b functions as a control gate. Therefore, while the semiconductor devices shown in Figures 1A to 1C store data by accumulating charge in the charge retention layer 28, the semiconductor device shown in Figure 4B can store data by accumulating charge in the conductor 30a.

[0081] In the above description, the insulator 26 is made into a single unit, including the portion that contacts the bottom and side surfaces of the opening and the portion that encloses the conductor 30a. However, the present invention is not limited to this. For example, the insulator that contacts the bottom and side surfaces of the opening and the insulator formed between the conductor 30a and the conductor 30b may be provided separately.

[0082] <Modification 2> In addition, a semiconductor device according to one aspect of the present invention may be configured such that transistors 10, 12, and 14 are each provided with a second gate electrode connected to the wiring BGL, as shown in Figure 4B. The second gate electrode may also be called a back gate electrode, and may be arranged so as to be superimposed on the conductor 30 via an insulator beneath the oxide 20. When a second gate electrode is provided, the conductor 30 may be called a first gate electrode or a top gate electrode.

[0083] By applying a potential to the wiring BGL in conjunction with the writing operation of the semiconductor device, it may be possible to reduce the writing potential applied to the conductor 30. This can reduce the power consumption of the semiconductor device. Furthermore, since damage to the gate insulator during writing can be reduced, the rewrite endurance of the semiconductor device can be improved.

[0084] Furthermore, during the data erasure operation, the erasure potential V is set to the wiring BGL corresponding to the wiring WL. Ｅ A potential equivalent to this may be applied to extract charge from the charge retention layer 28 of the corresponding transistor 10. This allows the data of the selected block to be erased all at once, thereby reducing the time required for data erasure.

[0085] (Embodiment 2) In this embodiment, an example of a specific configuration of the semiconductor device shown in the previous embodiment will be explained using Figures 5 to 15. In this embodiment, a semiconductor device having a plurality of transistors (transistors 200a to 200c) and a method for manufacturing the same will be described. In the following, transistors 200a to 200c have substantially the same structure and may be collectively referred to as transistor 200. Here, transistor 200 corresponds to transistor 10 shown in the previous embodiment. That is, transistors 200a to 200c also have a configuration in which their source electrodes and drain electrodes are connected in series with respect to each other.

[0086] Furthermore, Figures 5 to 15 illustrate semiconductor devices having transistors 200a to 200c, but the present invention is not limited thereto. As described in the previous embodiments, the number of memory cells, i.e., transistors 200, included in the string can be appropriately set according to the memory design. Also, although only one string is provided in Figures 5 to 15, the present invention is not limited thereto. As described in the previous embodiments, the number of strings can be appropriately set according to the memory design.

[0087] <Example of Semiconductor Device Configuration> The configuration of a semiconductor device having a transistor 200 will be explained using Figures 5A to 5D. Figures 5A to 5D are top views and cross-sectional views of a semiconductor device having a transistor 200. Figure 5A is a top view of the semiconductor device. Figures 5B to 5D are cross-sectional views of the semiconductor device. Here, Figure 5B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 5A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 5C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 5A, and is also a cross-sectional view of the transistor 200a in the channel width direction. Figure 5D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 5A, and is also a cross-sectional view of the source or drain of the transistor 200a in the channel width direction. Note that in the top view of Figure 5A, some elements have been omitted for clarity.

[0088] As shown in Figures 5A to 5D, the transistor 200 comprises an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, a conductor 205 (conductor 205a, conductor 205b, and conductor 205c) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxide 243a, and oxide 243b) on the oxide 230b, and an oxide 243a The device comprises a conductor 242a, a conductor 242b on the oxide 243b, an insulator 250a on the oxide 230b, a charge-holding layer 255 on the insulator 250a, an insulator 250b on the charge-holding layer 255, a conductor 260 (conductors 260a and 260b) located on the insulator 250b and overlapping with a portion of the oxide 230b, an insulator 275 arranged to cover the insulator 224 and the oxide 230, an insulator 280 on the insulator 275, an insulator 282 on the insulator 280, insulator 250a, insulator 250b, charge-holding layer 255, and conductor 260, and an insulator 283 on the insulator 282. Here, as shown in Figures 5B and 5C, the upper surface of the conductor 260 is positioned to substantially coincide with the uppermost part of the insulator 250a, the uppermost part of the insulator 250b, the uppermost part of the charge-holding layer 255, and the upper surface of the insulator 280.

[0089] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242. Furthermore, insulators 250a and 250b may be collectively referred to as insulator 250.

[0090] Here, oxide 230, in particular oxide 230b, corresponds to oxide 20 in the previous embodiment. Conductor 242 corresponds to conductor 22 in the previous embodiment. Insulator 280 corresponds to insulator 24 in the previous embodiment. Insulator 250a corresponds to insulator 26a in the previous embodiment. Charge retention layer 255 corresponds to charge retention layer 28 in the previous embodiment. Insulator 250b corresponds to insulator 26b in the previous embodiment. Conductor 260 corresponds to conductor 30 in the previous embodiment.

[0091] Insulators 280 and 275 are provided with openings that reach the oxide 230b. Insulator 250, charge retention layer 255, and conductor 260 are arranged within these openings. Furthermore, in the channel length direction of transistor 200, conductor 260, charge retention layer 255, and insulator 250 are provided between conductor 242a and oxide 243a and conductor 242b and oxide 243b. Here, it is preferable that insulator 250a is provided in contact with the upper surface of oxide 230b, the side surface of oxide 243, the side surface of conductor 242, the side surface of insulator 275, and the side surface of insulator 280. It is also preferable that the charge retention layer 255 is provided in contact with the upper surface and side surface of insulator 250a. Furthermore, it is preferable that insulator 250b is provided in contact with the upper surface and side surface of charge retention layer 255. Furthermore, it is preferable that the conductor 260 is provided in contact with the upper and side surfaces of the insulator 250b.

[0092] Here, in transistors 200a to 200c, insulators 212, 214, 216, 222, 224, oxide 230a, oxide 230b, insulator 275, 280, 282, and 283 are commonly used. On the other hand, conductor 205, insulator 250a, charge retention layer 255, insulator 250b, and conductor 260 are provided in transistors 200a to 200c, respectively. In addition, a plurality of conductors 242 are arranged linearly in the channel length direction. A plurality of openings are provided superimposed in the region between the conductors 242, and insulators 250a, charge retention layer 255, insulator 250b, and conductor 260 are formed within these openings.

[0093] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having the oxide 230a below the oxide 230b, the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b can be suppressed.

[0094] In the transistor 200, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited thereto. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure. Furthermore, when stacking oxide 230a or an oxide similar to oxide 230b on top of oxide 230b, the oxide may be provided in a shape that follows the bottom and side surfaces of the opening, as insulator 250a.

[0095] The conductor 260 functions, for example, as a first gate (also called a top gate) electrode, and the conductor 205 functions, for example, as a second gate (also called a back gate) electrode. In addition, the insulator 250 and the charge retention layer 255 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. As shown in the previous embodiment, since the charge retention layer 255 has the function of accumulating charge, the transistor 200 can function as a memory cell.

[0096] Conductor 242a functions as either a source or a drain, and conductor 242b functions as either a source or a drain. In addition, at least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0097] Here, Figure 6 shows an enlarged view of the vicinity of the channel formation region of transistor 200a in Figure 5B. As shown in Figure 6, the oxide 230b has a region 230bc that functions as the channel formation region of transistor 200a, and regions 230ba and 230bb that are provided so as to sandwich region 230bc and function as the source region or drain region. At least a portion of region 230bc is superimposed on the conductor 260. In other words, region 230bc is provided in the region between conductor 242a and conductor 242b. Region 230ba is provided superimposed on conductor 242a, and region 230bb is provided superimposed on conductor 242b.

[0098] Region 230bc, which functions as a channel-forming region, is a high-resistance region with a low carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to regions 230ba and 230bb. Regions 230ba and 230bb, which function as source or drain regions, are low-resistance regions with increased carrier concentrations due to more oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements. In other words, regions 230ba and 230bb are low-resistance regions with higher carrier concentrations compared to region 230bc.

[0099] Here, the carrier concentration in region 230bc, which functions as a channel-forming region, is 1 × 10⁻⁶. １８ cm −３ The following is preferable: 1 × 10 １７ cm −３ It is more preferable that it be less than 1 × 10 １６ cm −３ It is even more preferable that it be less than 1 × 10 １３ cm −３ It is even more preferable that it be less than 1 × 10 １２ cm −３ It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 230bc that functions as a channel-forming region, but for example, 1 × 10 −９ cm −３ It can be done this way.

[0100] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of region 230ba and region 230bb, and equal to or greater than that of region 230bc.

[0101] Although Figure 6 shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0102] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0103] Here, region 230bc is formed on each transistor 200, while regions 230ba and 230bb are shared by two adjacent transistors 200. For example, region 230ba functions as one of the source and drain of transistor 200a, and simultaneously as the other of the source and drain of transistor 200b. Similarly, region 230bb functions as the other of the source and drain of transistor 200a, and simultaneously as one of the source and drain of transistor 200c. In this way, multiple transistors 200 are connected in series, with their sources and drains connected, to form the string shown in the previous embodiment.

[0104] In the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region. As shown in Figure 5A, the oxide 230 has an island-like shape that extends in the A1-A2 direction.

[0105] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of transistor 200 can be reduced. By reducing the off-current of transistor 200 in this way, it is possible to suppress the generation of leakage current between wiring BL and wiring SL in the string shown in the above embodiment. As a result, the power consumption of the memory device using the string can be reduced.

[0106] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. For example, In-Ga-Zn oxide may be used as oxide 230, or an oxide obtained by adding tin to In-Ga-Zn oxide may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0107] The above-mentioned metal oxide can be deposited on a substrate using methods such as sputtering. Therefore, a memory cell array can be provided on top of peripheral circuits such as drive circuits formed on a silicon substrate. This reduces the area occupied by peripheral circuits on a single chip and increases the area occupied by the memory cell array, thereby increasing the storage capacity of the semiconductor device. Furthermore, by depositing multiple layers of the above-mentioned metal oxide film, memory cell arrays can be stacked. This allows for the integration and arrangement of cells without increasing the area occupied by the memory cell array. In other words, a 3D cell array can be constructed. As a result, it is possible to achieve high integration of memory cells and provide a semiconductor device with a large storage capacity.

[0108] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0109] In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed.

[0110] Furthermore, because oxides 230a and 230b share a common element other than oxygen (as the main component), the defect level density at the interface between oxide 230a and oxide 230b can be reduced. Since the defect level density at the interface between oxide 230a and oxide 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0111] The oxide 230b is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) instead of oxide 230b.

[0112] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen deficiencies (V)). Ｏ It is a metal oxide with few impurities (such as ). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0113] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat resistant and reliable.

[0114] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). ＯSometimes referred to as H, it forms a channel that can generate electron carriers even when no voltage is applied to the gate electrode of the transistor. For this reason, if the region in the oxide semiconductor where the channel is formed contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region in the oxide semiconductor where the channel is formed, impurities, oxygen vacancies, and V are likely to be present. Ｏ It is preferable that H is reduced as much as possible. In other words, when no voltage is applied to the gate electrode of the transistor, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0115] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0116] Therefore, in the oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V Ｏ It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0117] Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V Ｏ The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0118] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc Ｏ By cleaving H and removing hydrogen H from region 230bc, an oxygen-deficient V is created. Ｏ It can be supplemented with oxygen. In other words, in region 230bc, "V Ｏ H → H + V Ｏ The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V Ｏ This can reduce H and lower the carrier concentration.

[0119] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effects of oxygen plasma can be reduced by insulators 275 and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, V Ｏ Since H is reduced and excessive oxygen supply does not occur, a decrease in carrier concentration can be prevented.

[0120] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V ＯBy removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, and the n-type configuration can be maintained. This suppresses variations in the electrical characteristics of transistor 200 and prevents variations in the electrical characteristics of transistor 200 within the substrate plane.

[0121] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good electrical characteristics. Additionally, it is possible to provide a semiconductor device with good reliability.

[0122] In Figure 5 and other figures, the side surface of the opening into which the conductor 260 is embedded, including the groove portion of the oxide 230b, is generally perpendicular to the surface of the oxide 230b being formed. However, this embodiment is not limited to this. For example, the bottom of the opening may have a gently curved surface, resulting in a U-shape. Alternatively, for example, the side surface of the opening may be inclined with respect to the surface of the oxide 230b being formed.

[0123] Furthermore, as shown in Figure 5C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0124] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0125] The oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to the main component metal element is greater than the atomic ratio of element M to the main component metal element in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0126] Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0127] Here, at the junction of oxide 230a and oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b.

[0128] Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, then oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0129] Specifically, as oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it, may be used. Similarly, as oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it, may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0130] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0131] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high field-effect mobility, high on-current, and high frequency characteristics. By using such a transistor 200 in the string shown in the above embodiment, the readout speed can be improved.

[0132] It is preferable that at least one of insulators 212, 214, 275, 282, and 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 275, 282, and 283 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as copper atoms (i.e., the above-mentioned impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms or oxygen molecules) (i.e., the above-mentioned oxygen does not easily permeate).

[0133] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0134] As insulators 212, 214, 275, 282, and 283, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride or the like as insulators 212 and 283, as they have higher hydrogen barrier properties. Also, for example, it is preferable to use aluminum oxide or the like as insulators 214, 275, and 282, which have high hydrogen capture and hydrogen fixation functions and high oxygen barrier properties. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside of insulator 283 to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in insulator 224, etc., to the substrate side via insulators 212 and 214. Alternatively, the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. can be suppressed. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 275, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0135] The insulators 212, 214, 275, 282, and 283 can be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen as a deposition gas, the hydrogen concentration of insulators 212, 214, 275, 282, and 283 can be reduced. Furthermore, the film deposition method is not limited to sputtering; chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods may be used as appropriate.

[0136] Furthermore, it may be preferable to lower the resistivity of insulators 212 and 283. For example, the resistivity of insulators 212 and 283 may be approximately 1 × 10⁻⁶. １３ By setting the resistivity to Ωcm, insulators 212 and 283 may be able to mitigate charge-up of conductors 205, 242, or 260 during plasma-based processing in semiconductor device manufacturing processes. The resistivity of insulators 212 and 283 is preferably 1 × 10⁻⁶. １０ Ωcm or more, 1 x 10 １５ The density should be less than or equal to Ωcm.

[0137] Furthermore, it is preferable that the dielectric constants of insulators 216 and 280 are lower than those of insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216 and 280.

[0138] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In addition, a portion of the conductor 205 may be embedded in the insulator 214.

[0139] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately the same as the height of the upper surface of conductor 205a and the upper surface of insulator 216. In other words, conductor 205b is enclosed by conductors 205a and conductor 205c.

[0140] Here, conductors 205a and 205c are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule).

[0141] By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to prevent impurities such as hydrogen contained in conductor 205b from diffusing into oxide 230 via insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress oxidation of conductor 205b and a decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, conductors 205a and 205c may be made of the above conductive materials in a single layer or laminate. For example, titanium nitride may be used for conductors 205a and 205c.

[0142] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0143] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260, without linking it to the potential applied to the conductor 260. Furthermore, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 reduces the drain current when the potential applied to the conductor 260 is 0V compared to not applying a negative potential.

[0144] Furthermore, by applying a potential to the conductor 205 in conjunction with the memory device's write operation, the write potential applied to the conductor 260 can sometimes be reduced. This reduces the power consumption of the memory device. In addition, damage to the insulator 250 during writing can be reduced, thereby improving the rewrite endurance of the memory device.

[0145] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0146] Furthermore, as shown in Figure 5A, the conductor 205 is preferably provided in a size larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in Figure 5C, it is preferable that the conductor 205 extends to the area outside the ends of the oxide 230a and oxide 230b that intersect with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the oxide 230 with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0147] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the planar-type structure. By adopting the S-channel structure, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0148] Furthermore, as shown in Figure 5C, the conductor 205 is extended in the channel width direction and functions as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0149] In the transistor 200, the conductor 205 is shown as a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer, two layers, or a stacked structure of four or more layers.

[0150] Insulators 222 and 224 function as gate insulators.

[0151] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both of hydrogen and oxygen more effectively than the insulator 224.

[0152] The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0153] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, the insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0154] Furthermore, the insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO). ３ ), (Ba,Sr)TiO ３ Insulators containing so-called high-k materials such as (BST) may be used in single-layer or multi-layer configurations. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0155] The insulator 224 in contact with the oxide 230 preferably contains excess oxygen (oxygen is removed by heating). For example, silicon oxide, silicon oxynitride, etc., can be used as appropriate for the insulator 224. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0156] Specifically, as the insulator 224, it is preferable to use an oxide material from which some oxygen is desorbed by heating, in other words, an insulating material having an excess oxygen region. An oxide from which oxygen is desorbed by heating is defined as one in which the amount of oxygen molecules desorbed by TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10⁻⁶. １８ molecules / cm ３ Preferably 1.0 × 10 １９ molecules / cm ３ More preferably 2.0 × 10 １９ molecules / cm ３The above, or 3.0 x 10 ２０ molecules / cm ３ The above describes the oxide film. Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0157] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment while the surface of the oxide 230 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby preventing oxygen deficiency (V Ｏ This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0158] Furthermore, by performing an oxygenation treatment on the oxide 230, oxygen deficiencies in the oxide 230 are repaired by the supplied oxygen, in other words, "V Ｏ This can accelerate the reaction "+O → null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in the oxide 230, thereby converting the hydrogen into H ２ It can be removed as O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancy and V Ｏ This can suppress the formation of H.

[0159] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island shape by being superimposed with the oxide 230a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0160] Oxide 243a and oxide 243b are provided on oxide 230b. Oxide 243a and oxide 243b are provided separated by the conductor 260. Preferably, oxide 243 is provided superimposed on the conductor 242, and may be provided in a linear arrangement on oxide 230.

[0161] It is preferable that the oxide 243 (oxide 243a and oxide 243b) has the function of suppressing oxygen permeation. Placing the oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode and a drain electrode, and the oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and the oxide 230b. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. However, if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0162] As oxide 243, a metal oxide containing element M may be used. In particular, element M may be aluminum, gallium, yttrium, or tin. It is preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxide 243 is crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be suitably suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, the release of oxygen from oxide 230 can be suppressed.

[0163] It is preferable that the conductor 242a is provided in contact with the upper surface of the oxide 243a, and the conductor 242b is provided in contact with the upper surface of the oxide 243b. Conductors 242a and 242b function as the source electrode or drain electrode of the transistor 200, respectively. The conductor 242 may be provided arranged linearly on the oxide 230.

[0164] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0165] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0166] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 5D. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0167] The insulator 275 is provided covering the insulator 224, oxide 230, oxide 243, and conductor 242, and openings are formed in the regions where the insulator 250 and conductor 260 are provided. Preferably, the insulator 275 is provided in contact with the upper surface of the insulator 224, the side surface of the oxide 230, the side surface of the oxide 243, the side surface of the conductor 242, and the upper surface of the conductor 242. Preferably, the insulator 275 functions as a barrier insulating film that suppresses oxygen permeation. Preferably, the insulator 275 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 224 or oxide 230, and preferably has the function of capturing impurities such as hydrogen. As the insulator 275, for example, an insulator such as aluminum oxide or silicon nitride may be used.

[0168] By providing the insulator 275 as described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, it is possible to prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by oxygen contained in the insulator 280, which would increase its resistivity and reduce its field-effect mobility and on-current. In this way, by increasing the field-effect mobility and on-current of the transistor 200, the read speed of the memory device can be improved.

[0169] By providing an insulator 275 in the region sandwiched between insulators 212 and 283, in contact with insulators 280 and 224, and having the function of capturing impurities such as hydrogen, it is possible to capture impurities such as hydrogen contained in insulators 280 and 224, and to keep the amount of hydrogen in that region constant. In this case, it is preferable to use aluminum oxide or the like as the insulator 275.

[0170] The insulator 250 (insulator 250a and insulator 250b) functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper and side surfaces of the oxide 230b. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxides such as silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat.

[0171] Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0172] Furthermore, a metal oxide may be provided between the insulator 250b and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250b to the conductor 260. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250b to the conductor 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Additionally, oxidation of the conductor 260 by oxygen in the insulator 250b can be suppressed. For example, hafnium oxide can be used as the metal oxide.

[0173] Furthermore, the above-mentioned metal oxide may be configured to function as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 can be used as the above-mentioned metal oxide. In that case, the electrical resistance of the above-mentioned metal oxide can be reduced by depositing the conductor 260a by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0174] By having the above-mentioned metal oxide, the on-current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, by maintaining the distance between the conductor 260 and the oxide 230 through the physical thickness of the insulator 250b and the above-mentioned metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a laminated structure of the insulator 250b and the above-mentioned metal oxide, the physical distance between the conductor 260 and the oxide 230, and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0175] As the charge-holding layer 255, an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. For example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.

[0176] The charge-retaining layer 255 is positioned between insulators 250a and 250b. The charge-retaining layer 255 only needs to have the function of accumulating electrons. For example, an insulator having an electron trap is preferred. Electron traps can be formed by adding impurities or causing damage. Alternatively, an electron trap may be present at the interface between the charge-retaining layer 255 and insulator 250a, or at the interface between the charge-retaining layer 255 and insulator 250b. In this case, it is preferable that the charge-retaining layer 255 and insulator 250a and the charge-retaining layer 255 and insulator 250b are dissimilar junctions. If an electron trap is present at the interface between the charge-retaining layer 255 and insulator 250a, insulator 250b may not be required. Also, if an electron trap is present at the interface between the charge-retaining layer 255 and insulator 250b, insulator 250a may not be required. Furthermore, since the charge-holding layer 255 is shared between adjacent memory cells, it is preferable that electron movement within the charge-holding layer 255 is less likely to occur. However, if the charge-holding layer 255 is separated from adjacent memory cells, electron movement within the charge-holding layer 255 may occur. That is, the charge-holding layer 255 may be a semiconductor or a conductor.

[0177] Furthermore, in order to inject electrons into the charge-holding layer 255, it is preferable that the insulators 250a and 250b have a thickness that causes electron tunneling by the gate voltage or back gate voltage. However, in order to suppress electron outflow when the memory cell is holding data, it is preferable that the thickness is such that electron tunneling does not occur when the gate voltage or back gate voltage is not applied. However, since it is difficult to completely eliminate electron tunneling, it is sufficient to set the thickness so that electron tunneling does not occur to the extent that data can be held. For example, the thickness of insulators 250a and 250b may be 3 nm to 15 nm, preferably 4 nm to 10 nm. In addition, in order to suppress electron outflow, it is preferable to use an insulator with a large energy gap. For example, the energy gap of insulators 250a and 250b may be 6 eV to 10 eV, preferably 7 eV to 10 eV, and more preferably 8 eV to 10 eV.

[0178] Specifically, the charge-holding layer 255 can be a silicon nitride such as silicon nitride or silicon oxide nitride, which has a high defect level density. Alternatively, hafnium oxide may be used as the charge-holding layer 255.

[0179] As shown in Figure 5A, the conductor 260 is provided extending in the A3-A4 direction and functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 5B and 5C, the top surface of the conductor 260 substantially coincides with the top surfaces of the insulator 250 and the charge retention layer 255. In Figures 5B and 5C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0180] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0181] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0182] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0183] Furthermore, in transistor 200, the conductor 260 is formed in a self-aligning manner so as to fill the openings formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be placed in the region between the conductors 242a and 242b without the need for alignment.

[0184] Furthermore, as shown in Figure 5C, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, it becomes easier to apply the electric field of the conductor 260 to the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of the insulator 222, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0185] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0186] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0187] The insulator 280, like the insulator 224, preferably has an excess oxygen region or excess oxygen. Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, the insulator 280 may be made of an oxide containing silicon, such as silicon oxide or silicon oxynitride. By providing an insulator with excess oxygen in contact with the oxide 230, oxygen deficiencies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0188] The insulator 282 is positioned in contact with the upper surfaces of the conductor 260 and the insulator 280, and with the uppermost parts of the insulator 250 and the charge-holding layer 255. Preferably, the insulator 282 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, preferably the insulator 282 functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, for example, an insulator such as aluminum oxide may be used. By providing an insulator 282 in the region sandwiched between the insulator 212 and the insulator 283, in contact with the insulator 280, and having the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant.

[0189] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a silicon nitride film with high density and less susceptibility to porosity can be formed. Alternatively, as the insulator 283, silicon nitride deposited by CVD may be laminated on top of silicon nitride deposited by sputtering.

[0190] In the above, the configuration of transistor 200 corresponding to transistor 10 was described, but transistors 12 and 14 shown in the previous embodiment can also have a similar structure. That is, for transistors 12 and 14, the charge retention layer 255 and the insulator 250b in transistor 200 can be omitted. By configuring transistors 12 and 14 in this way, transistors with reduced off-current can be made. As a result, in the string shown in the previous embodiment, the leakage current between wiring BL and wiring SL can be reduced, and a semiconductor device with low power consumption can be provided.

[0191] <Materials for semiconductor devices> The following describes the materials that can be used in semiconductor devices.

[0192] <<Substrate>> For the substrate forming the transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides and substrates having metal oxides. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0193] <<Insulators>> Examples of insulators include oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides, which all possess insulating properties.

[0194] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0195] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0196] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0197] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0198] Furthermore, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0199] <<Conductors>> As conductors, it is preferable to use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys composed of the above metallic elements, or alloys combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0200] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0201] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0202] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride or tantalum nitride may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0203] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0204] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0205] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, in some cases, multiple elements mentioned above may be combined as element M.

[0206] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0207] <Classification of Crystal Structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 7A. Figure 7A is a diagram illustrating the classification of crystal structures of oxide semiconductors, specifically IGZO (metal oxides containing In, Ga, and Zn).

[0208] As shown in Figure 7A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." Furthermore, "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that the classification "Crystalline" excludes single crystals, poly crystals, and completely amorphous crystals. Furthermore, the category "Crystal" includes single crystals and poly crystals.

[0209] The structure within the thick border shown in Figure 7A is an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal."

[0210] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 7B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline". The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 7B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 7B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 7B is 500 nm.

[0211] As shown in Figure 7B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ = 31°. As shown in Figure 7B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0212] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 7C. Figure 7C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 7C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0213] As shown in Figure 7C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0214] <<Structure of Oxide Semiconductors>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 7A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0215] Here, we will explain the details of CAAC-OS, nc-OS, and a-like OS mentioned above.

[0216] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. Furthermore, a crystalline region is a region in which the atomic arrangement has periodicity. If the atomic arrangement is considered as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. In addition, CAAC-OS has a region in which multiple crystalline regions are connected in the a-b plane direction, and this region may have distortion. Distortion refers to a point in the region where multiple crystalline regions are connected where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In other words, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not have a clear orientation in the a-b plane direction.

[0217] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nm.

[0218] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) in which layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are stacked. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0219] When structural analysis of a CAAC-OS film is performed using, for example, an XRD instrument, an Out-of-plane XRD measurement using θ / 2θ scanning detects a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0220] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0221] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0222] A crystal structure in which clear grain boundaries are observed is called a polycrystalline structure. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more effectively than In oxide.

[0223] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0224] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (for example, regions between 1 nm and 10 nm, particularly regions between 1 nm and 3 nm). In other words, nc-OS has minute crystals. Since the size of these minute crystals is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm, these minute crystals are also called nanocrystals. Furthermore, nc-OS does not show any regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in Out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystal (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than that of the nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0225] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0226] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0227] [CAC-OS] CAC-OS is a material composition in which elements constituting a metal oxide are unevenly distributed, for example, at a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing the metal elements are mixed at a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0228] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0229] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of the In-Ga-Zn oxide, the first region is the region where [In] is greater than [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than [In] in the second region, and [Ga] is smaller than [Ga] in the second region. The second region is the region where [Ga] is greater than [Ga] in the first region, and [In] is smaller than [In] in the first region.

[0230] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0231] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0232] For example, in the CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using energy-dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0233] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. ｏｎ This enables high field-effect mobility (μ) and good switching operation.

[0234] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0235] <Transistors with Oxide Semiconductors> Next, we will explain the case in which the above oxide semiconductor is used in a transistor.

[0236] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0237] It is preferable to use an oxide semiconductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably １８ cm −３ or less, more preferably less than 1×10 １７ cm −３ , still more preferably less than 1×10 １６ cm −３ , still more preferably less than 1×10 １３ cm −３ , still more preferably less than 1×10 １２ cm −３ . When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0238] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the trap level density may also be low.

[0239] In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may become unstable.

[0240] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

[0241] <Impurities> Here, the effects of various impurities in the oxide semiconductor will be described.

[0242] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry)) are 2 × 10 １８ atoms / cm ３ or less, preferably 2 × 10 １７ atoms / cm ３ or less.

[0243] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1 × 10 １８ atoms / cm ３ or less, preferably 2 × 10 １６ atoms / cm ３ or less

[0244] In addition, when nitrogen is contained in the oxide semiconductor, carriers, electrons, are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is contained in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 5 × 10 １９ atoms / cm ３ preferably less than 5 × 10 １８ atoms / cm ３ more preferably 1 × 10 １８ atoms / cm ３ or less, even more preferably 5 × 10 １７ atoms / cm ３ or less.

[0245] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. ２０ atoms / cm ３ Less than 5 × 10 １９ atoms / cm ３ Less than, more preferably 1 × 10 １９ atoms / cm ３ Less than 5 × 10 １８ atoms / cm ３ Less than 1 × 10 １８ atoms / cm ３ Make it less than.

[0246] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0247] <<Other Semiconductor Materials>> The semiconductor materials that can be used for oxide 230 are not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as semiconductor materials. In particular, it is preferable to use layered materials that function as semiconductors as semiconductor materials.

[0248] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0249] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0250] As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specifically, as a transition metal chalcogenide applicable as oxide 230, molybdenum sulfide (typically MoS) ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0251] <Method for Manufacturing a Semiconductor Device> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention as shown in Figures 5A to 5D, will be explained using Figures 8A to 15A, 8B to 15B, 8C to 15C, and 8D to 15D.

[0252] Figures 8A to 15A each show a top view. Figures 8B to 15B each show a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figures 8A to 15A, and are also cross-sectional views of the transistor 200 in the channel length direction. Figures 8C to 15C each show a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figures 8A to 15A, and are also cross-sectional views of the transistor 200 in the channel width direction. Figures 8D to 15D each show a cross-sectional view of the area indicated by the dashed line A5-A6 in Figures 8A to 15A. Note that in the top views of Figures 8A to 15A, some elements have been omitted for clarity.

[0253] In the following, insulating materials for forming an insulator, conductive materials for forming a conductor, or semiconductor materials for forming a semiconductor can be deposited using sputtering, CVD, MBE, PLD, ALD, or other appropriate methods.

[0254] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0255] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo-CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD) methods depending on the source gas used.

[0256] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage these components. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in higher yields for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0257] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant.

[0258] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. In the PEALD method, the use of plasma allows for film deposition at even lower temperatures, which is sometimes preferable. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0259] Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form a film through a reaction on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and provide good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0260] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0261] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 8A to 8D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0262] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrode, improving the sputtering rate and film quality.

[0263] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0264] Next, an insulator 214 is deposited on the insulator 212 (see Figures 8A to 8D). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0265] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0266] By using aluminum oxide as the insulator 214, which has high hydrogen capture and hydrogen fixation capabilities, hydrogen contained in the insulator 216 and the like that formed on the insulator 214 can be captured or fixed, preventing the hydrogen from diffusing into the oxide 230.

[0267] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0268] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0269] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0270] Next, an opening is formed in the insulator 216 that reaches the insulator 214, extending in the A3-A4 direction. This opening may be appropriately provided to match the arrangement of the transistors 200. Note that the term "opening" includes, for example, grooves and slits. In addition, the term "opening" may refer to the region in which the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, then silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0271] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0272] After the opening is formed, a conductive film that will become the conductor 205a is deposited (see Figures 8A to 8D). The conductive film that will become the conductor 205a preferably contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy can be formed. The conductive film that will become the conductor 205a can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0273] In this embodiment, titanium nitride is formed as a conductive film that will become the conductor 205a. By using such a metal nitride as a layer beneath the conductor 205b, which will be described later, it is possible to suppress oxidation of the conductor 205b by the insulator 216 and the like. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0274] Next, a conductive film to become the conductor 205b is formed (see Figures 8A to 8D). As the conductive film to become the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc., can be used. The conductive film can be formed using plating, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, tungsten is formed as the conductive film to become the conductor 205b.

[0275] Next, by performing a CMP (Computerized Polymer Measure) treatment, a portion of the conductive film that will become conductor 205a and the conductive film that will become conductor 205b is removed, exposing the insulator 216. As a result, conductor 205a and conductor 205b remain only in the opening. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0276] Next, etching is performed to remove the upper part of the conductor 205b. As a result, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. Dry etching or wet etching can be used to etch the conductor 205b, but dry etching is preferable for microfabrication.

[0277] Next, a conductive film that will become conductor 205c is formed on the insulator 216, conductor 205a, and conductor 205b. It is desirable that the conductive film that will become conductor 205c contains a conductor that has the function of suppressing oxygen permeation, similar to the conductive film that will become conductor 205a.

[0278] In this embodiment, titanium nitride is formed as a conductive film that becomes the conductor 205c. By using such a metal nitride as the upper layer of the conductor 205b, oxidation of the conductor 205b by the insulator 222 and the like can be suppressed. Furthermore, even if a highly diffusible metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0279] Next, by performing CMP treatment, a portion of the conductive film that will become the conductor 205c is removed, exposing the insulator 216 (see Figures 8A to 8D). As a result, the conductors 205a, 205b, and 205c remain only in the opening. This makes it possible to form a conductor 205 with a flat top surface. Furthermore, the conductor 205b is enclosed by the conductors 205a and 205c. Therefore, it is possible to prevent impurities such as hydrogen from conductor 205b from diffusing out of conductors 205a and 205c, and to prevent oxygen from entering from outside conductors 205a and 205c and oxidizing conductor 205b. Note that in some cases, a portion of the insulator 216 may be removed by this CMP treatment.

[0280] Next, an insulator 222 is formed on the insulator 216 and the conductor 205 (see Figures 8A to 8D). It is preferable to form an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0281] The insulator 222 can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, hafnium oxide is deposited as the insulator 222 using the sputtering method. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in the insulator 222 can be reduced.

[0282] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0283] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0284] In this embodiment, as a heat treatment, after the insulator 222 is formed, the nitrogen gas and oxygen gas flow rate ratio is set to 4 slm:1 slm and the treatment is performed at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, this heat treatment can improve the crystallinity of the insulator 222. The heat treatment can also be performed at a later time, such as after the insulator 224 is formed.

[0285] Next, an insulator 224 is deposited on the insulator 222 (see Figures 8A to 8D). The insulator 224 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon oxide is deposited as the insulator 224 using the sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 224 can be reduced. Since the insulator 224 will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0286] Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use a device that has a power supply that generates high-density plasma using microwaves, for example. Alternatively, the substrate side may have a power supply that applies RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. By appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, heating treatment does not need to be performed.

[0287] Here, aluminum oxide may be deposited on the insulator 224, for example by sputtering, and then the aluminum oxide may be removed by CMP treatment until it reaches the insulator 224. This CMP treatment can planarize and smooth the surface of the insulator 224. Placing the aluminum oxide on the insulator 224 and performing the CMP treatment makes it easier to detect the end point of the CMP treatment. In addition, a part of the insulator 224 may be polished by the CMP treatment, which may reduce the thickness of the insulator 224, but this can be corrected by adjusting the thickness during the deposition of the insulator 224. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent deterioration of the coverage rate of the oxide that is deposited later and prevent a decrease in the yield of the semiconductor device. Furthermore, it is preferable to deposit aluminum oxide on the insulator 224 by sputtering because it is possible to add oxygen to the insulator 224.

[0288] Next, oxide films 230A and 230B are sequentially deposited on the insulator 224 (see Figures 8A to 8D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0289] The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods.

[0290] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0291] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0292] Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0293] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1. The deposition conditions and atomic ratios of each oxide film can be appropriately selected to match the desired properties of oxides 230a and 230b obtained through subsequent processing steps.

[0294] Next, an oxide film 243A is formed on the oxide film 230B (see Figures 8A to 8D). The oxide film 243A can be formed using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the atomic ratio of Ga to In in the oxide film 243A is greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4.

[0295] Furthermore, it is preferable to deposit the insulator 222, insulator 224, oxide film 230A, oxide film 230B, and oxide film 243A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus may be used. This allows for the deposition of the insulator 222, insulator 224, oxide film 230A, oxide film 230B, and oxide film 243A with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0296] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which oxide films 230A, 230B, and 243A do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0297] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water or other substances into the oxide film 230A, oxide film 230B, and oxide film 243A, etc.

[0298] In this embodiment, the heat treatment involves treating the material in a nitrogen atmosphere at 550°C for 1 hour, followed by a continuous treatment in an oxygen atmosphere at 550°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide films 230A, 230B, and 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities within the oxide film 230B.

[0299] Next, a conductive film 242A is deposited on the oxide film 243A (see Figures 8A to 8D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, oxide film 230B, and oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100°C to 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0300] Next, for example, using lithography, the oxide films 230A, 230B, 243A, and 242A are processed into island-like structures elongated in the A1-A2 direction to form oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B (see Figures 9A to 9D). The oxides 230a, 230b, oxide layer 243B, and conductive layer 242B may be appropriately arranged to match the arrangement of the transistors 200. Dry etching or wet etching can be used for this processing. Dry etching is suitable for microfabrication. The oxide films 230A, 230B, 243A, and conductive film 242A may be processed under different conditions. Note that in this process, the film thickness in areas of the insulator 224 that do not overlap with oxide 230a may become thinner. Furthermore, in this process, the insulator 224 may be superimposed with the oxide 230a to form an island-like structure.

[0301] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the resist mask is etched to process the conductor, semiconductor, or insulator into the desired shape. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, electron beams or ion beams can be used instead of the aforementioned light. When using electron beams or ion beams, a mask is unnecessary because the desired area of ​​the resist can be selected and irradiated with the beam. The resist mask can be removed by dry etching such as ashing, wet etching, wet etching after dry etching, or dry etching after wet etching.

[0302] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of that, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask is still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. For example, if the hard mask is formed of an insulating film, the hard mask may be left in place and used as a barrier insulating film.

[0303] Furthermore, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B are formed so that at least a portion of them overlaps with the conductor 205. It is also preferable that the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B are approximately perpendicular to the upper surface of the insulator 222. Having the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B approximately perpendicular to the upper surface of the insulator 222 allows for smaller area and higher density when providing multiple transistors 200. Alternatively, the angle between the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B and the upper surface of the insulator 222 may be low. In that case, the angle between the sides of the oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0304] Furthermore, by-products generated in the etching process may form in layers on the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B. In this case, the layered by-products will remain between oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, and the insulator 275 that will be deposited later. Similarly, layered by-products may remain on the insulator 224. Even if the insulator 275 is deposited with the layered by-products remaining on the insulator 224, the addition of oxygen to the insulator 224 will be hindered by the layered by-products. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 224.

[0305] Next, an insulator 275 is formed on the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B. (See Figures 10A to 10D.) The insulator 275 can be formed using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulator 275. For example, aluminum oxide can be formed as the insulator 275 by sputtering. By forming the insulator 275 by sputtering, oxygen can be added to the insulator 224.

[0306] Next, an insulating film that will become an insulator 280 is deposited on the insulator 275. The insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film that will become the insulator 280 using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, oxide layer 243B, and insulator 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0307] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat upper surface (see Figures 10A to 10D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0308] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. It is preferable that the opening be formed so as to overlap with the conductor 205. The formation of the opening creates the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b (see Figures 11A to 11D). In other words, the multiple conductors 242 and the multiple oxides 243 are separated by the opening and arranged in a linear fashion. At this point, the upper surface of the oxide 230b is exposed through the opening.

[0309] When forming the above-mentioned opening, the upper part of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the opening formation step or in a step different from the opening formation step.

[0310] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 275, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. In addition, each of these processes may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. Also, the processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B and the processing of a portion of the oxide 230b may be carried out under different conditions.

[0311] Here, it is preferable to remove impurities that have adhered to or diffused into the surface of oxide 230a, oxide 230b, etc. It is also preferable to remove damaged areas formed on the surface of oxide 230b by the dry etching described above. Examples of such impurities include those resulting from components contained in the insulator 280, insulator 275, and conductive layer 242B, components contained in the materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0312] In particular, impurities such as aluminum or silicon inhibit the CAAC-OS conversion of oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum or silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0313] Furthermore, the region of a metal oxide in which CAAC-OS formation is inhibited by impurities such as aluminum or silicon, resulting in a pseudo-amorphous oxide semiconductor (a-like OS), is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V Ｏ A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230b is reduced or removed.

[0314] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0315] To remove the impurities mentioned above, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and heat treatment. These cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process.

[0316] For wet cleaning, cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0317] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0318] Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides such as 230b.

[0319] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using dilute hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0320] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior of oxides 230a and 230b. Furthermore, it can improve the crystallinity of oxide 230b.

[0321] Previously, due to processes such as dry etching or the cleaning treatment described above, the film thickness of the insulator 224 in the region that overlaps with the opening and does not overlap with the oxide 230b may become thinner than the film thickness of the insulator 224 in the region that overlaps with the oxide 230b.

[0322] Heat treatment may be performed after etching or cleaning as described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby eliminating oxygen deficiency V Ｏ This can reduce the amount of heat. Furthermore, this heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0323] Next, an insulating film 250A is formed (see Figures 12A to 12D). A heat treatment may be performed before forming the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous formation of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and oxide 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0324] The insulating film 250A can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will become an insulator 250 that comes into contact with the oxide 230b in a later step, it is preferable that the hydrogen concentration is reduced in this manner.

[0325] Furthermore, it is preferable to deposit the insulating film 250A using the ALD method. The thickness of the insulator 250, which functions as a gate insulating film of the miniaturized transistor 200, needs to be extremely thin (for example, about 5 nm to 30 nm) and have minimal variation. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Therefore, the accuracy of the gate insulating film required by the miniaturized transistor 200 can be achieved. Also, as shown in Figures 12B and 12C, the insulating film 250A needs to be deposited with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be deposited with good coverage on the opening.

[0326] Furthermore, for example, when depositing an insulating film 250A using the PECVD method, the hydrogen-containing deposition gas is decomposed in the plasma, generating a large amount of hydrogen radicals. Through the reduction reaction of hydrogen radicals, oxygen is extracted from the oxide 230b, resulting in V Ｏ When H is formed, the hydrogen concentration in the oxide 230b increases. However, by depositing the insulating film 250A using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor is introduced and when the reactant is introduced. Therefore, by depositing the insulating film 250A using the ALD method, it is possible to prevent the hydrogen concentration in the oxide 230b from increasing. For example, as the insulating film 250A, a silicon oxide film such as silicon oxide can be deposited using the ALD method.

[0327] Next, microwave processing is performed in an oxygen-containing atmosphere (see Figures 12A to 12D). Here, the dotted lines shown in Figures 12B, 12C, and 12D represent microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. By using a high-density plasma, high-density oxygen radicals can be generated. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b. Furthermore, the above microwave processing is preferably performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Also, the oxygen flow rate ratio (O ２ / O ２ The treatment should be carried out with an oxygen plasma treatment of 50% or less, preferably between 10% and 30%. The treatment temperature should be 750°C or less, preferably 500°C or less, for example, around 400°C. After the oxygen plasma treatment, a continuous heat treatment may be performed without exposure to the outside air.

[0328] As shown in Figures 12B, 12C, and 12D, by performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 230bc. In other words, microwaves or high-frequency waves such as RF, oxygen plasma, etc., can be applied to region 230bc shown in Figure 6. Due to the action of plasma, microwaves, etc., the V of region 230bc Ｏ H can be cleaved and hydrogen H can be removed from region 230bc. In other words, in region 230bc, "V Ｏ H → H + V Ｏ The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V ＯThis reduces H and lowers the carrier concentration. Furthermore, by supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancy formed in region 230bc, the oxygen vacancy in region 230bc can be further reduced, and the carrier concentration can be lowered.

[0329] On the other hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Figure 6. As shown in Figures 12B, 12C, and 12D, conductors 242a and 242b shield against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, etc., so these effects do not extend to regions 230ba and 230bb. As a result, microwave processing does not cause V to be generated in regions 230ba and 230bb. Ｏ Since H is reduced and excessive oxygen supply does not occur, a decrease in carrier concentration can be prevented.

[0330] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V Ｏ By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, and the n-type configuration can be maintained. This suppresses variations in the electrical characteristics of transistor 200 and prevents variations in the electrical characteristics of transistor 200 within the substrate plane.

[0331] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability. Additionally, it is possible to provide a semiconductor device with good electrical characteristics.

[0332] Alternatively, a heat treatment may be performed while maintaining a reduced pressure state after microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, oxide 230b, and oxide 230a. In addition, some of the hydrogen may be gettered by the conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from the insulating film 250A, oxide 230b, and oxide 230a. The heat treatment temperature is preferably 300°C to 500°C.

[0333] Furthermore, by modifying the film quality of the insulating film 250A through microwave treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., through the insulator 250a to the oxide 230b, oxide 230a, etc. can be suppressed.

[0334] Next, a charge-retaining film 255A is deposited (see Figures 13A to 13D). The charge-retaining film 255A can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, the charge-retaining film 255A can be deposited using the same method as the insulating film 250A.

[0335] Furthermore, it is preferable to deposit the charge-retaining film 255A using the ALD method. This allows the charge-retaining film 255A to be deposited with a thin film thickness and with good coverage over the openings. For example, a silicon nitride film, such as silicon nitride, can be deposited as the charge-retaining film 255A using the ALD method.

[0336] Next, the insulating film 250B is deposited (see Figures 13A to 13D). The insulating film 250B can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, the insulating film 250B can be deposited using the same method as the insulating film 250A.

[0337] Furthermore, it is preferable to deposit the insulating film 250B using the ALD method. This allows the insulating film 250B to be deposited with a thin film thickness and with good coverage over the openings. For example, a silicon oxide film such as silicon oxide can be deposited as the insulating film 250B using the ALD method.

[0338] Furthermore, a barrier insulating film having the function of suppressing oxygen diffusion may be formed on top of the insulating film 250B. This suppresses the diffusion of oxygen contained in the insulator 250b into the conductor 260. In other words, it is possible to suppress the oxidation of the conductor 260 by oxygen contained in the insulator 250b. For example, the insulating film 250B can be made using the same material as the insulator 222, and can be deposited using the ALD method with hafnium oxide or the like.

[0339] Furthermore, it is preferable to continuously deposit the insulating film 250A, the charge-holding film 255A, the insulating film 250B, and the barrier insulating film without exposure to the atmospheric environment. For example, a multi-chamber processing apparatus may be used. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities such as hydrogen or moisture from the atmospheric environment from adhering to these films, and the vicinity of the interfaces of these films can be kept clean.

[0340] In the process shown in Figure 12, microwave treatment was performed after the deposition of the insulating film 250A, but the present invention is not limited to this. For example, microwave treatment may be performed before deposition of the insulating film 250A, before or after deposition of the charge-holding film 255A, before or after deposition of the insulating film 250B, or before or after deposition of the barrier insulating film. Furthermore, these microwave treatments may be performed not only once but multiple times. In addition, when the deposition of the insulating film 250A, insulating film 250B, and the barrier insulating film is performed by the PEALD method, the microwave treatment may be replaced by treatment with plasma-excited reactant (oxidizing agent) of the PEALD apparatus. Here, oxygen gas may be used as the reactant (oxidizing agent).

[0341] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, the conductive film to become conductor 260a and the conductive film to become conductor 260b are deposited using the CVD method.

[0342] Next, by CMP processing, the insulating film 250A, the charge-retaining film 255A, the insulating film 250B, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished until the insulator 280 is exposed, thereby forming the insulator 250a, the charge-retaining layer 255, the insulator 250b, and the conductor 260 (conductor 260a and conductor 260b) (see Figures 14A to 14D). As a result, the insulator 250a is formed to cover the openings that reach the oxide 230b and the inner walls (side walls and bottom surface) of the grooves in the oxide 230b. The conductor 260 is formed to fill the openings and grooves via the insulator 250 and the charge-retaining layer 255. The charge-retaining layer 255 and the insulator 250b are formed between the insulator 250a and the conductor 260.

[0343] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be formed continuously without exposure to the atmosphere.

[0344] Next, an insulator 282 is formed on the insulator 250, the charge-holding layer 255, the conductor 260, and the insulator 280 (see Figures 15A to 15D). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 282 can be reduced. Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 while the film is being deposited. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate.

[0345] In this embodiment, aluminum oxide is deposited as the insulator 282 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0346] Next, an insulator 283 is formed on the insulator 282 (see Figures 5A to 5D). The insulator 283 can be formed using sputtering, CVD, MBE, PLD, or ALD. It is preferable to form the insulator 283 using sputtering. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be formed using sputtering, and then silicon nitride may be formed on the silicon nitride using CVD. By sandwiching the transistor 200 between the highly barrier insulator 283 and insulator 212, moisture and hydrogen can be prevented from entering from the outside.

[0347] Next, a heat treatment may be performed. In this embodiment, the treatment is carried out in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment diffuses the oxygen added by the formation of the insulator 282 into the insulators 280 and 250, and selectively supplies it to the channel-forming region of the oxide 230. Note that this heat treatment may be performed not only after the formation of the insulator 283, but also after the formation of the insulator 282, etc.

[0348] As described above, a semiconductor device having the transistor 200 shown in Figures 5A to 5D can be fabricated. As shown in Figures 8A to 15A, 8B to 15B, 8C to 15C, and 8D to 15D, the transistor 200 can be fabricated using the semiconductor device fabrication method shown in this embodiment.

[0349] <Microwave Processing Equipment> Below, we will describe microwave processing equipment that can be used in the above-mentioned semiconductor device manufacturing method.

[0350] First, we will explain the configuration of a manufacturing apparatus that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 16, 17, and 18.

[0351] Figure 16 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0352] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0353] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0354] The back pressure (total pressure) of the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ −４ Pa or less, preferably 3 × 10 −５ Pa or less, more preferably 1 × 10 −５ The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) in the transport chamber 2704 and each chamber with a mass-to-charge ratio (m / z) of 18 shall be, for example, 3 × 10⁻⁶. −５ Pa or less, preferably 1 × 10 −５ Pa or less, more preferably 3 × 10 −６ The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. −５ Pa or less, preferably 1 × 10 −５ Pa or less, more preferably 3 × 10 −６ The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. −５ Pa or less, preferably 1 × 10 −５ Pa or less, more preferably 3 × 10 −６ It should be less than or equal to Pa.

[0355] The total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also known as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0356] Furthermore, it is desirable that the transport chamber 2704 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 2704 and each chamber should be 3 × 10 −６ Pa・m ３ / s or less, preferably 1 × 10 −６ Pa・m ３ The value should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 18 is 1 × 10⁻⁶. −７ Pa・m ３ / s or less, preferably 3 × 10 −８ Pa・m ３ The value should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 28 is 1 × 10⁻⁶. −５ Pa・m ３ / s or less, preferably 1 × 10 −６ Pa・m ３ The value should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10⁻⁶. −６ Pa・m ３ / s or less, preferably 1 × 10 −６ Pa・m ３ Set to / s or less.

[0357] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on both external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system through tiny holes or faulty seals. Internal leaks are caused by leaks from valves and other partitions within the vacuum system, or by gases released from internal components. To keep the leak rate below the values ​​mentioned above, countermeasures must be taken from both external and internal leaks.

[0358] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gasket is made of a metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have better adhesion than O-rings and can reduce external leakage. In addition, by using a passivation of metal coated with iron fluoride, aluminum oxide, chromium oxide, etc., the release of gas containing impurities from the metal gasket is suppressed, and internal leakage can be reduced.

[0359] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less gas containing impurities, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned components may be coated with an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the amount of gas emitted.

[0360] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0361] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0362] Adsorbent materials present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed on the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbent materials present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbent materials. Baking can increase the desorption rate of adsorbent materials by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if adsorbent materials are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbent materials can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0363] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances in the transport chamber 2704 and each chamber can be removed, and impurities present in the transport chamber 2704 and each chamber can be reduced. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the period for maintaining the pressure should be 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0364] Next, the chambers 2706b and 2706c will be described using the cross-sectional schematic diagram shown in FIG. 17.

[0365] The chambers 2706b and 2706c are, for example, chambers capable of performing microwave treatment on the object to be processed. Note that the chambers 2706b and 2706c differ only in the atmosphere during microwave treatment. Since the other configurations are common, they will be described together below.

[0366] The chambers 2706b and 2706c include a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also, outside the chambers 2706b and 2706c, etc., a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0367] The high-frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is arranged in contact with the dielectric plate 2809. Also, the gas supply source 2801 is connected to the mode converter 2805 via the valve 2802. Then, gas is sent to the chambers 2706b and 2706c by the gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c via the valve 2818 and the exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via the matching box 2815.

[0368] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from the high-frequency power supply 2816. Further, it has a heating mechanism 2813 inside and has a function of heating the substrate 2811.

[0369] As the vacuum pump 2817, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may be used. It is particularly preferable to use a cryopump and a cryotrap because water can be efficiently exhausted.

[0370] As the heating mechanism 2813, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as heated gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs a heat treatment using high-temperature gas. As the gas, an inert gas is used.

[0371] The gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas having a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gas (such as argon gas) may be used.

[0372] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0373] The high-frequency generator 2803 has the function of generating microwaves in the range of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals corresponding to the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0374] At this time, the substrate 2811 can be modified by ions and radicals generated in the high-density plasma 2810, which can alter the film on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias to the substrate, ions in the high-density plasma 2810 can be efficiently delivered to the back of openings in the film on the substrate 2811.

[0375] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0376] Next, chambers 2706a and 2706d will be described using the schematic cross-sectional diagrams shown in Figure 18.

[0377] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both chambers, they will be described together below.

[0378] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. A gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside chambers 2706a and 2706d.

[0379] The gas supply source 2821 is connected to the gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via a valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0380] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks at wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0381] For example, the lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0382] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0383] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0384] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0385] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0386] According to one aspect of the present invention, a semiconductor device with a large memory capacity can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0387] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, configurations and methods shown in other embodiments, or configurations and methods shown in the examples.

[0388] (Embodiment 3) In this embodiment, one form of a semiconductor device will be described with reference to Figures 19 to 20.

[0389] [Storage Device 1] Figure 19 shows an example of a semiconductor device (storage device) according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, transistors 200 and 201 are provided above transistor 300. Transistor 200 can be the same transistor 200 described in the previous embodiment. Transistor 201 corresponds to transistor 12 or transistor 14 shown in the previous embodiment and has the same structure as transistor 200, except that it does not have a charge retention layer 255 and an insulator 250b.

[0390] In the semiconductor device shown in Figure 19, the transistor 300 is provided with a structure similar to that of the semiconductor device shown in Embodiment 1. That is, multiple strings as shown in Embodiment 1 are arranged on the transistor 300. In this string, multiple transistors 200 are provided between two transistors 201, and their sources and drains are connected in series.

[0391] As described in the previous embodiment, metal oxides such as In-M-Zn oxide can be deposited on a substrate using sputtering or the like. Therefore, a memory cell array formed by transistors 200 and 201 can be placed on top of a drive circuit consisting of transistors 300 and the like formed on a silicon substrate. This reduces the area occupied by peripheral circuits on a single chip and increases the area occupied by the memory cell array, thereby increasing the storage capacity of the semiconductor device.

[0392] Furthermore, the memory device shown in Figure 19 can be configured as a memory cell array by arranging memory cells in a matrix.

[0393] <Transistor 300> The transistor 300 is provided on the substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0394] In Figure 19, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0395] Note that the transistor 300 shown in Figure 19 is just one example, and its structure is not limited to this example. Any appropriate transistor can be used depending on the circuit configuration and driving method.

[0396] <Wiring Layer> Between each structure, a wiring layer may be provided, which includes an interlayer film, wiring, and plugs. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor that functions as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0397] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Conductors 328 and 330 are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 function as plugs or wiring.

[0398] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0399] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 19, the insulator 350, the insulator 352, and the insulator 354 are sequentially stacked and provided. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0400] An insulator 210 is provided on the insulator 354 and the conductor 356. On the insulator 210, the insulator 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, the insulator 282, and the insulator 283 shown in the previous embodiment are provided, and the transistors 200 and the transistor 201 are formed in these insulators.

[0401] Further, a conductor 240 that functions as a plug is provided in contact with the upper surface of the source electrode or the drain electrode of the transistor 201. Note that an insulator 241 is provided in contact with the side surface of the conductor 240 that functions as a plug. Further, a conductor 246 that is electrically connected to the conductor 240 and functions as a wiring is provided on the insulator 283 and on the conductor 240. Further, an insulator 274 is provided in a region on the insulator 283 that does not overlap with the insulator 280. Further, an insulator 286 is provided on the conductor 246 and on the insulator 283. An insulator 287 is provided on the insulator 286.

[0402] Examples of the insulator that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc. that have insulating properties.

[0403] For example, by using a material with a low relative permittivity for the insulator that functions as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0404] For example, it is preferable that insulators 210, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxidnitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxidnitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0405] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0406] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0407] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0408] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, conductor 330, and conductor 356, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0409] <Wiring or plugs in the layer with oxide semiconductors> When oxide semiconductors are used in transistors 200 and 201, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0410] For example, in Figure 19, an insulator 241 may be provided between the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulators 275, 282, and 283, the insulator 224 and the transistor 200 can be sealed by the barrier insulator.

[0411] In other words, by providing the insulator 241, it is possible to suppress the absorption of excess oxygen present in the insulators 224 and 280 into the conductor 240. Furthermore, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, into the transistor 200 via the conductor 240.

[0412] Furthermore, as the insulator 241, an insulating material having the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferable. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide are preferred. Silicon nitride is particularly preferred because of its high barrier properties against hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0413] Furthermore, as shown in the above embodiment, the transistor 200 may be configured to be sealed with insulators 212, 214, 282, and 283. This configuration reduces the amount of hydrogen contained in insulator 274 and the like that can be mixed into insulator 280 and the like.

[0414] Here, the conductor 240 penetrates the insulators 283 and 282, but as described above, the insulator 241 is provided in contact with the conductor 240. This reduces the amount of hydrogen that enters the inside of the insulators 212, 214, 282, and 283 via the conductor 240. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, and 241, and the intrusion of impurities such as hydrogen contained in the insulator 274, etc., from the outside is reduced.

[0415] Furthermore, it is preferable to use an insulator 286 that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Here, the upper surface and the side surface of the conductor 246 are in contact with the insulator 286, and the lower surface of the conductor 246 is in contact with the insulator 283. In other words, the conductor 246 can be configured to be surrounded by the insulator 283 and the insulator 286. By using such a configuration, the permeation of oxygen from the outside can be suppressed and oxidation of the conductor 246 can be prevented. It is also preferable because it can prevent impurities such as water and hydrogen from diffusing from the conductor 246 to the outside.

[0416] <Dicing Lines> The following section describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when a large-area substrate is divided into semiconductor elements to extract multiple semiconductor devices in chip form. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0417] Here, for example, as shown in Figure 19, it is preferable to design the region where the insulator 283 and the insulator 212 are in contact to overlap with the dicing line. In other words, openings are provided in the insulators 282, 280, 275, 224, 222, 216, and 214 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0418] In other words, in the openings provided in insulators 282, 280, 275, 224, 222, 216, and 214, insulator 212 and insulator 283 are in contact. For example, in this case, insulator 212 and insulator 283 may be formed using the same material and method. By providing insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride is preferably used.

[0419] This structure allows transistors 200 and 201 to be enclosed by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor elements shown in this embodiment are formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into transistor 200.

[0420] Furthermore, this structure prevents excess oxygen from the insulators 280 and 224 from diffusing to the outside. Therefore, excess oxygen from the insulators 280 and 224 is efficiently supplied to the oxide in which the channel in transistor 200 is formed. This oxygen reduces oxygen deficiencies in the oxide in which the channel in transistor 200 is formed. As a result, the oxide in which the channel in transistor 200 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 200 can be suppressed and reliability can be improved.

[0421] Furthermore, the cell array, having multiple strings, may be configured not only in a planar arrangement but also by stacking them. Figure 20 shows a cross-sectional view of a configuration in which n layers of cell array 610 are stacked. As shown in Figure 20, by stacking multiple cell arrays (cell array 610_1 to cell array 610_n), cells can be integrated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be constructed. In this way, it is possible to achieve high integration of memory cells and provide a semiconductor device with a large storage capacity.

[0422] The configurations and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments.

[0423] (Embodiment 4) In this embodiment, a memory device (hereinafter sometimes referred to as an OS memory device) to which a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) according to one aspect of the present invention is applied will be described with reference to Figures 21A, 21B and 22.

[0424] <Example of Storage Device Configuration> Figure 21A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0425] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The wiring is connected to the memory cells of the memory cell array 1470. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0426] The storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The storage device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0427] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0428] An example of a circuit diagram of the memory cell array 1470 is shown in Figure 22. In the memory cell array shown in Figure 22, n strings and m wirings WL are arranged orthogonally to each other, and m × n memory cells MC are arranged in a matrix. Here, n and m are natural numbers of 2 or greater.

[0429] The string of the memory cell array 1470 has the sources and drains of m memory cells MC connected in series, with the drain of transistor ST1 connected to one end of the m memory cells MC and the source of transistor ST2 connected to the other end of the m memory cells MC. The string has the same structure as the string shown in Embodiment 1, with the memory cells MC corresponding to transistor 10, transistor ST1 to transistor 14, and transistor ST2 to transistor 12. Therefore, the detailed configuration of the string and the memory cell array 1470 can be found by referring to the description of the previous embodiment.

[0430] At both ends of the string, there are wires SL connected to the source of transistor ST1 and wires BL connected to the drain of transistor ST2. For example, wires BL_1 to BL_n may be configured to be connected to the column circuit 1430. Alternatively, for example, wires SL_1 to SL_n may also be configured to be connected to the column circuit 1430.

[0431] Furthermore, the gates of the memory cells MC in each string are connected to wirings WL_1 to WL_m for each row, forming m pages. In addition, the gates of transistors ST1 in each string are connected to wiring SGS, and the gates of transistors ST2 in each string are connected to wiring SGB. For example, wirings WL_1 to WL_m, wiring SGS, and wiring SGB may be configured to be connected to the row circuit 1420.

[0432] The memory cell array 1470 may also be configured to have multiple blocks, with each block consisting of n strings as shown in Figure 22.

[0433] Although Figure 21A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 21B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0434] As described in the previous embodiment, metal oxides such as In-M-Zn oxide can be deposited on a substrate using sputtering or the like. Therefore, the memory cell array 1470 can be placed on top of the peripheral circuit 1411 formed on the silicon substrate. This reduces the area occupied by the peripheral circuit on a single chip and increases the area occupied by the memory cell array, thereby increasing the storage capacity of the semiconductor device.

[0435] Alternatively, multiple memory cell arrays 1470 can be stacked. By stacking multiple memory cell arrays 1470, memory cells can be integrated and arranged without increasing the area occupied by each memory cell array 1470. In other words, a 3D cell array can be constructed. In this way, it is possible to achieve high integration of memory cells and provide a semiconductor device with a large storage capacity.

[0436] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary.

[0437] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0438] (Embodiment 5) In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown using Figures 23A and 23B. Multiple circuits (systems) are mounted on the chip 1200. The technology of integrating multiple circuits (systems) onto a single chip in this way is sometimes called System on Chip (SoC).

[0439] As shown in Figure 23A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog processing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0440] The chip 1200 is provided with bumps (not shown) and connects to the first surface of the printed circuit board (PCB) 1201, as shown in Figure 23B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connect to the motherboard 1203.

[0441] The motherboard 1203 may be provided with storage devices such as DRAM 1221 and flash memory 1222. It is preferable to use the semiconductor device shown in the previous embodiment as the flash memory 1222. By using the semiconductor device shown in the previous embodiment as the flash memory 1222, the storage capacity of the flash memory 1222 can be increased.

[0442] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing and multiply-accumulate operations. By providing image processing circuits and multiply-accumulate operation circuits on the GPU 1212, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0443] Furthermore, since the CPU 1211 and GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations are performed by the GPU 1212.

[0444] The analog arithmetic unit 1213 includes either an A / D (analog-to-digital) conversion circuit or a D / A (digital-to-analog) conversion circuit, or both. Alternatively, the analog arithmetic unit 1213 may also be provided with the sum-of-accumulate circuit.

[0445] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0446] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI® (High-Definition Multimedia Interface).

[0447] The network circuit 1216 has a function to control connections with LANs (Local Area Networks), etc. It may also have a circuit for network security.

[0448] The above-mentioned circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at a low cost.

[0449] A PCB 1201 equipped with a chip 1200 having a GPU 1212, a motherboard 1203 equipped with a DRAM 1221, and a flash memory 1222 can be called a GPU module 1204.

[0450] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN). Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 as an AI system module.

[0451] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0452] (Embodiment 6) This embodiment describes an application example of a storage device using the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 24A to 24E schematically show some configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memory.

[0453] Figure 24A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105, etc.

[0454] Figure 24B is a schematic diagram of the external appearance of an SD card, and Figure 24C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. By providing a memory chip 1114 on the back side of the circuit board 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114, etc.

[0455] Figure 24D is a schematic diagram of the external appearance of the SSD, and Figure 24E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1154, etc.

[0456] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0457] (Embodiment 7) A ROM for holding the program of a microcontroller can be formed using a semiconductor device according to one aspect of the present invention. As shown in the previous embodiment, the ROM can be formed by stacking it on a silicon substrate on which a CPU or the like is provided, so the microcontroller chip can be made smaller. Figures 25A to 25G show specific examples of electronic equipment having a microcontroller equipped with a memory device according to one aspect of the present invention.

[0458] <Electronic Devices and Systems> A microcontroller according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book readers, television equipment, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems, and sound playback devices. Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0459] An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images, information, etc. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0460] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0461] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0462] [Information Terminal] Figure 25A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. A touch panel is provided on the display unit 5102 as an input interface, and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the mobile phone. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0463] Figure 25B shows a notebook-type information terminal 5200. The notebook-type information terminal 5200 has a terminal body 5201, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook-type information terminal can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the notebook-type information terminal. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0464] In the above, smartphones and notebook computers were used as examples of electronic devices, as illustrated in Figures 25A and 25B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0465] [Game Machine] Figure 25C shows a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Housings 5302 and 5303 can be removed from housing 5301. By attaching the connection unit 5305 provided on housing 5301 to another housing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). At this time, housings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. A microcontroller according to one aspect of the present invention can be incorporated into chips provided on the circuit boards of housings 5301, 5302, and 5303.

[0466] Figure 25D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0467] By using a miniaturized microcontroller according to one aspect of the present invention in game consoles such as portable game consoles 5300 and home game consoles 5400, the limited space inside the game console can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used in the storage of a portable game console. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0468] Figures 25C and 25D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the microcontroller according to one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the microcontroller according to one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0469] [Large-scale computers] A microcontroller according to one aspect of the present invention can be applied to large-scale computers.

[0470] Figure 25E shows a supercomputer 5500, which is an example of a large-scale computer. Figure 25F shows a rack-mount computer 5502 that is part of the supercomputer 5500.

[0471] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. The computers 5502 are provided with a plurality of circuit boards 5504, on which a microcontroller according to one aspect of the present invention can be mounted. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space of the large computer can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the large computer. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0472] Figures 25E and 25F illustrate a supercomputer as an example of a large computer, but the large computers to which the microcontroller according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the microcontroller according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0473] [Electrical Appliances] Figure 25G shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0474] By applying a miniaturized microcontroller according to one aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0475] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0476] The electronic devices described in this embodiment, their functions, and their effects can be appropriately combined with descriptions of other electronic devices.

[0477] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0478] BGL: Wiring, BL: Wiring, BL_1: Wiring, BL_n: Wiring, MC: Memory cell, NWL: Wiring, SGB: Wiring, SGS: Wiring, SL: Wiring, SL_1: Wiring, SL_n: Wiring, SWL: Wiring, ST1: Transistor, ST2: Transistor, WL: Wiring, WL_1: Wiring, WL_m: Wiring, 10: Transistor, 12: Transistor, 14: Transistor, 20: Oxide, 20a: Region, 20b: Region, 22: Conductor, 24: Insulator, 26: Insulator, 26a: Insulator, 26b: Insulator, 28: Charge retention layer, 30: Conductor, 30a: Conductor, 30b: Conductor, 200: Transistor, 200a: Transistor, 200b: Transistor, 200c: Transistor, 201: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230ba: Region, 230bb: Region, 230bc: Region, 240: Conductor, 241: Insulator, 242: Conductor, 242a: Conductor 242A: conductive film, 242b: conductor, 242B: conductive layer, 243: oxide, 243a: oxide, 243A: oxide film, 243b: oxide, 243B: oxide layer, 246: conductor, 250: insulator, 250a: insulator, 250A: insulating film, 250b: insulator, 250B: insulating film, 255: charge retention layer, 255A: charge retention film, 260: conductor, 260a: conductor, 260b: conductor, 274: insulator, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 286: insulator, 287: insulator, 300: transistor, 311: substrate, 31 3: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 610: Cell array, 610_n: Cell array, 610_1: Cell array, 1100: USB memory, 1101: Housing, 1102: Cap, 1103: USB connector, 1104: Circuit board, 1105: Memory chip, 1106: Controller chip, 1110: SD card1111: Enclosure, 1112: Connector, 1113: Circuit board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: Enclosure, 1152: Connector, 1153: Circuit board, 1154: Memory chip, 1155: Memory chip, 1156: Controller chip, 1200: Chip, 1201: PCB, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog processing unit, 1214: Memory controller, 1215: Interface, 1216: Network 1221: Circuit, 1222: DRAM, 1222: Flash memory, 1400: Storage device, 1411: Peripheral circuit, 1420: Row circuit, 1430: Column circuit, 1440: Output circuit, 1460: Control logic circuit, 1470: Memory cell array, 2700: Manufacturing equipment, 2701: Atmospheric side substrate supply chamber, 2702: Atmospheric side substrate transport chamber, 2703a: Load lock chamber, 2703b: Unload lock chamber, 2704: Transport chamber, 2706a: Chamber, 2706b: Chamber, 2706c: Chamber, 2706d: Chamber, 2761: Cassette port T, 2762: Alignment port, 2763a: Transport robot, 2763b: Transport robot, 2801: Gas supply source, 2802: Valve, 2803: High-frequency generator, 2804: Waveguide, 2805: Mode converter, 2806: Gas tube, 2807: Waveguide, 2808: Slot antenna plate, 2809: Dielectric plate, 2810: High-density plasma, 2811: Substrate, 2812: Substrate holder, 2813: Heating mechanism, 2815: Matching box, 2816: High-frequency power supply, 2817: Vacuum pump, 2818: Valve, 2819: Exhaust port, 2820: Lamp, 28 21: Gas supply source, 2822: Valve, 2823: Gas inlet, 2824: Circuit board, 2825: Circuit board holder, 2826: Heating mechanism, 2828: Vacuum pump, 2829: Valve, 2830: Exhaust port, 5100: Information terminal, 5101: Housing, 5102: Display unit, 5200: Notebook-type information terminal, 5201: Main unit, 5202: Display unit, 5203: Keyboard, 5300: Portable game console, 5301: Housing, 5302: Housing, 5303: Housing, 5304: Display unit, 5305: Connection unit, 5306: Operation keys, 5400: Home game console, 5402: Controller,5500: Supercomputer, 5501: Rack, 5502: Calculator, 5504: Circuit board, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment

Claims

an oxide disposed on the substrate; a plurality of first conductors disposed on the oxide; a first insulator disposed on the plurality of first conductors, the first insulator having a plurality of openings formed therein and overlapping regions between the plurality of first conductors; a plurality of second insulators disposed in the plurality of openings, respectively; a plurality of charge retention layers disposed on the plurality of second insulators, respectively; a plurality of third insulators disposed on the plurality of charge retention layers, respectively; a plurality of second conductors respectively disposed on the plurality of third insulators; Semiconductor device. 　 In claim 1, The semiconductor device, wherein the plurality of first conductors are arranged in a straight line parallel to the top surface of the oxide. 　 In claim 1 or claim 2, the plurality of second insulators and the plurality of third insulators are oxides containing silicon; The semiconductor device, wherein the plurality of charge retention layers are a nitride containing silicon. 　 In claim 1 or claim 2, The semiconductor device, wherein the plurality of charge retention layers are conductors. 　 In any one of claims 1 to 4, The second insulator contacts an upper surface of the oxide and a side surface of the first insulator. 　 In any one of claims 1 to 5, a plurality of third conductors are respectively arranged below the oxide, overlapping the plurality of second conductors; 　 An oxide film is formed on the substrate, forming a first conductive film on the oxide film; The oxide film and the first conductive film are processed into an island shape to form an oxide and a first conductive material; forming a first insulator over the oxide and the first conductor; removing a portion of the first insulator to form a plurality of openings overlying the first conductor; removing a portion of the first conductor overlapping the plurality of openings to form a plurality of linearly arranged second conductors; and exposing the oxide in regions between the plurality of second conductors; forming a first insulating film in contact with an upper surface of the oxide; Microwave treatment is performed in an oxygen-containing atmosphere. forming a second insulating film on the first insulating film; forming a third insulating film on the second insulating film; forming a second conductive film on the third insulating film; performing a CMP process on the first insulating film, the second insulating film, the third insulating film, and the second conductive film until an upper surface of the first insulator is exposed, thereby forming a plurality of second insulators, a plurality of third insulators, a plurality of fourth insulators, and a plurality of third conductors, each of which is disposed in a region between the plurality of second conductors; A method for manufacturing a semiconductor device. 　 In claim 7, the first insulating film and the third insulating film are oxide films containing silicon, The method for manufacturing a semiconductor device, wherein the second insulating film is a nitride film containing silicon.

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