Semiconductor optical device and method for manufacturing the same

Abstract

To provide a semiconductor optical device capable of improving heat dissipation and a method of manufacturing the same.SOLUTION: A semiconductor optical device includes a substrate having an optical waveguide, a gain section formed of a III-V compound semiconductor, having an optical gain, bonded to an upper surface of the substrate, and including a first mesa, and a first wiring line electrically connected to the gain section. The first mesa of the gain section is optically coupled to the optical waveguide. The substrate includes a first layer, a second layer, and a third layer. A thermal conductivity of the first layer is higher than a thermal conductivity of the second layer. The second layer is stacked on the first layer. The third layer is stacked on the second layer and includes the optical waveguide. A recess that is sunk from the upper surface of the substrate in a thickness direction of the substrate.is provided in the substrate at a position spaced from the first mesa. The recess penetrates through the third layer and extends to the second layer in the thickness direction. The first wiring line extends from the first mesa of the gain section to the recess.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present disclosure relates to a semiconductor optical element and a method for manufacturing the same.

Background Art

[0002] A technique is known in which a semiconductor element formed of a group III-V compound semiconductor is bonded to a substrate such as an SOI (Silicon On Insulator) substrate (so-called silicon photonics) on which a waveguide is formed (for example, Patent Document 1).

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a semiconductor optical element is operated, heat is generated. If the temperature rises, the characteristics may deteriorate. In order to suppress the deterioration of the characteristics, it is important to improve the heat dissipation property and suppress the temperature rise. In Non-Patent Document 1, the heat dissipation property is improved by a shunt structure in which polysilicon having a high thermal conductivity is provided on the substrate.

[0005] A ridge mesa structure is formed to enhance optical confinement. Since the polysilicon is separated from the ridge mesa, heat generated near the ridge mesa is difficult to transfer, and the heat dissipation property is insufficient. Therefore, an object is to provide a semiconductor optical element capable of enhancing heat dissipation and a method for manufacturing the same.

Means for Solving the Problems

[0006] The semiconductor optical element according to the present disclosure includes a substrate having an optical waveguide, a gain portion formed of a group III-V compound semiconductor, having optical gain, and bonded to the upper surface of the substrate and having a first mesa, and a first wiring electrically connected to the gain portion. The first mesa of the gain portion is optically coupled to the optical waveguide. The substrate has a first layer, a second layer, and a third layer. The thermal conductivity of the first layer is higher than that of the second layer. The second layer is laminated on the first layer. The third layer is laminated on the second layer and has the optical waveguide. A recess recessed in the thickness direction of the substrate from the upper surface of the substrate is provided at a position of the substrate separated from the first mesa. The recess penetrates the third layer and extends in the thickness direction with respect to the second layer. The first wiring extends from the first mesa of the gain portion to the recess.

[0007] The method for manufacturing a semiconductor optical element according to the present disclosure includes a step of bonding a gain portion formed of a group III-V compound semiconductor and having optical gain to the upper surface of a substrate having an optical waveguide, a step of forming a first mesa on a portion of the gain portion above the optical waveguide, a step of forming a recess recessed in the thickness direction of the substrate from the upper surface of the substrate at a position of the substrate separated from the first mesa, and a step of forming a first wiring electrically connected to the gain portion. The substrate has a first layer, a second layer, and a third layer. The thermal conductivity of the first layer is higher than that of the second layer. The second layer is laminated on the first layer. The third layer is laminated on the second layer and has the optical waveguide. The recess penetrates the third layer and extends in the thickness direction with respect to the second layer. The first wiring extends from the first mesa of the gain portion to the inside of the recess.

Advantages of the Invention

[0008] According to the present disclosure, it is possible to enhance heat dissipation.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] [Description of Embodiments of the Present Disclosure] First, the content of the embodiments of the present disclosure will be listed and described.

[0011] One aspect of the present disclosure includes: (1) a substrate having an optical waveguide; a gain section formed of a Group III-V compound semiconductor, having optical gain, bonded to the upper surface of the substrate, and having a first mesa; and a first wiring electrically connected to the gain section. The first mesa of the gain section is optically coupled to the optical waveguide. The substrate has a first layer, a second layer, and a third layer. The thermal conductivity of the first layer is higher than that of the second layer. The second layer is laminated on the first layer. The third layer is laminated on the second layer and has the optical waveguide. A recess is provided at a position of the substrate spaced apart from the first mesa, recessed in the thickness direction of the substrate from the upper surface of the substrate. The recess penetrates the third layer and extends in the thickness direction with respect to the second layer. The first wiring is a semiconductor optical element extending from the first mesa of the gain section to the recess. The first wiring functions as a heat path. Heat generated at the first mesa is transmitted to the first layer of the substrate through the first wiring and released to the outside of the semiconductor optical element. It is possible to enhance heat dissipation. (2) The first layer and the third layer may be formed of silicon, and the second layer may be formed of silicon oxide. The thermal conductivity of the first layer is higher than that of the second layer. Heat is transmitted from the first wiring to the first layer of the substrate and released to the outside of the semiconductor optical element. Heat dissipation can be enhanced. (3) The recess penetrates the third layer and the second layer and includes an insulating film covering the bottom surface of the recess. The first wiring may be provided on the surface of the insulating film. Since the recess penetrates the second layer, the first wiring extends to the first layer. Heat is more likely to be transmitted to the first layer, and heat dissipation is improved. Since the first wiring is provided on the surface of the insulating film, the first wiring and the first layer are electrically insulated. Leakage current can be suppressed. (4) The recess penetrates the third layer and the second layer, and the first wiring may contact the first layer inside the recess. Since the recess penetrates the second layer, the first wiring extends to the first layer. Heat is more likely to be transmitted to the first layer, and heat dissipation is improved. (5) The concave portion may extend up to the middle of the second layer in the thickness direction. The second layer in the concave portion is thinner than the second layer in the portion other than the concave portion. Heat is more likely to be transmitted to the first layer, and the heat dissipation performance is improved. Leakage current between the first wiring and the first layer can be suppressed. (6) The inner wall of the concave portion may be inclined from the thickness direction. The first wiring is less likely to be disconnected. (7) The gain portion has an opening at a position overlapping the concave portion, and the first wiring may extend from the first mesa to the opening and the concave portion. A concave portion is provided near the first mesa, and the first wiring extends into the concave portion. Since there is a heat dissipation path near the first mesa, the heat dissipation performance is improved. (8) The gain portion has a second mesa, the second mesa is separated from the first mesa, the gain portion is at a position overlapping the concave portion, and has an opening between the second mesa and the first mesa, and the first wiring may extend from the first mesa to the opening and the concave portion. A concave portion is provided near the first mesa, and the first wiring extends into the concave portion. Since there is a heat dissipation path near the first mesa, the heat dissipation performance is improved. (9) The gain portion has a first semiconductor layer, an active layer, and a second semiconductor layer laminated in order from the upper surface of the substrate. The first mesa includes the second semiconductor layer. The first semiconductor layer has a first conductivity type and extends under and outside the first mesa in the direction in which the upper surface of the substrate spreads. The second semiconductor layer has a second conductivity type different from the first conductivity type. The active layer is located under the first mesa. The first wiring may include a second wiring electrically connected to the second semiconductor layer and electrically connected to the first semiconductor layer. Light is generated by injecting carriers into the active layer. Light can be strongly confined near the first mesa. Heat generated in the first mesa can be released to the first layer of the substrate through the first wiring. (10) A step of bonding a gain section formed of a group III-V compound semiconductor and having optical gain to the upper surface of a substrate having an optical waveguide; a step of forming a first mesa on a portion of the gain section above the optical waveguide; a step of forming a recess recessed in the thickness direction of the substrate from the upper surface of the substrate at a position spaced apart from the first mesa of the substrate; and a step of forming a first wiring electrically connected to the gain section. The substrate has a first layer, a second layer, and a third layer. The thermal conductivity of the first layer is higher than that of the second layer. The second layer is laminated on the first layer. The third layer is laminated on the second layer and has the optical waveguide. The recess penetrates the third layer and extends in the thickness direction with respect to the second layer. The first wiring extends from the first mesa of the gain section to the inside of the recess. This is a method for manufacturing a semiconductor optical element. The first wiring functions as a heat path. Heat generated at the first mesa is transmitted to the first layer of the substrate through the first wiring and released to the outside of the semiconductor optical element. It is possible to enhance heat dissipation performance. (11) It may include a step of forming an opening in a portion of the gain section spaced apart from the first mesa. The step of forming the recess may include a step of etching a portion of the substrate overlapping the opening. Since there is a heat dissipation path near the first mesa, heat dissipation performance is improved. (12) The step of forming the recess may include a step of performing dry etching on the substrate and a step of performing wet etching on the substrate after the step of performing dry etching. The inner wall of the recess becomes an inclined surface. Disconnection of the first wiring can be suppressed.

[0012] [Details of Embodiments of the Present Disclosure] Specific examples of a semiconductor optical element and a method for manufacturing the same according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is intended to be indicated by the claims and to include all modifications within the meaning and scope equivalent to the claims.

[0013] <First Embodiment> (Semiconductor Optical Element) FIG. 1A is a plan view illustrating a semiconductor optical element 100 according to the first embodiment. FIG. 1B is a cross-sectional view taken along line A-A of FIG. 1A. As shown in FIGS. 1A and 1B, the semiconductor optical element 100 is a hybrid laser element having a substrate 10 and a gain section 20. The substrate 10 has an upper surface parallel to the XY plane. The gain section 20 is bonded to the upper surface of the substrate 10.

[0014] Two sides of the substrate 10 extend in the X-axis direction. The other two sides extend in the Y-axis direction. The length of the side in the X-axis direction is, for example, 1.5 mm. The length of the side in the Y-axis direction is, for example, 0.6 mm. The Z-axis direction is the normal direction of the XY plane and is the layer stacking direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other. As shown in FIG. 1B, the insulating films 40 and 42 cover the substrate 10 and the gain section 20. In FIG. 1A, the insulating films 40 and 42 are shown in perspective.

[0015] The substrate 10 is a SOI substrate having a substrate 12 (first layer), a box layer 14 (second layer), and a silicon (Si) layer 16 (third layer). The substrate 12 is formed of Si having a thickness of, for example, 500 μm. The box layer 14 is formed of, for example, silicon oxide (SiO 2 ) having a thickness of 3 μm and is stacked on the upper surface of the substrate 12. The Si layer 16 is formed of Si having a thickness of, for example, 200 nm and is stacked on the upper surface of the box layer 14.

[0016] The Si layer 16 has an optical waveguide 15, two grooves 17, and two terraces 18. The groove 17 is a portion recessed in the thickness direction (Z-axis direction) from the upper surface of the Si layer 16 and is a cavity. The depth of the groove 17 is, for example, 150 nm. The groove 17 extends from the upper surface of the Si layer 16 to the middle of the Si layer 16 in the Z-axis direction. The bottom surface of the groove 17 is the Si layer 16. The optical waveguide 15 is sandwiched between the two grooves 17. The optical waveguide 15 and the groove 17 extend from the first end to the second end of the substrate 10 in the X-axis direction. The width of the optical waveguide 15 is, for example, 0.5 μm. The terrace 18 is located on the side of the groove 17 opposite to the optical waveguide 15. The terrace 18 is a plane of Si.

[0017] The gain section 20 is an element formed of a III-V compound semiconductor as described later and has a ridge mesa structure. The gain section 20 has optical gain and functions as a light-emitting element. The gain section 20 has mesas 22, 24, and 26, and an opening 20b. The mesa 22 (first mesa) is located at the central portion of the gain section 20 in the Y-axis direction. The mesas 24 and 26 (second mesas) are located on both sides of the mesa 22 in the X-axis direction. The opening 20b is located between the mesa 24 and the mesa 22.

[0018] As shown in FIG. 1B, the gain section 20 has a damage relaxation layer 30, a cladding layer 32, light confinement layers 34 and 37, an active layer 36, a cladding layer 38, and a contact layer 39. The damage relaxation layer 30, the cladding layer 32, the light confinement layer 34, and the active layer 36 are laminated in this order from the side closer to the upper surface of the substrate 10, are located under the mesas 22, 24, and 26, and spread between the mesa 22 and the mesa 24 and between the mesa 22 and the mesa 26. The damage relaxation layer 30 and the cladding layer 32 spread over a wider range than the active layer 36.

[0019] Each of the mesas 22, 24, and 26 includes a light confinement layer 37, a cladding layer 38, and a contact layer 39. The mesa 22 is located on the optical waveguide 15 and the groove 17 of the substrate 10 and is optically coupled to the optical waveguide 15. The mesas 24 and 26 are separated from the mesa 22. The opening 20b is a through hole that penetrates the gain section 20 in the Z-axis direction.

[0020] The length of the mesa 22 in the X-axis direction is, for example, 1 mm. The width W1 of the mesa 22 in the Y-axis direction is, for example, 3 μm. The widths of the mesas 24 and 26 may be equal to the width of the mesa 22, may be larger than the width of the mesa 22, or may be smaller. The height of the mesas 22, 24, and 26 with respect to the surface of the active layer 36 is, for example, 2 μm.

[0021] As shown in FIG. 1A, the mesa 22 extends in the X-axis direction. Both ends of the mesa 22 in the X-axis direction are tapered and become thinner along the direction from the gain section 20 toward the end of the substrate 10. The gain section 20 has tapered sections 20a at both ends in the X-axis direction. The tapered sections 20a are formed in the damage relaxation layer 30 and the cladding layer 32, are located on the optical waveguide 15, extend in the X-axis direction, and become thinner along the direction from the gain section 20 toward the end of the substrate 10.

[0022] The damage relaxation layer 30, the optical confinement layers 34 and 37 are formed of, for example, undoped gallium indium arsenide phosphide (i-GaInAsP). The thickness of the damage relaxation layer 30 is, for example, 200 nm. The thicknesses of the optical confinement layers 34 and 37 are, for example, 100 nm. The bandgap wavelengths of the damage relaxation layer 30, the optical confinement layers 34 and 37 are, for example, 1.2 μm, which is shorter than the wavelength of the emitted light from the gain section 20.

[0023] The cladding layer 32 is formed of, for example, n-type indium phosphide (n-InP). The thickness of the cladding layer 32 is, for example, 200 nm. For example, Si can be used as the n-type dopant. The dopant concentration of the cladding layer 32 is, for example, 1×10 19 cm -3 . The cladding layer 38 is formed of, for example, p-type InP (p-InP). The thickness of the cladding layer 38 is, for example, 1500 nm. The contact layer 39 is formed of, for example, p+-type gallium indium arsenide ((p+)-GaInAs). For example, zinc (Zn) can be used as the p-type dopant. The dopant concentration of the cladding layer 38 is, for example, 1×10 18 cm -3 . The dopant concentration of the contact layer 39 is, for example, 1×10 19 cm -3 .

[0024] The active layer 36 has a multi - quantum well structure (MQW: Multi Quantum Well), and includes a plurality of well layers and a plurality of barrier layers. The plurality of well layers and the plurality of barrier layers are alternately stacked. One well layer is formed of, for example, GaInAsP with a thickness of 6 nm. One barrier layer is formed of, for example, GaInAsP with a thickness of 10 nm.

[0025] The semiconductor optical element 100 has a recess 50. The recess 50 is located between the mesa 24 and the mesa 22 and overlaps the opening 20b of the gain section 20. The recess 50 extends along the mesa 22. The recess 50 is a portion that is recessed from the upper surface of the substrate 10 in the Z - axis direction, penetrates the Si layer 16 and the box layer 14 of the substrate 10, and extends to the substrate 12. The substrate 12 is the bottom surface of the recess 50. The recess 50 has a tapered shape that tapers downward in the Z - axis direction. Specifically, the width of the recess 50 becomes narrower as it approaches the bottom surface of the recess 50. The inner walls 52 and 54 of the recess 50 are inclined with respect to the plane including the Z - axis. The inner wall 52 is located above the inner wall 54. There is a flat portion between the inner wall 52 and the inner wall 54. The inclination angle of the inner wall 52 with respect to the XZ plane is, for example, 30° or more and 60° or less. Based on the portion between the inner wall 52 and the inner wall 54, the inner wall 54 is inclined in the opposite direction to the inner wall 52 with respect to the XZ plane, and the absolute value of the inclination angle is, for example, 30° or more and 60° or less.

[0026] The width W2 of the bottom surface of the recess 50 is, for example, 10 μm. The distance L1 from the end of the bottom surface of the recess 50 to the end of the mesa 22 is, for example, 15 μm.

[0027] The insulating films 40 and 42 cover the gain section 20 and the substrate 10. The insulating film 40 covers the upper surfaces and side surfaces of the mesas 22, 24, and 26, covers the upper surface of the active layer 36, and covers the side surfaces of the damage - relaxation layer 30, the clad layer 32, the optical confinement layer 34, and the active layer 36. The insulating film 42 covers the surface of the insulating film 40, covers the inner walls 52 and 54 of the recess 50, and covers the bottom surface of the recess 50. The insulating film 40 is, for example, SiO with a thickness of 600 nm 2It is formed thereby. The insulating film 40 is a cladding layer for confining light in the optical waveguide 15. The insulating film 42 is, for example, SiO with a thickness of 10 nm or more and 50 nm or less. 2 It is formed thereby.

[0028] The insulating films 40 and 42 have an opening between the mesa 22 and the mesa 26 and have an opening on the mesa 22. The electrode 44 is provided between the mesa 22 and the mesa 26 and contacts the upper surface of the cladding layer 32 exposed from the openings of the insulating films 40 and 42. The electrode 44 is an n-type electrode and is electrically connected to the cladding layer 32. The wiring 45 contacts the upper surface of the electrode 44 and extends to the side surface and the upper surface of the mesa 26. The wiring 45 is an n-type wiring and is electrically connected to the electrode 44.

[0029] The electrode 46 is provided on the upper surface of the mesa 22 and contacts the upper surface of the contact layer 39 exposed from the openings of the insulating films 40 and 42. The electrode 46 is a p-type electrode and is electrically connected to the contact layer 39. The wiring 48 contacts the upper surface of the electrode 46 and extends to the side surface of the mesa 22, the inside of the recess 50, the side surface and the upper surface of the mesa 24. The wiring 48 is a p-type wiring and is electrically connected to the electrode 46. The electrode 44 is formed of, for example, an alloy of gold, germanium, and Ni (AuGeNi). The electrode 46 is formed of, for example, a laminate of titanium, platinum, and gold (Ti / Pt / Au). The wirings 45 and 48 are formed of a metal such as gold (Au) with a thickness of 3 μm, for example, and are used for electrical connection with external devices.

[0030] The gain section 20 has optical gain and is evanescently optically coupled to the substrate 10. By applying a voltage to the semiconductor optical element 100 using the wirings 45 and 48, a current flows through the mesa 22. By injecting carriers into the active layer 36, the active layer 36 generates light. The light transitions from the gain section 20 to the substrate 10, propagates through the optical waveguide 15, and is emitted outside the semiconductor optical element 100. Since the gain section 20 is provided with the tapered section 20a, reflection of light between the gain section 20 and the optical waveguide 15 is suppressed, and light loss is suppressed.

[0031] (Manufacturing method) Figures 2A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 12A are plan views illustrating a method of manufacturing the semiconductor optical element 100. Figures 2B, 2C, 3A, 3B, 4B, 5B, 6B, 7B, 7C, 8B, 9B, 10B, 10C, 11A, 11B, and 12B are cross-sectional views illustrating a method of manufacturing the semiconductor optical element 100, and illustrate a cross-section (A-A cross-section) corresponding to FIG. 1B. In manufacturing the semiconductor optical element 100, a Si wafer (substrate 10) and a compound semiconductor wafer (substrate 31) are used.

[0032] As shown in FIGS. 2A and 2B, dry etching is performed on the Si layer 16 of the substrate 10 to form grooves 17. The portions not dry-etched become the optical waveguide 15 and the terraces 18.

[0033] As shown in FIG. 2C, for example, by an organometallic vapor phase epitaxy (OMVPE) method, a contact layer 39, a cladding layer 38, a light confinement layer 37, an active layer 36, a light confinement layer 34, a cladding layer 32, and a damage relaxation layer 30 are epitaxially grown in this order on the upper surface of the n+-type InP substrate 31. By dicing, the gain section 20 is formed. The mesa 22, 24, and 26, the opening 20b, the electrodes, and the wiring are not provided in the gain section 20 immediately after dicing.

[0034] As shown in FIG. 3A, the gain section 20 is bonded to the upper surface of the substrate 10. Nitrogen (N 2 ) plasma treatment is performed on the lower surface of the gain section 20 (the surface of the damage relaxation layer 30) and the upper surface of the substrate 10 (the surface of the Si layer 16) to activate them. The activated surfaces are ultrasonically cleaned in water. The surface of the damage relaxation layer 30 and the surface of the Si layer 16 are brought into contact in air at room temperature to perform temporary bonding (H 2 bonding). After temporary bonding, annealing is performed, for example, at 300° C. for 2 hours to remove moisture and strengthen the bonding strength (O 2 bonding). The gain section 20 overlaps on the optical waveguide 15.

[0035] As shown in FIG. 3B, wet etching is performed using, for example, hydrochloric acid (HCl) as an etchant to remove the substrate 31 of the gain section 20. The contact layer 39 functions as an etching stop layer. The semiconductor layer from the contact layer 39 to the damage relaxation layer 30 remains.

[0036] As shown in FIGS. 4A and 4B, an insulating film 60 is formed on the upper surface of the contact layer 39 by, for example, chemical vapor deposition (CVD). The insulating film 60 is formed of, for example, silicon nitride (SiN) or SiO with a thickness of 100 nm to 500 nm. 2 etc. A photoresist (not shown) is applied on the insulating film 60. Photolithography is performed to form a resist pattern. Wet etching using buffered hydrogen fluoride (BHF) and reactive ion etching (RIE: Reactive Ion Etching, CF 4 ) using carbon tetrafluoride (CF 4 -RIE), etc., are used to transfer the resist pattern to the insulating film 60. Using the insulating film 60 as an etching mask, RIE using methane and hydrogen (CH 4 / H 2 ) and wet etching, etc., are used to etch from the contact layer 39 to the damage relaxation layer 30 to mold the gain section 20. The planar shape of the gain section 20 is rectangular. The insulating film 60 is removed. In the portion of the substrate 10 where the gain section 20 is not joined, the optical waveguide 15 is exposed. An insulating film (not shown) is provided in the portion of the substrate 10 where the gain section 20 is not joined. This insulating film is a part of the insulating film 40 in FIG. 1B.

[0037] As shown in FIGS. 5A and 5B, mesas 22, 24, and 26 are formed in the gain section 20. For example, SiN or SiO with a thickness of 100 nm 2An insulating film (not shown) such as... is formed. A resist pattern (not shown) is provided on the insulating film, and the resist pattern is transferred onto the insulating film by wet etching, RIE, or the like. The insulating film has a shape corresponding to the mesas 22, 24, and 26. Using the insulating film as an etching mask, RIE using methane and hydrogen (CH 4 / H 2 ) and wet etching are performed on the contact layer 39, the cladding layer 38, and the optical confinement layer 37. By etching, the portions of the contact layer 39, the cladding layer 38, and the optical confinement layer 37 that are exposed from the mask are removed. Mesas 22, 24, and 26 are formed in the portions covered by the mask. Outside the mesas 22, 24, and 26, the active layer 36, the optical confinement layer 34, the cladding layer 32, and the damage relaxation layer 30 extend. The insulating film used as the mask is removed by etching using BHF.

[0038] As shown in FIGS. 6A and 6B, an insulating film 64 is provided on the gain section 20. A photoresist is applied on the insulating film 64, and a resist pattern 66 is formed by photolithography. The resist pattern 66 has a tapered portion and an opening. CH 4 The shape of the resist pattern 66 is transferred onto the insulating film 64 by RIE using... The insulating film 64 is formed with a tapered portion 64a and an opening 64b. The opening 64b is located between the mesa 22 and the mesa 24. The tapered portion 64a has a tapered shape along the X-axis direction. The resist pattern 66 is removed.

[0039] As shown in FIGS. 7A and 7B, using the insulating film 64 as a mask, CH 4 and H 2Perform RIE using this. The active layer 36, the optical confinement layer 34, the cladding layer 32, and the damage relaxation layer 30 exposed from the insulating film 64 are removed. An opening 20b and two tapered portions 20a are formed in the gain section 20. The opening 20b is formed at a position overlapping the opening 64b of the insulating film 64. The opening 20b is located between the mesas 22 and 24 of the gain section 20 and penetrates the active layer 36, the optical confinement layer 34, the cladding layer 32, and the damage relaxation layer 30. From the opening 20b, the Si layer 16 (terrace 18) of the substrate 10 is exposed.

[0040] After forming the tapered portions 20a and the opening 20b, remove the insulating film 64 by wet etching using BHF. Remove a part of the active layer 36 and the optical confinement layer 34 by etching or the like. As shown in FIG. 7A, the active layer 36 spreads from under the mesas 22, 24, and 26 to the vicinity of the mesas. The damage relaxation layer 30 and the cladding layer 32 extend wider than the active layer 36 and the optical confinement layer 34.

[0041] As shown in FIG. 7C, form an insulating film 40 of SiO 2 by, for example, the CVD method or the like. The insulating film 40 covers the mesas 22, 24, and 26, covers the inner wall and the bottom surface of the opening 20b, and also covers the portion of the substrate 10 exposed from the gain section 20.

[0042] As shown in FIGS. 8A and 8B, apply a photoresist on the substrate 10 and the gain section 20 and form a resist pattern 66 by photolithography. The resist pattern 66 has an opening 66a. The opening 66a overlaps the opening 20b of the gain section 20. The length of the opening 66a in the X-axis direction is, for example, equal to the length of the opening 20b. The width of the opening 66a in the Y-axis direction is smaller than the width of the opening 20b. The inner wall of the opening 66a is located inside the inner wall of the opening 20b. The insulating film 40 is exposed from the opening 66a. By adjusting the exposure amount and focus of photolithography, etc., the inner wall of the opening 66a can be inclined with respect to the Z-axis direction as shown in FIG. 8B. The inclination angle of the inner wall from the Z-axis is, for example, 30° or more and 60° or less.

[0043] As shown in FIGS. 9A and 9B, using the resist pattern 66 as a mask, CF 4 -RIE is performed on the insulating film 40 and the substrate 10 to form a recess 50 in the substrate 10. The etching proceeds from the upper surface of the substrate 10 to a position where the depth is 1 μm or more and 2 μm or less. The recess 50 extends to the middle of the box layer 14 and does not reach the substrate 12. The etching selectivity between the resist pattern 66 and the insulating film 40 is, for example, 0.8. Depending on the etching selectivity, the portion of the insulating film 40 and the substrate 10 located under the inclined inner wall of the resist pattern 66 is also etched. An inclined inner wall 52 is formed corresponding to the inclined inner wall of the resist pattern 66. The resist pattern 66 is removed.

[0044] As shown in FIGS. 10A and 10B, a resist pattern 68 is formed by photolithography. The resist pattern 68 has an opening 68a at a position overlapping the recess 50. The length of the opening 68a in the X-axis direction is equal to the length of the recess 50. The inner wall of the opening 68a is located inside the inner wall 52. Using the resist pattern 68 as a mask, wet etching is performed, for example, using BHF, to deeply process the recess 50.

[0045] As shown in FIG. 10C, by wet etching, the portion of the box layer 14 of the substrate 10 exposed from the opening 68a is removed. After the wet etching, the recess 50 penetrates the box layer 14 and extends to the substrate 12. By side etching, an inclined inner wall 54 is formed in the box layer 14. After the etching, the resist pattern 68 is removed.

[0046] As shown in FIG. 11A, an insulating film 42 is formed on the surface of the insulating film 40, the inner wall and the bottom surface of the recess 50, for example, by atomic layer deposition (ALD: Atomic Layer Deposition).

[0047] As shown in FIG. 11B, a resist pattern 69 is formed on the upper surfaces of the substrate 10 and the gain section 20. The resist pattern 69 has an opening 69a between the mesas 22 and 26 of the gain section 20. Using the resist pattern 69 as a mask, wet etching is performed using an etchant containing, for example, sulfuric acid. By the wet etching, openings are formed in the insulating films 40 and 42 at positions overlapping the opening 69a. After the wet etching, the resist pattern 69 is removed.

[0048] Etching is performed using the insulating films 40 and 42 as masks, and the portions of the active layer 36 and the optical confinement layer 34 that are exposed from the insulating films 40 and 42 are removed. The clad layer 32 is exposed. The portions of the insulating films 40 and 42 above the mesa 24 are removed by wet etching or the like using a resist pattern (not shown) as a mask.

[0049] As shown in FIGS. 12A and 12B, electrodes 44 and 46 are formed, for example, by vacuum evaporation and lift-off. The electrode 44 is located between the mesas 24 and 26 and is provided on the upper surface of the clad layer 32. The electrode 46 is located on the upper surface of the mesa 24 and is provided on the upper surface of the contact layer 39. Wiring 45 and 48 are formed, for example, by plating. The wiring 45 extends from the upper surface of the electrode 44 to the upper surface of the mesa 26. The wiring 48 extends from the upper surface of the electrode 46 to the side wall and bottom surface of the recess 50 and further to the upper surface of the mesa 22. The semiconductor optical element 100 is formed by dicing the wafer-shaped substrate 10.

[0050] FIG. 13 is a cross-sectional view illustrating a semiconductor optical element 100R according to a comparative example. The semiconductor optical element 100R is not provided with the insulating film 42, the opening 20b, and the recess 50. The wiring 48 extends over the gain section 20.

[0051] When a carrier is injected and the semiconductor optical element 100R is operated, heat is generated in the vicinity of the mesa 22. The thermal conductivity of the box layer 14 of the substrate 10 is lower than that of, for example, the Si substrate 12 and the Si layer 16. Since the box layer 14 becomes a barrier to heat transfer, heat dissipation is inhibited. As the heat dissipation property deteriorates, the temperature rises and the characteristics deteriorate. The thermal resistance of the semiconductor optical element 100R is, for example, 140 K / W. When 0.3 W of power is input to the semiconductor optical element 100R, the temperature in the vicinity of the mesa 22 rises by 40°C. The optical output saturates and it becomes difficult to increase the output power.

[0052] According to the first embodiment, a recess 50 is provided at a position separated from the mesa 22 of the substrate 10. The wiring 48 extends from the mesa 22 to the inside of the recess 50. Since the wiring 48 extends inside the recess 50, the wiring 48 and the substrate 12 approach each other. The substrate 12 is formed of, for example, Si and has a higher thermal conductivity than the box layer 14. The wiring 48 serves as a path for releasing heat from the mesa 22 to the substrate 12. The substrate 12 serves as a path for releasing heat to the outside of the semiconductor optical element 100. The heat generated at the mesa 22 is transmitted to the substrate 12 through the metal wiring 48 and released to the outside of the semiconductor optical element 100. As a result, the heat dissipation property of the semiconductor optical element 100 is improved. The temperature rise can be suppressed, and the deterioration of the characteristics can also be suppressed.

[0053] According to the first embodiment, the thermal resistance can be, for example, 80 K / W. When 0.3 W of power is injected, the rise in the temperature in the vicinity of the mesa 22 can be suppressed to about 20°C. Saturation of the optical output of the semiconductor optical element 100 and the like can be suppressed, and the characteristics can be improved. The semiconductor optical element 100 is mounted on, for example, a heat sink (not shown). Heat is released from the mesa 22 through the wiring 48 and the substrate 12 to the heat sink.

[0054] The substrate 10 is an SOI substrate, and the Si substrate 12, SiO are laminated in order. 2It has a box layer 14 and an Si layer 16. The thermal conductivity of the substrate 12 is higher than that of the box layer 14. By providing the recess 50 in the substrate 10, the box layer 14 is less likely to become an obstacle to heat dissipation, and heat is more likely to be transmitted to the substrate 12. The heat dissipation performance can be improved, and the deterioration of characteristics due to temperature rise can be suppressed.

[0055] As shown in FIG. 1B, the recess 50 penetrates the Si layer 16 and the box layer 14 and extends to the substrate 12. The bottom surface of the recess 50 is the Si substrate 12. At the bottom surface of the recess 50, the box layer 14 is not provided between the wiring 48 and the substrate 12. Heat is more likely to be transmitted between the wiring 48 and the substrate 12, and the heat dissipation performance is further improved.

[0056] The insulating film 42 covers the inner wall and the bottom surface of the recess 50. The wiring 48 is electrically insulated from the Si substrate 12 by the insulating film 42. Leakage current can be suppressed, and a decrease in efficiency can be suppressed. If the insulating film 42 is thick, heat is less likely to be transmitted. On the other hand, if the insulating film 42 is thin, there is a risk that the insulating film 42 will be defective and leakage current will flow. The thickness of the insulating film 42 is, for example, 10 nm or more and 50 nm or less. Heat can be released from the wiring 48 to the substrate 12, and leakage current can be suppressed.

[0057] The inner wall 52 of the recess 50 is formed by performing dry etching on the substrate 10. Thereafter, the inner wall 54 is formed by performing wet etching. The inner walls 52 and 54 of the recess 50 are inclined with respect to the Z-axis direction. The wiring 48 is deposited on the inclined inner walls 52 and 54 and extends along the inner walls 52 and 54, so it is less likely to break. Injection and heat dissipation of current through the wiring 48 are effectively performed. The inclination angles of the inner walls 52 and 54 are, for example, 45°, and are within the range of 30° to 60°.

[0058] For example, a concave portion of the substrate 10 can be provided outside the gain section 20, and the wiring 48 can be routed to the outside of the gain section 20. However, by providing a heat dissipation path (the wiring 48 and the substrate 12) near the mesa 22 that serves as a heat source, heat can be effectively dissipated. According to the first embodiment, the opening 20b of the gain section 20 overlaps with the concave portion 50 of the substrate 10. The wiring 48 extends from the mesa 22 to the opening 20b and the concave portion 50. The wiring 48 extending to the opening 20b and the concave portion 50 serves as a heat path. The heat generated in the mesa 22 is dissipated in the vicinity of the mesa 22. The temperature rise can be more effectively suppressed, and the deterioration of the special case can be suppressed.

[0059] The gain section 20 has mesas 22, 24, and 26. The mesas 24 and 26 are spaced apart from the mesa 22. It is preferable to provide the concave portion 50 and the opening 20b between the mesa 22 and the mesa 24. By forming a heat dissipation path near the mesa 22, heat can be effectively dissipated. The distance L1 between the concave portion 50 and the mesa 22 shown in FIG. 1B is preferably, for example, within 20 μm. The thicker the wiring 48, the higher the thermal conductivity of the wiring 48. The thickness of the wiring 48 is, for example, 3 μm or the like, and it is preferably 1 μm or more. The wiring 48 is provided, for example, by plating or the like along the bottom surface of the concave portion 50 and the inclined inner walls 52 and 54 of the concave portion 50. The wiring 48 can be thickly deposited. When the wiring 48 is formed of a metal such as Au, the thermal conductivity becomes high.

[0060] The upper surfaces of the mesas 22, 24, and 26 are located in the same plane. In the dicing process and the handling of the semiconductor optical element 100, a collet or the like may come into contact with the mesas 22, 24, and 26. By alleviating the concentration of stress on one mesa and suppressing breakage, the yield can be improved. In particular, by arranging the mesas 24 and 26 symmetrically with respect to the mesa 22, the stress can be evenly distributed.

[0061] The gain section 20 includes a damage relaxation layer 30, a cladding layer 32, a light confinement layer 34, an active layer 36, a light confinement layer 37, a cladding layer 38, and a contact layer 39, which are laminated in order from the upper surface of the substrate 10. The damage relaxation layer 30, the cladding layer 32, the light confinement layer 34, and the active layer 36 extend under and outside the three mesas.

[0062] Current flows through the n-type cladding layer 32 and the p-type cladding layer 38 to the mesa 22. By injecting carriers into the active layer 36 under the mesa 22, laser light is emitted from the semiconductor optical element 100. Heat generated in the vicinity of the mesa 22 is released through the wiring 48 and the substrate 12. It is possible to suppress the temperature rise associated with the operation of the semiconductor optical element 100 and suppress the deterioration of characteristics.

[0063] Optical elements such as ring resonators and diffraction gratings, as well as heaters, may be provided on the substrate 10. The wavelength of the emitted light from the gain section 20 can be controlled.

[0064] <Second Embodiment> FIG. 14 is a cross-sectional view illustrating a semiconductor optical element 200 according to the second embodiment, showing a cross-section corresponding to FIG. 1B. Description of the same configuration as in the first embodiment is omitted.

[0065] As shown in FIG. 14, the recess 50 penetrates the box layer 14 of the substrate 10 and extends to the substrate 12. The insulating film 42 is not provided. The wiring 48 contacts the inner walls 52 and 54 of the recess 50 and the bottom surface of the recess 50 (the surface of the substrate 12).

[0066] In the manufacturing process of the semiconductor optical element 200, the steps from FIG. 2A to FIG. 10C are performed to form the recess 50. The electrodes 44 and 46 and the wirings 45 and 48 are formed without forming the insulating film 42.

[0067] According to the second embodiment, the wiring 48 extends from the mesa 22 to the recess 50 and contacts the surface of the substrate 12 inside the recess 50. The heat generated in the mesa 22 is transmitted through the wiring 48 and released from the wiring 48 to the substrate 12. By contacting the substrate 12, the wiring 48 has higher heat dissipation performance, and the temperature rise can be effectively suppressed.

[0068] The substrate 12 is formed of Si and has a higher thermal conductivity than the box layer 14. By contacting the substrate 12, the wiring 48 can easily release heat. On the other hand, the substrate 12 has a higher electrical conductivity than the box layer 14. A leakage current may flow from the wiring 48 to the substrate 12. In order to suppress the leakage current, it is preferable to increase the electrical resistance of the substrate 12. The electrical resistivity of the substrate 12 is, for example, 1 kΩ·cm or more.

[0069] <Third Embodiment> FIG. 15 is a cross-sectional view illustrating a semiconductor optical element 300 according to the third embodiment, and illustrates a cross-section corresponding to FIG. 1B. The description of the same configuration as that of the first embodiment is omitted.

[0070] As shown in FIG. 15, the recess 50 penetrates the Si layer 16 and extends to the middle of the box layer 14. The recess 50 does not penetrate the box layer 14 and does not extend to the substrate 12. The thickness T1 of the box layer 14 in the portion other than the recess 50 is, for example, 3 μm. The thickness T2 from the upper surface of the substrate 12 to the bottom surface of the recess 50 (the surface of the box layer 14) is smaller than the thickness T1, and is, for example, 100 nm or more and 200 nm or less. The insulating film 42 is not provided.

[0071] In the manufacturing process of the semiconductor optical element 200, the processes from FIG. 2A to FIG. 10B are performed. In the process corresponding to FIG. 10C, the etching is stopped in the middle of the box layer 14. The electrodes 44 and 46, and the wirings 45 and 48 are formed without forming the insulating film 42.

[0072] According to the third embodiment, the wiring 48 extends from the mesa 22 to the recess 50. Inside the recess 50, the box layer 14 that is thinner than the portions other than the recess 50 remains. Because the box layer 14 is thin, heat is easily transmitted in the recess 50. The heat generated in the mesa 22 is transmitted through the wiring 48 and released from the wiring 48 to the substrate 12. By increasing the heat dissipation property, the temperature rise can be suppressed.

[0073] The thinner the box layer 14 at the bottom of the recess 50 is, the higher the heat dissipation property becomes. The thickness T2 of the box layer 14 is preferably, for example, 1 / 5 or less, 1 / 10 or less of the thickness T1.

[0074] As described above in detail for the embodiments of the present disclosure, the present disclosure is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present disclosure described in the claims.

Explanation of Reference Numerals

[0075] 10, 12, 31 Substrate 14 Box layer 16 Si layer 15 Optical waveguide 17 Groove 18 Terrace 20 Gain section 20a, 64a Taper section 20b, 64b, 66a, 68a, 69a Opening 22, 24, 26 Mesa 30 Damage relaxation layer 32, 38 Clad layer 34, 37 Optical confinement layer 36 Active layer 39 Contact layer 40, 42, 60, 64 Insulating film 44, 46 Electrode 45, 48 Wiring 50 Recess 52, 54 Inner wall 66, 68, 69 Resist pattern 100, 100R, 200, 300 Semiconductor element

Claims

1. A substrate having an optical waveguide, a gain section formed of a group III-V compound semiconductor, having optical gain, bonded to the upper surface of the substrate, and having a first mesa, a first wiring electrically connected to the gain section, the first mesa of the gain section being optically coupled to the optical waveguide, the substrate having a first layer, a second layer, and a third layer, the thermal conductivity of the first layer being higher than that of the second layer, the second layer being laminated on the first layer, the third layer being laminated on the second layer and having the optical waveguide, a recess recessed in the thickness direction of the substrate from the upper surface of the substrate is provided at a position of the substrate separated from the first mesa, the recess penetrating the third layer and extending in the thickness direction with respect to the second layer, the gain section having a first semiconductor layer, an active layer, and a second semiconductor layer laminated in order from the upper surface of the substrate, the first mesa including the second semiconductor layer, the first semiconductor layer having a first conductivity type and spreading under and outside the first mesa in the direction in which the upper surface of the substrate spreads, the second semiconductor layer having a second conductivity type different from the first conductivity type, the active layer being located under the first mesa, the first wiring being electrically connected to the second semiconductor layer at the first mesa of the gain section and being a semiconductor optical element extending from the first mesa to the recess.

2. The first layer and the third layer are formed of silicon, The semiconductor optical element according to claim 1, wherein the second layer is formed of silicon oxide.

3. The recess penetrates the third layer and the second layer, including an insulating film covering the bottom surface of the recess, The semiconductor optical element according to claim 1 or claim 2, wherein the first wiring is provided on the surface of the insulating film.

4. The recess penetrates the third layer and the second layer, The semiconductor optical element according to claim 1 or claim 2, wherein the first wiring contacts the first layer inside the recess.

5. The semiconductor optical element according to claim 1 or claim 2, wherein the recess extends to the middle of the second layer in the thickness direction.

6. The semiconductor optical element according to any one of claims 1 to 5, wherein the inner wall of the recess is inclined from the thickness direction.

7. The gain section has an opening at a position separated from the first mesa, the opening penetrating the first semiconductor layer, In a plan view, the opening overlaps with the recess of the substrate. The semiconductor optical element according to any one of claims 1 to 6, wherein the first wiring extends from the first mesa to the opening and the recess. **Claim 8** The gain section has a second mesa. The second mesa is spaced apart from the first mesa. The gain section has an opening between the second mesa and the first mesa. The opening penetrates the first semiconductor layer. In a plan view, the opening overlaps with the recess of the substrate. The semiconductor optical element according to any one of claims 1 to 7, wherein the first wiring extends from the first mesa to the opening and the recess. The semiconductor optical element according to any one of claims 1 to 8, further comprising a second wiring electrically connected to the first semiconductor layer. **Claim 10** A step of bonding a gain section formed of a group III-V compound semiconductor and having an optical gain to an upper surface of a substrate having an optical waveguide; A step of forming a first mesa on a portion of the gain section above the optical waveguide; A step of forming a recess recessed in a thickness direction of the substrate from an upper surface of the substrate at a position spaced apart from the first mesa of the substrate; A step of forming a first wiring electrically connected to the gain section, the method for manufacturing a semiconductor optical element comprising: The substrate has a first layer, a second layer, and a third layer. The thermal conductivity of the first layer is higher than the thermal conductivity of the second layer. The second layer is laminated on the first layer. The third layer is laminated on the second layer and has the optical waveguide. The recess penetrates the third layer and extends in the thickness direction with respect to the second layer. The gain section has a first semiconductor layer, an active layer, and a second semiconductor layer laminated in order from an upper surface of the substrate. The first mesa includes the second semiconductor layer. The first semiconductor layer has a first conductivity type and spreads under and outside the first mesa in a direction in which the upper surface of the substrate spreads. The second semiconductor layer has a second conductivity type different from the first conductivity type. The active layer is located under the first mesa. The first wiring is electrically connected to the second semiconductor layer at the first mesa of the gain section and extends from the first mesa to the inside of the recess, the method for manufacturing a semiconductor optical element. **Claim 11** A step of forming an opening in a portion of the gain section spaced apart from the first mesa, the opening penetrating the first semiconductor layer. The opening penetrates the first semiconductor layer. The method for manufacturing a semiconductor optical element according to claim 10, wherein the step of forming the concave portion includes a step of performing etching on a portion of the substrate that overlaps the opening in a plan view.

12. The method for manufacturing a semiconductor optical element according to claim 10 or claim 11, wherein the step of forming the concave portion includes a step of performing dry etching on the substrate and a step of performing wet etching on the substrate after the step of performing dry etching.

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