Semiconductor Device

Abstract

This semiconductor device comprises: a semiconductor chip having a main surface; a first conductive drift area formed on a surface layer portion of the main surface; and a second conductive column area that is formed in a columnar shape extending in the thickness direction inside the drift area and has a lower end portion, an intermediate portion, and an upper end portion, wherein the column area includes a low concentration portion formed between the lower end portion and the intermediate portion, and a high concentration portion formed between the intermediate portion and the upper end portion, and has a compensation area that compensates for a charge balance in an impurity concentration range between the low concentration portion and the high concentration portion.

Description

[Technical field]

[0001] This application corresponds to Patent Application No. 2020-060630 filed with the Japan Patent Office on March 30, 2020, the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to a semiconductor device. [Background technology]

[0003] Patent Document 1 discloses a semiconductor device having a super junction structure (hereinafter simply referred to as "SJ structure"). This semiconductor device includes a semiconductor chip, an n-type drift region, and a p-type pillar region (column region). The drift region is formed in a surface layer of the semiconductor chip. The pillar region is formed within the drift region, and forms an SJ structure between the drift region and the pillar region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2011-0018101 Summary of the Invention [Problem to be solved by the invention]

[0005] In the SJ structure, the column region, which has a certain p-type impurity concentration, achieves charge balance with the drift region to maximize the breakdown voltage. A charge-balanced state refers to a state in which the amount of p-type charge (p-type impurity concentration) in the column region is in equilibrium with the amount of n-type charge (n-type impurity concentration) in the drift region. In the SJ structure, the tolerance of the column region for process errors (i.e., the process margin) is extremely narrow, so process errors occurring in the column region significantly reduce the breakdown voltage.

[0006] For example, if the width of the column region is increased beyond the design value, the amount of p-type charge will exceed the amount of n-type charge. In this case, the electric field will concentrate at the bottom end of the column region, lowering the breakdown voltage. On the other hand, if the width of the column region is decreased beyond the design value, the amount of n-type charge will exceed the amount of p-type charge. In this case, the electric field will concentrate at the top end of the column region, lowering the breakdown voltage. These process errors can cause yield reductions.

[0007] Therefore, one embodiment of the present invention provides a semiconductor device capable of suppressing fluctuations in breakdown voltage caused by process errors. [Means for solving the problem]

[0008] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; and a column region of a second conductivity type formed in the drift region in a column shape extending in a thickness direction and having a lower end, an intermediate portion and an upper end, wherein the column region includes a low concentration portion formed between the lower end and the intermediate portion, and a high concentration portion formed between the intermediate portion and the upper end, and has a compensation region that compensates for charge balance in an impurity concentration range between the low concentration portion and the high concentration portion.

[0009] According to this semiconductor device, even if the width of the column region increases due to a process error, the low concentration portion of the compensation region can alleviate the electric field concentration at the lower end of the column region. On the other hand, even if the width of the column region decreases due to a process error, the high concentration portion of the compensation region can alleviate the electric field concentration at the upper end of the column region. This makes it possible to suppress fluctuations in breakdown voltage caused by process errors.

[0010] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; and a column region of a second conductivity type formed in the drift region in a column shape extending in a thickness direction and having a lower end, an intermediate portion, and an upper end, wherein the column region includes a low concentration portion formed between the lower end and the intermediate portion, and a lower high concentration portion formed between the low concentration portion and the lower end, and a lower compensation region that compensates for charge balance in an impurity concentration range between the low concentration portion and the lower high concentration portion; and an upper compensation region that includes a high concentration portion formed between the intermediate portion and the upper end, and an upper low concentration portion formed between the high concentration portion and the upper end, and compensates for charge balance in an impurity concentration range between the high concentration portion and the upper low concentration portion.

[0011] According to this semiconductor device, even if the width of the column region increases due to a process error, the low concentration portion of the lower compensation region can alleviate the electric field concentration at the lower end of the column region. On the other hand, even if the width of the column region decreases due to a process error, the high concentration portion of the upper compensation region can alleviate the electric field concentration at the upper end of the column region. Furthermore, according to this semiconductor device, the charge balance can be compensated for by the lower compensation region and the upper compensation region. This makes it possible to suppress fluctuations in breakdown voltage caused by process errors.

[0012] The above and other objects, features and advantages of the present invention will become apparent from the embodiments described with reference to the accompanying drawings. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of region II shown in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4] FIG. 4 is a diagram for explaining the impurity concentration of the column region according to the first embodiment. [Diagram 5] FIG. 5 is a graph for explaining the breakdown voltage when the column region shown in FIG. 4 is adopted. [Figure 6] FIG. 6 is a diagram for explaining the impurity concentration of the column region according to the second embodiment. [Figure 7] FIG. 7 is a graph in which the measurement results of the breakdown voltage when the column region according to the second embodiment is adopted are reflected in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present invention, Fig. 2 is an enlarged view of a region II shown in Fig. 1, Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 2.

[0015] 1 to 3, semiconductor device 1 is a semiconductor switching device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of an insulated gate transistor. Semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape. In this embodiment, semiconductor chip 2 is made of a Si (silicon) chip.

[0016] The semiconductor chip 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The first side surface 5A and the second side surface 5B extend in a first direction X and face a second direction Y perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] The semiconductor chip 2 includes an n-type (first conductivity type) drift region 6 formed in a surface layer portion of the first main surface 3. The drift region 6 is exposed from the first main surface 3 and parts of the first to fourth side surfaces 5A to 5D. The n-type impurity concentration of the drift region 6 is 1×10 15 cm -3 More than 1×10 17 cm -3 In this embodiment, the drift region 6 is formed by an n-type epitaxial layer (a Si epitaxial layer).

[0018] The drift region 6 may have a thickness of 20 μm or more and 100 μm or less. The thickness of the drift region 6 may be 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. The thickness of the drift region 6 is preferably 45 μm or more and 65 μm or less.

[0019] The semiconductor device 1 includes a drain region 7 formed in a region on the second main surface 4 side of the drift region 6. The drain region 7 is exposed from the second main surface 4 and parts of the first to fourth side surfaces 5A to 5D, and is electrically connected to the drift region 6. The drain region 7 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 6. The n-type impurity concentration of the drain region 7 may be approximately constant. The n-type impurity concentration of the drain region 7 is 1×10 18 cm -3 More than 1×10 21 cm -3 In this embodiment, the drain region 7 is formed of an n-type semiconductor substrate (Si substrate).

[0020] The thickness of the drain region 7 may be 10 μm or more and 450 μm or less. The thickness of the drain region 7 may be 10 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 350 μm or less, or 350 μm or more and 450 μm or less. The thickness of the drain region 7 is preferably 50 μm or more and 150 μm or less.

[0021] The semiconductor chip 2 further includes an n-type buffer region 8 interposed between the drift region 6 and the drain region 7. The buffer region 8 is exposed from a portion of the first to fourth side surfaces 5A to 5D. The buffer region 8 is a concentration transition region between the drift region 6 and the drain region 7, and has an n-type impurity concentration that gradually increases from the drift region 6 toward the drain region 7. In this embodiment, the buffer region 8 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0022] The buffer region 8 has a thickness less than the thickness of the drift region 6. The buffer region 8 may have a thickness of 1 μm or more and 10 μm or less. The buffer region 8 may have a thickness of 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less.

[0023] The semiconductor device 1 includes a plurality of p-type (second conductivity type) base regions 9 formed in a surface layer portion of the drift region 6 on the first main surface 3. The p-type impurity concentration (peak concentration) of the base regions 9 is 1×10 16 cm -3 More than 1×10 18 cm -3 The base regions 9 may be formed as follows. The base regions 9 are exposed from the first main surface 3. The base regions 9 are each formed in a band shape extending in the first direction X in a plan view, and are formed at intervals in the second direction Y. As a result, the base regions 9 are formed in a stripe shape extending in the first direction X as a whole in a plan view. The base regions 9 are formed at intervals from the bottom of the drift region 6 toward the first main surface 3.

[0024] Each of the base regions 9 has a first width W1 (base width) in plan view. The first width W1 is a width in a direction (second direction Y) perpendicular to the direction (first direction X) in which the base regions 9 extend in plan view. The first width W1 may be 1 μm or more and 10 μm or less. The first width W1 is preferably 2 μm or more and 5 μm or less.

[0025] The semiconductor device 1 includes a plurality of n-type source regions 10 formed in the surface layer portions of the plurality of base regions 9, respectively. In this embodiment, two source regions 10 are formed in the surface layer portions of the plurality of base regions 9, respectively. The plurality of source regions 10 are exposed from the first main surface 3. The plurality of source regions 10 each have an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 6. The n-type impurity concentration (peak concentration) of the plurality of source regions 10 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following.

[0026] The multiple source regions 10 are formed in strip shapes extending in a first direction X in the surface layer portions of the multiple base regions 9 in a plan view, and are formed at intervals in the second direction Y. The multiple source regions 10 are formed at intervals from the bottoms of the base regions 9 toward the first main surface 3. The multiple source regions 10 are formed at intervals from the edges of the corresponding base regions 9 within the corresponding base regions 9. As a result, the multiple source regions 10 define drift regions 6 and channel regions 11 in the surface layer portions of the corresponding base regions 9.

[0027] The semiconductor device 1 includes a plurality of p-type contact regions 12 formed in regions different from the plurality of source regions 10 in the surface layer portions of the plurality of base regions 9. In this embodiment, one contact region 12 is formed in a region between two source regions 10 in the surface layer portions of the plurality of base regions 9. The plurality of contact regions 12 have a p-type impurity concentration that exceeds the p-type impurity concentration of the base region 9. The p-type impurity concentration (peak concentration) of the plurality of contact regions 12 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following.

[0028] The multiple contact regions 12 are each formed in a band shape extending in the first direction X in a plan view. The multiple contact regions 12 are formed at intervals from the bottom of the base region 9 toward the first main surface 3. The number of contact regions 12 in each base region 9 is arbitrary, and the multiple contact regions 12 may be formed at intervals in a surface layer portion of each base region 9.

[0029] The semiconductor device 1 includes a plurality of p-type column regions 20 formed in the drift region 6. Each of the plurality of column regions 20 forms a pn junction with the drift region 6. As a result, the plurality of column regions 20 form a super junction structure (hereinafter simply referred to as an "SJ structure") with the drift region 6.

[0030] The multiple column regions 20 are formed in columns extending in the thickness direction (normal direction Z) of the drift region 6 in regions directly below the multiple base regions 9. The multiple column regions 20 face the multiple base regions 9 in a one-to-one correspondence with each other in the thickness direction of the drift region 6. The multiple column regions 20 are formed in stripes extending in the first direction X in a plan view and are formed at intervals in the second direction Y, so that the multiple base regions 9 are formed in stripes extending in the first direction X as a whole in a plan view.

[0031] The multiple column regions 20 may be formed at a pitch P of 1 μm or more and 15 μm or less in plan view. The pitch P is preferably 3 μm or more and 10 μm or less. The multiple column regions 20 may have a thickness in the thickness direction (normal direction Z) of 10 μm or more and 100 μm or less. The multiple column regions 20 preferably have a thickness of 20 μm or more and 80 μm or less. The multiple column regions 20 preferably have a thickness less than the thickness of the drift region 6.

[0032] Each of the column regions 20 has a second width W2 (column width) less than the first width W1 of the base region 9 in a plan view. The second width W2 is the width (the width of the widest portion) in a direction (second direction Y) perpendicular to the direction in which the column regions 20 extend (first direction X) in a plan view. The second width W2 may be 1 μm or more and 8 μm or less. The first width W1 is preferably 1 μm or more and 5 μm or less.

[0033] Each of the column regions 20 has a lower end 21, an intermediate portion 22, and an upper end 23 in the normal direction Z. The lower end 21 of the column region 20 is formed at an interval from the bottom of the drift region 6 toward the first main surface 3 (upper end 23 side). The lower end 21 faces the drain region 7 (buffer region 8) with a part of the drift region 6 interposed therebetween. The upper end 23 of the column region 20 is connected to the base region 9. The column region 20 faces the contact region 12 with a part of the base region 9 interposed therebetween.

[0034] Each of the column regions 20 has a stacked structure including a plurality of (ten in this embodiment) impurity regions 24 stacked in a column shape in the thickness direction (normal direction Z) of the drift region 6. Hereinafter, the ten impurity regions 24 are referred to as first to tenth impurity regions 24A to 24J. The first to tenth impurity regions 24A to 24J are stacked in this order from the drift region 6 side toward the base region 9 side. The first to tenth impurity regions 24A to 24J are stacked so as to be connected to each other, and together form one column region 20.

[0035] The bottom ends 21 of the column regions 20 are each formed by a first impurity region 24A at the bottom. The top ends 23 of the column regions 20 are each formed by a tenth impurity region 24J at the top. The middle portions 22 of the column regions 20 are each formed by one or two impurity regions 24 (fifth to sixth impurity regions 24E to 24F in this embodiment) located between the first impurity region 24A at the bottom and the tenth impurity region 24J at the top.

[0036] The p-type impurity concentration (peak concentration) of the first to tenth impurity regions 24A to 24J is 1×10 15 cm -3 More than 1×10 18 cm -3 or less. That is, the plurality of column regions 20 have a plurality of peak concentrations formed by the plurality of first to tenth impurity regions 24A to 24J in the thickness direction. The first to tenth impurity regions 24A to 24J each preferably have a thickness of 2 μm or more and 10 μm or less in the thickness direction (normal direction Z).

[0037] The number of impurity regions 24 is adjusted according to the thickness of the column region 20. The number of impurity regions 24 is arbitrary, but is preferably 5 to 20. The multiple impurity regions 24 may be formed by a multi-epitaxial growth method in which a p-type impurity introduction step and an epitaxial growth step are alternately performed.

[0038] The semiconductor device 1 includes a plurality of planar gate structures 25 (gate structures) formed on the first main surface 3. The plurality of planar gate structures 25 are each formed in a band shape extending in a first direction X, and are formed at intervals in a second direction Y. As a result, the plurality of planar gate structures 25 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0039] The planar gate structures 25 each extend across the periphery of two adjacent base regions 9 so as to cover the channel region 11 on the first main surface 3. The planar gate structures 25 are formed spaced apart from the column regions 20 in a planar view. It is preferable that the planar gate structures 25 do not overlap the column regions 20 in a planar view.

[0040] Each of the planar gate structures 25 has a laminated structure including a gate insulating film 26 and a gate electrode 27. Each gate insulating film 26 spans the periphery of two adjacent base regions 9, and covers the drift region 6, the channel region 11, and the source region 10. The gate insulating film 26 may contain at least one of silicon oxide, silicon nitride, and aluminum oxide. In this embodiment, the gate insulating film 26 has a single-layer structure made of a silicon oxide film.

[0041] Each gate electrode 27 is formed on the gate insulating film 26 so as to straddle the periphery of two adjacent base regions 9, and faces the drift region 6, the channel region 11, and the source region 10 across the gate insulating film 26. The gate electrode 27 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the gate electrode 27 includes conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon.

[0042] The semiconductor device 1 includes an interlayer insulating film 30 covering the multiple planar gate structures 25 on the first main surface 3. The interlayer insulating film 30 may include silicon oxide. The interlayer insulating film 30 has multiple contact holes 31. The multiple contact holes 31 include multiple source contact holes that expose the source region 10 and the contact region 12. The multiple contact holes 31 also include multiple gate contact holes that expose the gate electrodes 27 of the multiple planar gate structures 25 in a region not shown.

[0043] 1 and 3, the semiconductor device 1 includes a gate terminal 32 and a source terminal 33 formed on an interlayer insulating film 30. In this embodiment, the gate terminal 32 includes a body portion 32A and a finger portion 32B. The body portion 32A is disposed on the interlayer insulating film 30 at the center side of the first side surface 5A. The body portion 32A may be formed in a quadrangular shape in a planar view. The body portion 32A may be disposed at any corner side of the semiconductor chip 2 in a planar view.

[0044] The finger portion 32B is drawn out in a strip shape from the gate terminal 32 toward an arbitrary region. In this embodiment, the finger portion 32B extends in a strip shape from the gate terminal 32 along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D in a plan view, and divides the inner region of the semiconductor chip 2 from three directions. The finger portion 32B enters the multiple contact holes 31 from above the interlayer insulating film 30, and is electrically connected to the multiple gate electrodes 27.

[0045] The source terminal 33 is disposed on the interlayer insulating film 30 in a region partitioned by the gate terminal 32 and spaced apart from the gate terminal 32. The source terminal 33 penetrates the multiple contact holes 31 from above the interlayer insulating film 30 and is electrically connected to the multiple source regions 10 and the multiple contact regions 12.

[0046] The gate terminal 32 and the source terminal 33 may each have a laminated structure including a barrier electrode film 34 and a main electrode film 35 laminated in this order from the semiconductor chip 2 side. The barrier electrode film 34 may include at least one of a Ti film and a TiN film. The main electrode film 35 may each include at least one of a pure Al film, a pure Cu film, an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. A plating film may be formed on the outer surface of the gate terminal 32 and the source terminal 33. The plating film may include at least one of a Ni film, a Pd film, and an Au film.

[0047] The semiconductor device 1 includes a drain terminal 36 formed on the second main surface 4. The drain terminal 36 is electrically connected to the drain region 7. The drain terminal 36 may include at least one of a Ti film, a Ni film, an Au film, an Ag film, and an Al film.

[0048] Next, the p-type impurity concentrations of the multiple column regions 20 will be specifically described with reference to Fig. 4. Since the multiple column regions 20 have the same structure, an example of the structure of one column region 20 will be described below. In Fig. 4, a region including one column region 20 is shown on the left side of the page, and the concentration gradient of the p-type impurity concentration of the column region 20 is shown on the right side of the page. The concentration gradient of the column region 20 is specifically formed by the peak concentrations of the multiple first to tenth impurity regions 24A to 24J.

[0049] In FIG. 4, the charge balance concentration Icb, which is a constant value, is indicated by a two-dot chain line. The charge balance concentration Icb is a concentration at which the column region 20 maintains charge balance with the drift region 6 in an ideal form. The charge balance is a balance between the n-type charge amount (n-type impurity concentration) in the drift region 6 and the p-type charge amount (p-type impurity concentration) in the column region 20. The charge-balanced state refers to a state in which the balance between the n-type charge amount in the drift region 6 and the p-type charge amount in the column region 20 is maintained. When the column region 20 is formed with the charge balance concentration Icb, the breakdown voltage (specifically, the breakdown voltage BVDSS) of the semiconductor device 1 reaches its theoretical maximum value.

[0050] 4, the column region 20 includes a compensation region 40 formed between the lower end 21 and the upper end 23. Specifically, the compensation region 40 includes a low concentration portion 41 on the lower end 21 side and a high concentration portion 42 on the upper end 23 side. The low concentration portion 41 is a region having a relatively low p-type impurity concentration between the lower end 21 and the intermediate portion 22. The high concentration portion 42 is a region having a relatively high p-type impurity concentration between the intermediate portion 22 and the upper end 23. The high concentration portion 42 has a p-type impurity concentration that exceeds the p-type impurity concentration of the low concentration portion 41. The compensation region 40 compensates for charge balance in a p-type impurity concentration range between the low concentration portion 41 and the high concentration portion 42.

[0051] In this embodiment, the low concentration portion 41 has a p-type impurity concentration less than the charge balance concentration Icb. The low concentration portion 41 may have a p-type impurity concentration less than the average concentration Iav of the column region 20. The average concentration Iav is preferably set within a range of ±5% of the charge balance concentration Icb. The average concentration Iav may be equal to the charge balance concentration Icb. The p-type impurity concentration of the low concentration portion 41 may be set in a range of 85% or more and less than 100% (preferably 95% or more and less than 100%) of the charge balance concentration Icb (or the average concentration Iav).

[0052] In this embodiment, the low concentration portion 41 is formed in the entire region between the bottom end portion 21 and the intermediate portion 22. That is, the low concentration portion 41 is formed by the first to fifth impurity regions 24A to 24E. The peak concentrations of the first to fifth impurity regions 24A to 24E gradually increase from the bottom end portion 21 toward the intermediate portion 22.

[0053] Therefore, the low concentration portion 41 has a concentration gradient in which the p-type impurity concentration increases (specifically, gradually increases) from the lower end portion 21 toward the intermediate portion 22. As long as the p-type impurity concentration on the intermediate portion 22 side exceeds the p-type impurity concentration on the lower end portion 21 side, at least two of the first to fifth impurity regions 24B to 24E may have the same p-type impurity concentration (peak concentration).

[0054] In this embodiment, the high concentration portion 42 has a p-type impurity concentration that exceeds the charge balance concentration Icb. The high concentration portion 42 may be set to a value that exceeds the average concentration Iav. The p-type impurity concentration of the high concentration portion 42 may be set in a range of more than 100% and not more than 115% (preferably more than 100% and not more than 105%) of the charge balance concentration Icb (or the average concentration Iav).

[0055] In this embodiment, the high concentration portion 42 is formed in the entire region between the intermediate portion 22 and the upper end portion 23. That is, the high concentration portion 42 is formed by the sixth to tenth impurity regions 24F to 24J. The peak concentrations of the sixth to tenth impurity regions 24F to 24J gradually increase from the intermediate portion 22 toward the upper end portion 23. Therefore, the high concentration portion 42 has a concentration gradient in which the p-type impurity concentration increases (specifically, gradually increases) from the intermediate portion 22 toward the upper end portion 23.

[0056] In this embodiment, the peak concentrations of the sixth to tenth impurity regions 24F to 24J gradually increase continuously from the first to fifth impurity regions 24A to 24E (i.e., the low concentration portion 41). Therefore, the high concentration portion 42 has a concentration gradient in which the p-type impurity concentration increases continuously from the low concentration portion 41. As long as the condition that the p-type impurity concentration on the upper end portion 23 side exceeds the p-type impurity concentration on the intermediate portion 22 side is satisfied, at least two of the sixth to tenth impurity regions 24F to 24J may have the same p-type impurity concentration (peak concentration).

[0057] Thus, in this embodiment, the compensation region 40 has a concentration gradient in which the p-type impurity concentration increases (specifically, gradually increases) from the lower end 21 toward the upper end 23. Also, the concentration gradient of the compensation region 40 extends from the low concentration portion 41 across the charge balance concentration Icb to the high concentration portion 42. That is, in the column region 20 according to the first embodiment, a concentration gradient deviated from the charge balance concentration Icb is introduced between the lower end 21 and the upper end 23 by the compensation region 40.

[0058] Fig. 5 is a graph for explaining the breakdown voltage BVDSS (actual measurement) when the column region 20 shown in Fig. 4 is employed. In Fig. 5, the vertical axis indicates the breakdown voltage BVDSS [V], and the horizontal axis indicates the second width W2 [μm] of the column region 20. The relationship between the breakdown voltage BVDSS and the second width W2 indicates the process error occurring in the column region 20. Fig. 5 shows a first broken line L1 (two-dot chain line) and a second broken line L2 (solid line).

[0059] The first broken line L1 shows the result when a column region 20 having a constant charge balance concentration Icb (hereinafter simply referred to as the "column region 20 according to the comparative example") is formed. In the column region 20 according to the comparative example, the design value of the second width W2 at which the breakdown voltage BVDSS is maximized is about 1.5 μm. The second broken line L2 shows the result when a column region 20 having a compensation region 40 (the column region 20 according to the first embodiment) is formed. In the column region 20 according to the first embodiment, the design value of the second width W2 at which the breakdown voltage BVDSS is maximized is about 1.42 μm.

[0060] Referring to the first broken line L1, in the case of the column region 20 according to the comparative example, when the second width W2 is formed according to the design value, a relatively high breakdown voltage BVDSS can be realized. However, when the second width W2 deviates from the design value, the breakdown voltage BVDSS drops sharply. From this result, it was found that while the column region 20 according to the comparative example can realize a relatively high breakdown voltage BVDSS, the variation of the breakdown voltage BVDSS with respect to the process error of the second width W2 is extremely large.

[0061] On the other hand, referring to the second broken line L2, in the case of the column region 20 according to the first embodiment, the increase in the breakdown voltage BVDSS is small, but the sudden decrease in the breakdown voltage BVDSS caused by the process error is suppressed. In other words, it was found that, in the column region 20 according to the first embodiment, the breakdown voltage BVDSS is decreased, but the change in the breakdown voltage BVDSS caused by the process error is slower, compared to the column region 20 according to the comparative example.

[0062] In the column region 20 according to the comparative example, when the second width W2 is increased from the design value, the amount of p-type charge in the column region 20 exceeds the amount of n-type charge in the drift region 6. In this case, an electric field is concentrated at the lower end 21 of the column region 20, and the breakdown voltage BVDSS is reduced. On the other hand, when the second width W2 is decreased from the design value, the amount of n-type charge in the drift region 6 exceeds the amount of p-type charge in the column region 20. In this case, an electric field is concentrated at the upper end 23 of the column region 20, and the breakdown voltage BVDSS is reduced.

[0063] In contrast, the column region 20 according to the first embodiment includes a compensation region 40 having a concentration gradient deviated from the charge balance concentration Icb in a region between the lower end 21 and the upper end 23. Specifically, the compensation region 40 includes a low concentration portion 41 on the lower end 21 side and a high concentration portion 42 on the upper end 23 side, and compensates for charge balance in the p-type impurity concentration range between the low concentration portion 41 and the high concentration portion 42.

[0064] The column region 20 according to the first embodiment does not have a structure that achieves charge balance over the entire thickness direction, and therefore has a lower breakdown voltage BVDSS than the column region 20 according to the comparative example. However, the low concentration portion 41 of the compensation region 40 is formed in the region between the lower end portion 21 and the intermediate portion 22 where the electric field is likely to concentrate, and has a relatively low p-type impurity concentration. On the other hand, the high concentration portion 42 of the compensation region 40 is formed in the region between the intermediate portion 22 and the lower end portion 21 where the electric field is likely to concentrate, and has a relatively high p-type impurity concentration.

[0065] Therefore, even if the second width W2 increases from the design value due to a process error, the low concentration portion 41 can alleviate the electric field concentration at the bottom end 21. Also, even if the second width W2 decreases from the design value due to a process error, the high concentration portion 42 can alleviate the electric field concentration at the top end 23. As a result, the fluctuation of the breakdown voltage BVDSS caused by the process error of the second width W2 can be suppressed. Therefore, the semiconductor device 1 having a breakdown voltage BVDSS equal to or higher than a certain value can be stably manufactured.

[0066] Fig. 6 is a diagram for explaining the p-type impurity concentration of the column region 20 according to the second embodiment. In Fig. 6, a region including one column region 20 is shown on the left side of the paper, and the gradient of the p-type impurity concentration of the column region 20 is shown on the right side of the paper. The concentration gradient of the column region 20 is specifically formed by the peak concentrations of the first to tenth impurity regions 24A to 24J. In Fig. 6, the charge balance concentration Icb is indicated by a two-dot chain line.

[0067] The column region 20 includes a lower compensation region 50 on the lower end 21 side, and an upper compensation region 51 on the upper end 23 side. The column region 20 further includes a compensation region 52 formed between the lower compensation region 50 and the upper compensation region 51. Below, the lower compensation region 50, the upper compensation region 51, and the compensation region 52 will be described in order.

[0068] The lower compensation region 50 is formed in a region between the lower end 21 and the intermediate portion 22. Specifically, the lower compensation region 50 is formed in a region on the lower end 21 side with a gap from the intermediate portion 22 toward the lower end 21. In this embodiment, the lower compensation region 50 is formed by first to third impurity regions 24A to 24C.

[0069] The lower compensation region 50 includes a low concentration portion 53 formed between the lower end portion 21 and the intermediate portion 22, and a lower high concentration portion 54 formed between the low concentration portion 53 and the lower end portion 21. The lower high concentration portion 54 is a region having a p-type impurity concentration that exceeds the p-type impurity concentration of the low concentration portion 53 on the lower end portion 21 side of the low concentration portion 53. In other words, the lower compensation region 50 is composed of a concentration increasing region formed in a region on the lower end portion 21 side of the column region 20. The lower compensation region 50 compensates for charge balance in the impurity concentration range between the low concentration portion 53 and the lower high concentration portion 54.

[0070] The low concentration portion 53 is formed at least from the lower end portion 21 toward the intermediate portion 22 with a gap therebetween. In this embodiment, the low concentration portion 53 is formed from the intermediate portion 22 toward the lower end portion 21 with a gap therebetween. The low concentration portion 53 may overlap the intermediate portion 22. In this embodiment, the low concentration portion 53 has the p-type impurity concentration (peak concentration) of the second to third impurity regions 24B to 24C.

[0071] In this embodiment, the p-type impurity concentrations (peak concentrations) of the second to third impurity regions 24B to 24C are less than the charge balance concentration Icb. Therefore, in this embodiment, the low concentration portion 53 has a p-type impurity concentration less than the charge balance concentration Icb. The low concentration portion 53 may be set to a value less than the average concentration Iav of the column region 20. The average concentration Iav is preferably set within a range of ±5% of the charge balance concentration Icb. The average concentration Iav may be equal to the charge balance concentration Icb.

[0072] The p-type impurity concentration of the low concentration portion 53 may be set, for example, in a range of 85% or more and less than 100% (preferably in a range of 95% or more and less than 100%) of the charge balance concentration Icb (or the average concentration Iav). The low concentration portion 53 preferably has a p-type impurity concentration that is the minimum value in the concentration gradient of the column region 20. With this structure, electric field concentration at the lower end portion 21 can be appropriately suppressed.

[0073] The lower high concentration portion 54 is formed at the bottom end of the column region 20. In this embodiment, the lower high concentration portion 54 has the p-type impurity concentration (peak concentration) of the first and second impurity regions 24A and 24B. In this embodiment, the p-type impurity concentration (peak concentration) of the first impurity region 24A exceeds the charge balance concentration Icb. Therefore, in this embodiment, the lower high concentration portion 54 has a p-type impurity concentration that exceeds the charge balance concentration Icb. The lower high concentration portion 54 may be set to a value that exceeds the average concentration Iav.

[0074] The p-type impurity concentration of the lower high concentration portion 54 may be set in a range of more than 100% to not more than 115% (preferably more than 100% to not more than 105%) of the charge balance concentration Icb (or average concentration Iav). It is preferable that the lower high concentration portion 54 has a p-type impurity concentration less than the maximum value in the concentration gradient of the column region 20. With this structure, electric field concentration on the lower end portion 21 can be appropriately suppressed.

[0075] In this embodiment, the second impurity region 24B has a p-type impurity concentration (peak concentration) between the p-type impurity concentration (peak concentration) of the first impurity region 24A and the p-type impurity concentration (peak concentration) of the third impurity region 24C. As a result, the lower compensation region 50 has a concentration gradient in which the p-type impurity concentration increases (specifically, gradually increases) from the low concentration portion 53 toward the lower high concentration portion 54. The lower compensation region 50 also has a concentration gradient from the low concentration portion 53 across the charge balance concentration Icb to the lower high concentration portion 54.

[0076] The number of impurity regions 24 constituting the lower compensation region 50 varies depending on the number of impurity regions 24 constituting the column region 20, but is preferably 2 to 5. When the lower compensation region 50 includes three or more impurity regions 24, at least two of the three or more impurity regions 24 may have the same p-type impurity concentration (peak concentration) as long as the p-type impurity concentration of the lower high concentration portion 54 exceeds the p-type impurity concentration of the low concentration portion 53. For example, the second impurity region 24B may have a p-type impurity concentration equal to the p-type impurity concentration of either the first impurity region 24A or the third impurity region 24C.

[0077] The upper compensation region 51 is formed in a region between the intermediate portion 22 and the upper end portion 23. Specifically, the upper compensation region 51 is formed in a region on the upper end portion 23 side with a gap therebetween from the intermediate portion 22 toward the upper end portion 23. In this embodiment, the upper compensation region 51 is formed by sixth to tenth impurity regions 24F to 24J.

[0078] Specifically, the upper compensation region 51 includes a high concentration portion 55 formed between the intermediate portion 22 and the upper end portion 23, and an upper low concentration portion 56 formed between the high concentration portion 55 and the upper end portion 23. The upper low concentration portion 56 is a region that is closer to the upper end portion 23 than the high concentration portion 55 and has a p-type impurity concentration lower than the p-type impurity concentration of the high concentration portion 55. In other words, the upper compensation region 51 is made of a concentration decreasing region formed in a region on the upper end portion 23 side of the column region 20. The upper compensation region 51 compensates for charge balance in an impurity concentration range between the high concentration portion 55 and the upper low concentration portion 56.

[0079] The high concentration portion 55 is formed at least from the upper end portion 23 toward the intermediate portion 22 with a gap therebetween. The high concentration portion 55 may be formed from the intermediate portion 22 toward the upper end portion 23 with a gap therebetween. When the low concentration portion 53 is formed from the intermediate portion 22 to the lower end portion 21 with a gap therebetween, the high concentration portion 55 may overlap the intermediate portion 22. In this embodiment, the high concentration portion 55 has the p-type impurity concentrations (peak concentrations) of the sixth to ninth impurity regions 24F to 24I.

[0080] In this embodiment, the high concentration portion 55 has a p-type impurity concentration that exceeds the charge balance concentration Icb. The high concentration portion 55 may be set to a value that exceeds the average concentration Iav. The p-type impurity concentration of the high concentration portion 55 may be set, for example, in a range of more than 100% to not more than 115% (preferably more than 100% to not more than 105%) of the charge balance concentration Icb (or the average concentration Iav).

[0081] The high concentration portion 55 preferably has a p-type impurity concentration that is a maximum value in the concentration gradient of the column region 20. In other words, the high concentration portion 55 preferably has a p-type impurity concentration that exceeds the p-type impurity concentration of the lower high concentration portion 54. With this structure, electric field concentration on the upper end portion 23 can be appropriately suppressed. The high concentration portion 55 includes a plurality of (three in this embodiment) sixth to eighth impurity regions 24F to 24H in which the p-type impurity concentration (peak concentration) is set to a maximum value. In the high concentration portion 55, the number of impurity regions 24 that are set to the maximum value is arbitrary, and may be one or more.

[0082] The upper low concentration portion 56 is formed at the uppermost end of the column region 20. In this embodiment, the upper low concentration portion 56 has the p-type impurity concentration (peak concentration) of the ninth to tenth impurity regions 24I to 24J. In this embodiment, the tenth impurity region 24J has a p-type impurity concentration less than the charge balance concentration Icb. Therefore, in this embodiment, the upper low concentration portion 56 has a p-type impurity concentration less than the charge balance concentration Icb. The upper low concentration portion 56 may be set to a value less than the average concentration Iav.

[0083] The p-type impurity concentration of the upper low concentration portion 56 may be set, for example, in a range of 85% or more and less than 100% (preferably in a range of 95% or more and less than 100%) of the charge balance concentration Icb (or the average concentration Iav). The upper low concentration portion 56 preferably has a p-type impurity concentration that exceeds the minimum value and is less than the maximum value in the concentration gradient of the column region 20. In other words, the upper low concentration portion 56 preferably has a p-type impurity concentration that exceeds the p-type impurity concentration of the low concentration portion 53 and is less than the p-type impurity concentration of the high concentration portion 55. With this structure, electric field concentration on the upper end portion 23 can be appropriately suppressed.

[0084] The upper end 23 of the column region 20 is a path through which current flows in, and therefore the current density (i.e., the electric field) is particularly likely to increase. Therefore, it is preferable that the upper low concentration portion 56 has a thickness less than that of the high concentration portion 55. In other words, it is preferable that the proportion of the upper low concentration portion 56 in the upper compensation region 51 is less than the proportion of the high concentration portion 55 in the upper compensation region 51. According to this structure, the p-type impurity concentration that is reduced with the introduction of the upper low concentration portion 56 is complemented by the high concentration portion 55. This makes it possible to appropriately alleviate the electric field concentration at the upper end 23.

[0085] In this embodiment, the ninth impurity region 24I has a p-type impurity concentration (peak concentration) between the p-type impurity concentration (peak concentration) of the eighth impurity region 24I and the p-type impurity concentration (peak concentration) of the tenth impurity region 24J. As a result, the upper compensation region 51 has a concentration gradient in which the p-type impurity concentration decreases (specifically, gradually decreases) from the high concentration portion 55 toward the upper low concentration portion 56.

[0086] Moreover, the upper compensation region 51 has a concentration gradient that extends from the high concentration portion 55 across the charge balance concentration Icb to the upper low concentration portion 56. That is, the upper compensation region 51 has a p-type impurity concentration range (concentration gradient) that overlaps with the p-type impurity concentration range (concentration gradient) of the lower compensation region 50 on the upper end portion 23 side.

[0087] The number of impurity regions 24 constituting the upper compensation region 51 varies depending on the number of impurity regions 24 constituting the column region 20, but is preferably 2 to 5. When the upper compensation region 51 includes three or more impurity regions 24, at least two of the three or more impurity regions 24 may have the same p-type impurity concentration (peak concentration) as long as the p-type impurity concentration of the upper low concentration portion 56 is lower than the p-type impurity concentration of the high concentration portion 55. For example, the ninth impurity region 24I may have a p-type impurity concentration equal to the p-type impurity concentration of either the eighth impurity region 24H or the tenth impurity region 24J.

[0088] The compensation region 52 includes a low concentration portion 53 and a high concentration portion 55. That is, the compensation region 52 is composed of a concentration increasing region formed in the middle region of the column region 20. The compensation region 52 compensates for the charge balance between the low concentration portion 53 (lower compensation region 50) and the high concentration portion 55 (upper compensation region 51).

[0089] In this embodiment, the compensation region 52 has the p-type impurity concentrations (peak concentrations) of the third to sixth impurity regions 24C to 24F. In this embodiment, since the sixth to eighth impurity regions 24F to 24H have the same impurity concentrations, the compensation region 52 may include the seventh to eighth impurity regions 24G to 24H. The p-type impurity concentrations (peak concentrations) of the fourth and fifth impurity regions 24D to 24E increase (specifically, gradually increase) from the low concentration portion 53 to the high concentration portion 55. As a result, the compensation region 52 is formed such that the p-type impurity concentration increases (specifically, gradually increases) from the low concentration portion 53 to the high concentration portion 55.

[0090] The compensation region 52 has a concentration gradient that extends from the low concentration portion 53 across the charge balance concentration Icb to the high concentration portion 55. In other words, the compensation region 52 has a p-type impurity concentration range (concentration gradient) that overlaps with the p-type impurity concentration range (concentration gradient) of the lower compensation region 50 and the p-type impurity concentration range (concentration gradient) of the upper compensation region 51.

[0091] The number of impurity regions 24 in compensation region 52 varies depending on the number of impurity regions 24, but is preferably 2 to 10. When compensation region 52 includes three or more impurity regions 24, at least two of the three or more impurity regions 24 may have the same p-type impurity concentration (peak concentration), as long as the p-type impurity concentration of high concentration portion 55 exceeds the p-type impurity concentration of low concentration portion 53. For example, fourth and fifth impurity regions 24D to 24E may have the same p-type impurity concentration.

[0092] In this way, in the column region 20 according to the second embodiment, a concentration gradient deviated from the charge balance concentration Icb is introduced between the lower end 21 and the upper end 23 by the lower compensation region 50, the compensation region 52, and the upper compensation region 51. Therefore, in the column region 20 according to the second embodiment, the charge balance is not achieved over the entire region in the thickness direction. In the column region 20 according to the second embodiment, the charge balance with the drift region 6 is compensated for by three points, the lower compensation region 50, the compensation region 52, and the upper compensation region 51.

[0093] Fig. 7 is a graph in which the measurement results of the breakdown voltage BVDSS (actual measurement) when the column region 20 according to the second embodiment is adopted are reflected in Fig. 5. In Fig. 7, the vertical axis indicates the breakdown voltage BVDSS, and the horizontal axis indicates the second width W2 of the column region 20. Fig. 7 shows the process error occurring in the column region 20.

[0094] 7 shows a third broken line L3 (thick line) in addition to the first broken line L1 (two-dot chain line) and the second broken line L2 (solid line). The third broken line L3 shows the result when the column region 20 according to the second embodiment is formed. In the column region 20 according to the second embodiment, the design value of the second width W2 at which the breakdown voltage BVDSS is maximized is about 1.42 μm.

[0095] Referring to the third broken line L3, in the case of the column region 20 according to the second embodiment, the breakdown voltage BVDSS is lower than that of the column region 20 according to the comparative example, but the amount of change in the breakdown voltage BVDSS caused by the process error is slower.

[0096] On the other hand, in the case of the column region 20 according to the second embodiment, the amount of change in the breakdown voltage BVDSS caused by the process error became steeper than in the column region 20 according to the first embodiment, but the breakdown voltage BVDSS improved. Thus, it was found that the column region 20 according to the second embodiment can suppress the fluctuation in the breakdown voltage BVDSS caused by the process error while suppressing the decrease in the breakdown voltage BVDSS.

[0097] The column region 20 according to the second embodiment includes a lower compensation region 50 on the lower end 21 side, and an upper compensation region 51 on the upper end 23 side. The lower compensation region 50 includes a low concentration region 53 formed between the lower end 21 and the intermediate region 22, and a lower high concentration region 54 formed between the low concentration region 53 and the lower end 21. On the other hand, the upper compensation region 51 includes a high concentration region 55 formed between the intermediate region 22 and the upper end 23, and an upper low concentration region 56 formed between the high concentration region 55 and the upper end 23.

[0098] The lower compensation region 50 includes a low-concentration portion 53 having a relatively low p-type impurity concentration between the lower end portion 21 and the intermediate portion 22 where the electric field is likely to concentrate. Therefore, even if the second width W2 increases from the design value due to a process error, the low-concentration portion 53 can alleviate the electric field concentration on the lower end portion 21.

[0099] On the other hand, the upper compensation region 51 includes a high concentration portion 55 having a relatively high p-type impurity concentration between the intermediate portion 22 and the lower end portion 21 where the electric field is likely to concentrate. Therefore, even if the second width W2 is reduced from the design value due to a process error, the high concentration portion 55 can alleviate the electric field concentration on the upper end portion 23. As a result, the fluctuation of the breakdown voltage BVDSS due to the process error of the second width W2 can be suppressed.

[0100] The lower compensation region 50 also has a lower high concentration region 54 located on the lower end 21 side relative to the low concentration region 53. The lower compensation region 50 compensates for the charge balance in the impurity concentration range between the low concentration region 53 and the lower high concentration region 54. On the other hand, the upper compensation region 51 has an upper low concentration region 56 located on the upper end 23 side relative to the high concentration region 55. The upper compensation region 51 compensates for the charge balance in the impurity concentration range between the high concentration region 55 and the upper low concentration region 56.

[0101] Therefore, according to the column region 20 of the second embodiment, charge balance can be achieved by the lower compensation region 50 on the lower end 21 side and the upper compensation region 51 on the upper end 23 side. As a result, it is possible to suppress the fluctuation of the breakdown voltage BVDSS caused by the process error of the second width W2 while suppressing the decrease of the breakdown voltage BVDSS. Therefore, it is possible to stably manufacture the semiconductor device 1 having a breakdown voltage BVDSS equal to or higher than a certain value.

[0102] The column region 20 according to the second embodiment further includes a compensation region 52 interposed between the lower compensation region 50 and the upper compensation region 51. The compensation region 52 compensates for the charge balance in an impurity concentration range between the lower compensation region 50 and the upper compensation region 51. This allows the charge balance to be compensated for at three locations, the lower compensation region 50, the upper compensation region 51, and the compensation region 52. Therefore, while appropriately suppressing a decrease in the breakdown voltage BVDSS, it is possible to appropriately suppress fluctuations in the breakdown voltage BVDSS caused by process errors in the second width W2.

[0103] The present invention can be embodied in other forms. For example, in the above-mentioned embodiment, an example in which a MISFET having an SJ structure is formed has been described. However, the column region 20 according to the first and second embodiments is not limited to MISFETs and can be applied to various devices having an Sj structure. The column region 20 according to the first and second embodiments may be applied to, for example, an SBD (Schottky Barrier Diode) having an SJ structure.

[0104] In the above embodiment, an example has been described in which the semiconductor chip 2 is a Si chip. However, the semiconductor chip 2 may be a wide band gap semiconductor chip. In this case, the semiconductor chip 2 may be a SiC (silicon carbide) chip.

[0105] In the above embodiment, an example has been described in which the multiple column regions 20 are formed in a stripe pattern in a plan view. However, the multiple column regions 20 may each be formed in a circular or polygonal shape in a plan view. In this case, the multiple column regions 20 may be formed at intervals in the first direction X and the second direction Y in a plan view. The multiple column regions 20 may be arranged, for example, in a matrix or a staggered pattern in a plan view.

[0106] Examples of features extracted from this specification and the drawings are given below. The following [A1] to [A18] provide a semiconductor device capable of suppressing fluctuations in breakdown voltage caused by process errors.

[0107] [A1] A semiconductor device comprising: a semiconductor chip having a main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; and a column region of a second conductivity type formed in the drift region in a column shape extending in a thickness direction, the column region having a lower end, an intermediate portion and an upper end, the column region including a low concentration portion formed between the lower end and the intermediate portion, and a high concentration portion formed between the intermediate portion and the upper end, the column region having a compensation region that compensates for charge balance in an impurity concentration range between the low concentration portion and the high concentration portion.

[0108] [A2] The semiconductor device according to A1, wherein the compensation region is formed so that the impurity concentration increases from the low concentration portion to the high concentration portion.

[0109] [A3] The semiconductor device according to A1 or A2, wherein the lower end is formed at a distance from a bottom of the drift region.

[0110] [A4] The semiconductor device according to any one of A1 to A3, wherein the column region is composed of a plurality of impurity regions of the second conductivity type stacked in a column shape in a thickness direction of the drift region.

[0111] [A5] The semiconductor device according to any one of A1 to A4, further including a base region of a second conductivity type formed in a surface layer portion of the drift region, and the column region is formed in a region of the drift region directly below the base region.

[0112] [A6] The semiconductor device according to A5, wherein the upper end is connected to the base region.

[0113] [A7] The semiconductor device according to A5 or A6, wherein the base region has a first width, and the column region has a second width less than the first width.

[0114] [A8] The semiconductor device according to any one of A5 to A7, further including: a drain region of a first conductivity type formed in a region directly below the drift region in the semiconductor chip; a source region of the first conductivity type formed in a surface layer portion of the base region and defining a channel region between the drift region and the source region; and a planar gate structure formed on the main surface to face the channel region.

[0115] [A9] The semiconductor device according to any one of A1 to A8, wherein the low concentration portion is formed at an interval from the lower end toward the intermediate portion.

[0116] [A10] The semiconductor device according to any one of A1 to A9, wherein the high concentration portion is formed at an interval from the upper end portion toward the intermediate portion.

[0117] [A11] The semiconductor device according to any one of A1 to A10, wherein the column region includes the low concentration portion, and a lower high concentration portion formed between the low concentration portion and the lower end portion, and has a lower compensation region that compensates for charge balance in an impurity concentration range between the low concentration portion and the lower high concentration portion.

[0118] [A12] The semiconductor device according to A11, wherein the lower compensation region is formed so that the impurity concentration increases from the low concentration portion toward the lower high concentration portion.

[0119] [A13] The semiconductor device according to any one of A1 to A12, wherein the column region includes the high concentration portion and an upper low concentration portion formed between the high concentration portion and the upper end portion, and has an upper compensation region that compensates for charge balance in an impurity concentration range between the high concentration portion and the upper low concentration portion.

[0120] [A14] The semiconductor device according to A13, wherein the upper compensation region is formed such that the impurity concentration decreases from the high concentration portion toward the upper low concentration portion.

[0121] [A15] A semiconductor device comprising: a semiconductor chip having a main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; and a column region of a second conductivity type formed in the drift region in a column shape extending in a thickness direction and having a lower end, an intermediate portion, and an upper end, wherein the column region includes a low concentration portion formed between the lower end and the intermediate portion, and a lower high concentration portion formed between the low concentration portion and the lower end, and a lower compensation region that compensates for charge balance in an impurity concentration range between the low concentration portion and the lower high concentration portion; and an upper compensation region that includes a high concentration portion formed between the intermediate portion and the upper end, and an upper low concentration portion formed between the high concentration portion and the upper end, and

[0122] [A16] The semiconductor device according to A15, wherein the lower compensation region is formed so that the impurity concentration increases from the low concentration portion toward the lower high concentration portion.

[0123] [A17] The semiconductor device according to A15 or A16, wherein the upper compensation region is formed such that the impurity concentration decreases from the high concentration portion toward the upper low concentration portion.

[0124] [A18] The semiconductor device according to any one of A15 to A17, wherein the high concentration portion has a higher concentration than the lower high concentration portion, and the upper low concentration portion has a higher concentration than the low concentration portion.

[0125] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0126] 1 Semiconductor device 2. Semiconductor chips 3 First main surface 6 Drift Region 7 Drain Region 9 Base Area 10 Source Area 11 Channel Region 20 Column Area 21 Lower end 22 Middle section 23 Upper end 25 Planar gate structure 40 Compensation area 41 Low concentration part 42 High concentration area 50 upper compensation area 51 Lower compensation area 52 Compensation area 53 Low concentration part 55 High concentration area W1 1st width W2 Second width

Claims

1. A semiconductor chip having a main surface, A drift region of a first conductivity type formed in a surface layer portion of the main surface, A column region of a second conductivity type formed in a column shape extending in the thickness direction within the drift region, having a lower end portion, an intermediate portion, and an upper end portion, The column region has a lower compensation region and a compensation region, and a high concentration portion formed between the intermediate portion and the upper end portion, The lower compensation region is formed between the lower end portion and the intermediate portion, has a low concentration portion having an impurity concentration less than the impurity concentration of the high concentration portion, and is formed between the low concentration portion and the lower end portion, and includes a lower high concentration portion having an impurity concentration exceeding the impurity concentration of the low concentration portion, and compensates for charge balance within the impurity concentration range between the low concentration portion and the lower high concentration portion, The semiconductor device, wherein the compensation region compensates for charge balance within the impurity concentration range between the lower compensation region and the high concentration portion.

2. The semiconductor device according to claim 1, wherein the compensation region is formed such that the impurity concentration increases from the low concentration portion toward the high concentration portion.

3. The semiconductor device according to claim 1 or 2, wherein the lower end portion of the column region is formed at a distance from the bottom of the drift region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the column region is composed of a plurality of impurity regions of the second conductivity type stacked in a column shape in the thickness direction of the drift region.

5. Further including a base region of the second conductivity type formed in a surface layer portion of the drift region, The semiconductor device according to any one of claims 1 to 4, wherein the column region is formed in a region directly below the base region in the drift region.

6. The semiconductor device according to claim 5, wherein the upper end portion of the column region is connected to the base region.

7. The base region has a first width, The semiconductor device according to claim 5 or 6, wherein the column region has a second width less than the first width.

8. A drain region of the first conductivity type formed in a region of the semiconductor chip opposite to the main surface with respect to the drift region, A source region of the first conductivity type formed in a surface layer portion of the base region and defining a channel region with the drift region, The semiconductor device according to any one of claims 5 to 7, further comprising a planar gate structure formed on the main surface so as to face the channel region.

9. The semiconductor device according to any one of claims 1 to 8, wherein the low-concentration portion is formed at a distance from the lower end portion toward the intermediate portion side.

10. The semiconductor device according to any one of claims 1 to 9, wherein the high-concentration portion is formed at a distance from the upper end portion toward the intermediate portion side.

11. The semiconductor device according to any one of claims 1 to 10, wherein the lower compensation region is formed such that the impurity concentration increases from the low-concentration portion toward the lower high-concentration portion.

12. The column region further has an upper compensation region, The upper compensation region includes the high-concentration portion and an upper low-concentration portion formed between the high-concentration portion and the upper end portion and having an impurity concentration less than that of the high-concentration portion, and compensates for charge balance within the impurity concentration range between the high-concentration portion and the upper low-concentration portion. The semiconductor device according to any one of claims 1 to 11.

13. The semiconductor device according to claim 12, wherein the upper compensation region is formed such that the impurity concentration decreases from the high-concentration portion toward the upper low-concentration portion.

14. A semiconductor chip having a main surface, A drift region of a first conductivity type formed in a surface layer portion of the main surface, A column region of a second conductivity type formed in a column shape extending in the thickness direction within the drift region and having a lower end portion, an intermediate portion, and an upper end portion, The column region has a lower compensation region and an upper compensation region, The lower compensation region includes a low-concentration portion formed between the lower end portion and the intermediate portion, and a lower high-concentration portion formed between the low-concentration portion and the lower end portion and having an impurity concentration exceeding that of the low-concentration portion, and compensates for charge balance within the impurity concentration range between the low-concentration portion and the lower high-concentration portion. The upper compensation region includes a high-concentration portion formed between the intermediate portion and the upper end portion, and an upper low-concentration portion formed between the high-concentration portion and the upper end portion and having an impurity concentration less than that of the high-concentration portion, and compensates for charge balance within the impurity concentration range between the high-concentration portion and the upper low-concentration portion. A semiconductor device.

15. The semiconductor device according to claim 14, wherein the lower compensation region is formed such that the impurity concentration increases from the low-concentration portion toward the lower high-concentration portion.

16. The semiconductor device according to claim 14 or 15, wherein the upper compensation region is formed such that the impurity concentration decreases from the high-concentration portion toward the upper low-concentration portion.

17. The lower end region of the high-concentration portion has a higher concentration than the lower end region of the lower high-concentration portion, The semiconductor device according to any one of claims 14 to 16, wherein the upper end region of the upper low-concentration portion has a higher concentration than the upper end region of the low-concentration portion.

18. The column region further has a compensation region, The semiconductor device according to any one of claims 14 to 17, wherein the compensation region compensates for charge balance within the impurity concentration range between the low-concentration portion and the high-concentration portion.

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