Imaging device

Abstract

An imaging device according to one embodiment in the present disclosure comprises: a pixel region which includes a pixel transistor including a gate; a first peripheral region which includes at least one first peripheral transistor including a gate and is positioned to the outer side of the pixel region; and a semiconductor substrate which includes a first substrate section. The length of the gate of the at least one first peripheral transistor is shorter than the length of the gate of the pixel transistor. When at least one type of impurity contributing to the suppression of transient accelerated diffusion of conductive impurities is defined as a specific type, the at least one first peripheral transistor is positioned within the first substrate section and includes a first specific layer containing conductive impurities and the specific type.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] 2. Description of the Related Art Image sensors are used in digital cameras etc. Examples of image sensors include CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors.

[0003] In an image sensor according to one example, a photodiode is provided on a semiconductor substrate.

[0004] In another example of the image sensor, a photoelectric conversion layer is provided above a semiconductor substrate. An imaging device having such a structure is sometimes called a stacked type imaging device.

[0005] In a stacked-type imaging device according to a specific example, signal charges are generated by photoelectric conversion. The generated charges are stored in a charge storage node. A signal corresponding to the amount of charge stored in the charge storage node is read out via a CCD circuit or a CMOS circuit formed on a semiconductor substrate.

[0006] An imaging device is described in Patent Document 1. The imaging device in Patent Document 1 includes a pixel region and a peripheral region located outside the pixel region. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2019-24075 A [Patent Document 2] Patent No. 5235486 Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Document 1, there is no detailed consideration of improving the performance of the imaging device by taking into account the presence of transistors in the peripheral region. [Means for solving the problem]

[0009] An imaging device according to an embodiment of the present disclosure includes a pixel region including a pixel transistor including a gate, a first peripheral region including at least one first peripheral transistor including a gate and located outside the pixel region, and a semiconductor substrate including a first substrate portion. The gate length of the at least one first peripheral transistor is shorter than the gate length of the pixel transistor. When at least one type of impurity that contributes to suppression of transient enhanced diffusion of a conductive impurity is defined as a specific species, the at least one first peripheral transistor includes a first specific layer located in the first substrate portion and containing the conductive impurity and the specific species. Effect of the Invention

[0010] The technology according to the present disclosure is suitable for improving the performance of an imaging device by taking into account the presence of a first peripheral transistor in a first peripheral region. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an example configuration of an imaging device. [Diagram 2] FIG. 2 is a diagram illustrating an exemplary circuit configuration of the imaging device. [Diagram 3] FIG. 3 is a schematic cross-sectional view showing a pixel region and a peripheral region, and a blocking region located between them. [Figure 4] FIG. 4 is a schematic plan view showing another example of the shape of the blocking region. [Diagram 5] FIG. 5 is a cross-sectional view showing a transistor according to the first configuration example. [Figure 6] FIG. 6 is a cross-sectional view showing a transistor according to a first modified example of the first configuration example. [Figure 7] FIG. 7 is a cross-sectional view showing a transistor according to a second modification of the first configuration example. [Figure 8] FIG. 8 is a diagram showing an impurity profile in the depth direction in a P-type source / drain diffusion layer according to the third modification of the first configuration example. [Figure 9] 9A to 9C are cross-sectional views illustrating a method for manufacturing a transistor according to the first configuration example. [Figure 10] 10A to 10C are cross-sectional views illustrating a method for manufacturing the transistor according to the first configuration example. [Figure 11] 11A to 11C are cross-sectional views illustrating a method for manufacturing the transistor according to the first configuration example. [Figure 12] FIG. 12 is a graph showing an impurity profile in the depth direction in the extension formation region according to the first configuration example. [Figure 13] FIG. 13 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 14] FIG. 14 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 15] FIG. 15 is a schematic cross-sectional view showing transistors in the pixel region and transistors in the peripheral region. [Figure 16] FIG. 16 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 17] FIG. 17 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 18] FIG. 18 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 19] FIG. 19 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 20] FIG. 20 is a schematic cross-sectional view showing transistors in a pixel region and transistors in a peripheral region. [Figure 21]FIG. 21 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Figure 22] FIG. 22 is a schematic plan view showing transistors in the pixel region and transistors in the peripheral region. [Diagram 23] FIG. 23 is a schematic cross-sectional view showing transistors in the pixel region and transistors in the peripheral region. [Figure 24] FIG. 24 is a schematic cross-sectional view showing transistors in the pixel region and transistors in the peripheral region. [Diagram 25] FIG. 25 is a schematic diagram of a back-illuminated imaging device. [Figure 26] FIG. 26 is a schematic diagram of a back-illuminated imaging device. [Figure 27] FIG. 27 is a schematic diagram of a back-illuminated imaging device. [Figure 28] FIG. 28 is a schematic diagram showing possible shapes of a pixel region and a peripheral region of an imaging device. [Figure 29] FIG. 29 is a schematic diagram showing possible shapes of a pixel region and a peripheral region of an imaging device. [Diagram 30] FIG. 30 is a schematic diagram showing possible shapes of a pixel region and a peripheral region of an imaging device. [Diagram 31] FIG. 31 is a schematic diagram showing possible shapes of a pixel region and a peripheral region of an imaging device. [Diagram 32] FIG. 32 is a schematic diagram of an imaging device for a chip stack. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Summary of one aspect of the present disclosure) An imaging device according to a first aspect of the present disclosure includes a pixel region including a pixel transistor including a gate, a first peripheral region including at least one first peripheral transistor including a gate and located outside the pixel region, and a semiconductor substrate including a first substrate portion. The gate length of the at least one first peripheral transistor is shorter than the gate length of the pixel transistor. When at least one type of impurity that contributes to suppression of transient enhanced diffusion of a conductive impurity is defined as a specific species, the at least one first peripheral transistor includes a first specific layer located in the first substrate portion and containing the conductive impurity and the specific species. In the imaging device according to the first aspect of the present disclosure, the pixel transistor may be an amplifying transistor.

[0013] The technique according to the first aspect is suitable for improving the performance of an imaging device by taking into account the presence of a first peripheral transistor in a first peripheral region.

[0014] In a second aspect of the present disclosure, for example, in the imaging device according to the first aspect, The specific species may include at least one selected from the group consisting of carbon, nitrogen, and fluorine.

[0015] The specific species of the second embodiment can suppress the transient enhanced diffusion of the conductive impurities.

[0016] In a third aspect of the present disclosure, for example, in the imaging device according to the first or second aspect, The specific species may include at least one selected from the group consisting of germanium, silicon, and argon.

[0017] The specific species of the third embodiment may include a trace of pre-amorphization that can enhance the effect of impurities such as carbon in suppressing the diffusion of conductive impurities.

[0018] In a fourth aspect of the present disclosure, for example, in the imaging device according to any one of the first to third aspects, the at least one first peripheral transistor includes a first gate insulating film; The pixel transistor may include a second gate insulating film, The first gate insulating film may be thinner than the second gate insulating film.

[0019] The configuration of the fourth aspect is an example of the configuration of an imaging device.

[0020] An imaging device according to a fifth aspect of the present disclosure, a pixel region including a pixel transistor including a gate; a first peripheral region located outside the pixel region, the first peripheral region including at least one first peripheral transistor including a gate; a semiconductor substrate including a first substrate portion; Equipped with. the at least one first peripheral transistor includes a first gate insulating film; the pixel transistor includes a second gate insulating film; the first gate insulating film is thinner than the second gate insulating film; When at least one type of impurity that contributes to suppression of the transient enhanced diffusion of the conductive impurity is defined as a specific type, The at least one first peripheral transistor is located within the first substrate portion and includes a first specific layer containing a conductivity type impurity and the specific species.

[0021] The technique according to the fifth aspect is suitable for improving the performance of an imaging device by taking into account the presence of the first peripheral transistor in the first peripheral region.

[0022] In a sixth aspect of the present disclosure, for example, in the imaging device according to the fifth aspect, The specific species may include at least one selected from the group consisting of carbon, nitrogen, and fluorine.

[0023] The specific species of the sixth embodiment can suppress the transient enhanced diffusion of the conductive impurities.

[0024] In a seventh aspect of the present disclosure, for example, in the imaging device according to the fifth or sixth aspect, The specific species may include at least one selected from the group consisting of germanium, silicon, and argon.

[0025] The specific species of the seventh embodiment may include a trace of pre-amorphization that may enhance the effect of impurities such as carbon in suppressing the diffusion of conductive impurities.

[0026] In an eighth aspect of the present disclosure, for example, in the imaging device according to any one of the first to seventh aspects, The at least one first peripheral transistor may include a first source, a first drain, and a first extension diffusion layer; The first extension diffusion layer may be adjacent to the first source or the first drain and may be shallower than the first source and the first drain, The first extension diffusion layer may include the first specific layer.

[0027] The configuration of the eighth aspect is an example of the configuration of an imaging device.

[0028] In a ninth aspect of the present disclosure, for example, in the imaging device according to any one of the first to eighth aspects, The at least one first peripheral transistor may include a first source, a first drain, and a first pocket diffusion layer adjacent to the first source or the first drain, The first pocket diffusion layer may include the first specific layer.

[0029] The configuration of the ninth aspect is an example of the configuration of an imaging device.

[0030] In a tenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to ninth aspects, The at least one first peripheral transistor may include a first source and a first drain; At least one selected from the group consisting of the first source and the first drain may include the first specific layer.

[0031] The configuration of the tenth aspect is an example of the configuration of an imaging device.

[0032] In an eleventh aspect of the present disclosure, for example, in the imaging device according to any one of the first to tenth aspects, The pixel region may include a charge accumulation region that is an impurity region and accumulates charges generated by photoelectric conversion, The concentration of carbon in the first specific layer may be higher than the concentration of carbon in the charge accumulation region.

[0033] The eleventh aspect has a feature that can be possessed by a high-performance imaging device.

[0034] In a twelfth aspect of the present disclosure, for example, in the imaging device according to any one of the first to eleventh aspects, The concentration of carbon in the first specific layer may be higher than the concentration of carbon under the gate of the pixel transistor.

[0035] The twelfth aspect has a feature that can be possessed by a high-performance imaging device.

[0036] In a thirteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to twelfth aspects, The semiconductor substrate may include a pixel substrate portion, The pixel region may include a photoelectric conversion layer laminated on the pixel substrate portion.

[0037] The configuration of the thirteenth aspect is an example of the configuration of an imaging device.

[0038] In a fourteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to thirteenth aspects, The pixel region may include a photodiode.

[0039] The configuration of the fourteenth aspect is an example of the configuration of an imaging device.

[0040] In a fifteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fourteenth aspects, The pixel transistor and the at least one first peripheral transistor may be provided on a single semiconductor substrate.

[0041] The configuration of the fifteenth aspect is an example of the configuration of an imaging device.

[0042] In a sixteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fifteenth aspects, the at least one first peripheral transistor may include an end-of-range (EOR) defect; At least a portion of the first specific layer may be located above the EOR defect and overlap with the EOR defect in a plan view.

[0043] The EOR defect of the sixteenth mode may be a trace of pre-amorphization that can enhance the effect of impurities such as carbon in suppressing the diffusion of conductive impurities.

[0044] In a seventeenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to sixteenth aspects, The at least one first peripheral transistor may include a segregation portion in which a specific species is segregated in a depth direction of the first substrate portion, At least a portion of the first specific layer may be located above the segregation portion and overlap with the segregation portion in a plan view.

[0045] The segregation portion of the seventeenth embodiment may be a trace of pre-amorphization that can enhance the effect of suppressing the diffusion of conductive impurities by impurities such as carbon.

[0046] In an eighteenth aspect of the present disclosure, for example, in the imaging device according to the seventeenth aspect, The pixel region may include a charge accumulation region that is an impurity region and accumulates charges generated by photoelectric conversion, The segregation portion may be shallower than the charge storage region.

[0047] The configuration of the 18th embodiment is an example of the configuration of an imaging device.

[0048] In a nineteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to eighteenth aspects, The at least one first peripheral transistor may include a plurality of first peripheral transistors; The first plurality of peripheral transistors may include first direction transistors and second direction transistors, In a plan view, the first direction transistor may be located in a first direction from the pixel region, In a plan view, the second direction transistor may be located in a second direction from the pixel region.

[0049] The configuration of the 19th embodiment is an example of the configuration of an imaging device.

[0050] In a twentieth aspect of the present disclosure, for example, in the imaging device according to any one of the first to nineteenth aspects, The at least one first peripheral transistor may include two first peripheral transistors; The first peripheral region may include a shallow trench isolation (STI) structure, The STI structure may isolate the two first peripheral transistors. The STI structure may include a trench. A distribution range of the specific species in the first specific layer of at least one of the two first peripheral transistors may be shallower than a bottom of the trench.

[0051] The configuration of the twentieth aspect is an example of the configuration of an imaging device.

[0052] In a twenty-first aspect of the present disclosure, for example, an imaging device according to any one of the first to twentieth aspects, The liquid crystal display may further include a second peripheral region located between the pixel region and the first peripheral region in a plan view, The second peripheral region may include a second peripheral transistor including a gate.

[0053] The configuration of the 21st embodiment is an example of the configuration of an imaging device.

[0054] In a twenty-second aspect of the present disclosure, for example, in the imaging device according to the twenty-first aspect, The at least one first peripheral transistor may include a first source, a first drain, and a first extension diffusion layer; The first extension diffusion layer may be adjacent to the first source or the first drain and may be shallower than the first source and the first drain, The second peripheral transistor may include a second source, a second drain, and a second extension diffusion layer; The second extension diffusion layer may be adjacent to the second source or the second drain and may be shallower than the second source and the second drain, A concentration of the conductive impurity in the second extension diffusion layer may be lower than a concentration of the conductive impurity in the first extension diffusion layer; The second extension diffusion layer may be deeper than the first extension diffusion layer.

[0055] The configuration of the twenty-second embodiment is an example of the configuration of the second peripheral transistor.

[0056] In a twenty-third aspect of the present disclosure, for example, in the imaging device according to the twenty-first or twenty-second aspect, A gate length of the at least one first peripheral transistor may be shorter than a gate length of the second peripheral transistor.

[0057] The configuration of the 23rd embodiment is an example of the configuration of an imaging device.

[0058] In a twenty-fourth aspect of the present disclosure, for example, in an imaging device according to any one of the twenty-first to twenty-third aspects, The gate length of the pixel transistor may be longer than the gate length of the second peripheral transistor.

[0059] The configuration of the 24th embodiment is an example of the configuration of an imaging device.

[0060] In a twenty-fifth aspect of the present disclosure, for example, in an imaging device according to any one of the twenty-first to twenty-fourth aspects, The semiconductor substrate may include a second substrate portion, The second peripheral transistor may include a second specific layer located in the second substrate portion and having a conductivity type impurity, The concentration of the specific species in the first specific layer may be higher than the concentration of the specific species in the second specific layer.

[0061] The configuration of the 25th aspect is an example of the configuration of an imaging device.

[0062] In a 26th aspect of the present disclosure, for example, in an imaging device according to any one of the 21st to 25th aspects, The semiconductor substrate may include a second substrate portion, The second peripheral transistor may include a second specific layer located in the second substrate portion and containing a conductive impurity, The concentration of carbon in the second specific layer may be higher than the concentration of carbon under the gate of the pixel transistor.

[0063] The configuration of the 26th embodiment is an example of the configuration of an imaging device.

[0064] In a 27th aspect of the present disclosure, for example, in the imaging device according to the 25th or 26th aspect, The second peripheral transistor may include a second source, a second drain, and a second extension diffusion layer; The second extension diffusion layer may be adjacent to the second source or the second drain and may be shallower than the second source and the second drain, The second extension diffusion layer may include the second specific layer.

[0065] The configuration of the 27th embodiment is an example of the configuration of an imaging device.

[0066] In a 28th aspect of the present disclosure, for example, in an imaging device according to any one of the 25th to 27th aspects, The second peripheral transistor may include a second source, a second drain, and a second pocket diffusion layer adjacent to the second source or the second drain, The second pocket diffusion layer may include the second specific layer.

[0067] The configuration of the 28th embodiment is an example of the configuration of an imaging device.

[0068] In a 29th aspect of the present disclosure, for example, in an imaging device according to any one of the 25th to 28th aspects, The second peripheral transistor may include a second source and a second drain, At least one selected from the group consisting of the second source and the second drain may include the second specific layer.

[0069] The configuration of the 29th embodiment is an example of the configuration of an imaging device.

[0070] In a 30th aspect of the present disclosure, for example, in an imaging device according to any one of the 21st to 29th aspects, The second peripheral transistor may include a second source, a second drain, and a second extension diffusion layer; The second extension diffusion layer may be adjacent to the second source or the second drain and may be shallower than the second source and the second drain, The second extension diffusion layer may contain nitrogen.

[0071] The configuration of the 30th embodiment is an example of the configuration of the second peripheral transistor.

[0072] In a thirty-first aspect of the present disclosure, for example, in the imaging device according to the thirtieth aspect, The second peripheral transistor may be an N-channel transistor.

[0073] According to the thirty-first aspect, the reliability of the imaging device can be improved.

[0074] In a thirty-second aspect of the present disclosure, for example, in the imaging device according to any one of the twenty-first to thirty-first aspects, The at least one first peripheral transistor may include a first gate insulating film; The second peripheral transistor may include a third gate insulating film, The first gate insulating film may be thinner than the third gate insulating film.

[0075] The configuration of the 32nd embodiment is an example of the configuration of an imaging device.

[0076] In a thirty-third aspect of the present disclosure, for example, in the imaging device according to any one of the twenty-first to thirty-second aspects, The pixel transistor may include a second gate insulating film, The second peripheral transistor may include a third gate insulating film, The second gate insulating film may be thicker than the third gate insulating film.

[0077] The configuration of the 33rd embodiment is an example of the configuration of an imaging device.

[0078] In a thirty-fourth aspect of the present disclosure, for example, in the imaging device according to any one of the first to thirty-third aspects, The at least one first peripheral transistor may be a load transistor; The pixel region may be connected to the load transistor via a vertical signal line.

[0079] The configuration of the 34th embodiment is an example of the configuration of an imaging device.

[0080] An imaging device according to a 35th aspect of the present disclosure, a pixel region having a pixel transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate length of the first peripheral transistor is shorter than a gate length of the pixel transistor; the pixel transistor is an amplification transistor, When at least one type of impurity containing at least one selected from the group consisting of carbon, nitrogen, and fluorine is defined as a specific type, The first peripheral transistor is located within a first substrate portion and has a first specific layer containing a conductivity type impurity and the specific species.

[0081] An imaging device according to a 36th aspect of the present disclosure, a pixel region having a pixel transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate length of the first peripheral transistor is shorter than a gate length of the pixel transistor; the pixel transistor is an amplification transistor, When at least one kind of impurity including at least one selected from the group consisting of germanium, silicon, and argon is defined as a specific kind, The first peripheral transistor is located within a first substrate portion and has a first specific layer containing a conductivity type impurity and the specific species.

[0082] An imaging device according to a 37th aspect of the present disclosure, a pixel region having a pixel transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate insulating film of the first peripheral transistor is thinner than a gate insulating film of the pixel transistor; When at least one type of impurity containing at least one selected from the group consisting of carbon, nitrogen, and fluorine is defined as a specific type, The first peripheral transistor is located within a first substrate portion and has a first specific layer containing a conductivity type impurity and the specific species.

[0083] An imaging device according to a 38th aspect of the present disclosure, a pixel region having a pixel transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate insulating film of the first peripheral transistor is thinner than a gate insulating film of the pixel transistor; When at least one kind of impurity including at least one selected from the group consisting of germanium, silicon, and argon is defined as a specific kind, The first peripheral transistor is located within a first substrate portion and has a first specific layer containing a conductivity type impurity and the specific species.

[0084] An imaging device according to a thirty-ninth aspect of the present disclosure, a pixel region having an amplifying transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate length of the first peripheral transistor is shorter than a gate length of the amplifying transistor; The first peripheral transistor has a first extension diffusion layer adjacent to its first source or first drain, shallower than the first source and the first drain, and containing a first impurity and carbon.

[0085] An imaging device according to a 40th aspect of the present disclosure, a pixel region having an amplifying transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate length of the first peripheral transistor is shorter than a gate length of the amplifying transistor; The first peripheral transistor includes a first impurity and carbon in a first source or a first drain thereof.

[0086] In the 39th embodiment, the first extension diffusion layer may contain at least one selected from the group consisting of nitrogen, fluorine, germanium, silicon, and argon instead of or together with carbon. In the 40th embodiment, the first source or the first drain may contain at least one selected from the group consisting of nitrogen, fluorine, germanium, silicon, and argon instead of or together with carbon. In the 39th and 40th embodiments, the first impurity is an impurity having a conductivity type. The description of the conductivity type impurity described later may be applied to the first impurity. In the 39th and 40th embodiments, the "first impurity" can be read as a "conductivity type impurity". In the 39th and 40th embodiments, the "carbon" can be read as "at least one type of impurity that contributes to suppression of the transient enhanced diffusion of the first impurity".

[0087] An imaging device according to a 41st aspect of the present disclosure, a pixel region having a pixel transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate length of the first peripheral transistor is shorter than a gate length of the pixel transistor; A high-k metal gate is configured in the first peripheral transistor.

[0088] An imaging device according to a 42nd aspect of the present disclosure, a pixel region having a pixel transistor; a first peripheral region having a first peripheral transistor and located outside the pixel region; Equipped with a gate insulating film of the first peripheral transistor is thinner than a gate insulating film of the pixel transistor; A high-k metal gate is configured in the first peripheral transistor.

[0089] As long as there is no contradiction, the techniques of the first to forty-second aspects can be combined as appropriate.

[0090] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection forms of components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components.

[0091] In the following description, components having substantially the same functions are denoted by common reference symbols, and descriptions thereof may be omitted. In addition, in order to avoid overly complicated drawings, illustrations of some elements may be omitted. The dimensions and appearances of various elements of the imaging device shown in the drawings may differ from the dimensions and appearances of the actual imaging device. In other words, the attached drawings are merely schematic diagrams for understanding the present disclosure, and do not necessarily strictly reflect the scale of the actual imaging device.

[0092] In this specification, "planar view" refers to a view from a direction perpendicular to the semiconductor substrate, the first substrate portion, the second substrate portion, or the pixel substrate portion. The first substrate portion, the second substrate portion, and the pixel substrate portion will be described later. In this specification, terms such as "above," "below," "top surface," and "bottom surface" are used only to specify the relative arrangement of components, and are not intended to limit the position of the imaging device when in use.

[0093] In this specification, the extension diffusion layer is a concept including a so-called LDD (Lightly Doped Drain) diffusion layer.

[0094] (Embodiment of Imaging Apparatus) Fig. 1 is a schematic diagram showing an exemplary configuration of an imaging device according to an embodiment of the present disclosure. The imaging device 100A shown in Fig. 1 has a plurality of pixels 110 arranged in a plurality of rows and columns. In the configuration shown in Fig. 1, the pixels 110 are arranged in m rows and n columns to form a pixel region R1 having a substantially rectangular shape. Here, m and n independently represent integers of 1 or more.

[0095] As described later, in the embodiment of the present disclosure, each of these pixels 110 has a photoelectric conversion structure supported by the semiconductor substrate 130 and a readout circuit formed on the semiconductor substrate 130 and electrically connected to the photoelectric conversion structure. That is, the embodiment of the present disclosure will be described below by taking a so-called "stacked type" imaging device as an example. As will be described later in detail with reference to the drawings, each of the multiple pixels 110 includes an impurity region provided in the semiconductor substrate 130, which functions as a part of a charge accumulation region that temporarily holds a signal charge generated by the photoelectric conversion structure. However, instead of providing the photoelectric conversion structure as described above, a photodiode may be provided in the semiconductor substrate as a photoelectric conversion unit.

[0096] The imaging device 100A further includes a peripheral circuit 120A that drives the multiple pixels 110. In the example shown in FIG. 1, the peripheral circuit 120A includes a vertical scanning circuit 122, a horizontal signal readout circuit 124, a voltage supply circuit 126, and a control circuit 128. In the embodiment of the present disclosure, some or all of these circuits are formed on a semiconductor substrate 130, similarly to the readout circuits of the pixels. As shown typically in FIG. 1, the peripheral circuit 120A is located in a first peripheral region R2 of the semiconductor substrate 130, which is located outside a pixel region R1 including the multiple pixels 110.

[0097] The imaging device 100A further includes a blocking region 200A provided between the pixel region R1 and the first peripheral region R2. As shown in Fig. 1, the blocking region 200A includes an impurity region 131 formed in the semiconductor substrate 130 and a plurality of contact plugs 211 provided on the impurity region 131. The impurity region 131 is typically a p-type diffusion region.

[0098] The multiple contact plugs 211 are provided on the impurity regions 131, and are thereby electrically connected to the impurity regions 131 of the semiconductor substrate 130. As will be described later, the multiple contact plugs 211 are configured to be able to supply a predetermined voltage to the impurity regions 131 by being connected to a power supply not shown in FIG. 1. That is, during operation of the imaging device 100A, the impurity regions 131 are in a state in which a predetermined voltage is applied via the contact plugs 211.

[0099] The blocking region 200A also has an element isolation 220. The element isolation 220 is a structure formed in the semiconductor substrate 130 by, for example, an STI (shallow trench isolation) process. The element isolation 220 has at least a portion of the semiconductor substrate 130 located between the pixels located in the outermost periphery of the pixel region R1 among the multiple pixels 110 and a digital circuit such as a vertical scanning circuit 122 that operates based on a digital clock. Here, the element isolation 220 is located between the pixels 110 located in the outermost periphery of the pixel region R1 and the vertical scanning circuit 122, and between the pixels 110 located in the outermost periphery of the pixel region R1 and the horizontal signal readout circuit 124. As described later, the element isolation 220 can be provided in the semiconductor substrate 130 so as to surround the pixel region R1 in a top view. The element isolation 220 corresponds to a shallow trench isolation structure in this disclosure.

[0100] In a configuration in which peripheral circuits including a circuit that operates based on a digital clock are formed on a semiconductor substrate provided with an impurity region that temporarily holds a signal charge obtained by photoelectric conversion, the circuit that operates based on the digital clock can be a noise source that generates noise at each rising and falling edge of an input pulse. More specifically, the potential of a signal line that supplies a digital clock to a digital circuit, such as a CMOS logic circuit, fluctuates with the digital clock. The fluctuation in the potential of the signal line caused by the digital clock fluctuates the substrate potential, which can result in excess charge being generated in a well inside the semiconductor substrate. If excess charge caused by the fluctuation in the substrate potential flows into the impurity region in a pixel that holds the signal charge, the signal-to-noise ratio decreases, causing degradation of the obtained image.

[0101] In contrast, in the imaging device 100A shown in FIG. 1, a blocking region 200A including an impurity region 131 configured to be connectable to a power source such as ground by providing a plurality of contact plugs 211 is disposed between a pixel region R1 including a plurality of pixels 110 and a digital circuit. During operation of the imaging device 100A, the potential of the impurity region 131 of the blocking region 200A can be fixed by connecting a predetermined voltage source to the plurality of contact plugs 211. For example, the potential of the impurity region 131 of the blocking region 200A can be grounded via the plurality of contact plugs 211. At this time, the blocking region 200A functions as a low impedance path for discharging excess charge generated inside the semiconductor substrate 130. That is, electrostatic coupling between the impurity region in the pixel that holds the signal charge and the peripheral circuit 120A can be suppressed, and dark currents caused by a signal line that supplies a digital clock as a noise source can be advantageously suppressed. However, the blocking region 200A is not essential.

[0102] Here, each circuit constituting the peripheral circuit 120A will be described in detail. The vertical scanning circuit 122 is connected to a plurality of address signal lines 34. These address signal lines 34 are provided corresponding to each row of the plurality of pixels 110. Each address signal line 34 is connected to one or more pixels belonging to the corresponding row. The vertical scanning circuit 122 controls the timing of reading out signals from the pixels 110 to vertical signal lines 35 (described later) by applying a row selection signal to the address signal line 34. The vertical scanning circuit 122 is also called a row scanning circuit. Note that the signal lines connected to the vertical scanning circuit 122 are not limited to the address signal lines 34. A plurality of types of signal lines may be connected to the vertical scanning circuit 122 for each row of the plurality of pixels 110.

[0103] As shown in FIG. 1, the imaging device 100A also has a plurality of vertical signal lines 35. The vertical signal lines 35 are provided for each column of a plurality of pixels 110. Each vertical signal line 35 is connected to one or more pixels belonging to the corresponding column. These vertical signal lines 35 are connected to a horizontal signal readout circuit 124. The horizontal signal readout circuit 124 sequentially outputs signals read out from the pixels 110 to output lines not shown in FIG. 1. The horizontal signal readout circuit 124 is also called a column scanning circuit.

[0104] The control circuit 128 receives command data, a clock, and the like provided from, for example, the outside of the imaging device 100A, and controls the entire imaging device 100A. The control circuit 128 typically has a timing generator and supplies drive signals to the vertical scanning circuit 122, the horizontal signal read circuit 124, a voltage supply circuit 126 (described later), and the like. In FIG. 1, the arrows extending from the control circuit 128 represent the flow of output signals from the control circuit 128. The control circuit 128 can be realized by, for example, a microcontroller including one or more processors. The functions of the control circuit 128 may be realized by a combination of a general-purpose processing circuit and software, or may be realized by hardware specialized for such processing.

[0105] In the embodiment of the present disclosure, the peripheral circuit 120A includes a voltage supply circuit 126 electrically connected to each pixel 110 in the pixel region R1. The voltage supply circuit 126 supplies a predetermined voltage to the pixels 110 via a voltage line 38. The voltage supply circuit 126 is not limited to a specific power supply circuit, and may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or may be a circuit that generates a predetermined voltage. The voltage supply circuit 126 may be a part of the vertical scanning circuit 122 described above. As shown in FIG. 1, these circuits constituting the peripheral circuit 120A are arranged in a first peripheral region R2 outside the pixel region R1.

[0106] The number and arrangement of the pixels 110 are not limited to the illustrated example. For example, the number of pixels 110 included in the imaging device 100 may be one. In this example, the center of each pixel 110 is located on a lattice point of a square lattice, but for example, the multiple pixels 110 may be arranged so that the center of each pixel 110 is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. For example, the pixels 110 may be arranged one-dimensionally, in which case the imaging device 100A may be used as a line sensor.

[0107] Fig. 2 is a schematic diagram showing an exemplary circuit configuration of the imaging device 100A shown in Fig. 1. In Fig. 2, in order to avoid overcomplicating the drawing, four pixels 110 arranged in two rows and two columns are shown out of the multiple pixels 110. Each of these pixels 110 includes a photoelectric conversion structure 10 supported by a semiconductor substrate 130 and a readout circuit 20 electrically connected to the photoelectric conversion structure 10. As will be described in detail later with reference to the drawings, the photoelectric conversion structure 10 includes a photoelectric conversion layer disposed above the semiconductor substrate 130.

[0108] The photoelectric conversion structure 10 of each pixel 110 is connected to a voltage line 38 that is connected to a voltage supply circuit 126, and is configured to be able to apply a predetermined voltage via the voltage line 38 during operation of the imaging device 100A. For example, if the positive charge of the positive and negative charges generated by photoelectric conversion is used as a signal charge, a positive voltage of, for example, about 10 V may be applied to the voltage line 38 during operation of the imaging device 100A. The following describes an example in which holes are used as signal charges.

[0109] 2, the read circuit 20 includes an amplifier transistor 22, an address transistor 24, and a reset transistor 26. The amplifier transistor 22, the address transistor 24, and the reset transistor 26 are typically field effect transistors formed on a semiconductor substrate 130. In the following, unless otherwise specified, an example will be described in which an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the transistor.

[0110] As shown in FIG. 2, the gate of the amplifying transistor 22 is electrically connected to the photoelectric conversion structure 10. In operation, a predetermined voltage is applied from a voltage supply circuit 126 to the photoelectric conversion structure 10 of each pixel 110 via a voltage line 38, so that, for example, holes can be accumulated as signal charges in the charge storage node FD. Here, the charge storage node FD is a node that connects the gate of the amplifying transistor 22 to the photoelectric conversion structure 10. The charge storage node FD has a function of temporarily holding charges generated by the photoelectric conversion structure 10. The charge storage node FD includes an impurity region formed in the semiconductor substrate 130 as a part thereof. The symbol Z in FIG. 3, which will be described later, corresponds to the impurity region included in the charge storage node FD.

[0111] 2, the drain of the amplification transistor 22 of each pixel 110 is connected to a power supply wiring 32. The power supply wiring 32 supplies a power supply voltage VDD of, for example, about 3.3 V to the amplification transistor 22 during operation of the imaging device 100A. On the other hand, the source of the amplification transistor 22 is connected to a vertical signal line 35 via an address transistor 24. By receiving the power supply voltage VDD at its drain, the amplification transistor 22 outputs a signal voltage according to the amount of signal charge stored in the charge storage node FD.

[0112] An address signal line 34 is connected to the gate of the address transistor 24 connected between the amplifying transistor 22 and the vertical signal line 35. The vertical scanning circuit 122 controls the on and off of the address transistor 24 by applying a row selection signal to the address signal line 34. That is, the vertical scanning circuit 122 can read out the output of the amplifying transistor 22 of the selected pixel 110 to the corresponding vertical signal line 35 by controlling the row selection signal. The arrangement of the address transistor 24 is not limited to the example shown in FIG. 2, and may be between the drain of the amplifying transistor 22 and the power supply wiring 32.

[0113] A load circuit 45 and a column signal processing circuit 47 are connected to each of the vertical signal lines 35. The load circuit 45 forms a source follower circuit together with the amplifying transistor 22. The column signal processing circuit 47 performs noise suppression signal processing represented by correlated double sampling, analog-to-digital conversion, and the like. The column signal processing circuit 47 is also called a row signal storage circuit. The horizontal signal readout circuit 124 sequentially reads out signals from the multiple column signal processing circuits 47 to a horizontal common signal line 49. The column signal processing circuit 47 may be a part of the horizontal signal readout circuit 124. The load circuit 45 and the column signal processing circuit 47 may be a part of the above-mentioned peripheral circuit 120A.

[0114] In this example, the readout circuit 20 includes a reset transistor 26 in addition to the amplification transistor 22 and the address transistor 24. One of the drain and source of the reset transistor 26 is a part of the charge storage node FD, and the other of the drain and source is connected to a reset voltage line 39. The one of the drain and source of the reset transistor 26 corresponds to the charge storage region Z in FIG. 3, specifically, to the impurity region 60n. The reset voltage line 39 is connected to a reset voltage supply circuit not shown in FIG. 2, so that a predetermined reset voltage Vref can be supplied to the reset transistor 26 of each pixel 110 during operation of the imaging device 100A. For example, 0V or a voltage close to 0V is selected as the reset voltage Vref. As with the voltage supply circuit 126 described above, the reset voltage supply circuit only needs to be able to apply a predetermined reset voltage Vref to the reset voltage line 39, and the specific configuration thereof is not limited to a specific power supply circuit. The reset voltage supply circuit may be a part of the vertical scanning circuit 122. The voltage supply circuit 126 and the reset voltage supply circuit may be separate circuits, or may be arranged in the imaging device 100A as a single voltage supply circuit. The reset voltage supply circuit may also be part of the peripheral circuit 120A described above.

[0115] A reset signal line 36 is connected to the gate of the reset transistor 26. The reset signal line 36 is provided for each row of the pixels 110, similar to the address signal line 34, and is connected to the vertical scanning circuit 122 here. As described above, the vertical scanning circuit 122 can select the pixels 110 from which signals are to be read out, row by row, by applying a row selection signal to the address signal line 34. Similarly, the vertical scanning circuit 122 can turn on the reset transistor 26 of the selected row by applying a reset signal to the gate of the reset transistor 26 via the reset signal line 36. By turning on the reset transistor 26, the potential of the charge storage node FD is reset.

[0116] (Pixels and blocking areas) 3 is a schematic diagram showing a cross section including the pixel region R1, the first peripheral region R2, and the blocking region 200A. Here, cross sections of two pixels located near the blocking region 200A are shown as representative of the multiple pixels 110.

[0117] First, attention is focused on the pixel region R1. A photoelectric conversion layer 12 is provided in the pixel region R1. The photoelectric conversion layer 12 is supported by a semiconductor substrate 130. A light-transmitting counter electrode 13 is disposed on the photoelectric conversion layer 12. As shown in FIG. 3, each of the photoelectric conversion layer 12 and the counter electrode 13 is typically provided continuously above the semiconductor substrate 130 across a plurality of pixels 110.

[0118] The pixel 110 is a unit structure constituting the pixel region R1, and includes a photoelectric conversion structure 10 having a part of the photoelectric conversion layer 12, a part of the counter electrode 13, and a pixel electrode 11. The pixel electrode 11 of the photoelectric conversion structure 10 is located between the photoelectric conversion layer 12 and the semiconductor substrate 130, and is formed of a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to provide conductivity. As shown in FIG. 3, the pixel electrode 11 of each pixel 110 is spatially separated from the pixel electrodes 11 of other adjacent pixels, and is thus electrically separated.

[0119] The photoelectric conversion layer 12 of the photoelectric conversion structure 10 is formed of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 12 receives light incident via the counter electrode 13 and generates positive and negative charges by photoelectric conversion. In other words, the photoelectric conversion structure 10 has a function of converting light into charges. The photoelectric conversion layer 12 may include a layer composed of an organic material and a layer composed of an inorganic material.

[0120] The counter electrode 13 of the photoelectric conversion structure 10 is an electrode formed of a transparent conductive material such as ITO. In this specification, the term "translucent" means that the photoelectric conversion layer 12 transmits at least a part of the light of a wavelength that can be absorbed, and does not necessarily transmit light over the entire wavelength range of visible light. Although not shown in FIG. 3, the counter electrode 13 has a connection with the above-mentioned voltage line 38. During operation of the imaging device 100A, the potential of the voltage line 38 is controlled to make the potential of the counter electrode 13 higher than the potential of the pixel electrode 11, for example, so that the positive charge among the positive and negative charges generated by the photoelectric conversion can be selectively collected by the pixel electrode 11. By forming the counter electrode 13 in the form of a single continuous layer across multiple pixels 110, it is possible to collectively apply a predetermined potential to the counter electrodes 13 of multiple pixels 110 via the voltage line 38.

[0121] Each of the plurality of pixels 110 further includes a portion of a semiconductor substrate 130. As shown in FIG. 3, the semiconductor substrate 130 has a plurality of impurity regions 60n as first impurity regions near its surface. The impurity region 60n functions as one of the drain and source of the reset transistor 26 included in the readout circuit 20 described above. The semiconductor substrate 130 also has an impurity region 61n which is the other of the drain and source of the reset transistor 26. As shown in FIG. 3, the impurity region 61n is connected to the above-mentioned reset voltage line 39 via a polysilicon plug or the like. Here, the impurity region 60n and the impurity region 61n have an n-type conductivity. These plurality of impurity regions 60n, 61n are typically n-type diffusion regions.

[0122] As can be understood from this, a plurality of readout circuits 20 corresponding to a plurality of pixels 110 are formed on the semiconductor substrate 130. The readout circuit 20 of each pixel is electrically isolated from the readout circuits 20 of other pixels by an element isolation 221 provided on the semiconductor substrate 130.

[0123] As shown in FIG. 3, an interlayer insulating layer 90 covering the semiconductor substrate 130 is located between the photoelectric conversion structure 10 and the semiconductor substrate 130. The interlayer insulating layer 90 generally includes multiple insulating layers and multiple wiring layers. The multiple wiring layers arranged in the interlayer insulating layer 90 may include a wiring layer having an address signal line 34 and a reset signal line 36, etc., in a part thereof, a wiring layer having a vertical signal line 35, a power supply line 32, a reset voltage line 39, etc., in a part thereof, etc. The number of insulating layers and the number of wiring layers in the interlayer insulating layer 90 are not limited to this example and can be set arbitrarily.

[0124] A conductive structure 89 is provided inside the interlayer insulating layer 90, electrically connecting the pixel electrode 11 of the photoelectric conversion structure 10 to the readout circuit 20 formed on the semiconductor substrate 130. As shown in FIG. 3, the conductive structure 89 includes wiring and vias arranged in the interlayer insulating layer 90. These wiring and vias are typically formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The conductive structure 89 also includes a contact plug cx connected to the above-mentioned impurity region 60n. The contact plug cx connected to the impurity region 60n is typically a polysilicon plug, and is doped with an impurity such as phosphorus to increase conductivity. Although not shown in FIG. 3, the conductive structure 89 also has an electrical connection with the gate electrode of the amplification transistor 22. A plug cy is connected to the contact plug cx. Examples of metals that the plug cy may contain include tungsten, copper, and the like.

[0125] Focus on the semiconductor substrate 130. The semiconductor substrate 130 includes a support substrate 140 and one or more semiconductor layers formed on the support substrate 140. In the example shown in FIG. 3, the semiconductor substrate 130 has an n-type impurity layer 62 provided on the support substrate 140. In the following, a p-type silicon substrate is exemplified as the support substrate 140. The support substrate 140 may have a lower electrical resistivity than the impurity layer 62. The semiconductor substrate 130 may be an SOI (silicon-on-insulator) substrate, or a substrate having a semiconductor layer provided on its surface by epitaxial growth or the like.

[0126] In the configuration illustrated in Fig. 3, attention is first focused on the pixel region R1. The semiconductor substrate 130 has an n-type semiconductor layer 62an on the support substrate 140 and a p-type semiconductor layer 63p on the n-type semiconductor layer 62an. The n-type semiconductor layer 62an located between the support substrate 140 and the p-type semiconductor layer 63p is a part of the above-mentioned impurity layer 62. During operation of the imaging device 100A, the potential of the impurity layer 62 is controlled via a well contact not shown in Fig. 3. By providing the impurity layer 62, which includes the n-type semiconductor layer 62an located in the pixel region R1 as a part thereof, inside the semiconductor substrate 130, it is possible to suppress the inflow of minority carriers from the support substrate 140 or peripheral circuits into the charge accumulation region that accumulates the signal charge.

[0127] In the configuration illustrated in FIG. 3, the semiconductor substrate 130 further includes a p-type semiconductor layer 66p located on the p-type semiconductor layer 63p and a p-type impurity region 65p formed in the p-type semiconductor layer 66p. In this example, the above-mentioned impurity region 60n having a connection to the conductive structure 89 is provided in the p-type impurity region 65p. A junction capacitance formed by a pn junction between the impurity region 60n and the p-type impurity region 65p as a p-well functions as a capacitance for storing at least a part of the signal charge collected by the pixel electrode 11. That is, the impurity region 60n constitutes a charge storage region for temporarily holding the signal charge. On the other hand, the impurity region 61n is provided in the p-type semiconductor layer 66p. Here, the impurity concentration in the p-type impurity region 65p is lower than the impurity concentration in the p-type semiconductor layer 66p.

[0128] The semiconductor substrate 130 also has a plurality of p-type regions 64 provided in the semiconductor substrate 130 so as to penetrate the impurity layer 62. The p-type regions 64 have a relatively high impurity concentration. By providing the p-type regions 64 inside the semiconductor substrate 130, it becomes possible to electrically connect two regions of a common conductivity type that are separated by the impurity layer 62.

[0129] Here, the multiple p-type regions 64 include multiple p-type regions 64a located in the pixel region R1 when viewed from the normal direction of the semiconductor substrate 130, and one or more p-type regions 64b located below the multiple contact plugs 211 in the blocking region 200A. The p-type region 64a is formed between the p-type semiconductor layer 63p and the support substrate 140 so as to penetrate the n-type semiconductor layer 62an, and has the function of electrically connecting the p-type semiconductor layer 63p and the support substrate 140. On the other hand, the p-type region 64b is electrically connected to the impurity region 131 by having one end reach the impurity region 131 in the blocking region 200A, and electrically connects the impurity region 131 and the support substrate 140.

[0130] Therefore, here, an electrical path is formed in the semiconductor substrate 130 from the impurity region 131 of the blocking region 200A to the p-type semiconductor layer 63p via the p-type region 64b, the support substrate 140, and the p-type region 64a. As described above, the impurity region 131 of the blocking region 200A is connected to a plurality of contact plugs 211, and these contact plugs 211 are configured to be connectable to a power source (not shown) such as ground. For example, the potential of the impurity region 131 of the blocking region 200A can be grounded via the plurality of contact plugs 211. By connecting an appropriate power source to the plurality of contact plugs 211 of the blocking region 200A, the potential of the p-type impurity region 65p and the p-type semiconductor layer 66p can be controlled via the p-type semiconductor layer 63p using the electrical path including the impurity region 131, the p-type region 64b, the support substrate 140, and the p-type region 64a.

[0131] 3, an impurity region 131a having a relatively high impurity concentration is formed in a portion of the impurity region 131 located near the surface of the semiconductor substrate 130. The contact plug 211 is typically made of a metal. By providing the impurity region 131a having a relatively high impurity concentration in the impurity region 131 and connecting a plurality of contact plugs 211 to the impurity region 131a, an effect of reducing contact resistance between the plurality of contact plugs 211 and the impurity region 131 can be obtained.

[0132] Furthermore, in this example, a silicide layer 131s is formed between the multiple contact plugs 211 and the impurity region 131. By providing the silicide layer 131s in the impurity region 131a near the surface of the semiconductor substrate 130 and connecting the multiple contact plugs 211, the contact resistance can be further reduced.

[0133] Next, attention is paid to the first peripheral region R2 of the semiconductor substrate 130. As described above, in the first peripheral region R2, a circuit for driving the plurality of pixels 110 and a circuit for processing signals read out from the plurality of pixels 110 are formed. The first peripheral region R2 includes, for example, a plurality of transistors 25 and a first peripheral transistor 27 constituting a logic circuit such as a multiplexer. As shown in FIG. 3, an n-type semiconductor layer 62bn, which is another part of the impurity layer 62, is formed on the support substrate 140, and an n-type impurity region 81n and a p-type impurity region 82p are formed as wells on the n-type semiconductor layer 62bn. The drain and source of the transistor 25 are located in the p-type impurity region 82p, and the drain and source of the first peripheral transistor 27 are located in the n-type impurity region 81n. The n-type semiconductor layer 62bn is separated from the n-type semiconductor layer 62an over the entire periphery of the pixel region R1 by a part of the support substrate 140. A predetermined voltage is supplied to the n-type semiconductor layer 62bn by connecting it to a power supply (not shown). Hereinafter, the n-type impurity region 81n may be referred to as an N-type well.

[0134] The depth of the n-type semiconductor layer 62an in the pixel region R1 and the depth of the n-type semiconductor layer 62bn in the first peripheral region R2 may be the same as or different from each other.

[0135] In the configuration illustrated in FIG. 3, the drain, source, and gate electrodes of peripheral transistors such as transistors 25 and 27 are connected to contact plugs cp.

[0136] 3, the blocking region 200A further includes an n-type impurity region 83n located near the boundary with the first peripheral region R2. The n-type impurity region 83n is located on the n-type semiconductor layer 62bn of the impurity layer 62, and is electrically connected to the n-type semiconductor layer 62bn. A plug may be provided in the n-type impurity region 83n. By connecting an appropriate power supply to the plug connected to the n-type impurity region 83n, it becomes possible to control the potentials of the n-type impurity region 83n and the n-type semiconductor layer 62bn.

[0137] The impurity layer and the impurity region located above the support substrate 140 are typically formed by ion implantation of impurities into a semiconductor layer obtained by epitaxial growth on the support substrate 140. Note that the p-type region 64a located in the pixel region R1 of the p-type region 64 may be formed at a position that does not overlap with the element isolation in the pixel in a plan view.

[0138] In this embodiment, the blocking region 200A is formed between the pixel region R1 and the first peripheral region R2. As described above, the blocking region 200A includes the element isolation 220 located between the pixel region R1 and the first peripheral region R2, and the impurity region 131 in which the multiple contact plugs 211 are arranged. Since the blocking region 200A includes at least the impurity region 131, the dopant in the impurity region 131 can be used to exert a so-called gettering effect. For example, it is known that when metal impurities diffuse into a region in which pixels are arranged in a semiconductor substrate supporting a photoelectric conversion layer, a deterioration in image quality occurs. By making the dopant in the impurity region 131 function as a gettering center, the diffusion of metal impurities into the charge accumulation region can be suppressed, and the deterioration in image quality caused by the diffusion of metal impurities can be avoided.

[0139] An example of a p-type impurity or dopant for a silicon substrate is boron, and an example of an n-type dopant is phosphorus, arsenic, or antimony. Of these, it is known that the p-type dopant can have a gettering effect on most metals, and is therefore suitable as a dopant for the impurity region 131. In a typical embodiment of the present disclosure, the p-type is selected as the conductivity type of the impurity region 131 of the blocking region 200A. For example, by disposing the blocking region 200A including the impurity region 131 doped with a p-type impurity between the pixel region R1 and the first peripheral region R2, the diffusion of metal impurities into the pixel region R1 can be effectively suppressed. That is, the diffusion of metal impurities into the charge accumulation region of the pixel 110 can be suppressed, and the deterioration of image quality caused by the diffusion of metal impurities can be suppressed.

[0140] FIG. 4 shows another example of the shape of the blocking region. Compared to the imaging device 100A shown in FIG. 1, the imaging device 100B shown in FIG. 4 has a blocking region 200B surrounding the pixel region R1 in a rectangular shape instead of the blocking region 200A. Compared to the above-mentioned blocking region 200A, the impurity region 131 of the blocking region 200B surrounds the pixel region R1 in a ring shape without any breaks in a plan view. As shown in FIG. 4, in this example, a plurality of contact plugs 211 are also connected to the impurity region 131. In this example, the element isolation 220 of the blocking region 200B also surrounds the pixel region R1 in a ring shape without any breaks inside the impurity region 131. In such a configuration, it can be said that the element isolation 220 defines the boundary between the pixel region R1 and the first peripheral region R2.

[0141] Here, the peripheral circuit 120B provided in the first peripheral region R2 includes a second vertical scanning circuit 129 and a second horizontal signal readout circuit 127 in addition to the vertical scanning circuit 122, the horizontal signal readout circuit 124, the voltage supply circuit 126, and the control circuit 128. The vertical scanning circuit 129 is disposed on the opposite side to the vertical scanning circuit 122 with the pixel region R1 in between. As shown in the figure, the vertical scanning circuit 129 is also connected to the address signal lines 34 provided corresponding to each row of the multiple pixels 110. Similarly, the horizontal signal readout circuit 127 is disposed on the opposite side to the horizontal signal readout circuit 124 with the pixel region R1 in between, and is connected to the vertical signal lines 35 provided corresponding to each column of the multiple pixels 110.

[0142] For example, the vertical scanning circuit 122 is responsible for row selection of pixels in the left half of the pixel region R1, and the vertical scanning circuit 129 is responsible for row selection of pixels in the right half of the pixel region R1. The horizontal signal readout circuit 124 is responsible for processing signals read out from pixels in the lower half of the pixel region R1, and the horizontal signal readout circuit 127 is responsible for processing signals read out from pixels in the upper half of the pixel region R1. In this way, by partitioning the pixel region R1 and reading out signals using multiple vertical scanning circuits and horizontal signal readout circuits, it is possible to speed up operations such as reducing the frame rate.

[0143] 4, the vertical scanning circuits 122 and 129 and the horizontal signal readout circuits 124 and 127 are arranged along the four sides of the rectangular pixel region R1. In other words, in this example, blocking regions 200B are interposed between the vertical scanning circuit 122 and the set of pixels 110, between the vertical scanning circuit 129 and the set of pixels 110, between the horizontal signal readout circuit 124 and the set of pixels 110, and between the horizontal signal readout circuit 127 and the set of pixels 110.

[0144] By forming the blocking region 200B in the semiconductor substrate 130 in a shape that surrounds the pixel region R1 including an array of a plurality of pixels 110 in a plan view, the movement of charges between the charge accumulation region of the pixel and the circuit formed in the first peripheral region R2 can be more effectively suppressed. In addition, in the case where the circuit group that constitutes the peripheral circuit is arranged to surround the pixel region R1, for example, rectangular in shape, as in the example shown in FIG. 4, it is not essential in the embodiment of the present disclosure that the blocking region surrounds the pixel region R1 in a ring shape without interruption in a plan view. For example, the blocking region may include a plurality of parts that each include the element isolation 220 and the impurity region 131 and are arranged to surround the pixel region R1 as a whole. Even in such a configuration, the same effect as when the blocking region is provided to surround the pixel region R1 in a ring shape without interruption in a plan view can be expected. In addition, the blocking region 200B may not be required.

[0145] (Transistor in the first peripheral region R2) As described above, the first peripheral region R2 includes the first peripheral transistor 27. Hereinafter, configuration examples of the first peripheral transistor 27 according to the embodiment will be described with reference to FIGS.

[0146] 5 shows a cross-sectional configuration of a first peripheral transistor 27 according to the first configuration example. This first peripheral transistor 27 is specifically an MIS transistor, and more specifically a MOSFET.

[0147] As shown in FIG. 5, for example, a silicon oxide (SiO 2A gate electrode 302 made of polysilicon or a metal gate is formed on the semiconductor substrate 130, with a gate insulating film 301 made of polysilicon or a metal gate interposed therebetween. An N-type channel diffusion layer 303 in which, for example, arsenic (As) is diffused, and an impurity region 81n which is an N-type well in which, for example, arsenic (As) and phosphorus (P) are diffused and has a deeper junction depth than the N-type channel diffusion layer 303 are formed in the upper part of the semiconductor substrate 130. In the semiconductor substrate 130, a support substrate 140, an n-type semiconductor layer 62bn, and an impurity region 81n which is an N-type well are laminated in this order.

[0148] In a region in the gate length direction of the N-type channel diffusion layer 303, i.e., in the region where the source and drain are formed, first extension diffusion layers 306a, 306b are formed by diffusing a P-type impurity such as boron (B) into the first extension diffusion layers 306a, 306b, which are P-type extension high-concentration diffusion layers having relatively shallow junctions, and first pocket diffusion layers 307a, 307b are formed below the first extension diffusion layers 306a, 306b, which are N-type pocket diffusion layers by diffusing an N-type impurity such as arsenic (As).

[0149] The first extension diffusion layers 306a and 306b, which are P-type extension high concentration diffusion layers, contain carbon (C).

[0150] In this configuration example, carbon is used to suppress boron diffusion, so that the first extension diffusion layers 306a and 306b have a shallow and steep impurity profile and a high activation concentration. This allows the formation of an extension diffusion layer with a shallow junction depth and low resistance, realizing a fine device with high driving force.

[0151] Incidentally, in the manufacturing process of the imaging device, a heat treatment may be performed to heat the pixel region R1. This heat treatment may also heat the first peripheral region R2. However, due to the above-mentioned diffusion suppression effect caused by carbon, even if the first peripheral region R2 is heated by such a heat treatment, redistribution of impurities is suppressed in the first peripheral transistor 27 of the first peripheral region R2, and a shallow junction can be maintained.

[0152] In addition, by containing carbon in the first extension diffusion layers 306a, 306b, the occurrence of residual defects in the first extension diffusion layers 306a, 306b can be suppressed. An example of the residual defects is an EOR (end of range) defect. Here, the EOR defect refers to a defect layer formed in a region immediately below the amorphous-crystal (a / c) interface before heat treatment when the semiconductor substrate 130 made of silicon is subjected to heat treatment in an amorphous state.

[0153] Carbon is also implanted to suppress transient enhanced diffusion (TED) caused by boron. Carbon forms carbon-interstitial silicon complexes, clusters, etc. with excess point defects that cause TED, thereby suppressing excess point defects. Considering that excess point defects can grow and generate secondary defects such as dislocation loops, carbon can also be said to suppress crystal defects. In this way, by using a crystal layer in which the generation of residual defect layers such as secondary defects is suppressed in the extension formation region of the semiconductor substrate 130, the occurrence of junction leakage caused by the residual defect layer can also be suppressed.

[0154] Furthermore, in the region outside the first extension diffusion layers 306a, 306b in the semiconductor substrate 130, P-type source / drain diffusion layers 313a, 313b are formed, which are connected to the first extension diffusion layers 306a, 306b and have a junction depth deeper than the first extension diffusion layers 306a, 306b. In this configuration example, the P-type source / drain diffusion layers 313a, 313b contain carbon (C). However, one or both of the P-type source / drain diffusion layers 313a, 313b may not contain carbon (C). Note that the "source / drain diffusion layer" refers to a diffusion layer that functions as a source or drain.

[0155] Insulating offset spacers 309a, 309b are formed on both side surfaces of the gate electrode 302, and the offset spacers 309a, 309b contain carbon. Furthermore, first sidewalls 308Aa, 308Ab having an L-shaped cross section are formed, extending from the outer side surfaces of the offset spacers 309a, 309b to the upper portions of the inner ends of the P-type source-drain diffusion layers 313a, 313b on the semiconductor substrate 130. Furthermore, insulating second sidewalls 308Ba, 308Bb are formed on the outer sides of the first sidewalls 308Aa, 308Ab, respectively.

[0156] In the first configuration example, arsenic ions are used as impurities for the N-type channel diffusion layer 303. Alternatively, ions of an element having a larger mass than that of the arsenic ions and exhibiting an N-type may be used, or both arsenic ions and ions of an element having a larger mass than that of the arsenic ions and exhibiting an N-type may be used.

[0157] The impurity that contributes to the suppression of TED is not limited to carbon. At least one selected from the group consisting of nitrogen, fluorine, germanium, silicon and argon may be used instead of or together with carbon. Nitrogen, fluorine, germanium, silicon, argon, etc. may also contribute to the suppression of TED. Specifically, like carbon, impurities such as nitrogen and fluorine also form complexes, clusters, etc. of impurities-interstitial silicon or impurity-atomic vacancies with excess point defects that cause TED, thereby suppressing excess point defects. Specifically, excess point defects are suppressed by forming complexes such as carbon-interstitial silicon, nitrogen-interstitial silicon, fluorine-interstitial silicon, and fluorine-atomic vacancies. Germanium, silicon, argon, etc. contribute to the suppression of TED through the pre-amorphization action. In addition, at least one selected from the group consisting of elements of groups 14, 17, and 18 that do not have electrical conductivity may be used as an impurity that contributes to the suppression of TED.

[0158] In the first configuration example, the transistor is a P-channel MIS transistor, but instead of this, an N-channel MIS transistor may be used. In the case of an N-channel MIS transistor, for example, a 5B group element having a larger mass than an arsenic ion, such as phosphorus (P) ion, arsenic (As) ion, antimony (Sb) ion, or bismuth (Bi) ion, may be used as the N-type impurity ion constituting the extension diffusion layer. In the case of an N-channel MIS transistor, for example, a III group element having a larger mass than a boron ion, such as boron (B) ion or indium (In) ion, or a combination thereof, may be used as the P-type pocket diffusion layer. As a result, the TED of the P-type pocket diffusion layer is suppressed by carbon, so that the variation in threshold voltage caused by the pocket profile can be suppressed. As the N-type impurity ion constituting the extension diffusion layer, one of the above impurities may be used, or two or more of them may be used in combination. The same applies to the elements used in the P-type pocket diffusion layer.

[0159] (First modified example of the first configuration example) FIG. 6 shows a cross-sectional configuration of a transistor according to a first modification of the first configuration example. As shown in FIG. 6, in the transistor according to the first modification, the impurity profile of the first extension diffusion layers 306a and 306b, which are P-type extension high concentration diffusion layers, is asymmetric with respect to the gate electrode 302. As shown in FIG. 6, by making the source region shallower and steeper in extension profile than the drain region, the carrier concentration gradient between the source region and the channel region becomes large, and the driving force of the MIS transistor is improved. In addition, since the extension profile of the drain region is deeper than that of the source region, the generation of hot carriers is suppressed compared to a symmetrical, shallow, and steep profile structure. The transistor having the configuration of FIG. 6 can be manufactured with reference to, for example, Patent Document 2.

[0160] 6, the first extension diffusion layer 306a is shallower than the first extension diffusion layer 306b. However, a configuration in which the first extension diffusion layer 306b is shallower than the first extension diffusion layer 306a may also be adopted.

[0161] (Second modified example of the first configuration example) A cross-sectional configuration of a transistor according to a second modified example of the first configuration example is shown in Fig. 7. As shown in Fig. 7, the transistor according to the second modified example has a P-type extension high-concentration diffusion layer only on one side of the P-type source / drain diffusion layers 313a and 313b.

[0162] 7, the transistor according to the second modification has a first extension diffusion layer 306a which is a P-type extension high concentration diffusion layer adjacent to the P-type source / drain diffusion layer 313a, and does not have a first extension diffusion layer adjacent to the P-type source / drain diffusion layer 313b. However, a configuration may also be adopted in which the first extension diffusion layer is not adjacent to the P-type source / drain diffusion layer 313a, and the first extension diffusion layer 306b is adjacent to the P-type source / drain diffusion layer 313b.

[0163] 7, the transistor according to the second modification has an N-type pocket diffusion layer only on one side of the P-type source / drain diffusion layers 313a, 313b. Specifically, the transistor according to the second modification has a first pocket diffusion layer 307a adjacent to the P-type source / drain diffusion layer 313a, but does not have a first pocket diffusion layer adjacent to the P-type source / drain diffusion layer 313b. However, a configuration may also be adopted in which the transistor does not have a first pocket diffusion layer adjacent to the P-type source / drain diffusion layer 313a, but has a first pocket diffusion layer 307b adjacent to the P-type source / drain diffusion layer 313b.

[0164] (Third modified example of the first configuration example) In a third modification of the first configuration example, the P-type source / drain diffusion layers 313a, 313b contain fluorine (F) and carbon (C). Fluorine can cause partial amorphization of the semiconductor substrate 130. Fluorine can also suppress the transient enhanced diffusion (TED) of impurities. FIG. 8 shows an example of concentration distribution of impurities in the P-type source / drain diffusion layers 313a, 313b in the depth direction of the semiconductor substrate 130. The vertical axis shows the concentrations of fluorine (F), carbon (C), boron (B) and germanium (Ge) on a logarithmic scale. The concentration distribution in FIG. 8 relates to a case where fluorine is implanted for amorphization and suppression of impurity diffusion and diffused during annealing. In the example of FIG. 8, the concentration distribution of fluorine has segregation near the original a / c interface position.

[0165] According to the third modification, the diffusion of impurities is suppressed after the above-mentioned annealing. Furthermore, even if the first peripheral region R2 is heated during the heat treatment for the pixel region R1, the redistribution of impurities can be limited to a small range.

[0166] A method for manufacturing the transistor shown in Fig. 5 will be described below with reference to the drawings. Note that, in the following, a description of a method for manufacturing the n-type semiconductor layer 62bn will be omitted. The n-type semiconductor layer 62bn can be manufactured by a known method.

[0167] Parts (a) to (e) of FIG. 9, parts (a) to (d) of FIG. 10, and parts (a) to (c) of FIG. 11 show cross-sectional configurations of the MIS transistor in the order of steps in a manufacturing method for the MIS transistor according to the first configuration example.

[0168] First, as shown in part (a) of FIG. 9, N-type impurity ions, for example, phosphorus (P) ions, are implanted into a channel formation region of a semiconductor substrate 130 made of P-type silicon at an implantation energy of 260 keV and an implantation dose of 4×10 12 / cm 2 The first ion implantation, the implantation energy is 540 keV and the implantation dose is 1×10 13 / cm 2 The second ion implantation is performed to form an N-type well impurity implanted layer 304A. Then, arsenic (As) ions are implanted into the semiconductor substrate 130 with an implantation energy of about 90 keV and an implantation dose of 5×10 12 / cm 2 The ion implantation is performed to a degree of about 1000 nm to form the N-type channel impurity implantation layer 303A on the N-type well impurity implantation layer 304A. At this time, a silicon oxide film may be deposited on the surface of the semiconductor substrate 130 before the ion implantation. The order in which the N-type well impurity implantation layer 304A and the N-type channel impurity implantation layer 303A are formed is not particularly important.

[0169] 9(b), the ion-implanted semiconductor substrate 130 is heated from 850°C to 1050°C at a heating rate of about 100°C / sec or more, for example, about 200°C / sec, and a first rapid thermal process (RTA) is performed in which the peak temperature is held for a maximum of about 10 seconds or less or the peak temperature is not held. This first rapid thermal process forms an N-type channel diffusion layer 303 and an impurity region 81n, which is an N-type well, in the upper part of the semiconductor substrate 130. The rapid thermal process without holding the peak temperature refers to a thermal process in which the thermal process temperature is lowered at the same time as it reaches the peak temperature.

[0170] 9(c), a gate insulating film 301 made of silicon oxide and having a thickness of about 1.5 nm is selectively formed on the semiconductor substrate 130. A gate electrode 302 made of polysilicon and having a thickness of about 100 nm is selectively formed thereon. Here, silicon oxide is used for the gate insulating film 301, but silicon oxynitride (SiON), hafnium oxide (HfO x Alternatively, a high-k insulating film such as hafnium silicon oxynitride (HfSiON) may be used. In addition, instead of polysilicon, the gate electrode 302 may be made of a metal gate, a laminated film of polysilicon and a metal gate, or polysilicon whose upper portion is silicided or fully silicided.

[0171] 9(d), an insulating film made of silicon oxide with a thickness of about 8 nm is deposited, and then, by anisotropic etching, offset spacers 309a and 309b with a final thickness of about 4 nm are formed on both side surfaces of the gate electrode 302 and the gate insulating film 301. Here, silicon oxide is used for the offset spacers 309a and 309b, but silicon nitride (SiN) or HfO 2 A high-k insulating film such as the above may be used.

[0172] Next, as shown in FIG. 9(e), the offset spacers 309a and 309b and the gate electrode 302 are used as a mask to implant ions into the semiconductor substrate 130 at an implantation energy of 40 keV and an implantation dose of 2×10 13 / cm 2 Next, an N-type impurity, such as phosphorus (P) ions, is implanted at an angle with an implantation energy of 80 keV and an implantation dose of 1×10 13 / cm 2 For example, arsenic (As) ions, which are N-type impurities, are implanted at an angle to form N-type pocket impurity implantation layers 307Aa and 307Ab. The order of implanting P ions and As ions is not particularly important.

[0173] In this example, both P ions and As ions are implanted into the N-type pocket impurity implantation layers 307Aa and 307Ab, although only one of P ions and As ions may be implanted into the N-type pocket impurity implantation layers 307Aa and 307Ab.

[0174] Next, as shown in part (a) of FIG. 10, the offset spacers 309a and 309b and the gate electrode 302 are used as a mask to implant ions into the semiconductor substrate 130 at an implantation energy of 10 keV and an implantation dose of 5×10 14 / cm 2 By implanting germanium (Ge) ions of about 100 Å, amorphous layers 310a and 310b are selectively formed in the semiconductor substrate 130. Here, germanium is used to form the amorphous layers 310a and 310b, but silicon (Si), argon (Ar), krypton (Kr), xenon (Xe), carbon (C), or the like may also be used.

[0175] Next, as shown in part (b) of FIG. 10, in a state where the amorphous layers 310a and 310b are formed, the offset spacers 309a and 309b and the gate electrode 302 are used as masks to implant ions of 1×10 ions into the semiconductor substrate 130 at an implantation energy of 5 keV and an implantation dose of 1×10 ions. 15 / cm 2 Carbon (C) ions of about 1000 .mu.m are implanted to form the carbon implanted layers 311Aa and 311Ab. Note that the carbon ion implantation is performed, for example, with an implantation energy of 1 keV to 10 keV and an implantation dose of 1×10 14 / cm 2 From 3×10 15 / cm 2 In this case, instead of carbon ions, molecules containing carbon, such as C 5 H 5 , C 7 H 7Molecular ions such as germanium (Ge) may be used. Instead of carbon ions, which are impurity ions for preventing diffusion, nitrogen ions, fluorine ions, etc. may be used. When carbon or molecular ions containing carbon are used instead of germanium to form the amorphous layers 310a, 310b, the process of forming the amorphous layers 310a, 310b and the process of forming the carbon implanted layers 311Aa, 311Ab can be performed simultaneously. In addition, ions with a relatively large mass number such as antimony (Sb) may be used for N-type pocket impurity implantation to make the semiconductor substrate 130 amorphous during the pocket implantation.

[0176] Next, as shown in part (c) of FIG. 10, the offset spacers 309a and 309b and the gate electrode 302 are used as a mask to implant ions into the semiconductor substrate 130 at an implantation energy of 0.5 keV and an implantation dose of 5×10 14 / cm 2 A P-type impurity of about 1000 nm, for example, boron (B) ions are implanted to form first P-type impurity implanted layers 306Aa and 306Ab on the carbon implanted layers 311Aa and 311Ab. Note that instead of boron, boron difluoride (BF 2 ), or for example B 18 H x Or B 10 H x Clusters such as boron or indium (In) may also be used.

[0177] Here, part (a) of Fig. 12 shows, on a logarithmic scale, the concentration distribution (impurity profile) of each impurity (boron (B), carbon (C), and germanium (Ge)) in the depth direction of the semiconductor substrate 130 immediately after the implantation of boron ions. As shown in part (a) of Fig. 12, under the germanium implantation conditions according to this example manufacturing method, the depth of the amorphous layers 310a, 310b is about 30 nm.

[0178] Next, the semiconductor substrate 130 is subjected to a second rapid thermal processing in which the substrate temperature is raised from 1200°C to 1350°C by, for example, laser annealing, and the temperature is kept at about the peak temperature for about 1 ms. As a result of this second rapid thermal processing, as shown in part (d) of Fig. 10, first extension diffusion layers 306a, 306b having relatively shallow junctions formed by the diffusion of boron ions, and first pocket diffusion layers 307a, 307b as N-type pocket diffusion layers formed by the diffusion of phosphorus ions and arsenic ions contained in the N-type pocket impurity implantation layers 307Aa, 307Ab, are formed in the regions on the sides of the gate electrode 302 in the semiconductor substrate 130. Here, laser annealing is used for the second rapid thermal processing in milliseconds, but a so-called millisecond annealing (MSA) method such as flash lamp annealing may also be used. Furthermore, the second rapid thermal process may involve heating the semiconductor substrate 130 from 850° C. to 1050° C. at a heating rate of about 200° C. / sec, and holding the peak temperature for a maximum of about 10 seconds, or may involve annealing without holding the peak temperature, such as low-temperature spike-RTA.

[0179] Part (b) of FIG. 12 shows the concentration distribution of impurities (B, C, Ge) in the first extension diffusion layers 306a, 306b, which are P-type extension high concentration diffusion layers formed by the second rapid thermal processing, in the depth direction of the semiconductor substrate 130, on a logarithmic scale. After the second rapid thermal processing is performed, the amorphous layers 310a, 310b formed during the germanium ion implantation are restored to crystalline layers. Boron diffuses and has a peak at a position slightly deeper than immediately after the ion implantation. Carbon has a first peak consisting of carbon clusters near the concentration peak position during ion implantation, and a second peak segregated near the original amorphous-crystal (a / c) interface. Germanium has a concentration distribution that is almost the same as immediately after the ion implantation.

[0180] Here, the concept of "pre-amorphization" will be explained. It is assumed that a certain region in a semiconductor substrate is made amorphous and an impurity having a polarity, i.e., a conductivity type, is implanted into the region (for example, implantation of B ions, etc.). In this case, it is conceivable to perform amorphization and impurity implantation in this order. In this case, amorphization can be called pre-amorphization. If ions are implanted after the substrate is made amorphous, channeling during ion implantation can be suppressed, and a shallow implantation distribution can be formed. Specifically, an implantation distribution with a small tail can be formed. Then, by performing annealing afterwards, solid phase epitaxial regrowth occurs in which the amorphous layer recovers to a crystalline layer, resulting in a high activation rate of the impurity and a shallow junction depth. In this example of the manufacturing method, it can be said that pre-amorphization is performed before B ion implantation for forming the first extension diffusion layers 306a and 306b.

[0181] Next, a first insulating film made of silicon oxide having a thickness of about 10 nm and a second insulating film made of silicon nitride having a thickness of about 40 nm are sequentially deposited on the entire surface of the semiconductor substrate 130 including the offset spacers 309a, 309b and the gate electrode 302 by, for example, chemical vapor deposition (CVD). Thereafter, the deposited first insulating film and second insulating film are anisotropically etched to form first sidewalls 308Aa, 308Ab from the first insulating film and second sidewalls 308Ba, 308Bb from the second insulating film on the side surface of the gate electrode 302 in the gate length direction, as shown in part (a) of FIG. Here, the second sidewalls 308Ba, 308Bb may be silicon oxide instead of silicon nitride, or may be formed of a laminated film made of silicon oxide and silicon nitride.

[0182] Next, as shown in part (b) of FIG. 11, the gate electrode 302, the offset spacers 309a and 309b, the first sidewalls 308Aa and 308Ab, and the second sidewalls 308Ba and 308Bb are used as a mask to implant ions into the semiconductor substrate 130 at an implantation energy of 3 keV and an implantation dose of 3×10 15 / cm 2 Boron ions, which are a P-type impurity, are implanted to about 100 nm to form second P-type impurity implanted layers 313Aa and 313Ab.

[0183] Next, as shown in part (c) of Fig. 11, the semiconductor substrate 130 is subjected to a third rapid thermal processing, for example by laser annealing, in which the substrate temperature is raised from 1200°C to 1350°C and held at the peak temperature for about 1 ms. This third rapid thermal processing causes boron ions to diffuse into the lateral regions of the first sidewalls 308Aa, 308Ab and the second sidewalls 308Ba, 308Bb in the semiconductor substrate 130, forming P-type source / drain diffusion layers 313a, 313b that are P-type high-concentration impurity diffusion layers connected to the first extension diffusion layers 306a, 306b and have a junction deeper than the first extension diffusion layers 306a, 306b. Here, laser annealing is used for the rapid thermal processing in milliseconds, but a so-called millisecond annealing (MSA) method such as flash lamp annealing may also be used. In addition, the third rapid thermal process may involve annealing, such as spike-RTA, in which the temperature is increased to about 850°C to 1050°C at a rate of about 200°C / sec to 250°C / sec and the peak temperature is held for a maximum of about 10 seconds or not held.

[0184] The second rapid thermal processing shown in part (d) of FIG. 10 may be omitted, and in that case, the third rapid thermal processing serves as the second rapid thermal processing.

[0185] Thus, according to this manufacturing method, in the process of forming the first P-type impurity implanted layers 306Aa and 306Ab shown in part (c) of FIG. 10, before performing ion implantation for forming the extension diffusion layer with low energy, the semiconductor substrate 130 is amorphized with germanium in the process shown in part (a) of FIG. 10, and then carbon is implanted as an impurity for preventing diffusion in the process shown in part (b) of FIG. 10. Carbon has the effect of suppressing the transient enhanced diffusion (TED) of impurity atoms. Carbon significantly suppresses the diffusion of boron and phosphorus, and is therefore effective in forming shallow diffusion layers of P-type field effect transistors (pFETs) and N-type field effect transistors (nFETs).

[0186] Since carbon is co-implanted into the formation regions of the first extension diffusion layers 306a and 306b, the carbon plays a role in removing excess point defects in the semiconductor substrate 130 during heat treatment. This reduces excess point defects introduced by ion implantation, suppresses TED of impurity atoms such as boron and phosphorus, and keeps the junction depth of each diffusion layer shallow.

[0187] From the above, by implanting carbon that satisfies the above conditions, it is possible to reliably form the first extension diffusion layers 306 a, 306 b that have shallow junctions, suppress junction leakage, and have low resistance in which an increase in resistance value due to dose loss is suppressed.

[0188] As described above, the heat treatment is performed to heat the pixel region R1, and the first peripheral region R2 may also be heated by the heat treatment. However, even when such a heat treatment is performed, the diffusion suppression effect and related effects based on the carbon implantation can be obtained.

[0189] In one specific example, after the activation heat treatment of part (c) of FIG. 11, an interlayer film is deposited in both the pixel region R1 and the first peripheral region R2. The interlayer film is, for example, a NSG (No doped Silicate Glass) film. Next, an opening is formed in the interlayer film in the pixel region R1. After the opening is formed, an impurity region constituting the charge storage region Z may be implanted in the pixel region R1. Next, polysilicon is deposited in the pixel region R1 so as to fill the above opening, thereby embedding the opened plug portion. The polysilicon may be phosphorus-doped. Next, a heat treatment is performed to heat the pixel region R1 including the plug portion. This heat treatment is, for example, a heat treatment at 850° C. for about 10 minutes. The first peripheral region R2 is also heated by this heat treatment. However, in the first peripheral region R2, the redistribution of impurities is suppressed due to the diffusion suppression effect based on the carbon injection, and a shallow junction can be maintained.

[0190] The diffusion suppression effect based on the carbon injection is effective even when focusing only on the manufacturing process of the first peripheral transistor 27 in the first peripheral region R2. Furthermore, as described above, the diffusion suppression effect based on the carbon injection can be exerted even when an additional process of a heat treatment for heating the pixel region R1 is performed.

[0191] The first pocket diffusion layers 307a and 307b, which are N-type pocket diffusion layers, may be formed using only phosphorus (P). The use of phosphorus provides a stronger carbon ion diffusion prevention effect than the use of arsenic (As).

[0192] INDUSTRIAL APPLICABILITY The transistor and method for manufacturing the same according to the present disclosure can realize shallower junctions and lower resistance of extension diffusion layers associated with miniaturization, and are useful for MIS-type transistors having high driving power and methods for manufacturing the same, etc.

[0193] (Transistors in pixel region R1 and first peripheral region R2) The transistors in the pixel region R1 and the first peripheral region R2 will be further described below with reference to Figures 13 to 24. Note that in Figures 13 to 24, the blocking regions 200A and 200B are omitted from illustration.

[0194] In the following, the terms used above may be replaced with other terms. For example, one of the P-type source / drain diffusion layers 313a and 313b may be referred to as the source, and the other as the drain.

[0195] Hereinafter, the P-type source-drain diffusion layer 313a which is the source of the first peripheral transistor 27 may be referred to as a first source, and the P-type source-drain diffusion layer 313b which is the drain of the first peripheral transistor 27 may be referred to as a first drain.

[0196] As shown in FIGS. 18 and 19, the imaging device may include a second peripheral region R3 located between the pixel region R1 and the first peripheral region R2 in a plan view.

[0197] One semiconductor substrate 130 may extend over both the pixel region R1 and the first peripheral region R2, or the pixel region R1 may be formed using one semiconductor substrate and the first peripheral region R2 may be formed using another semiconductor substrate. One semiconductor substrate 130 may extend over three regions, the pixel region R1, the first peripheral region R2, and the second peripheral region R3, or the pixel region R1 may be formed using one semiconductor substrate, the first peripheral region R2 may be formed using another semiconductor substrate, and the second peripheral region R3 may be formed using yet another semiconductor substrate. One semiconductor substrate 130 may extend over the pixel region R1 and the first peripheral region R2, and the second peripheral region R3 may be formed using another semiconductor substrate. Also, the pixel region R1 may be formed using one semiconductor substrate, and one semiconductor substrate 130 may extend over the first peripheral region R2 and the second peripheral region R3. In this way, the imaging device may have at least one semiconductor substrate.

[0198] Hereinafter, the terms pixel substrate portion, first substrate portion, and second substrate portion may be used. The pixel substrate portion refers to a portion of at least one semiconductor substrate 130 that belongs to a pixel region R1. The first substrate portion refers to a portion of at least one semiconductor substrate 130 that belongs to a first peripheral region R2. The second substrate portion refers to a portion of at least one semiconductor substrate 130 that belongs to a second peripheral region R3.

[0199] The pixel substrate portion may be specifically referred to as a pixel semiconductor substrate portion, the first substrate portion may be specifically referred to as a first semiconductor substrate portion, and the second substrate portion may be specifically referred to as a second semiconductor substrate portion.

[0200] The term "pixel transistor" will be explained. A pixel transistor is a transistor that the pixel region R1 has. For example, the amplification transistor 22, the address transistor 24, and the reset transistor 26 can correspond to pixel transistors. In Figs. 13 to 32, the amplification transistor 22 is illustrated as an example of a pixel transistor. In the following, a case where the pixel transistor is the amplification transistor 22 will be described. However, unless there is a contradiction, in the following description, the amplification transistor 22 can be read as a pixel transistor, an address transistor 24, or a reset transistor 26. Elements of a transistor, such as a source and a drain, and elements associated with a transistor, such as wiring, can also be read as appropriate.

[0201] Fig. 13 shows a schematic diagram of the amplifier transistor 22 in the pixel region R1 and the first peripheral transistor 27 in the first peripheral region R2 when the configuration of Fig. 1 is adopted. Fig. 14 shows a schematic diagram of the amplifier transistor 22 in the pixel region R1 and the first peripheral transistor 27 in the first peripheral region R2 when the configuration of Fig. 4 is adopted.

[0202] 13 and 14, the first peripheral region R2 is located outside the pixel region R1. Specifically, in a plan view, the first peripheral region R2 is located outside the pixel region R1.

[0203] 15 shows a possible configuration of the amplifying transistor 22 in the pixel region R1 and the first peripheral transistor 27 in the first peripheral region R2 in the examples of Fig. 13 and Fig. 14. In the example of Fig. 15, the amplifying transistor 22 is an N-channel MOSFET, and the first peripheral transistor 27 is a P-channel MOSFET. However, as described above, the conductivity types of these transistors are not particularly limited. This also applies to transistors 427, 727, and 827 described below.

[0204] In the example of Fig. 15, the first peripheral transistor 27 is similar to that described with reference to Fig. 5. However, in the example of Fig. 15, it is also possible to adopt another transistor instead of the first peripheral transistor 27. For example, it is also possible to adopt the transistor described with reference to Fig. 6, Fig. 7 or Fig. 8.

[0205] 15, a contact plug cp is connected to a P-type source-drain diffusion layer 313a which is the source of the first peripheral transistor 27. A contact plug cp is connected to a P-type source-drain diffusion layer 313b which is the drain of the first peripheral transistor 27. A contact plug cp is connected to a gate electrode 302 of the first peripheral transistor 27.

[0206] The contact plug cp is, for example, a metal plug. Examples of the metal that the contact plug cp may contain include tungsten and copper.

[0207] 15, the amplifier transistor 22 has a source 67a, a drain 67b, and a gate electrode 67c. The source 67a is an n-type impurity region. The drain 67ba is an n-type impurity region. The gate electrode 67c is made of, for example, a polysilicon material.

[0208] Between the source 67a and the drain 67b, a channel diffusion layer 68 is formed. The channel diffusion layer 68 is an n-type impurity region.

[0209] Between the gate electrode 67c and the pixel substrate portion, a gate insulating film 69 is formed. Specifically, the gate insulating film 69 is an oxide film. The gate insulating film 69 includes silicon oxide in one example, and silicon dioxide in one specific example.

[0210] An offset spacer 70 is formed on the gate electrode 67c and the gate insulating film 69. The offset spacer 70 includes silicon oxide in one example, and silicon dioxide in one specific example.

[0211] On the source 67a side, a first sidewall 71a is formed on the offset spacer 70. In the example of Fig. 15, the first sidewall 71a has an L-shaped cross section. A second sidewall 72a is formed on the outer side of the first sidewall 71a.

[0212] On the drain 67b side, a first sidewall 71b is formed on the offset spacer 70. In the example of Fig. 15, the first sidewall 71b has an L-shaped cross section. A second sidewall 72b is formed on the outer side of the first sidewall 71b.

[0213] The first sidewall 71a includes silicon oxide in one example, and silicon dioxide in one specific example. This also applies to the first sidewall 71b. The second sidewall 72a has a laminated structure including a plurality of insulating layers in one example, and includes a silicon dioxide layer and a silicon nitride layer in one specific example. This also applies to the second sidewall 72b.

[0214] Above the gate electrode 67c, a through hole is formed in the offset spacer 70. A contact plug cx is connected to the gate electrode 67c via the through hole. Above the drain 67b, a through hole is formed in the gate insulating film 69 and the offset spacer 70. A contact plug cx is connected to the drain 67b via the through hole.

[0215] The contact plug cx is, for example, a polysilicon plug, and may be doped with impurities such as phosphorus to enhance conductivity.

[0216] In addition, a configuration in which the contact plug cx is connected to the source 67a may also be adopted. Specifically, a through hole may be formed in the gate insulating film 69 and the offset spacer 70 above the source 67a, and the contact plug cx may be connected to the source 67a via the through hole.

[0217] The contact plug cx connected to the gate electrode 67c is connected to the plug cy. The contact plug cx connected to the drain 67b is connected to the plug cy. If there is a contact plug cx connected to the source 67a, the contact plug cx may be connected to the plug cy.

[0218] The plug cy is, for example, a metal plug. Examples of metals that the plug cy may contain include tungsten and copper.

[0219] As can be understood from the description with reference to FIG. 1 to FIG. 15, the imaging device according to the present embodiment includes a pixel region R1 and a first peripheral region R2. The first peripheral region R2 is located outside the pixel region R1. Specifically, in a planar view, the first peripheral region R2 is located outside the pixel region R1. "Planar view" refers to a view from a direction perpendicular to the semiconductor substrate 130, the first substrate portion, the second substrate portion, or the pixel substrate portion. The pixel region R1 has an amplification transistor 22. The first peripheral region R2 has a first peripheral transistor 27. In one example, the first peripheral transistor 27 is a logic transistor. The first peripheral transistor 27 may be a planar type transistor or a three-dimensional structure transistor such as a FinFET (Fin Field-Effect Transistor).

[0220] In this embodiment, the amplification transistor 22 outputs a signal voltage according to the signal charge obtained by photoelectric conversion. The photoelectric conversion is performed in the photoelectric conversion layer 12. Specifically, a path for guiding the signal charge from the photoelectric conversion layer 12 to the charge accumulation region Z and a path for guiding the signal charge from the charge accumulation region Z to the gate electrode 67c of the amplification transistor 22 are formed. In the example of FIG. 3, the charge accumulation region Z corresponds to the impurity region 60n. As described above, the charge accumulation region Z is included in the charge accumulation node FD.

[0221] In FIG. 15, the symbol L 22 is the gate length of the amplifying transistor 22. 27 is the gate length of the first peripheral transistor 27. In this embodiment, the gate length L 27 is the gate length L of the amplifying transistor 22 22 is shorter than.

[0222] The gate length L of the amplifying transistor 22 22 The gate length L of the first peripheral transistor 27 27 The ratio of L 27 / L 22 For example, the ratio may be equal to or smaller than 0.8 and may be equal to or smaller than 0.34. The ratio may be equal to or larger than 0.01 and may be equal to or larger than 0.05.

[0223] Here, the gate length refers to the dimension of the gate electrode in the direction from the source to the drain or from the drain to the source. The gate width refers to the dimension of the gate electrode in a direction perpendicular to the gate length direction in a plan view. The direction perpendicular to the gate length direction in a plan view may also be referred to as the depth direction.

[0224] In this embodiment, the gate insulating film 301 of the first peripheral transistor 27 is thinner than the gate insulating film 69 of the amplifying transistor 22 .

[0225] The thickness T of the gate insulating film 69 of the amplifying transistor 22 69 The thickness T of the gate insulating film 301 of the first peripheral transistor 27 301The ratio of T 301 / T 69 This ratio may be, for example, 0.7 or less and may be 0.36 or less. This ratio may be, for example, 0.1 or more and may be 0.2 or more.

[0226] In one example, the first peripheral transistor 27 has a first specific layer located in the first substrate portion, the first specific layer including a conductivity type impurity and a specific species.

[0227] A conductivity type impurity is an impurity having a conductivity type, i.e., a conductivity type impurity is a p-type or n-type impurity.

[0228] In this embodiment, the specific species is at least one type of impurity that contributes to suppression of the transient accelerated diffusion of the conductive impurity. The specific species may include at least one selected from the group consisting of carbon, nitrogen, and fluorine. Carbon, nitrogen, and fluorine may suppress the transient accelerated diffusion of the conductive impurity. That is, the specific species may include at least one type of impurity that suppresses the transient accelerated diffusion of the conductive impurity. The specific species may also include at least one selected from the group consisting of germanium, silicon, and argon. Germanium, silicon, and argon may be traces of pre-amorphization that can enhance the diffusion suppression effect of the conductive impurity by the impurity exemplified by carbon. That is, the specific species may include at least one type of impurity that is a trace of pre-amorphization that can enhance the diffusion suppression effect of the conductive impurity by the impurity exemplified by carbon. In the above example, the specific species may also be referred to as a co-implanted species.

[0229] As described above, the first specific layer includes a conductive impurity and a specific species. Such a technique using the first specific layer is suitable for improving the performance of the imaging device in consideration of the presence of the first peripheral transistor 27 in the first peripheral region R2.

[0230] In one example, the first peripheral transistor 27 has a P-type source / drain diffusion layer 313a which is a first source and a P-type source / drain diffusion layer 313b which is a first drain. At least one of the P-type source / drain diffusion layer 313a which is the first source and the P-type source / drain diffusion layer 313b which is the first drain includes a first specific layer.

[0231] In one example, the first peripheral transistor 27 has a first extension diffusion layer EX1. The first extension diffusion layer EX1 is adjacent to the P-type source-drain diffusion layer 313a which is the first source or the P-type source-drain diffusion layer 313b which is the first drain. The first extension diffusion layer EX1 is shallower than the P-type source-drain diffusion layer 313a which is the first source and the P-type source-drain diffusion layer 313b which is the first drain. The first extension diffusion layer EX1 includes a first specific layer. The first extension diffusion layer EX1 is the first extension diffusion layer 306a or the first extension diffusion layer 306b.

[0232] The expression "the extension diffusion layer and the source are adjacent" specifically means that the extension diffusion layer and the source are connected. The same applies to similar expressions such as "the extension diffusion layer and the drain are adjacent", "the pocket diffusion layer and the source are adjacent", and "the pocket diffusion layer and the drain are adjacent", and specifically means that those elements are connected.

[0233] "The first extension diffusion layer EX1 is shallower than the P-type source-drain diffusion layer 313a which is the first source and the P-type source-drain diffusion layer 313b which is the first drain" means that, in the depth direction of the first substrate part, the deepest part of the first extension diffusion layer EX1 is located shallower than the deepest parts of the P-type source-drain diffusion layer 313a which is the first source and the P-type source-drain diffusion layer 313b which is the first drain. In this context, "shallow" can also be referred to as "having a shallow junction depth." The boundary between the extension diffusion layer, the source, and the drain is a junction. The junction is a portion where the concentration of N-type impurities and the concentration of P-type impurities are equal.

[0234] In the illustrated example, the first peripheral transistor 27 has a first extension diffusion layer 306a and a first extension diffusion layer 306b. The first extension diffusion layer 306a is adjacent to the P-type source-drain diffusion layer 313a which is the first source. The first extension diffusion layer 306a is shallower than the P-type source-drain diffusion layer 313a which is the first source and the P-type source-drain diffusion layer 313b which is the first drain. The first extension diffusion layer 306b is adjacent to the P-type source-drain diffusion layer 313b which is the first drain. The first extension diffusion layer 306b is shallower than the P-type source-drain diffusion layer 313a which is the first source and the P-type source-drain diffusion layer 313b which is the first drain. The first extension diffusion layer 306a and the first extension diffusion layer 306b include a first specific layer.

[0235] In one example, the first peripheral transistor 27 has a first pocket diffusion layer P1. The first pocket diffusion layer P1 is adjacent to the P-type source-drain diffusion layer 313a which is the first source or the P-type source-drain diffusion layer 313b which is the first drain. The first pocket diffusion layer P1 includes a first specific layer. The first pocket diffusion layer P1 is the first pocket diffusion layer 307a or the first pocket diffusion layer 307b.

[0236] In the illustrated example, the first peripheral transistor 27 has a first pocket diffusion layer 307a and a first pocket diffusion layer 307b. The first pocket diffusion layer 307a is adjacent to a P-type source-drain diffusion layer 313a which is a first source. The first pocket diffusion layer 307b is adjacent to a P-type source-drain diffusion layer 313b which is a first drain. The first pocket diffusion layer 307a and the first pocket diffusion layer 307b include a first specific layer.

[0237] Only one selected from the P-type source-drain diffusion layer 313a which is the first source, the P-type source-drain diffusion layer 313b which is the first drain, the first extension diffusion layer EX1, and the first pocket diffusion layer P1 may include the first specific layer. Specifically, only one selected from the P-type source-drain diffusion layer 313a which is the first source, the P-type source-drain diffusion layer 313b which is the first drain, the first extension diffusion layer 306a, the first extension diffusion layer 306b, the first pocket diffusion layer 307a, and the first pocket diffusion layer 307b may include the first specific layer.

[0238] Two or more selected from the P-type source-drain diffusion layer 313a as the first source, the P-type source-drain diffusion layer 313b as the first drain, the first extension diffusion layer EX1, and the first pocket diffusion layer P1 may include the first specific layer. Specifically, two or more selected from the P-type source-drain diffusion layer 313a as the first source, the P-type source-drain diffusion layer 313b as the first drain, the first extension diffusion layer 306a, the first extension diffusion layer 306b, the first pocket diffusion layer 307a, and the first pocket diffusion layer 307b may include the first specific layer. When two or more selected from these include the first specific layer, the types of specific species included therein may be the same or different. For example, the specific species of the P-type source-drain diffusion layer 313a as the first source may be carbon, and the specific species of the first extension diffusion layer EX1 may be nitrogen and fluorine. In this case, the conductivity types of the conductive impurities contained therein may be the same or different. For example, one of the P-type source / drain diffusion layer 313a serving as the first source and the first pocket diffusion layer P1 may contain boron and have a p-type conductivity, and the other may contain phosphorus and have an n-type conductivity.

[0239] As can be understood from the above description, the number of first specific layers included in the imaging device may be one or more.

[0240] An example of a situation in which the technology using the first specific layer can contribute to the above-mentioned performance improvement will be described below.

[0241] In the manufacturing process of the imaging device, a heat treatment may be performed. The heat treatment may reduce defects in the pixel substrate portion in the pixel region R1. By reducing the defects, dark current in the imaging device may be suppressed. On the other hand, in the first peripheral region R2, the need to reduce defects is not necessarily high. Rather, in the first peripheral region R2, there are cases where performance degradation of the first peripheral transistor 27 caused by diffusion of conductive impurities accompanying the heat treatment should be suppressed. The performance degradation is, for example, an undesired change in the threshold voltage of the first peripheral transistor 27.

[0242] In particular, in this embodiment, the first peripheral transistor 27 includes at least one of a first feature and a second feature. The first feature is that the gate length L 27 is the gate length L of the amplifying transistor 22 22 A second feature is that the gate insulating film 301 of the first peripheral transistor 27 is thinner than the gate insulating film 69 of the amplifying transistor 22. When the first peripheral transistor 27 has a microstructure including at least one of the first feature and the second feature, the performance of the first peripheral transistor 27 is easily affected by the diffusion and redistribution of conductive impurities due to additional heat treatment.

[0243] In this regard, as described above, in one example of the present embodiment, the first specific layer includes a conductive impurity and a specific species. The specific species can contribute to suppression of diffusion of the conductive impurity. This diffusion suppression effect can suppress performance degradation of the first peripheral transistor 27. Therefore, it is possible to suppress the above-mentioned disadvantage of performance degradation of the first peripheral transistor 27 while enjoying the above-mentioned advantage of dark current suppression.

[0244] Specifically, the first specific layer is included in the first extension diffusion layer EX1, and the gate length L of the first peripheral transistor 27 is 27 is the gate length L of the amplifying transistor 22 22 Consider a first specific example in which the length is shorter than L. Heat treatment may be performed during the manufacturing process of the image pickup device. Heat treatment can reduce defects in the pixel substrate portion in the pixel region R1. By reducing the defects, dark current in the image pickup device can be suppressed. On the other hand, L 27 <L 22In this case, the first peripheral transistor 27 is more susceptible to the short channel effect due to heating than the amplifying transistor 22. The short channel effect can change the threshold voltage of the transistor from a desired value, resulting in a decrease in the performance of the transistor. Thus, the heat treatment has the advantage of suppressing dark current in the pixel region R1, but can have the disadvantage of exposing the short channel effect in the first peripheral region R2. Here, the threshold voltage refers to the gate-source voltage of the transistor when a drain current starts to flow through the transistor.

[0245] In this regard, in the first specific example, the first extension diffusion layer EX1 includes a conductive impurity and a specific species. The specific species can contribute to suppression of diffusion of the conductive impurity. This diffusion suppression effect can suppress the short channel effect in the first peripheral transistor 27. Therefore, it is possible to suppress the above-mentioned disadvantage of the short channel effect while enjoying the above-mentioned advantage of dark current suppression.

[0246] As described above, in the first specific example, the short channel effect of the first peripheral transistor 27 caused by the heat treatment is suppressed by the diffusion suppression effect derived from the specific species of the first extension diffusion layer EX1. This means that the margin of the thermal budget of the heat treatment is wider than in the case where there is no diffusion suppression effect. Therefore, by increasing the time, temperature, etc. of the heat treatment, it is possible to suppress the dark current in the pixel region R1 without making the short channel effect in the first peripheral transistor 27 apparent.

[0247] The first specific layer is included in at least one of the P-type source-drain diffusion layer 313a which is the first source and the P-type source-drain diffusion layer 313b which is the first drain, and the gate length L 27 is the gate length L of the amplifying transistor 22 22In the second specific example, similarly to the first specific example, the dark current in the pixel region R1 can be suppressed without making the short channel effect in the first peripheral transistor 27 manifest by increasing the time and temperature of the heat treatment.

[0248] The first specific layer is included in the first pocket diffusion layer P1, and the gate length L of the first peripheral transistor 27 is 27 is the gate length L of the amplifying transistor 22 22 Consider a third specific example in which the length of the first peripheral transistor 27 is shorter than the length of the first pocket diffusion layer P1. In the third specific example, the variation in the threshold voltage of the first peripheral transistor 27 can be suppressed by suppressing the diffusion of the conductive impurities in the first pocket diffusion layer P1. Therefore, according to the third specific example, similar to the first specific example, by increasing the time and temperature of the heat treatment, the dark current in the pixel region R1 can be suppressed without making the variation in the threshold voltage of the first peripheral transistor 27 apparent.

[0249] As described above, the semiconductor substrate 130 may be a substrate having a semiconductor layer formed on its surface by epitaxial growth. The same applies to the pixel substrate portion, the first substrate portion, and the second substrate portion. In the semiconductor layer derived from epitaxial growth, it is easy to reduce the inclusion of unintended carbon. This can contribute to suppression of dark current in the pixel region R1. This also makes it easy to differentiate between the pixel region R1 and the first peripheral region R2 in terms of the concentration of a particular species such as carbon.

[0250] As described above, the semiconductor substrate 130 may be a p-type silicon substrate. However, the semiconductor substrate 130 may be an n-type silicon substrate. The same applies to the pixel substrate portion, the first substrate portion, and the second substrate portion.

[0251] In one example, the pixel region R1 has a pixel substrate portion and a photoelectric conversion layer 12. The photoelectric conversion layer 12 is laminated on the pixel substrate portion. In a typical example, when the pixel region R1 having such a configuration is manufactured, the above-mentioned heat treatment is performed. Therefore, in an imaging device including the pixel region R1 having such a configuration, it is possible to enjoy the above-mentioned effect of suppressing dark current while suppressing performance deterioration of the first peripheral transistor 27. Note that the "photoelectric conversion layer 12 is laminated on the pixel substrate portion" is a concept that includes a form in which an element such as an insulating layer is interposed between the photoelectric conversion layer 12 and the pixel substrate portion. It can also be said that the photoelectric conversion layer 12 is supported by the pixel substrate portion.

[0252] In one example, the amplifying transistor 22 and the first peripheral transistor 27 are provided on a single semiconductor substrate 130. In an imaging device having such a configuration, the first peripheral region R2 is likely to be heated by a heat treatment for heating the pixel region R1. In an imaging device having such a configuration, it is easy to enjoy the above-mentioned effect of suppressing dark current while suppressing performance deterioration of the first peripheral transistor 27. Typically, in an imaging device having such a configuration, the first peripheral region R2 is heated at the same time as the heat treatment for heating the pixel region R1.

[0253] The photoelectric conversion layer 12 may be a panchromatic film, or may be an orthochromatic film that has no sensitivity to light in a certain wavelength range.

[0254] The conductive impurity may be a P-type impurity. Examples of P-type conductive impurities include boron and indium. The conductive impurity may be an N-type impurity. Examples of N-type conductive impurities include phosphorus, arsenic, antimony, and bismuth.

[0255] The first source, the first drain and the first extension diffusion layer EX1 may have a first conductivity type impurity. The same applies to the first extension diffusion layer 306a and the first extension diffusion layer 306b. In contrast, the first pocket diffusion layer P1 may have a second conductivity type impurity. The same applies to the first pocket diffusion layer 307a and the first pocket diffusion layer 307b. The first conductivity type is n-type or p-type. The second conductivity type is the opposite conductivity type to the first conductivity type. The second conductivity type is p-type or n-type.

[0256] In one specific example, the first peripheral transistor 27 is a logic transistor. The first peripheral transistor 27 can perform digital operations. In such a first peripheral transistor 27, speed may be prioritized. To allow the transistor to operate at high speed, it is advantageous for the transistor to be a fine transistor. In addition, it is also advantageous from the viewpoint of ensuring high driving power of the transistor that the transistor is a fine transistor. In this regard, in this specific example, the gate length L 27 is the gate length L of the amplifying transistor 22 22 The gate insulating film 301 of the first peripheral transistor 27 is thinner than the gate insulating film 69 of the amplifying transistor 22. 27 The short gate length L and the thin gate insulating film 301 can be advantageous in terms of operating the first peripheral transistor 27 at high speed and with high driving power. 27 This advantage of the short length and thin gate insulating film 301 can be exhibited, for example, when the first peripheral transistor 27 is a planar type transistor. Also, the first peripheral transistor 27 of this specific example is located, for example, between the control unit and the pixel driver unit.

[0257] In one example, the first specific layer includes germanium. As can be understood from the above description, germanium can pre-amorphize the first substrate portion during the manufacturing process of the first peripheral transistor 27. In the pre-amorphized region, the impurity such as carbon is likely to have a high effect of suppressing the diffusion of conductive impurities. The germanium in this example can be a trace of pre-amorphization that can enhance the effect of suppressing the diffusion of conductive impurities such as carbon.

[0258] The first specific layer may contain silicon, argon, krypton, or xenon instead of or together with germanium. More generally, the first specific layer may contain at least one element selected from the group consisting of germanium, silicon, argon, krypton, and xenon. These elements may be traces of pre-amorphization that can enhance the effect of suppressing the diffusion of conductive impurities by impurities such as carbon.

[0259] In one example, the first peripheral transistor 27 includes an end-of-range (EOR) defect. At least a part of the first specific layer is located above the EOR defect and overlaps with the EOR defect in a plan view. In this context, above the EOR defect means the surface side of the first substrate part on which the gate electrode 302 is provided, as viewed from the EOR defect. As described above, in the pre-amorphized region in the first substrate part, the diffusion suppression effect of the impurity, exemplified by carbon, on the conductive impurity is likely to be enhanced. As can be understood from the above description, in the manufacturing process of the first peripheral transistor 27, when the first substrate part is subjected to a heat treatment in an amorphized state, an EOR defect may be formed in the region immediately below the amorphous-crystal (a / c) interface before the heat treatment. The EOR defect in this example may be a trace of pre-amorphization that may enhance the diffusion suppression effect of the impurity, exemplified by carbon, on the conductive impurity. The entire first specific layer may be located above the EOR defect and overlapping with the EOR defect in a plan view.

[0260] In one example, the first peripheral transistor 27 includes a segregation portion in which a specific species is segregated in the depth direction of the first substrate portion. At least a part of the first specific layer is located above the segregation portion and overlaps with the segregation portion in a plan view. As described above, in the pre-amorphized region in the first substrate portion, the diffusion suppression effect of impurities such as carbon is likely to be enhanced. In the manufacturing process of the first peripheral transistor 27, when the first substrate portion is subjected to a heat treatment in an amorphous state, a segregation portion may be formed in a region immediately below the amorphous-crystal (a / c) interface before the heat treatment. The segregation portion in this example may be a trace of pre-amorphization that can enhance the diffusion suppression effect of impurities such as carbon. The entire first specific layer may be located above the segregation portion and overlaps with the segregation portion in a plan view. In the expression "segregation portion where a specific species is segregated", "segregation" means that a specific species is unevenly distributed, and is not intended to limit the process of formation of the segregation portion.

[0261] The segregation portion will be explained using a concentration profile, which is the relationship between the concentration of a specific species and the depth in the first substrate portion. When a segregation portion exists, the concentration profile has a minimum value at a first depth that substantially corresponds to the depth of the amorphous-crystal (a / c) interface before heat treatment. The concentration profile has a maximum value at a second depth that is deeper than the first depth. The segregation portion refers to a portion of the first substrate portion that is deeper than the first depth and where the concentration of a specific species is higher than the minimum value. In the carbon profile in part (b) of Figure 12, the "original a / c interface" substantially corresponds to the first depth, and the upwardly convex portion directly below the "original a / c interface" corresponds to the segregation portion.

[0262] In this embodiment, the pixel region R1 includes a charge accumulation region Z. Charges generated by photoelectric conversion are accumulated in the charge accumulation region Z. The charge accumulation region Z is an impurity region. In the example of FIG. 3, the charge accumulation region Z corresponds to the impurity region 60n. Specifically, photoelectric conversion is performed in the photoelectric conversion structure 10, and the generated charges are sent to the charge accumulation region Z via the plug cy and the contact plug cx and accumulated in the charge accumulation region Z.

[0263] In one example, the segregation portion is shallower than the charge accumulation region Z. "The segregation portion is shallower than the charge accumulation region Z" means that the deepest part of the segregation portion is located shallower than the deepest part of the charge accumulation region Z in the depth direction of the pixel substrate portion or the first substrate portion.

[0264] In one example, the carbon concentration in the first specific layer is higher than the carbon concentration in the charge accumulation region Z. Carbon in the first specific layer can suppress the diffusion of conductive impurities. On the other hand, the presence of carbon in the charge accumulation region Z can cause dark current. Therefore, the feature that the carbon concentration in the first specific layer is higher than the carbon concentration in the charge accumulation region Z can be possessed by a high-performance imaging device. In the expression "the carbon concentration in the first specific layer is higher than the carbon concentration in the charge accumulation region Z", the carbon concentration in the charge accumulation region Z may be zero or may be higher than zero.

[0265] Here, the boundary of the charge storage region Z is a junction. As described above, the junction is a portion where the concentration of N-type impurities and the concentration of P-type impurities are equal.

[0266] In the first definition, the "carbon concentration" in the expression "the carbon concentration in the first specific layer is higher than the carbon concentration in the charge accumulation region Z" is the maximum concentration. In the second definition, the "carbon concentration" in this expression is the average concentration. In the above example, if it can be said that "the carbon concentration in the first specific layer is higher than the carbon concentration in the charge accumulation region Z" based on at least one of the first and second definitions, it will be treated as "the carbon concentration in the first specific layer is higher than the carbon concentration in the charge accumulation region Z."

[0267] Consider the case where the specific species is carbon. The ratio C2 / C1 of the concentration C2 of carbon in the first specific layer to the concentration C1 of carbon in the charge accumulation region Z is, for example, 1×10 5 This ratio is, for example, 1×10 11 The following is the result.

[0268] Consider the case where the specific species is carbon and the first specific layer is included in the first extension diffusion layer EX1. The concentration of the conductive impurity in the first extension diffusion layer EX1 is, for example, 1×10 17 atoms / cm 3 The carbon concentration in the first extension diffusion layer EX1 is, for example, 1×10 17 atoms / cm 3 The concentration of the conductive impurity in the first extension diffusion layer EX1 is, for example, 1×10 22 atoms / cm 3 The carbon concentration in the first extension diffusion layer EX1 is, for example, 1×10 22 atoms / cm 3 These descriptions can be applied to both the first extension diffusion layers 306a and 306b.

[0269] In one example, the concentration of carbon in the charge storage region Z is substantially zero. Here, the carbon concentration in the charge storage region Z being substantially zero means, for example, that the carbon concentration in the charge storage region Z is 5×10 16 atoms / cm 3The charge accumulation region Z may not have any intentionally added carbon. The concentration of carbon in the charge accumulation region Z is zero atoms / cm 3 may be also possible.

[0270] In one example, the carbon concentration in the first specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22. This configuration is advantageous from the viewpoint of reducing dark current. Here, "under the gate of the amplifying transistor 22" refers to a portion of the surface of the pixel substrate part on the gate 67c side that overlaps with the gate 67c of the amplifying transistor 22 in a planar view. In the expression "the carbon concentration in the first specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22", the carbon concentration under the gate of the amplifying transistor 22 may be zero or may be higher than zero.

[0271] In the first definition, the "carbon concentration" in the expression "the carbon concentration in the first specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22" is the maximum concentration. In the second definition, the "carbon concentration" in this expression is the average concentration. In the above example, if it can be said that "the carbon concentration in the first specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22" based on at least one of the first and second definitions, it will be treated as "the carbon concentration in the first specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22".

[0272] In one example, the amplifying transistor 22 does not have an extension diffusion layer.

[0273] Incidentally, for example, polysilicon doped with phosphorus can be used as the material of the gate electrode 302 of the first peripheral transistor 27. However, in that case, when the first peripheral region R2 is also heated by a heat treatment for heating the pixel region R1, phosphorus may seep into the first substrate portion. In this regard, in the imaging device according to the example, a high-k metal gate is configured in the first peripheral transistor 27. In this way, it is possible to suppress or avoid the seepage of impurities from the gate electrode 302 to the first substrate portion. This can contribute to suppressing the short channel effect in the first peripheral transistor 27. Specifically, a high-k metal gate can be configured by combining the gate electrode 302 made of metal and the gate insulating film 301 made of a high-k material. The high-k material refers to a material having a higher relative dielectric constant than silicon dioxide. Examples of the high-k material are hafnium (Hf), zirconium (Zr), aluminum (Al), and the like. The high-k material can also be called a high dielectric material.

[0274] The number of first peripheral transistors 27 in the first peripheral region R1 may be one or more.

[0275] Fig. 16 shows a schematic diagram of the amplifier transistor 22 in the pixel region R1 and the first peripheral transistors 27 in the first peripheral region R2 when the configuration of Fig. 1 is adopted. Fig. 17 shows a schematic diagram of the amplifier transistor 22 in the pixel region R1 and the first peripheral transistors 27 in the first peripheral region R2 when the configuration of Fig. 4 is adopted.

[0276] In the examples of FIGS. 16 and 17, there are a plurality of first peripheral transistors 27 in the first peripheral region R2. The plurality of first peripheral transistors 27 include a first direction transistor 27a and a second direction transistor 27b. The first direction transistor 27a is located in the first direction X1 from the pixel region R1 in a planar view. The second direction transistor 27b is located in the second direction X2 from the pixel region R1 in a planar view. Note that the expression "there are a plurality of first peripheral transistors 27" is not intended to require that the transistors are completely identical. The same applies to the "two first peripheral transistors" described below.

[0277] The first direction X1 and the second direction X2 are different directions from each other. In the examples of Fig. 16 and Fig. 17, the first direction X1 and the second direction X2 are directions perpendicular to each other.

[0278] 18 and 19, the imaging device may include a second peripheral region R3 located between the pixel region R1 and the first peripheral region R2 in a planar view. In the example of FIGS. 18 and 19, the second peripheral region R3 has a second peripheral transistor 427. In one example, the second peripheral transistor 427 is a logic transistor. The second peripheral transistor 427 may be a planar type transistor or a three-dimensional structure transistor such as a FinFET (Fin Field-Effect Transistor).

[0279] 18 and 19, the first peripheral region R2 is located outside the pixel region R1. Specifically, in a plan view, the first peripheral region R2 is located outside the pixel region R1.

[0280] In the example of Fig. 18, the first peripheral region R2 and the second peripheral region R3 are L-shaped in a planar view. In the example of Fig. 19, the first peripheral region R2 surrounds the second peripheral region R3, and the second peripheral region R3 surrounds the pixel region R1 in a planar view.

[0281] In the examples of Figures 18 and 19, a possible configuration of the second peripheral transistor 427 in the second peripheral region R3 is shown in Figure 20. In the example of Figure 20, the second peripheral transistor 427 is a P-channel MOSFET.

[0282] In the example of FIG. 20, the second peripheral transistor 427 in the second peripheral region R3 has similarities with the first peripheral transistor 27 in the first peripheral region R2. Specifically, the second peripheral transistor 427 is an MIS transistor, similar to the first peripheral transistor 27. The second peripheral transistor 427 includes a gate electrode 402, a second source 413a, a second drain 413b, second extension diffusion layers 406a, 406b, second pocket diffusion layers 407a, 407b, a channel diffusion layer 403, a gate insulating film 401, offset spacers 409a, 409b, first sidewalls 408Aa, 408Ab, and second sidewalls 408Ba, 408Bb, similar to the first peripheral transistor 27. Unless otherwise stated, the description of the first peripheral transistor 27 can be used to describe the second peripheral transistor 427 with respect to these components.

[0283] In one example, the second peripheral transistor 427 has a second specific layer located in the second substrate portion, the second specific layer including a conductivity type impurity.

[0284] The composition of the conductive type impurity in the second specific layer and the composition of the conductive type impurity in the first specific layer may be the same or different.

[0285] The second specific layer may contain a specific species. The specific species of the second specific layer may be the same as or different from the specific species of the first specific layer. For example, the specific species of the first specific layer may be carbon, and the specific species of the second specific layer may be nitrogen and fluorine.

[0286] In one example, the second peripheral transistor 427 has a second source 413a and a second drain 413b. At least one of the second source 413a and the second drain 413b includes the second specific layer.

[0287] In one example, the second peripheral transistor 427 has a second extension diffusion layer EX2. The second extension diffusion layer EX2 is adjacent to the second source 413a or the second drain 413b. The second extension diffusion layer EX2 is shallower than the second source 413a and the second drain 413b. The second extension diffusion layer EX2 includes a second specific layer. The second extension diffusion layer EX2 is the second extension diffusion layer 406a or the second extension diffusion layer 406b.

[0288] "The second extension diffusion layer is shallower than the second source 413a and the second drain 413b" means that, in the depth direction of the second substrate portion, the deepest part of the second extension diffusion layer is located shallower than the deepest parts of the second source 413a and the second drain 413b. In this context, "shallow" can also be referred to as "having a shallow junction depth."

[0289] In the illustrated example, the second peripheral transistor 427 has a second extension diffusion layer 406a and a second extension diffusion layer 406b. The second extension diffusion layer 406a is adjacent to the second source 413a. The second extension diffusion layer 406a is shallower than the second source 413a and the second drain 413b. The second extension diffusion layer 406b is adjacent to the second drain 413b. The second extension diffusion layer 406b is shallower than the second source 413a and the second drain 413b. The second extension diffusion layer 406a and the second extension diffusion layer 406b include a second specific layer.

[0290] In one example, the second peripheral transistor 427 has a second pocket diffusion layer P2. The second pocket diffusion layer P2 is adjacent to the second source 413a or the second drain 413b. The second pocket diffusion layer P2 includes a second specific layer. The second pocket diffusion layer P2 is the second pocket diffusion layer 407a or the second pocket diffusion layer 407b.

[0291] In the illustrated example, the second peripheral transistor 427 includes a second pocket diffusion layer 407a and a second pocket diffusion layer 407b. The second pocket diffusion layer 407a is adjacent to the second source 413a. The second pocket diffusion layer 407b is adjacent to the second drain 413b. The second pocket diffusion layer 407a and the second pocket diffusion layer 407b include a second specific layer.

[0292] Only one selected from the second source 413a, the second drain 413b, the second extension diffusion layer EX2, and the second pocket diffusion layer P2 may include the second specific layer. Specifically, only one selected from the second source 413a, the second drain 413b, the second extension diffusion layer 406a, the second extension diffusion layer 406b, the second pocket diffusion layer 407a, and the second pocket diffusion layer 407b may include the second specific layer.

[0293] Two or more selected from the second source 413a, the second drain 413b, the second extension diffusion layer EX2, and the second pocket diffusion layer P2 may include the second specific layer. Specifically, two or more selected from the second source 413a, the second drain 413b, the second extension diffusion layer 406a, the second extension diffusion layer 406b, the second pocket diffusion layer 407a, and the second pocket diffusion layer 407b may include the first specific layer. When two or more selected from these include the first specific layer, the types of specific species contained therein may be the same or different. For example, the specific species of the second source 413a may be carbon, and the specific species of the second extension diffusion layer EX2 may be nitrogen and fluorine. In this case, the conductivity types of the conductive impurities contained therein may be the same or different. For example, one of the second source 413a and the second pocket diffusion layer P2 may contain boron and have a p-type conductivity, and the other may contain phosphorus and have an n-type conductivity.

[0294] As can be understood from the above description, the number of second specific layers included in the imaging device may be one or more.

[0295] In one example, the concentration of conductive impurities in the second extension diffusion layer EX2 is lower than the concentration of conductive impurities in the first extension diffusion layer EX1. The second extension diffusion layer EX2 is deeper than the first extension diffusion layer EX1. As described above, the first extension diffusion layer EX1 is the first extension diffusion layer 306a or the first extension diffusion layer 306b. Also, the second extension diffusion layer EX2 is the second extension diffusion layer 406a or the second extension diffusion layer 406b.

[0296] "The second extension diffusion layer is deeper than the first extension diffusion layer" means that the deepest part of the second extension diffusion layer is located deeper than the deepest part of the first extension diffusion layer in the depth direction of the pixel substrate unit or the second substrate unit. In this context, "deep" can also be referred to as "having a deep junction depth."

[0297] In the first definition, the "concentration of conductive impurities" in the expression "the concentration of conductive impurities in the second extension diffusion layer is lower than the concentration of conductive impurities in the first extension diffusion layer" is the maximum concentration. In the second definition, the "concentration of conductive impurities" in this expression is the average concentration. In the above example, if it can be said that "the concentration of conductive impurities in the second extension diffusion layer is lower than the concentration of conductive impurities in the first extension diffusion layer" based on at least one of the first and second definitions, it is treated as "the concentration of conductive impurities in the second extension diffusion layer is lower than the concentration of conductive impurities in the first extension diffusion layer". In this expression, the type of conductive impurities in the first extension diffusion layer and the type of conductive impurities in the second extension diffusion layer may be the same or different. For example, the conductive impurities in the first extension diffusion layer may be boron, and the conductive impurities in the first extension diffusion layer may be indium.

[0298] In the illustrated example, the second peripheral transistor 427 has a second extension diffusion layer 406a and a second extension diffusion layer 406b. The second extension diffusion layer 406a is adjacent to the second source 413a. The second extension diffusion layer 406a is shallower than the second source 413a and the second drain 413b. The second extension diffusion layer 406a has a conductive impurity. The second extension diffusion layer 406b is adjacent to the second drain 413b. The second extension diffusion layer 406b is shallower than the second source 413a and the second drain 413b. The second extension diffusion layer 406b has a conductive impurity. The concentration of the conductive impurity in the second extension diffusion layer 406a is lower than the concentration of the conductive impurity in the first extension diffusion layer 306a. The second extension diffusion layer 406a is deeper than the first extension diffusion layer 306a. The concentration of the conductive impurities in the second extension diffusion layer 406b is lower than the concentration of the conductive impurities in the first extension diffusion layer 306b. The second extension diffusion layer 406b is deeper than the first extension diffusion layer 306b.

[0299] In one example, the gate length L of the first peripheral transistor 27 27 is the gate length L of the second peripheral transistor 427 427 The gate length L of the first peripheral transistor 27 is shorter than 27 A short gate length is advantageous for miniaturizing the first peripheral transistor 27, and is advantageous from the viewpoint of operating the first peripheral transistor 27 at high speed. In one specific example, the second peripheral transistor 427 is included in the analog processing section, and the first peripheral transistor 27 is included in the digital processing section. In this specific example, by adopting different gate lengths for the first peripheral transistor 27 and the second peripheral transistor 427, the gate length L 27 Digital processing can be realized by taking advantage of the high-speed operation of the first peripheral transistor 27 having a short gate length L. Since the first peripheral transistor 27 is finer, the digital processing speed in the digital processing unit can be increased. 427Since the length is relatively long, it is possible to suppress variations in the threshold voltage of the second peripheral transistor 427. Therefore, it is also possible to improve the analog characteristics of the second peripheral transistor 427 in the analog processing section.

[0300] The gate length L of the second peripheral transistor 427 427 The gate length L of the first peripheral transistor 27 27 The ratio of L 27 / L 427 For example, the ratio may be equal to or smaller than 0.8 and may be equal to or smaller than 0.34. The ratio may be equal to or larger than 0.01 and may be equal to or larger than 0.05.

[0301] In one example, the gate length L of the amplification transistor 22 22 is the gate length L of the second peripheral transistor 427 427 The gate length L of the amplifying transistor 22 is longer than 22 A long gate length L may be advantageous for improving the characteristics of the amplifier transistor 22. In one specific example, the amplifier transistor 22 is included in the analog processing section. In this specific example, the gate length L 22 This makes it easier to lengthen the time required for the amplifier transistor 22 to have a smaller variation in the threshold voltage and to improve the Peligrom coefficient. In the analog processing section, analog processing can be realized by making the most of the excellent analog characteristics of the amplifier transistor 22 based on this.

[0302] The gate length L of the amplifying transistor 22 22 The gate length L of the second peripheral transistor 427 427 The ratio of L 427 / L 22 This ratio may be, for example, 0.95 or less and may be 0.9 or less. This ratio may be, for example, 0.1 or more and may be 0.36 or more.

[0303] In one example, the gate insulating film 301 of the first peripheral transistor 27 is thinner than the gate insulating film 401 of the second peripheral transistor 427. The thin gate insulating film 301 of the first peripheral transistor 27 is advantageous for miniaturizing the first peripheral transistor 27, and is advantageous from the viewpoint of operating the first peripheral transistor 27 at high speed. In one specific example, the second peripheral transistor 427 is included in the analog processing section, and the first peripheral transistor 27 is included in the digital processing section. In this specific example, by adopting different gate insulating film thicknesses for the first peripheral transistor 27 and the second peripheral transistor 427, digital processing can be realized in the digital processing section by taking advantage of the high-speed operation of the first peripheral transistor 27 having a thin gate insulating film 301. Since the first peripheral transistor 27 is finer, the digital processing section can speed up. On the other hand, since the gate insulating film 401 is relatively thick, the variation in the threshold voltage of the second peripheral transistor 427 can be suppressed. Therefore, the analog characteristics of the second peripheral transistor 427 in the analog processing section can be improved.

[0304] The thickness T of the gate insulating film 401 of the second peripheral transistor 427 401 The thickness T of the gate insulating film 301 of the first peripheral transistor 27 301 The ratio of T 301 / T 401 For example, the ratio may be equal to or smaller than 0.7 and may be equal to or smaller than 0.36. The ratio may be equal to or larger than 0.1 and may be equal to or larger than 0.22.

[0305] In one example, the gate insulating film 69 of the amplifying transistor 22 is thicker than the gate insulating film 401 of the second peripheral transistor 427. A thick gate insulating film 69 of the amplifying transistor 22 can be advantageous in improving the characteristics of the amplifying transistor 22. In one specific example, the amplifying transistor 22 is included in the analog processing section. In this specific example, it is easy to make the gate insulating film 69 thicker to reduce the variation in the threshold voltage of the amplifying transistor 22 and improve the Peligrom coefficient. In the analog processing section, analog processing can be realized by making use of the excellent analog characteristics of the amplifying transistor 22 based on this.

[0306] The thickness T of the gate insulating film 69 of the amplifying transistor 22 69 The thickness T of the gate insulating film 401 of the second peripheral transistor 427 401 The ratio of T 401 / T 69 is, for example, less than 1. This ratio is, for example, greater than or equal to 0.68.

[0307] In one specific example, the second peripheral transistor 427 is a logic transistor. The second peripheral transistor 427 can perform analog operations while being incorporated in a pixel driver, a load cell, a column amplifier, a comparator, or the like. In analog operations, a wide dynamic range can be advantageous. To ensure a wide dynamic range, it is advantageous for the transistor to have a high operating voltage and a wide voltage range. For example, when the pixel voltage is about 3V to 3.5V, it can be advantageous for the operating voltage to be 3.3V. In this regard, in this specific example, the gate length L of the second peripheral transistor 427 is 427 is the gate length L of the first peripheral transistor 27 27 The gate insulating film 401 of the second peripheral transistor 427 is thicker than the gate insulating film 301 of the first peripheral transistor 27. The gate length L 427 The long and thick gate insulating film 401 is advantageous in terms of increasing the operating voltage of the second peripheral transistor 427. In the above context, the operating voltage is the drain voltage of the transistor when the transistor is on. The pixel voltage is the voltage of the charge storage node in the pixel.

[0308] In this specific example, the operating voltage of the second peripheral transistor 427 is higher than the operating voltage of the first peripheral transistor 27. The operating voltage of the second peripheral transistor 427 is, for example, 3.3V. The operating voltage of the first peripheral transistor 27 is, for example, 1.2V.

[0309] In this specific example, the second peripheral transistor 427 has a longer gate length and a thicker gate insulating film than the first peripheral transistor 27, and therefore has a smaller variation in threshold voltage. The small variation in threshold voltage is also an advantageous feature. In this specific example, the threshold voltage of the second peripheral transistor 427 is higher than the threshold voltage of the first peripheral transistor 27. The threshold voltage of the second peripheral transistor 427 is, for example, about 0.5V. The threshold voltage of the first peripheral transistor 27 is, for example, about 0.3V.

[0310] In one example, the concentration of the specific species in the first specific layer is higher than the concentration of the specific species in the second specific layer. In the expression "the concentration of the specific species in the first specific layer is higher than the concentration of the specific species in the second specific layer," the concentration of the specific species in the second specific layer may be zero or may be higher than zero.

[0311] In the first definition, the "concentration of the specific species" in the expression "the concentration of the specific species in the first specific layer is higher than the concentration of the specific species in the second specific layer" is the maximum concentration. In the second definition, the "concentration of the specific species" in this expression is the average concentration. In the above example, if it can be said that "the concentration of the specific species in the first specific layer is higher than the concentration of the specific species in the second specific layer" based on at least one of the first definition and the second definition, it will be treated as "the concentration of the specific species in the first specific layer is higher than the concentration of the specific species in the second specific layer". In this expression, the type of the specific species in the first specific layer and the type of the specific species in the second specific layer may be the same or different. For example, the specific species in the first specific layer may be carbon, and the specific species in the second specific layer may be nitrogen and fluorine.

[0312] When a specific species is composed of multiple types of impurities, the concentration of the specific species refers to the total concentration of the multiple types of impurities.

[0313] The concentration of carbon in the first specific layer may be higher than the concentration of carbon in the second specific layer. The concentration of nitrogen in the first specific layer may be higher than the concentration of nitrogen in the second specific layer. The concentration of fluorine in the first specific layer may be higher than the concentration of fluorine in the second specific layer. The concentration of germanium in the first specific layer may be higher than the concentration of germanium in the second specific layer. The concentration of silicon in the first specific layer may be higher than the concentration of silicon in the second specific layer. The concentration of argon in the first specific layer may be higher than the concentration of argon in the second specific layer.

[0314] In one example, the carbon concentration in the second specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22. As described above, "under the gate of the amplifying transistor 22" refers to a portion of the surface of the pixel substrate part on the gate 67c side that overlaps with the gate 67c of the amplifying transistor 22 in a planar view. In the expression "the carbon concentration in the second specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22", the carbon concentration under the gate of the amplifying transistor 22 may be zero or may be higher than zero.

[0315] In the first definition, the "carbon concentration" in the expression "the carbon concentration in the second specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22" is the maximum concentration. In the second definition, the "carbon concentration" in this expression is the average concentration. In the above example, if it can be said based on at least one of the first and second definitions that "the carbon concentration in the second specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22," this will be treated as "the carbon concentration in the second specific layer is higher than the carbon concentration under the gate of the amplifying transistor 22."

[0316] In one example, the second extension diffusion layer EX2 contains nitrogen.

[0317] In the illustrated example, the second extension diffusion layer 406a contains nitrogen, and the second extension diffusion layer 406b contains nitrogen.

[0318] The nitrogen in the second extension diffusion layer EX2 may be derived from ion implantation of nitrogen (N) ions, and may be derived from nitrogen molecules N 2 In the illustrated example, the nitrogen in the second extension diffusion layer 406a may be derived from the ion implantation of nitrogen (N) ions, and may be derived from the ion implantation of nitrogen molecules N 2 The nitrogen in the second extension diffusion layer 406b may be derived from the ion implantation of nitrogen (N) ions, and may be derived from the ion implantation of nitrogen molecules N 2 The carbon in the first extension diffusion layer EX1 and the first extension diffusion layers 306a and 306b may be derived from ion implantation.

[0319] Of course, transistors other than those shown in Figs. 18 to 20 may be provided. In the examples shown in Figs. 21 to 24, the first peripheral region R2 has the first peripheral transistor 27 and the first peripheral transistor 727. Between the first peripheral transistor 27 and the first peripheral transistor 727, an element isolation 222 is arranged. The second peripheral region R3 has the second peripheral transistor 427 and the second peripheral transistor 827. Between the second peripheral transistor 427 and the second peripheral transistor 827, an element isolation 222 is arranged. Note that in Fig. 24, the first peripheral transistor 27, the second peripheral transistor 427, and the amplifying transistor 22 are depicted in a simplified manner, and the element isolation 222 is omitted from illustration.

[0320] 21 to 24, the first peripheral transistor 727 has similarities to the first peripheral transistor 27. Specifically, the first peripheral transistor 727 is an MIS transistor, similar to the first peripheral transistor 27. Like the first peripheral transistor 27, the first peripheral transistor 727 includes a gate electrode 702, a source 713a, a drain 713b, extension diffusion layers 706a and 706b, pocket diffusion layers 707a and 707b, a channel diffusion layer 703, a gate insulating film 701, offset spacers 709a and 709b, first sidewalls 708Aa and 708Ab, and second sidewalls 708Ba and 708Bb.

[0321] However, the first peripheral transistor 27 and the first peripheral transistor 727 are transistors of opposite polarity. Specifically, the first peripheral transistor 27 is a P-channel transistor, while the first peripheral transistor 727 is an N-channel transistor. The P-type source-drain diffusion layer 313a, which is the source, is P-type, while the source 713a is N-type. The P-type source-drain diffusion layer 313b, which is the drain, is P-type, while the drain 713b is N-type. The first extension diffusion layer 306a is P-type, while the extension diffusion layer 706a is N-type. The first extension diffusion layer 306b is P-type, while the extension diffusion layer 706b is N-type. The first pocket diffusion layer 307a is N-type, while the pocket diffusion layer 707a is P-type. The first pocket diffusion layer 307b is N-type, while the pocket diffusion layer 707b is P-type. The channel diffusion layer 303 is of N-type, while the channel diffusion layer 703 is of P-type.

[0322] Hereinafter, the ordinal number "first" may be added to the components of the first peripheral transistor 727. For example, the source 713a may be referred to as the first source, and the drain 713b may be referred to as the first drain.

[0323] In the illustrated example, the element isolation 222 is an STI structure. The STI structure has a trench and a filling material filled in the trench. The filling material is, for example, an oxide. The depth of the trench is, for example, about 500 nm. The STI structure can be formed in the semiconductor substrate 130 by an STI process.

[0324] In the illustrated example, the first peripheral region R2 has two first peripheral transistors 27 and 727, and an isolation 222 having an STI structure. The isolation 222 having an STI structure isolates the two first peripheral transistors 27 and 727. The isolation 222 having an STI structure has a trench. The distribution range of the specific species in the first specific layer of at least one of the two first peripheral transistors 27 and 727 is shallower than the bottom of the trench. In this context, the "distribution range of the specific species" refers to a range in which the concentration of the specific species is 5×10 16 atoms / cm 3 The term "trench bottom" refers to the region where the concentration of the specific species is equal to or greater than the concentration of the specific species. The same applies to the distribution range of carbon, etc. The "bottom of the trench" refers to the deepest part of the trench in the depth direction of the first substrate portion. As described above, when the specific species is composed of multiple types of impurities, the concentration of the specific species refers to the total concentration of the multiple types of impurities.

[0325] The distribution range of carbon in the first specific layer of at least one of the two first peripheral transistors 27 and 727 may be shallower than the bottom of the trench. The distribution range of nitrogen in the first specific layer of at least one of the two first peripheral transistors 27 and 727 may be shallower than the bottom of the trench. The distribution range of fluorine in the first specific layer of at least one of the two first peripheral transistors 27 and 727 may be shallower than the bottom of the trench. The distribution range of germanium in the first specific layer of at least one of the two first peripheral transistors 27 and 727 may be shallower than the bottom of the trench. The distribution range of silicon in the first specific layer of at least one of the two first peripheral transistors 27 and 727 may be shallower than the bottom of the trench. The distribution range of argon in the first specific layer of at least one of the two first peripheral transistors 27 and 727 may be shallower than the bottom of the trench.

[0326] Specifically, the two first peripheral transistors 27 and 727 are transistors having opposite polarities. In a plan view, the element isolation 222, which is an STI structure, is disposed between the two first peripheral transistors 27 and 727, more specifically, on the line segment connecting them. The specific species contributes to suppression of impurity diffusion. As illustrated in FIG. 23, the STI structure may protrude upward from a portion of the first substrate portion surrounding it.

[0327] The element isolation 222 may be an implantation isolation region.

[0328] 21 to 24, the second peripheral transistor 827 has similarities to the second peripheral transistor 427. Specifically, the second peripheral transistor 827 is an MIS transistor, similar to the second peripheral transistor 427. Like the second peripheral transistor 427, the second peripheral transistor 827 includes a gate electrode 802, a source 813a, a drain 813b, extension diffusion layers 806a and 806b, pocket diffusion layers 807a and 807b, a channel diffusion layer 803, a gate insulating film 801, offset spacers 809a and 809b, first sidewalls 808Aa and 808Ab, and second sidewalls 808Ba and 808Bb.

[0329] However, the second peripheral transistor 427 and the second peripheral transistor 827 are transistors of opposite polarity. Specifically, the second peripheral transistor 427 is a P-channel transistor, while the second peripheral transistor 827 is an N-channel transistor. The second source 413a is P-type, while the source 813a is N-type. The second drain 413b is P-type, while the drain 813b is N-type. The second extension diffusion layer 406a is P-type, while the extension diffusion layer 806a is N-type. The second extension diffusion layer 406b is P-type, while the extension diffusion layer 806b is N-type. The second pocket diffusion layer 407a is N-type, while the pocket diffusion layer 807a is P-type. The second pocket diffusion layer 407b is N-type, while the pocket diffusion layer 807b is P-type. The channel diffusion layer 403 is of N-type, while the channel diffusion layer 803 is of P-type.

[0330] The ordinal number "second" may be added to the components of the second peripheral transistor 427. For example, the source 813a may be referred to as the second source, and the drain 813b may be referred to as the second drain.

[0331] Just to be clear, the second peripheral region R3 is not essential. Of course, the second peripheral transistors 427 and 827 are not essential. Also, in the first peripheral region R2, at least one of the first peripheral transistors 27 and 727 may be used for analog processing. In one specific example, in the first peripheral region R2, a first peripheral transistor is used for digital processing, and another first peripheral transistor is used for analog processing.

[0332] Unless otherwise contradictory, the description of the first peripheral transistor 27 and its elements can be used in the description of the first peripheral transistor 727 and its elements. Unless otherwise contradictory, the description of the second peripheral transistor 427 and its elements can be used in the description of the second peripheral transistor 827 and its elements. Unless otherwise contradictory, the description of the relationship between the first peripheral transistor 27, the second peripheral transistor 427, and the amplifier transistor 22 can be used in the description of the relationship between the first peripheral transistor 727, the second peripheral transistor 827, and the amplifier transistor 22.

[0333] For example, the gate length L of the first peripheral transistor 727 727 is the gate length L of the amplifying transistor 22 22 The gate length L of the first peripheral transistor 727 may be shorter than 727 is the gate length L of the second peripheral transistor 827 827 The gate length L of the second peripheral transistor 827 may be shorter than 827 is the gate length L of the amplifying transistor 22 22. The extension diffusion layer 706a may be shallower than the source 713a and the drain 713b. The extension diffusion layer 706b may be shallower than the source 713a and the drain 713b. The extension diffusion layer 806a may be shallower than the source 813a and the drain 813b. The extension diffusion layer 806b may be shallower than the source 813a and the drain 813b. The extension diffusion layer 706a may contain a conductive impurity and a specific species. The extension diffusion layer 706b may contain a conductive impurity and a specific species. The extension diffusion layer 806a may contain nitrogen. The nitrogen in the extension diffusion layer 806a may be derived from ion implantation of nitrogen (N) ions, or may be nitrogen molecules N 2 The extension diffusion layer 806b may include nitrogen. The nitrogen in the extension diffusion layer 806b may be derived from the ion implantation of nitrogen (N) ions, or may be derived from the ion implantation of nitrogen molecules N 2 It may also result from injection of

[0334] As can be understood from the above description, in the imaging device, at least one of the extension diffusion layer 806a and the extension diffusion layer 806b of the second peripheral transistor 827, which is an N-channel transistor, may contain nitrogen. This nitrogen affects not only the impurity distribution in the second substrate portion but also the interface characteristics of the gate insulating film of the second peripheral transistor 827, thereby improving the reliability of the imaging device. At least one of the extension diffusion layer 806a and the extension diffusion layer 806b containing nitrogen may be a so-called LDD diffusion layer.

[0335] In an example in which at least one of the extension diffusion layer 806a and the extension diffusion layer 806b of the second peripheral transistor 827, which is an N-channel transistor, contains nitrogen, the extension diffusion layer 706a of the second peripheral transistor 727, which is a P-channel transistor, may or may not contain nitrogen. In this example, the extension diffusion layer 706b of the second peripheral transistor 727, which is a P-channel transistor, may or may not contain nitrogen.

[0336] In a plan view, the amplification transistor 22, the second peripheral transistor 427, the second peripheral transistor 827, the first peripheral transistor 27, and the first peripheral transistor 727 are arranged in this order.

[0337] Unless otherwise stated, the matters described with reference to FIGS. 21 to 24 can also be applied to the examples of FIGS. 13 to 17.

[0338] In the above description, a front side illumination (FSI) type imaging device has been taken as an example, but the above description is also applicable to a back side illumination (BSI) type imaging device.

[0339] FIG. 25 is a schematic diagram of a back-illuminated imaging device 100C according to an example.

[0340] 25, the semiconductor substrate 130 has a front surface 130a and a back surface 130b. The back surface 130b is the surface on the side on which light is incident. The front surface 130a is the surface opposite to the side on which light is incident.

[0341] The photoelectric conversion unit 10, the color filter 84, and the on-chip lens 85 are laminated in this order on the back surface 130b. In a typical example, the photoelectric conversion unit 10 is attached to the polished back surface 130b, thereby bonding the semiconductor substrate 130 and the photoelectric conversion unit 10. The color filter 84 and the on-chip lens 85 may be omitted. In addition, an interlayer insulating film for the purpose of planarization, protection, etc. may be provided at least one between the photoelectric conversion unit 10 and the color filter 84 and between the color filter 84 and the on-chip lens 85.

[0342] A wiring section 86 is laminated on the surface 130a. In the wiring section 86, a plurality of wirings 87 are provided inside an insulator. The plurality of wirings 87 are used to electrically connect the amplifying transistor 22, the first peripheral transistor 27, and the second peripheral transistor 427 to their destinations. For example, the wirings 87 constitute a part of an electrical path 88 that electrically connects the pixel electrode 11 of the photoelectric conversion section 10 and the gate electrode 67c of the amplifying transistor 22. Specifically, in this example, the electrical path 88 includes a through-silicon electrode (Through-Silicon Via, TSV) provided in the semiconductor substrate 130. In FIG. 25, the through-silicon electrode is omitted. In FIG. 25, the dotted line representing the electrical path 88 is schematic and is not drawn with the intention of limiting the position of the electrical path 88. Note that a Cu-Cu connection may be adopted instead of the TSV connection.

[0343] 25, the transistor 22, the first peripheral transistor 27, and the second peripheral transistor 427 may have the characteristics described with reference to FIGS. 1 to 24. The same applies to other elements such as the photoelectric conversion unit 10. Specifically, in this example, the first peripheral transistor 27 and the second peripheral transistor 427 include a source, a drain, an extension diffusion layer, a pocket diffusion layer, etc. The semiconductor substrate 130 includes a support substrate 140.

[0344] FIG. 26 is a schematic diagram of a back-illuminated imaging device 100D according to another example.

[0345] The imaging device 100D shown in Fig. 26 includes elements of the imaging device 100C shown in Fig. 25. The imaging device 100D further includes a photodiode 80 and a transfer transistor 29. The photodiode 80 and the transfer transistor 29 are provided in a semiconductor substrate 130. Specifically, the pixel region R1 has the photodiode 80 provided in a pixel substrate portion. As described above, the pixel substrate portion refers to a portion of at least one semiconductor substrate 130 that is located in the pixel region R1.

[0346] The photodiode 80 corresponds to a photoelectric conversion section, similar to the photoelectric conversion section 10. The photodiode 80 generates a signal charge by photoelectric conversion. The transfer transistor 29 transfers this signal charge to a charge accumulation region (not shown).

[0347] 26, irradiation of light from the on-chip lens 85 and color filter 84 side to the photodiode 80 is not hindered by the wiring 87 of the wiring section 86. This allows efficient photoelectric conversion by the photodiode 80.

[0348] FIG. 27 is a schematic diagram of a back-illuminated imaging device 100E according to another example.

[0349] An imaging device 100E shown in Fig. 27 includes some of the elements of imaging device 100D shown in Fig. 26. However, imaging device 100E shown in Fig. 27 does not include photoelectric conversion unit 10.

[0350] 28 to 31 are schematic diagrams showing possible shapes of the pixel region R1, the first peripheral region R2, and the second peripheral region R3 of the imaging device 100E shown in FIG.

[0351] In the example of Fig. 28, the second peripheral region R3 surrounds the pixel region R1 in a planar view. In the example of Fig. 28, the first peripheral region R2 surrounds the second peripheral region R3 in a planar view. Specifically, in the example of Fig. 28, the second peripheral region R3 is shaped like a square outside the pixel region R1 in a planar view. In the example of Fig. 28, the first peripheral region R2 is shaped like a square outside the second peripheral region R3 in a planar view.

[0352] 29, the second peripheral region R3 is U-shaped outside the pixel region R1 in a plan view, and the first peripheral region R2 is U-shaped outside the second peripheral region R3 in a plan view.

[0353] 30, in a plan view, the second peripheral region R3 is outside the pixel region R1 and has an L-shape. In a plan view, the first peripheral region R2 is outside the second peripheral region R3 and has an L-shape.

[0354] 31, the second peripheral region R3 extends straight outside the pixel region R1 in a plan view, and the first peripheral region R2 extends straight outside the second peripheral region R3 in a plan view.

[0355] The shapes of the pixel region R1, the first peripheral region R2, and the second peripheral region R3 shown in Figures 28 to 31 are also applicable to the image pickup devices 100C and 100D shown in Figures 25 and 26. These shapes are also applicable to the image pickup devices 100A and 100B shown in Figures 1 to 24.

[0356] In the above description, an imaging device using a single semiconductor substrate has been taken as an example. However, the above description is also applicable to a so-called chip-stack imaging device in which multiple semiconductor substrates are stacked on top of each other. A chip-stack imaging device may also be called a chip-stack type imaging device.

[0357] FIG. 32 is a schematic diagram of an imaging device 100F of a chip stack according to an example.

[0358] In the imaging device 100F shown in Fig. 32, a first semiconductor substrate 130A and a second semiconductor substrate 130B are stacked on each other. The first semiconductor substrate 130A is provided with a pixel region R1 and a first peripheral region R2. The second semiconductor substrate 130B is provided with a peripheral circuit 120C. The peripheral circuit 120C may include a part or all of a circuit equivalent to the peripheral circuit 120A or the peripheral circuit 120B.

[0359] Although not shown, at least one of a TSV connection and a Cu-Cu connection can be used for electrical connection between elements provided on the first semiconductor substrate 130A and elements provided on the second semiconductor substrate 130B.

[0360] The pixel region R1 includes an amplifying transistor 22. The first peripheral region R2 includes a first peripheral transistor 27.

[0361] In one example, in the imaging device 100F, the first peripheral transistor 27 is a load transistor. The pixel region R1 is connected to the load transistor via a vertical signal line 35. Specifically, the amplification transistor 22 is connected to the load transistor via the vertical signal line 35.

[0362] In one specific example, the load transistor functions as a constant current source. A constant current determined by the load transistor flows through the amplifier transistor 22, the vertical signal line 35, and the load transistor in this order. The amplifier transistor 22 and the load transistor form a source follower. Therefore, a voltage corresponding to the gate voltage of the amplifier transistor 22, i.e., the voltage of the charge storage region Z, appears on the vertical signal line 35. This state continues while the address transistor 24 is on. The load transistor can be included in a load circuit 45 shown in FIG. 2.

[0363] In the imaging device 100F, the first peripheral transistor 27 may be included in at least one of the comparator and the driver.

[0364] In the example of Fig. 32, the first peripheral transistor 27 may or may not be included in the peripheral circuit 120C. In the example of Fig. 32, a second peripheral region R3 may be provided outside the first peripheral region R2.

[0365] Also in the examples of Figures 25 to 32, the specific species of the first specific layer contributes to suppressing diffusion, thereby making it possible to suppress dark current in the pixel region R1 while suppressing performance degradation of the first peripheral transistor 27 caused by heat treatment.

[0366] 25 to 32, the pixel region R1, the first peripheral region R2, and the second peripheral region R3 may have the features described using FIGS. 1 to 24. For example, the pixel region R1 may include an address transistor 24, a reset transistor 26, etc. in addition to the amplification transistor 22. The first peripheral region R2 may include a first peripheral transistor 727 in addition to the first peripheral transistor 27. The second peripheral region R3 may include a second peripheral transistor 827 in addition to the second peripheral transistor 427.

[0367] Various modifications can be applied to the technology according to the present disclosure. For example, the pocket diffusion layer 707a and the pocket diffusion layer 707b of the first peripheral transistor 727 and the pocket diffusion layer 807a and the pocket diffusion layer 807b of the second peripheral transistor 827 can be omitted. Also, the blocking regions 200A and 200B can be omitted. Also, a silicide layer may be formed on the drain, source, and gate electrode of the first peripheral transistor 27.

[0368] In the first peripheral transistor, the specific species may be contained only in the pocket diffusion layer. When an N-channel MIS transistor is fabricated as such a first peripheral transistor, for example, the specific species is implanted only in the P-type pocket diffusion layer of the transistor. In this case, the concentration of the specific species implanted in the P-type pocket diffusion layer may be lower than the concentration of the specific species implanted in the extension diffusion layer when the first peripheral transistor of FIG. 5 is fabricated.

[0369] The features relating to the second peripheral region R3 may be applied to the first peripheral region R2. For example, the features of the second peripheral transistors 427 and 827 may be applied to the first peripheral transistors 27 and 727.

[0370] The features relating to the first peripheral region R2 may be applied to the second peripheral region R3. For example, the features of the first peripheral transistors 27 and 727 may be applied to the second peripheral transistors 427 and 827. [Industrial Applicability]

[0371] The imaging device of the present disclosure is useful for, for example, an image sensor, a digital camera, etc. The imaging device of the present disclosure can be used for, for example, a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc. [Explanation of symbols]

[0372] 10 Photoelectric conversion structure 11 Pixel electrode 12 Photoelectric conversion layer 13 Counter electrode 20 Readout circuit 22 Amplifying transistor 24 Address transistor 25, 27, 29, 427, 727, 827 transistors 26 Reset transistor 32 Power wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 38 Voltage Line 39 Reset voltage line 45 Load circuit 47 Column signal processing circuit 49 Horizontal common signal line 60n, 61n, 131, 131a impurity region 62 Impurity layer 62an, 62bn n-type semiconductor layer 63p p-type semiconductor layer 64, 64a, 64b p-type region 65p, 82p p-type impurity region 66p p-type semiconductor layer 67a, 313a, 413a, 713a, 813a Source 67b, 313b, 413b, 713b, 813b Drain 67c, 302, 402 Gate electrode 68, 303, 403 Channel diffusion layer 69, 301, 401 Gate insulating film 70, 309a, 309b, 409a, 409b, 709a, 709b, 809a, 809b Offset spacer 71a, 71b, 308Aa, 308Ab, 408Aa, 408Ab, 708Aa, 708Ab, 808Aa, 808Ab First sidewall 72a, 72b, 308Ba, 308Bb, 408Ba, 408Bb, 708Ba, 708Bb, 808Ba, 808Bb 2nd Sidewall 80 Photodiode 81n, 83n n-type impurity region 84 Color Filters 85 On-chip lens 86 Wiring section 87 Wiring 88 Electrical Path 89 Conductive structure 90 Interlayer insulation layer 100A, 100B, 100C, 100D, 100E, 100F Imaging device 110 pixels 120A, 120B, 120C peripheral circuits 122, 129 Vertical scanning circuit 124, 127 Horizontal signal readout circuit 126 Voltage supply circuit 128 Control Circuit 130, 130A, 130B Semiconductor substrate 130a surface 130b Back 131s Silicide layer 140 Support substrate 200A, 200B cutoff area 211, cp, cx contact plug cy plug 220, 221, 222 Element isolation 303A N-type channel impurity implantation layer 304A N-type well impurity implantation layer 306a, 306b, 406a, 406b, 706a, 706b, 806a, 806b P-type extension high concentration diffusion layer 306Aa, 306Ab First P-type impurity implanted layer 307a, 307b, 407a, 407b, 707a, 707b, 807a, 807b N-type pocket diffusion layer 307Aa, 307Ab N-type pocket impurity implanted layer 310a, 310b amorphous layer 311Aa, 311Ab Carbon implantation layer 313Aa, 313Ab Second P-type impurity implanted layer FD Charge storage node R1 pixel area R2, R3 surrounding area X1, X2 direction Z charge accumulation region

Claims

1. a pixel region including an impurity region in which a signal charge generated by photoelectric conversion is accumulated, and an amplifying transistor including a first gate and outputting a signal voltage according to an amount of the signal charge; a first peripheral region including a first peripheral transistor including a second gate, the first peripheral region being located outside the pixel region; a semiconductor substrate on which the amplifying transistor and the first peripheral transistor are provided; Equipped with a length of the second gate of the first peripheral transistor is shorter than a length of the first gate of the amplifying transistor; When at least one type of impurity that contributes to suppression of the transient enhanced diffusion of the conductive impurity is defined as a specific type, the first peripheral transistor includes a first specific layer located in the semiconductor substrate and containing a conductivity type impurity and the specific species; The ratio of the concentration of the specific species in the first specific layer to the concentration of the specific species in the impurity region is 1×10 5 That's all. The concentration of the specific species in the first specific layer is 5×10 atoms / cm 3 That's all. Imaging device.

2. the amplifying transistor includes a second gate insulating film located between the semiconductor substrate and the first gate; the first peripheral transistor includes a first gate insulating film located between the semiconductor substrate and the second gate; The first gate insulating film is thinner than the second gate insulating film. The imaging device according to claim 1 .

3. The specific species includes at least one selected from the group consisting of carbon, nitrogen, and fluorine.

3. The imaging device according to claim 1.

4. The specific species includes at least one selected from the group consisting of germanium, silicon, and argon. The imaging device according to claim 1 .

5. the first peripheral transistor includes a first source, a first drain, and a first extension diffusion layer; the first extension diffusion layer is adjacent to the first source or the first drain and is shallower than the first source and the first drain; The first extension diffusion layer includes the first specific layer. The imaging device according to claim 1 .

6. the first peripheral transistor includes a first source, a first drain, and a first pocket diffusion layer adjacent to the first source or the first drain; The first pocket diffusion layer includes the first specific layer. The imaging device according to claim 1 .

7. the first peripheral transistor includes an end-of-range defect; At least a portion of the first specific layer is located above the end-of-range defect and overlaps with the end-of-range defect in a plan view. The imaging device according to claim 1 .

8. the first peripheral transistor includes a segregation portion in which the specific species is segregated in a depth direction of the semiconductor substrate, At least a portion of the first specific layer is located above the segregation portion and overlaps with the segregation portion in a plan view. The imaging device according to claim 1 .

9. The segregation portion is shallower than the impurity region. The imaging device according to claim 8.

10. a second peripheral region located between the pixel region and the first peripheral region in a plan view, the second peripheral region includes a second peripheral transistor including a third gate and included in an analog processing circuit; the first peripheral transistor is included in a digital processing circuit; a length of the third gate of the second peripheral transistor is longer than a length of the second gate of the first peripheral transistor and shorter than a length of the first gate of the amplifying transistor; The imaging device according to claim 1 .

11. the second peripheral transistor includes a second specific layer located in the semiconductor substrate and containing a conductivity type impurity; The concentration of the specific species in the first specific layer is higher than the concentration of the specific species in the second specific layer. The imaging device according to claim 10.

12. the second peripheral transistor includes a second specific layer located in the semiconductor substrate and containing a conductivity type impurity; a carbon concentration in the second specific layer is higher than a carbon concentration under the first gate of the amplifying transistor; The imaging device according to claim 10 or 11.

13. the amplifying transistor includes a second gate insulating film located between the semiconductor substrate and the first gate; the first peripheral transistor includes a first gate insulating film located between the semiconductor substrate and the second gate; the second peripheral transistor includes a third gate insulating film located between the semiconductor substrate and the third gate; the third gate insulating film is thicker than the first gate insulating film and thinner than the second gate insulating film; The imaging device according to claim 10 .

14. an operating voltage of the first peripheral transistor is lower than an operating voltage of the second peripheral transistor; The imaging device according to claim 10 .

15. a threshold voltage of the first peripheral transistor is lower than a threshold voltage of the second peripheral transistor; The imaging device according to claim 10 .

16. the second peripheral transistor includes a second source, a second drain, and a second extension diffusion layer; the second extension diffusion layer is adjacent to the second source or the second drain and is shallower than the second source and the second drain; the second extension diffusion layer contains nitrogen; The imaging device according to claim 10 .

17. the second peripheral transistor includes a second specific layer located in the semiconductor substrate and containing a conductivity type impurity; The specific species in the first specific layer is different from the specific species in the second specific layer; The imaging device according to claim 10 .

18. the specific species is distributed over a continuous region including at least a part of the first extension diffusion layer and at least a part of the first source or the first drain; The imaging device according to claim 5 .

19. a pixel region including an impurity region in which a signal charge generated by photoelectric conversion is accumulated, and an amplifying transistor that outputs a signal voltage according to the amount of the signal charge; a first peripheral region including a first peripheral transistor and located outside the pixel region; a semiconductor substrate on which the amplifying transistor and the first peripheral transistor are provided; Equipped with When at least one type of impurity that contributes to suppression of the transient enhanced diffusion of the conductive impurity is defined as a specific type, the first peripheral transistor includes a first specific layer located in the semiconductor substrate and containing a conductivity type impurity and the specific species; The ratio of the concentration of the specific species in the first specific layer to the concentration of the specific species in the impurity region is 1×10 5 That's all. The concentration of the specific species in the first specific layer is 5×10 atoms / cm 3 That's all. Each of the amplifying transistor and the first peripheral transistor is a transistor including a gate. Imaging device.

20. the pixel region includes a plug including polysilicon, the plug being connected to the impurity region; The imaging device according to any one of claims 1 to 19.

Images