Imaging device

Abstract

An aspect of the present disclosure relates to an imaging device comprising a first electrode, a second electrode, a photoelectric conversion layer, a substrate, and a through-electrode. The photoelectric conversion layer is disposed between the first electrode and the second electrode and converts light into charge. The substrate includes a through-hole and a first transistor comprising a first impurity region functioning as one of a source and a drain, a second impurity region functioning as the other of the source and the drain, and a first gate electrode. The first impurity region includes a charge storage region for storing the charge. The through-electrode is provided in the through-hole and electrically connects the first electrode and the charge storage region. In plan view, the distance between the charge storage region and the through-electrode is greater than the distance between the second impurity region and the through-electrode.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] 2. Description of the Related Art Charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors are widely used in digital cameras etc. These image sensors have photodiodes formed on a semiconductor substrate.

[0003] Patent Documents 1 and 2 propose a structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate. An imaging device having such a structure is sometimes called a stacked imaging device. In a stacked imaging device, charges generated by photoelectric conversion are accumulated in a charge accumulation region. A signal corresponding to the amount of charge accumulated in the charge accumulation region is read out via a CCD circuit or a CMOS circuit formed on the semiconductor substrate.

[0004] Patent Document 3 proposes a back-illuminated imaging device. In the imaging device of Patent Document 3, a photodiode is formed in a semiconductor substrate. Also, in the imaging device of Patent Document 3, a photoelectric conversion unit having a photoelectric conversion layer is provided on the light receiving surface side, which is the back side of the semiconductor substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2014 / 002330 [Patent Document 2] International Publication No. 2012 / 147302 [Patent Document 3] International Publication No. 2015 / 025723 Summary of the Invention [Problem to be solved by the invention]

[0006] The present disclosure provides techniques suitable for suppressing leakage current to a charge storage region. [Means for solving the problem]

[0007] The present disclosure relates to A first electrode; A second electrode; a photoelectric conversion layer located between the first electrode and the second electrode and configured to convert light into electric charges; a substrate including a through hole, a first impurity region functioning as one of a source and a drain, a second impurity region functioning as the other of the source and the drain, and a first transistor including a first gate electrode, the first impurity region including a charge accumulation region that accumulates the charge; a through electrode provided in the through hole and electrically connecting the first electrode and the charge storage region; Equipped with In a plan view, a distance between the charge storage region and the through electrode is longer than a distance between the second impurity region and the through electrode. An imaging device is provided. Effect of the Invention

[0008] The technology according to the present disclosure is suitable for suppressing leakage current to a charge storage region. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing an exemplary circuit configuration of the imaging device according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is a schematic plan view showing an exemplary configuration of a pixel according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an exemplary configuration of a pixel according to the first embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing an example of an electric path around a through electrode, a charge storage region, and a gate electrode. [Figure 6] FIG. 6 is a diagram showing an example of an electrical path around a through electrode, a charge storage region, and a gate electrode. [Figure 7] FIG. 7 is a diagram showing an example of an electric path around a through electrode, a charge storage region, and a gate electrode. [Figure 8] FIG. 8 is a diagram showing an example of an electric path around a through electrode, a charge storage region, and a gate electrode. [Figure 9] FIG. 9 is a diagram showing an example of a configuration in which a through electrode and an electrode structure are directly connected to each other. [Figure 10] FIG. 10 is a diagram illustrating an exemplary circuit configuration of an imaging device according to the second embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic plan view showing an exemplary configuration of a pixel according to the second embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic cross-sectional view illustrating an exemplary configuration of a pixel according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram illustrating an exemplary circuit configuration of an imaging device according to the third embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic plan view showing an exemplary configuration of a pixel according to the third embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic cross-sectional view illustrating an exemplary configuration of a pixel according to the third embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram illustrating an exemplary circuit configuration of an imaging device according to the fourth embodiment of the present disclosure. [Figure 17] FIG. 17 is a schematic plan view showing an exemplary configuration of a pixel according to the fourth embodiment of the present disclosure. [Figure 18] FIG. 18 is a schematic cross-sectional view showing an exemplary configuration of a pixel according to the fourth embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram illustrating an exemplary circuit configuration of an imaging device according to the fifth embodiment of the present disclosure. [Figure 20] FIG. 20 is a schematic plan view showing an exemplary configuration of a pixel according to the fifth embodiment of the present disclosure. [Figure 21] FIG. 21 is a schematic cross-sectional view illustrating an exemplary configuration of a pixel according to the fifth embodiment of the present disclosure. [Figure 22] FIG. 22 is a diagram showing an exemplary configuration of a photoelectric conversion stack. [Figure 23] FIG. 23 is a diagram showing an exemplary configuration of a photoelectric conversion stack. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Findings on which this disclosure is based) In stacked imagers, leakage currents into the charge storage regions can occur, which can degrade the resulting images.

[0011] The present disclosure provides techniques suitable for suppressing leakage current to a charge storage region.

[0012] (Summary of one aspect of the present disclosure) An imaging device according to a first aspect of the present disclosure, A first electrode; A second electrode; a photoelectric conversion layer located between the first electrode and the second electrode and configured to convert light into electric charges; a substrate including a through hole, a first impurity region functioning as one of a source and a drain, a second impurity region functioning as the other of the source and the drain, and a first gate electrode, the first impurity region including a charge accumulation region that accumulates the charge; a through electrode provided in the through hole and electrically connecting the first electrode and the charge storage region; In a plan view, the distance between the charge storage region and the through electrode is longer than the distance between the second impurity region and the through electrode.

[0013] The technique according to the first aspect is suitable for suppressing leakage current to a charge storage region.

[0014] In a second aspect of the present disclosure, for example, in the imaging device according to the first aspect, In a plan view, the first gate electrode may be located between the through electrode and the charge storage region.

[0015] The technique according to the second aspect is suitable for suppressing leakage current to the charge storage region.

[0016] In a third aspect of the present disclosure, for example, the imaging device according to the first or second aspect includes: A second transistor may further include a second gate electrode electrically connected to the charge storage region, In a plan view, a distance between the charge storage region and the through electrode may be longer than a distance between the second gate electrode and the through electrode.

[0017] The technique according to the third aspect is suitable for suppressing noise from being introduced into the electrical path between the second gate electrode of the second transistor and the through electrode while suppressing leakage current to the charge storage region.

[0018] In a fourth aspect of the present disclosure, for example, in the imaging device according to any one of the first to third aspects, In a plan view, an area of ​​the charge storage region may be smaller than an area of ​​the second impurity region.

[0019] The technique according to the fourth aspect is suitable for suppressing leakage current to a charge storage region.

[0020] In a fifth aspect of the present disclosure, for example, the imaging device according to any one of the first to fourth aspects comprises: The semiconductor device may further include a first electrical path electrically connecting the through electrode and the charge storage region, In a plan view, at least a portion of the first electrical path may be curved.

[0021] According to the fifth aspect, it is possible to increase the degree of freedom in the layout of the electrical paths.

[0022] In a sixth aspect of the present disclosure, for example, the imaging device according to the fifth aspect is The semiconductor device may further include a gate wiring electrically connected to the first gate electrode, When a combination of the first gate electrode and the gate wiring is defined as a second electrical path, the first electrical path may bypass the second electrical path in a plan view.

[0023] According to the sixth aspect, the coupling between the first electrical path and the second electrical path can be suppressed.

[0024] In a seventh aspect of the present disclosure, for example, an imaging device according to any one of the first to fourth aspects, a first electrical path electrically connecting the through electrode and the charge storage region; A gate wiring connected to the first gate electrode may be further included, When a combination of the first gate electrode and the gate wiring is defined as a second electrical path, at least a portion of the first electrical path and at least a portion of the second electrical path may overlap in a plan view.

[0025] According to the seventh aspect, coupling between the first electrical path and the second electrical path can be generated.

[0026] In an eighth aspect of the present disclosure, for example, in the imaging device according to any one of the first to seventh aspects, In a plan view, at least a portion of the first electrode and at least a portion of the charge storage region may overlap.

[0027] According to the eighth aspect, the first electrode can suppress light irradiation onto the charge accumulation region.

[0028] In a ninth aspect of the present disclosure, for example, in the imaging device according to any one of the first to eighth aspects, The first transistor may be a reset transistor that resets the potential of the charge storage region.

[0029] The reset transistor of the ninth embodiment is a specific example of the first transistor.

[0030] An imaging device according to a tenth aspect of the present disclosure, An imaging device having a plurality of pixels, Each of the plurality of pixels is A first electrode; A second electrode; a photoelectric conversion layer located between the first electrode and the second electrode and configured to convert light into electric charges; a substrate including a through hole and a first transistor, one of a source and a drain of the first transistor including a charge storage region that stores the charge; a through electrode provided in the through hole and electrically connecting the first electrode and the charge storage region; In each of the plurality of pixels, a distance between the charge storage region and the through electrode is longer than a distance between the other of the source and the drain of the first transistor and the through electrode in a plan view.

[0031] According to the tenth aspect, the effect of the first aspect can be obtained for a plurality of pixels.

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to these embodiments.

[0033] In this specification, terms such as "upper," "lower," "top," and "bottom" are used merely to specify the relative arrangement of components, and are not intended to limit the position of the imaging device when in use.

[0034] The generic or specific aspects may be realized as an element, a device, a module, a system, or a method. Also, the generic or specific aspects may be realized as any combination of an element, a device, a module, a system, and a method.

[0035] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings, in which the benefits and advantages are provided individually by the various embodiments or features disclosed, and not all are required to obtain one or more of them.

[0036] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as there is no contradiction. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. In the following description, components having substantially the same functions are indicated by common reference symbols and may be omitted from description. In addition, in order to avoid excessive complexity of the drawings, illustration of some elements may be omitted.

[0037] (First embodiment) Fig. 1 shows an exemplary configuration of an image pickup device according to a first embodiment of the present disclosure. The image pickup device 100 shown in Fig. 1 has a plurality of pixels 10 and peripheral circuits formed on a semiconductor substrate 1.

[0038] Each pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges, typically hole-electron pairs, upon receiving incident light. The photoelectric conversion unit 12 may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 1. Note that in FIG. 1, the photoelectric conversion units 12 of each pixel 10 are shown spatially separated from one another, but this is merely for convenience of explanation, and the photoelectric conversion units 12 of a plurality of pixels 10 may be continuously disposed on the semiconductor substrate 1 without any gaps between them.

[0039] In the example shown in Fig. 1, pixels 10 are arranged in a plurality of rows and columns of m rows and n columns. Here, m and n independently represent integers of 1 or more. The pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 1 to form an imaging region R1. When each pixel 10 has a photoelectric conversion structure as a photoelectric conversion unit 12, for example, above the semiconductor substrate 1, the imaging region R1 can be defined as a region of the semiconductor substrate 1 that is covered by the photoelectric conversion structure.

[0040] The number and arrangement of the pixels 10 are not limited to the illustrated example. For example, the number of pixels 10 included in the imaging device 100 may be one. In this example, the center of each pixel 10 is located on a lattice point of a square lattice, but for example, a plurality of pixels 10 may be arranged so that the center of each pixel 10 is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. For example, by arranging the pixels 10 one-dimensionally, the imaging device 100 can be used as a line sensor.

[0041] In the configuration illustrated in Fig. 1, the peripheral circuit includes a vertical scanning circuit 52 and a horizontal signal readout circuit 54. As illustrated in Fig. 1, the peripheral circuit may additionally include a control circuit 56 and a voltage supply circuit 58. The peripheral circuit may further include a signal processing circuit, an output circuit, and the like. In the example illustrated in Fig. 1, each circuit included in the peripheral circuit is provided on a semiconductor substrate 1. However, a part of the peripheral circuit may be disposed on a substrate other than the semiconductor substrate 1 on which the pixels 10 are formed.

[0042] The vertical scanning circuit 52 is also called a row scanning circuit, and is connected to address signal lines 44 provided corresponding to each row of the plurality of pixels 10. As will be described later, the signal lines provided corresponding to each row of the plurality of pixels 10 are not limited to the address signal lines 44, and a plurality of types of signal lines may be connected to the vertical scanning circuit 52 for each row of the plurality of pixels 10. The horizontal signal readout circuit 54 is also called a column scanning circuit, and is connected to vertical signal lines 45 provided corresponding to each column of the plurality of pixels 10.

[0043] The control circuit 56 receives command data, a clock, and the like provided from, for example, the outside of the imaging device 100, and controls the entire imaging device 100. Typically, the control circuit 56 has a timing generator and supplies drive signals to the vertical scanning circuit 52, the horizontal signal read circuit 54, the voltage supply circuit 58, and the like. In FIG. 1, the arrows extending from the control circuit 56 represent the flow of output signals from the control circuit 56. The control circuit 56 can be realized by, for example, a microcontroller including one or more processors. The functions of the control circuit 56 may be realized by a combination of a general-purpose processing circuit and software, or may be realized by hardware specialized for such processing.

[0044] The voltage supply circuit 58 supplies a predetermined voltage to each pixel 10 via the voltage line 48. The voltage supply circuit 58 is not limited to a specific power supply circuit, and may be a circuit that converts a voltage supplied from a power source such as a battery into a predetermined voltage, or may be a circuit that generates a predetermined voltage. The voltage supply circuit 58 may be a part of the above-mentioned vertical scanning circuit 52. As shown typically in FIG. 1, these circuits constituting the peripheral circuit are arranged in a peripheral region R2 outside an imaging region R1.

[0045] FIG. 2 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to a first embodiment of the present disclosure. In FIG. 2, in order to avoid complicating the drawing, four pixels 10A arranged in two rows and two columns are shown as representatives. Each of these pixels 10A is an example of the pixel 10 shown in FIG. 1, and includes a signal detection circuit 60 electrically connected to a photoelectric conversion unit 12 that is a photoelectric conversion structure. As will be described in detail later with reference to the drawings, the photoelectric conversion structure includes a photoelectric conversion layer disposed above a semiconductor substrate 1. That is, here, a stacked type imaging device is exemplified as the imaging device 100. Also, here, a back-illuminated type imaging device is exemplified as the imaging device 100.

[0046] The vertical scanning circuit 52 is connected to the counter electrode power supply line 21. In this embodiment, the counter electrode power supply line 21 may also be referred to as an accumulation control line.

[0047] The photoelectric conversion unit 12, which is a photoelectric conversion structure of each pixel 10A, is connected to a counter electrode power line 21. When the imaging device 100 is in operation, a predetermined voltage is applied to the counter electrode power line 21. For example, if the positive charge of the positive and negative charges generated by photoelectric conversion is used as a signal charge, a positive voltage of, for example, about 10 V can be applied to the counter electrode power line 21 when the imaging device 100 is in operation. In this embodiment, a case where holes are used as the signal charge will be illustrated.

[0048] 2, one counter electrode power line 21 is connected to a plurality of pixels 10A belonging to one row. However, one counter electrode power line 21 may be connected to a plurality of pixels 10A belonging to a plurality of rows. Also, one counter electrode power line 21 may be connected to all the pixels 10A in the imaging device 100.

[0049] 2, the signal detection circuit 60 includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. The signal detection transistor 22 may also be referred to as an amplification transistor.

[0050] The signal detection transistor 22, the address transistor 24, and the reset transistor 26 are typically field effect transistors formed on a semiconductor substrate 1 supporting a photoelectric conversion unit 12, which is a photoelectric conversion structure. In the following, unless otherwise specified, an example will be described in which an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as a transistor.

[0051] As shown in FIG. 2, the gate electrode 22e of the signal detection transistor 22 is electrically connected to the charge accumulation region FD and the photoelectric conversion unit 12. By applying a predetermined voltage to the counter electrode power line 21 during operation, for example, holes can be accumulated as signal charges in the charge accumulation region FD. In the configuration illustrated in FIG. 2, the charge accumulation region FD is an impurity region formed in the semiconductor substrate 1. In the illustrated example, the charge accumulation region FD has a function of temporarily holding charges generated by the photoelectric conversion unit 12. The charge accumulation region FD may also be referred to as a floating diffusion.

[0052] The drain of the signal detection transistor 22 is connected to a power supply wiring 42 that supplies a power supply voltage VDD of, for example, about 3.3 V to each pixel 10A when the imaging device 100 is in operation, and the source is connected to a vertical signal line 45 via an address transistor 24. By receiving the power supply voltage VDD at its drain, the signal detection transistor 22 outputs a signal voltage according to the amount of signal charge accumulated in the charge accumulation region FD.

[0053] An address signal line 44 is connected to the gate electrode 24e of the address transistor 24 connected between the signal detection transistor 22 and the vertical signal line 45. Therefore, the vertical scanning circuit 52 can read out the output of the signal detection transistor 22 of the selected pixel 10A to the corresponding vertical signal line 45 by applying a row selection signal that controls the on and off of the address transistor 24 to the address signal line 44. The arrangement of the address transistor 24 is not limited to the example shown in FIG. 2, and may be between the drain of the signal detection transistor 22 and the power supply line 42.

[0054] A reset signal line 47 connected to a vertical scanning circuit 52 is connected to the gate electrode 26e of the reset transistor 26. The reset signal line 47 is provided for each row of the pixels 10A, similar to the address signal line 44. The vertical scanning circuit 52 can turn on the reset transistor 26 by applying a reset signal that controls the on / off of the reset transistor 26 to the gate electrode 26e of the reset transistor 26 via the reset signal line 47. When the reset transistor 26 is turned on, the potential of the charge storage region FD is reset.

[0055] (Device structure of pixel 10A) Fig. 3 shows an example of the layout of each element in pixel 10A. Fig. 4 shows a schematic diagram of an example of the device structure of pixel 10A. Fig. 3 shows a schematic diagram of the arrangement of each element formed on semiconductor substrate 1 when pixel 10A shown in Fig. 4 is viewed along the normal direction of semiconductor substrate 1. If pixel 10A is cut along dashed line IV-IV in Fig. 3 and developed, the cross section shown in Fig. 4 is obtained.

[0056] Hereinafter, the term "first conductivity type" may be used. In this embodiment, the first conductivity type is n-type. The second conductivity type is p-type. However, the first conductivity type may be p-type. The second conductivity type may be n-type.

[0057] 3 and 4, the pixel 10A includes an insulating layer 71, an insulating layer 70, a semiconductor substrate 1, a photoelectric conversion unit 12, an insulating layer 31, and a microlens 30. The insulating layer 71, the insulating layer 70, the semiconductor substrate 1, the photoelectric conversion unit 12, the insulating layer 31, and the microlens 30 are stacked in this order. Specifically, these are stacked in the thickness direction of the semiconductor substrate 1. The pixel 10A also includes a through electrode 81, a dielectric layer 32, and a fixed charge layer 33.

[0058] The semiconductor substrate 1 is, for example, a silicon substrate. The semiconductor substrate 1 has a first main surface 1A and a second main surface 1B. The first main surface 1A is a surface on the side on which light is incident. The second main surface 1B is a surface on the opposite side to the side on which light is incident. In this embodiment, the first main surface 1A and the second main surface 1B are perpendicular to the thickness direction of the semiconductor substrate 1.

[0059] 4, the semiconductor substrate 1 includes an impurity region 1i. The impurity region 1i can be, for example, a p+ region or an n+ region. "+" indicates that the concentration of p-type or n-type impurities is high. The impurity region 1i has a first main surface 1A.

[0060] A reset transistor 26, a signal detection transistor 22, and an address transistor 24 are provided on the semiconductor substrate 1. Specifically, the reset transistor 26, the signal detection transistor 22, and the address transistor 24 are provided on the second main surface 1B.

[0061] In this embodiment, the reset transistor 26, the signal detection transistor 22, and the address transistor 24 are MOSFETs. Specifically, the reset transistor 26, the signal detection transistor 22, and the address transistor 24 are N-channel MOSFETs.

[0062] The reset transistor 26 includes a first diffusion region 67n, which is an example of a first impurity region, as one of the source and drain. The reset transistor 26 includes a second diffusion region 68an, which is an example of a second impurity region, as the other of the source and drain. The reset transistor 26 also includes a gate electrode 26e and an insulating layer 70. The insulating layer 70 is interposed between the gate electrode 26e and the semiconductor substrate 1. The reset transistor 26 is an example of a first transistor.

[0063] The signal detection transistor 22 includes a third diffusion region 68bn as one of a source and a drain. The signal detection transistor 22 includes a fourth diffusion region 68cn as the other of a source and a drain. The signal detection transistor 22 also includes a gate electrode 22e and an insulating layer 70. The insulating layer 70 is interposed between the gate electrode 22e and the semiconductor substrate 1. The signal detection transistor 22 is an example of a second transistor.

[0064] The address transistor 24 includes a fourth diffusion region 68cn as one of a source and a drain. The address transistor 24 includes a fifth diffusion region 68dn as the other of a source and a drain. The address transistor 24 also includes a gate electrode 24e and an insulating layer 70. The insulating layer 70 is interposed between the gate electrode 24e and the semiconductor substrate 1.

[0065] The first diffusion region 67n, the second diffusion region 68an, the third diffusion region 68bn, the fourth diffusion region 68cn, and the fifth diffusion region 68dn are located in the semiconductor substrate 1. The first diffusion region 67n, the second diffusion region 68an, the third diffusion region 68bn, the fourth diffusion region 68cn, and the fifth diffusion region 68dn contain impurities of the first conductivity type.

[0066] The first diffusion region 67n corresponds to the charge accumulation region FD. The first diffusion region 67n accumulates the photoelectric charges converted by the photoelectric conversion unit 12. The fourth diffusion region 68cn is shared by the signal detection transistor 22 and the address transistor .

[0067] In this embodiment, the first diffusion region 67n is the drain of the reset transistor 26. The second diffusion region 68an is the source of the reset transistor 26. The third diffusion region 68bn is the drain of the signal detection transistor 22. The fourth diffusion region 68cn is the source of the signal detection transistor 22 and the drain of the address transistor 24. The fifth diffusion region 68dn is the source of the address transistor 24.

[0068] The photoelectric conversion unit 12 has a pixel electrode 13, a photoelectric conversion layer 14, and a counter electrode 15. The counter electrode 15 faces the pixel electrode 13. The photoelectric conversion layer 14 is disposed between the pixel electrode 13 and the counter electrode 15.

[0069] The photoelectric conversion layer 14 has a film shape. The photoelectric conversion layer 14 includes at least one selected from the group consisting of organic materials and inorganic materials. An example of the inorganic material is amorphous silicon. The photoelectric conversion layer 14 receives light incident through the counter electrode 15 and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 14 is typically formed across a plurality of pixels 10A. The photoelectric conversion layer 14 may include a layer composed of an organic material and a layer composed of an inorganic material.

[0070] The counter electrode 15 is a transparent electrode. Specifically, the counter electrode 15 contains a transparent conductive material such as ITO (Indium Tin Oxide). The counter electrode 15 is disposed on the light receiving surface side of the photoelectric conversion layer 14. The counter electrode 15 is typically formed across a plurality of pixels 10A, similar to the photoelectric conversion layer 14.

[0071] Although not shown in FIG. 4, the counter electrode 15 is connected to the counter electrode power line 21. During operation of the imaging device 100, the potential of the counter electrode power line 21 is controlled to make the potential of the counter electrode 15 different from the potential of the pixel electrode 13, so that the signal charge generated by photoelectric conversion can be collected by the pixel electrode 13. For example, the potential of the counter electrode power line 21 is controlled so that the potential of the counter electrode 15 is higher than the potential of the pixel electrode 13. Specifically, for example, a positive voltage of about 10V is applied to the counter electrode power line 21. This allows the pixel electrode 13 to collect the holes of the hole-electron pairs generated in the photoelectric conversion layer 14. The signal charge collected by the pixel electrode 13 is accumulated in the first diffusion region 67n via the through electrode 81 and the wiring structure 80.

[0072] The pixel electrode 13 includes at least one selected from the group consisting of, for example, metal, metal nitride, and polysilicon. Examples of metals include titanium and tantalum. Examples of metal nitrides include titanium nitride and tantalum nitride. Examples of polysilicon include polysilicon doped with impurities to provide electrical conductivity. The pixel electrode 13 is spatially separated from the pixel electrodes 13 of other adjacent pixels 10A, and is thus electrically separated from the pixel electrodes 13 of other pixels 10A.

[0073] The microlens 30 has a light collecting effect. The light incident on the microlens 30 is supplied to the photoelectric conversion unit 12. The photoelectric conversion unit 12 converts the light thus supplied into an electric charge.

[0074] The insulating layer 31 is provided between the microlens 30 and the photoelectric conversion unit 12. The insulating layer 31 functions as a protective layer that protects the photoelectric conversion unit 12. The insulating layer 31 has the shape of a film.

[0075] A wiring structure 80 is provided in the insulating layer 71. In the example shown in Fig. 4, the wiring structure 80 includes a first wiring layer 80a, a second wiring layer 80b, and a third wiring layer 80c.

[0076] The first wiring layer 80a, the second wiring layer 80b, and the third wiring layer 80c typically contain at least one selected from the group consisting of metals and metal compounds. Examples of metals include copper and tungsten. Examples of metal compounds include metal nitrides and metal oxides.

[0077] A first contact plug cp1, a second contact plug cp2, a third contact plug cp3, and a fourth contact plug cp4 are provided in the insulating layer 71. Furthermore, a gate electrode 26e, a gate electrode 22e, and a gate electrode 24e are provided in the insulating layer 71.

[0078] Typically, the first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 contain a semiconductor material. In this embodiment, the first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 are polysilicon layers doped with impurities of a first conductivity type. However, the semiconductor material contained in the first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 may be polycrystalline silicon, germanium, or the like. The first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 may contain a metal together with or instead of the semiconductor material.

[0079] When the first contact plug cp1 contains a semiconductor material, an alloying reaction is unlikely to occur at the contact interface between the charge storage region FD and the first contact plug cp1, which can reduce crystal defects that may occur at the contact portion between the charge storage region FD and the first contact plug cp1, thereby reducing noise.

[0080] In this embodiment, the conductivity type of the charge storage region FD is the same as the conductivity type of the semiconductor material contained in the first contact plug cp1. In this way, a potential difference between the charge storage region FD and the first contact plug cp1 is unlikely to occur. Therefore, the contact resistance between the charge storage region FD and the first contact plug cp1 can be reduced.

[0081] The semiconductor substrate 1 is provided with a through hole 82. Specifically, openings are provided in the first main surface 1A and the second main surface 1B of the semiconductor substrate 1, and the through hole 82 connects these openings. Specifically, the through hole 82 extends along the thickness direction of the semiconductor substrate 1.

[0082] A through electrode 81 is provided in the through hole 82. The through electrode 81 can electrically connect elements electrically separated by the semiconductor substrate 1 in the thickness direction of the semiconductor substrate 1 to each other.

[0083] The through electrode 81 typically contains at least one selected from the group consisting of metals and metal compounds. Examples of metals include copper and tungsten. Examples of metal compounds include metal nitrides and metal oxides. However, the through electrode 81 may contain the same semiconductor material as the material contained in the semiconductor substrate 1, and may be doped with a first conductivity type or a second conductivity type impurity. Examples of semiconductor materials that the semiconductor substrate 1 and the through electrode 81 may contain include silicon, polycrystalline silicon, germanium, etc.

[0084] In one specific example, the pixel electrode 13 contains at least one of titanium nitride and tantalum nitride, and the through electrode 81 contains copper. In this specific example, copper originating from the through electrode 81 is unlikely to diffuse into the pixel electrode 13.

[0085] The pixel electrode 13, the through electrode 81, the second contact plug cp2, the first wiring layer 80a, the first contact plug cp1, and the charge storage region FD are electrically connected in this order. Therefore, the signal charge can be sent from the pixel electrode 13 to the charge storage region FD through the through electrode 81, the second contact plug cp2, the first wiring layer 80a, and the first contact plug cp1 in this order. In this embodiment, the positive hole as the signal charge can be sent from the pixel electrode 13 to the charge storage region FD through the through electrode 81, the second contact plug cp2, the first wiring layer 80a, and the first contact plug cp1 in this order.

[0086] The charge storage region FD, the first contact plug cp1, the first wiring layer 80a, the third contact plug cp3, and the gate electrode 22e of the signal detection transistor 22 are electrically connected in this order. Therefore, the signal charge can be sent from the charge storage region FD to the gate electrode 22e through the first contact plug cp1, the first wiring layer 80a, and the third contact plug cp3 in this order.

[0087] The second diffusion region 68an and the fourth contact plug cp4 are electrically connected to each other. Therefore, charges can flow between the second diffusion region 68an and the fourth contact plug cp4. Note that the wiring connected to the fourth contact plug cp4 is not shown in the figure.

[0088] The dielectric layer 32 has insulating properties. The dielectric layer 32 includes a first flat film portion 32A and a first tubular portion 32B. The first flat film portion 32A is provided between the first main surface 1A and the pixel electrode 13. The first tubular portion 32B is provided so as to surround the through electrode 81.

[0089] The dielectric layer 32 includes at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, for example. The dielectric layer 32 may include TEOS.

[0090] The fixed charge layer 33 has a fixed charge. The fixed charge layer 33 includes a second flat membrane portion 33A and a second cylindrical portion 33B. The second flat membrane portion 33A is provided between the first main surface 1A and the first flat membrane portion 32A. The second cylindrical portion 33B is provided so as to surround the first cylindrical portion 32B.

[0091] The fixed charge layer 33 may have a positive fixed charge or a negative fixed charge. Examples of materials for layers having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride, hafnium oxynitride, and aluminum oxynitride. The fixed charge layer 33 may be a laminate having two or more types of layers.

[0092] As can be understood from the above description, in this embodiment, the imaging device 100 includes a pixel 10A. The pixel 10A includes a pixel electrode 13 as a first electrode, a counter electrode 15 as a second electrode, a photoelectric conversion layer 14, a semiconductor substrate 1 as a substrate, and a through electrode 81. The photoelectric conversion layer 14 is located between the first electrode 13 and the second electrode 15. The photoelectric conversion layer 14 converts light into electric charges. The semiconductor substrate 1 includes a through hole 82 and a reset transistor 26 as a first transistor. The first diffusion region 67n, which is one of the source and drain of the reset transistor 26, includes a charge accumulation region FD that accumulates electric charges. The through electrode 81 is provided in the through hole 82. The through electrode 81 electrically connects the pixel electrode 13 and the charge accumulation region FD.

[0093] The expression "the through electrode 81 is provided in the through hole 82" will be explained. This expression is a concept including a form in which the through electrode 81 extends in the through hole 82 over a range shorter than the through hole 82 in the extending direction of the through hole 82. This expression is a concept including a form in which the extending range of the through electrode 81 is the same as the extending range of the through hole 82 in the extending direction of the through hole 82. This expression is a concept including a form in which the through electrode 81 extends beyond the through hole 82 in the extending direction of the through hole 82. In this embodiment, it can also be said that "the through electrode 81 extends in a region including at least a part of the through hole 82."

[0094] The expression "the through electrode 81 electrically connects the pixel electrode 13 and the charge accumulation region FD" will be explained. This expression is a concept that includes a form in which the pixel electrode 13 and the charge accumulation region FD are electrically connected only by the through electrode 81. This expression is a concept that includes a form in which the pixel electrode 13 and the charge accumulation region FD are electrically connected by the through electrode 81 and one or more other members. The same applies to other similar expressions.

[0095] In this embodiment, the substrate corresponds to the semiconductor substrate 1. The first electrode corresponds to the pixel electrode 13. The second electrode corresponds to the counter electrode 15. The first transistor corresponds to the reset transistor 26. The reset transistor 26 resets the potential of the charge storage region FD.

[0096] 3, in a plan view, the distance L1 between the charge storage region FD and the through electrode 81 is longer than the distance L2 between the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, and the through electrode 81. Having L1>L2 is suitable for suppressing a leak current to the charge storage region FD. The leak current may also be referred to as a dark current.

[0097] In this embodiment, the first diffusion region 67n, which is one of the source and drain of the reset transistor 26, is the charge storage region FD.

[0098] The reason why L1>L2 is suitable for suppressing the leakage current to the charge storage region FD will be explained below.

[0099] Typically, crystal defects are present in the portion of the substrate surrounding the through hole 82. The crystal defects can cause a leakage current to the charge accumulation region FD. The crystal defects can occur for various reasons.

[0100] In one example, the substrate is a semiconductor substrate 1 having silicon, and a through hole 82 is formed in the semiconductor substrate 1 by plasma etching. In this example, the portion of the semiconductor substrate 1 surrounding the through hole 82 is exposed to plasma when the through hole 82 is formed. As a result, the crystals of silicon atoms in the surrounding portion are disturbed by energetic ions, and the surrounding portion is physically damaged. Thus, crystal defects may occur in the surrounding portion. Also, in this example, some of the constituent elements of the etching gas may be introduced into the semiconductor substrate 1 by ion collision. Crystal defects may occur due to the elements introduced in this way. In one specific example, the etching gas contains fluorine. Etching progresses as fluorine reacts with silicon of the semiconductor substrate 1 to form SiF. During this etching, fluorine may be introduced into the portion of the semiconductor substrate 1 surrounding the through hole 82. Fluorine is diffused by heat treatment after etching. This means that crystal defects due to fluorine are likely to cause leakage current to the charge storage region FD.

[0101] However, when L1>L2, it is easy to ensure the distance between the region where the crystal defects exist and the charge storage region FD, which is advantageous from the viewpoint of suppressing the PN junction leakage current to the charge storage region FD caused by the crystal defects.

[0102] Below, the terms related to L1>L2 will be explained.

[0103] In this embodiment, the term "planar view" refers to a view along the thickness direction of the semiconductor substrate 1. The thickness direction of the semiconductor substrate 1 may also be referred to as the normal direction of the semiconductor substrate 1.

[0104] In the first definition of this embodiment, the distance L1 is the distance between the geometric center of the charge storage region FD in a plan view and the geometric center of the through electrode 81. The distance L2 is the distance between the geometric center of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26 in a plan view, and the geometric center of the through electrode 81.

[0105] As described above, the charge storage region FD, the source, and the drain are diffusion regions. In the first definition of this embodiment, the boundary of the diffusion region is a junction. The junction is a portion where the concentration of N-type impurities and the concentration of P-type impurities are equal. In the first definition of this embodiment, the geometric center of the diffusion region in plan view is determined based on the concept of such a boundary. The concept of the geometric center of the diffusion region is the same in the following description.

[0106] In the second definition of this embodiment, the distance L1 is the distance between the geometric center of the contact surface between the charge storage region FD and the electrode connected to the charge storage region FD and the geometric center of the through electrode 81 in a plan view. In the example shown in FIG. 4, the electrode connected to the charge storage region FD is configured by the first contact plug cp1. The distance L2 is the distance between the geometric center of the contact surface between the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, and the electrode connected to the second diffusion region 68an and the geometric center of the through electrode 81 in a plan view. In the example shown in FIG. 4, the electrode connected to the second diffusion region 68an is configured by the fourth contact plug cp4.

[0107] In this embodiment, when it can be said that L1>L2 is true based on at least one of the first definition and the second definition, it is treated as being true that L1>L2 is true.

[0108] In this embodiment, in plan view, the gate electrode 26e of the reset transistor 26 is located between the through electrode 81 and the charge storage region FD. This positional relationship is suitable for suppressing a leak current to the charge storage region FD.

[0109] The reason why the above positional relationship is suitable for suppressing the leakage current to the charge accumulation region FD will be explained below.

[0110] First, the above positional relationship makes it easy to ensure a distance between the region where crystal defects exist and the charge accumulation region FD, which is suitable for suppressing leakage current to the charge accumulation region FD.

[0111] Secondly, when the above positional relationship is established, the leak current to the charge accumulation region FD can be suppressed by controlling the voltage applied to the gate electrode 26e of the reset transistor 26, which is the first transistor. In one example, the control performed by the imaging device 100 includes negative bias control. The negative bias control is a control that maintains a state in which a negative bias voltage is applied to the gate electrode 26e of the reset transistor 26, which is the first transistor. By the negative bias control, it is possible to put a portion of the region along the second main surface 1B of the semiconductor substrate 1 that overlaps with the gate electrode 26e in a plan view and a portion that overlaps with a part of the charge accumulation region FD into an accumulation state. By performing the negative bias control, it is possible to reduce the depletion layer in these portions. This can contribute to suppressing the leak current to the charge accumulation region FD. In this context, a certain portion being in an accumulation state means that an accumulation layer is formed in the portion. The accumulation layer is a layer in which the density of majority carriers is higher than that around the accumulation layer. In this embodiment, the majority carriers are positive charges, specifically holes. The minority carriers are negative charges, specifically electrons. According to the negative bias control, the potential gradient from the gate electrode 26e makes it easier for minority carriers from the through electrode 81 to move in a direction away from the second main surface 1B inside the semiconductor substrate 1. This can also contribute to suppressing leakage current to the charge accumulation region FD. The negative bias control is performed, for example, when the operation mode of the imaging device 100 is a mode in which signal charges are accumulated in the charge accumulation region FD.

[0112] In the specific example of the above example, the first transistor is the reset transistor 26. The control performed by the imaging device 100 includes reset control. The reset control is a control for applying a positive voltage to the gate electrode 26e of the reset transistor 26 to turn the reset transistor 26 on and resetting the potential of the charge storage region FD. The absolute value of the voltage applied to the gate electrode 26e during the negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26e during the negative bias control.

[0113] The expression "in a plan view, the gate electrode 26e of the reset transistor 26, which is the first transistor, is located between the through electrode 81 and the charge storage region FD" will be explained. In the first definition of this embodiment, this expression means that in a plan view, at least a part of the gate electrode 26e of the reset transistor 26, which is the first transistor, overlaps with at least a part of a line segment connecting the geometric center of the through electrode 81 and the geometric center of the charge storage region FD. In the second definition of this embodiment, this expression means that in a plan view, at least a part of the gate electrode 26e of the reset transistor 26, which is the first transistor, overlaps with at least a part of a line segment connecting the geometric center of the through electrode 81 and the geometric center of the contact surface between the charge storage region FD and the electrode connected to the charge storage region FD.

[0114] In this embodiment, if it can be explained based on at least one of the first definition and the second definition that "in a planar view, the gate electrode 26e of the reset transistor 26, which is the first transistor, is located between the through electrode 81 and the charge storage region FD," then the explanation will be treated as valid.

[0115] In this embodiment, the imaging device 100 has a second transistor, that is, a signal detection transistor 22. A gate electrode 22e of the signal detection transistor 22, that is, the second transistor, is electrically connected to the charge accumulation region FD.

[0116] In a plan view, the distance L1 between the charge storage region FD and the through electrode 81 is greater than the distance L3 between the gate electrode 22e of the signal detection transistor 22, which is the second transistor, and the through electrode 81. If L1>L3, it is easy to shorten the electrical path between the gate electrode 22e of the signal detection transistor 22, which is the second transistor, and the through electrode 81 while ensuring the distance between the region where crystal defects exist and the charge storage region FD. For this reason, L1>L3 is suitable for suppressing noise from being introduced into the electrical path between the gate electrode 22e of the signal detection transistor 22, which is the second transistor, and the through electrode 81 while suppressing leakage current to the charge storage region FD.

[0117] In this embodiment, the second transistor corresponds to the signal detection transistor 22 .

[0118] In this embodiment, the distance L3 is the distance between the geometric center of the gate electrode 22e of the signal detection transistor 22, which is the second transistor, and the geometric center of the through electrode 81 in plan view.

[0119] In this embodiment, in a plan view, the area S1 of the charge storage region FD is smaller than the area S2 of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, which is the first transistor. This size relationship between the areas can reduce the probability that carriers from the through electrode 81 flow into the charge storage region FD. Therefore, this size relationship is suitable for suppressing leakage current to the charge storage region FD.

[0120] In the first definition of this embodiment, the area S1 is the area of ​​a region extending inward from a junction that defines the charge storage region FD in a plan view. The area S2 is the area of ​​a region extending inward from a junction that defines the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, which is the first transistor, in a plan view.

[0121] In one example, the ratio S1 / S2 of the area S1 to the area S2 is 4 / 5 or less. The ratio S1 / S2 may be 2 / 3 or less, or may be 1 / 2 or less.

[0122] However, the area S1 and the area S2 may be the same, or the area S1 may be larger than the area S2.

[0123] In this embodiment, the second cylindrical portion 33B of the fixed charge layer 33 is provided so as to surround the through-hole 82. The second cylindrical portion 33B can suppress leakage current to the charge accumulation region FD caused by crystal defects.

[0124] In this embodiment, the pixel 10A has a first electrical path 83. The first electrical path 83 electrically connects the through electrode 81 and the charge accumulation region FD.

[0125] In this embodiment, the first electrical path 83 is formed using the second contact plug cp2, the first wiring layer 80a, and the first contact plug cp1.

[0126] 5 to 8 show examples of the first electrical path 83. FIG.

[0127] 5 to 7, at least a portion of the first electrical path 83 is curved in a plan view, which can increase the degree of freedom in the layout of the electrical paths.

[0128] The expression "at least a part of the first electrical path 83 is bent in a plan view" will be described. In the present embodiment, this expression is a concept including a form in which at least a part of the first electrical path 83 is bent in a plan view, as shown in Figs. 5 and 7. Specifically, in the examples of Figs. 5 and 7, the first electrical path 83 is bent at a portion 83j and a portion 83k in a plan view. In addition, the above expression is a concept including a form in which at least a part of the first electrical path 83 is gently bent in a plan view, as shown in Fig. 6. Specifically, in the example of Fig. 6, the first electrical path 83 is gently bent at a portion 83c in a plan view.

[0129] In this embodiment, the pixel 10A has a gate wiring 26w. The gate wiring 26w is electrically connected to the gate electrode 26e of the first transistor. Note that the gate wiring 26w is not illustrated in FIGS. 3 and 4. In an example in which the first transistor is the reset transistor 26, the gate wiring 26w may include a reset signal line 47. Also, in an example in which the first transistor is the reset transistor 26, the gate wiring 26w may be the reset signal line 47.

[0130] Hereinafter, the term "second electrical path 26m" may be used. The second electrical path 26m refers to the combination of the gate electrode 26e and the gate wiring 26w of the first transistor.

[0131] 5 and 6, the first electrical path 83 bypasses the second electrical path 26m in a plan view. According to this example, coupling between the first electrical path 83 and the second electrical path 26m can be suppressed.

[0132] In the specific example shown in FIG. 5 and FIG. 6, the first transistor is the reset transistor 26. The control performed by the imaging device 100 includes a reset control in which a voltage is applied to the gate electrode 26e of the reset transistor 26 to turn the reset transistor 26 on and reset the potential of the charge storage region FD. When the reset transistor 26 is turned on or subsequently turned off due to the reset control, the voltage of the gate electrode 26e is switched. That is, the voltage of the second electric path 26m is switched. When this switching occurs, the voltage of the first electric path 83 also fluctuates due to coupling between the first electric path 83 and the second electric path 26m, and this fluctuation may cause the voltage of the charge storage region FD to fluctuate as well. Such fluctuation of the voltage of the charge storage region FD may cause noise. However, if the first electric path 83 bypasses the second electric path 26m, the noise that may occur as described above can be suppressed.

[0133] The expression "in a plan view, the first electric path 83 bypasses the second electric path 26m" will be explained. In the present embodiment, this expression indicates that, in a plan view, at least a part of a line segment 83s connecting the through electrode 81 and the charge accumulation region FD overlaps with at least a part of the second electric path 26m, while the first electric path 83 is separated from the second electric path 26m. In the first definition, the line segment 83s is a line segment that connects the geometric center of the through electrode 81 and the geometric center of the charge accumulation region FD. In the second definition, the line segment 83s is a line segment that connects the geometric center of the through electrode 81 and the geometric center of the contact surface between the charge accumulation region FD and the electrode connected to the charge accumulation region FD.

[0134] 7 and 8, at least a part of the first electrical path 83 and at least a part of the second electrical path 26m overlap in a plan view. According to the example shown in Fig. 7 and 8, coupling can be generated between the first electrical path 83 and the second electrical path 26m. For example, by generating coupling, it is possible to lower the voltage of the charge storage region FD and suppress the leakage current of the charge storage region FD.

[0135] In the example shown in Fig. 7, at least a portion of the first electrical path 83 is curved in a plan view. In the example shown in Fig. 8, the first electrical path 83 extends linearly in a plan view. In either the example shown in Fig. 7 or the example shown in Fig. 8, at least a portion of the first electrical path 83 and at least a portion of the second electrical path 26m can be overlapped in a plan view.

[0136] In this embodiment, as shown in Fig. 3, at least a part of the pixel electrode 13, which is the first electrode, overlaps with at least a part of the charge storage region FD in a plan view. Therefore, the pixel electrode 13, which is the first electrode, can suppress the irradiation of light to the charge storage region FD. This is advantageous from the viewpoint of suppressing the leakage current of the charge storage region FD.

[0137] Specifically, in this embodiment, as shown in FIG. 3, the entire charge storage region FD overlaps with a part of the pixel electrode 13, which is the first electrode, in plan view.

[0138] In this embodiment, the pixel electrode 13, which is the first electrode, contains at least one of a metal and a metal compound, thereby making it possible to form the first electrode 13 having the above-mentioned leakage current suppressing effect.

[0139] In this embodiment, the pixel electrode 13 serving as the first electrode contains a metal, which makes it easy to configure the pixel electrode 13 serving as the first electrode having the above-mentioned leakage current suppressing effect.

[0140] In this embodiment, the pixel electrode 13, which is the first electrode, contains a material having at least one of the following characteristics: lower light transmittance than the semiconductor substrate 1 and lower light transmittance than ITO. This characteristic can also be advantageous in ensuring the above-mentioned leakage current suppression effect. In this context, light transmittance is, for example, transmittance of at least one of visible light and near-infrared light. The wavelength range of visible light is, for example, 400 nm to 780 nm. The wavelength range of near-infrared light is, for example, 780 nm to 2000 nm. The transmittance can be calculated by a method specified in Japanese Industrial Standard JIS R3106 (1998).

[0141] In this embodiment, a photodiode is not provided in the semiconductor substrate 1. In this case, it is not necessary to consider irradiating the photodiode with light, so it is easy to adopt a configuration in which light irradiation to the charge accumulation region FD is suppressed by overlapping at least a part of the pixel electrode 13, which is the first electrode, with at least a part of the charge accumulation region FD in a plan view. However, even if a photodiode is provided in the semiconductor substrate 1, it is possible to adopt a configuration in which light irradiation to the charge accumulation region FD is suppressed by overlapping at least a part of the pixel electrode 13, which is the first electrode, with at least a part of the charge accumulation region FD in a plan view.

[0142] In this embodiment, as shown in Fig. 4, the second contact plug cp2 is interposed between the through electrode 81 and the first wiring layer 80a. However, as shown in Fig. 9, the through electrode 81 and the first wiring layer 80a may be directly connected. This also applies to the embodiments described later.

[0143] In this embodiment, there are a plurality of pixels 10 A. This also applies to the embodiments described below.

[0144] Below, some other embodiments will be described. In the following, elements common to the already described embodiment and the embodiment to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applied unless there is a technical contradiction. The respective embodiments may be mutually combined unless there is a technical contradiction.

[0145] Second Embodiment Fig. 10 is a diagram showing an exemplary circuit configuration of pixel 10B. Fig. 12 is a schematic diagram showing an example of a device structure of pixel 10B. Fig. 11 is a schematic diagram showing the arrangement of each element formed on semiconductor substrate 1 when pixel 10B shown in Fig. 12 is viewed along the normal direction of semiconductor substrate 1. If pixel 10B is cut along dashed line XII-XII in Fig. 11 and developed, the cross section shown in Fig. 12 is obtained.

[0146] In the second embodiment, unlike the first embodiment, three photoelectric conversion layers are stacked. Typically, these three photoelectric conversion layers exhibit sensitivity to light in wavelength ranges of different colors. Specifically, these three photoelectric conversion layers exhibit sensitivity to light in the wavelength ranges of red (R), green (G), and blue (B). In the second embodiment, it is possible to use optimal photoelectric conversion layers exhibiting sensitivity to light in these wavelength ranges. The second embodiment is advantageous from the viewpoint of improving photoelectric conversion efficiency.

[0147] The second embodiment will be described in detail below.

[0148] 10, the pixel 10B has three combinations of the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge accumulation region FD. Hereinafter, the three combinations may be referred to as a first combination memX, a second combination memY, and a third combination memZ.

[0149] In the second embodiment, the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge storage region FD of the first combination memX may be respectively written as the photoelectric conversion unit 12X, the through electrode 81X, the signal detection circuit 60X, and the charge storage region FDX. The pixel electrode 13, the photoelectric conversion layer 14, and the counter electrode 15 of the photoelectric conversion unit 12X may be respectively written as the pixel electrode 13X, the photoelectric conversion layer 14X, and the counter electrode 15X. The signal detection transistor 22, the address transistor 24, and the reset transistor 26 of the signal detection circuit 60X may be respectively written as the signal detection transistor 22X, the address transistor 24X, and the reset transistor 26X. The gate electrode 22e of the signal detection transistor 22X, the gate electrode 24e of the address transistor 24X, and the gate electrode 26e of the reset transistor 26X may be respectively written as the gate electrode 22eX, the gate electrode 24eX, and the gate electrode 26eX.

[0150] In the second embodiment, the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge accumulation region FD of the second combination memY may be respectively written as the photoelectric conversion unit 12Y, the through electrode 81Y, the signal detection circuit 60Y, and the charge accumulation region FDY. The pixel electrode 13, the photoelectric conversion layer 14, and the counter electrode 15 of the photoelectric conversion unit 12Y may be respectively written as the pixel electrode 13Y, the photoelectric conversion layer 14Y, and the counter electrode 15Y. The signal detection transistor 22, the address transistor 24, and the reset transistor 26 of the signal detection circuit 60Y may be respectively written as the signal detection transistor 22Y, the address transistor 24Y, and the reset transistor 26Y. The gate electrode 22e of the signal detection transistor 22Y, the gate electrode 24e of the address transistor 24Y, and the gate electrode 26e of the reset transistor 26Y may be respectively written as the gate electrode 22eY, the gate electrode 24eY, and the gate electrode 26eY.

[0151] In the second embodiment, the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge accumulation region FD of the third combination memZ may be referred to as the photoelectric conversion unit 12Z, the through electrode 81Z, the signal detection circuit 60Z, and the charge accumulation region FDZ, respectively. The pixel electrode 13, the photoelectric conversion layer 14, and the counter electrode 15 of the photoelectric conversion unit 12Z may be referred to as the pixel electrode 13Z, the photoelectric conversion layer 14Z, and the counter electrode 15Z, respectively. The signal detection transistor 22, the address transistor 24, and the reset transistor 26 of the signal detection circuit 60Z may be referred to as the signal detection transistor 22Z, the address transistor 24Z, and the reset transistor 26Z, respectively. The gate electrode 22e of the signal detection transistor 22Z, the gate electrode 24e of the address transistor 24Z, and the gate electrode 26e of the reset transistor 26Z may be referred to as the gate electrode 22eZ, the gate electrode 24eZ, and the gate electrode 26eZ, respectively.

[0152] The first combination memX, the second combination memY, and the third combination memZ may have other elements described in the first embodiment. The first combination memX, the second combination memY, and the third combination memZ may be associated with other elements described in the first embodiment. Each element of the first combination memX, the second combination memY, and the third combination memZ may have similar features to each element of the first embodiment.

[0153] 12, for example, in this embodiment, the through electrode 81X for the first combination memX is provided in the through hole 82 for the first combination memX. Although not shown, the through electrode 81Y for the second combination memY is provided in the through hole 82 for the second combination memY. The through electrode 81Z for the third combination memZ is provided in the through hole 82 for the third combination memZ.

[0154] In this embodiment, as shown in Fig. 12, in the first combination memX, the pixel electrode 13X, the through electrode 81X, the second contact plug cp2 for the first combination memX, the first wiring layer 80a, the first contact plug cp1 for the first combination memX, and the charge storage region FDX are connected in this order. Although not shown, the second combination memY also has a similar connection using the second contact plug cp2 and the first contact plug cp1 for the second combination memY. The third combination memZ also has a similar connection using the second contact plug cp2 and the first contact plug cp1 for the third combination memZ.

[0155] In this embodiment, as shown in Fig. 12, the photoelectric conversion unit 12X and the through electrode 81X for the first combination memX are associated with the dielectric layer 32 and the fixed charge layer 33 for the first combination memX. As can be seen from Fig. 4 and Fig. 12, these are associated in the same manner as the photoelectric conversion unit 12, the through electrode 81, the dielectric layer 32 and the fixed charge layer 33 in the first embodiment. Although not shown in the figure, the same is true for the second combination memY and the third combination memZ.

[0156] In this embodiment, an insulating layer 31X corresponding to the insulating layer 31 of embodiment 1 is provided above a photoelectric conversion unit 12X related to the first combination memX. An insulating layer 31Y corresponding to the insulating layer 31 of embodiment 1 is provided above a photoelectric conversion unit 12Y related to the second combination memY. An insulating layer 31Z corresponding to the insulating layer 31 of embodiment 1 is provided above a photoelectric conversion unit 12Z related to the third combination memZ.

[0157] In this embodiment, the insulating layer 71, the insulating layer 70, the semiconductor substrate 1, the photoelectric conversion unit 12X, the insulating layer 31X, the photoelectric conversion unit 12Y, the insulating layer 31Y, the photoelectric conversion unit 12Z, the insulating layer 31Z, and the microlens 30 are laminated in this order. Specifically, these are laminated in the thickness direction of the semiconductor substrate 1.

[0158] In this embodiment, the first combination memX, the second combination memY, and the third combination memZ share the insulating layer 71, the insulating layer 70, the wiring structure 80, and the semiconductor substrate 1.

[0159] In this embodiment, the photoelectric conversion layer 14X associated with the first combination memX exhibits sensitivity to light in the red (R) wavelength region. The photoelectric conversion layer 14Y associated with the second combination memY exhibits sensitivity to light in the green (G) wavelength region. The photoelectric conversion layer 14Z associated with the third combination memZ exhibits sensitivity to light in the blue (B) wavelength region. Thus, in this embodiment, a photoelectric conversion layer sensitive to red light, a photoelectric conversion layer sensitive to green light, and a photoelectric conversion layer sensitive to blue light are stacked in this order. However, the order in which the photoelectric conversion layers are stacked is not particularly limited.

[0160] In this embodiment, in plan view, the outer contour of the pixel electrode 13Y is located inside the outer contour of the pixel electrode 13Z. In plan view, the outer contour of the pixel electrode 13X is located inside the outer contour of the pixel electrode 13Y.

[0161] In the present embodiment, the horizontal signal read circuit 54 is connected to the vertical signal line 45X, the vertical signal line 45Y, and the vertical signal line 45Z.

[0162] In this embodiment, the vertical scanning circuit 52 is connected to the address signal line 44X, the address signal line 44Y, and the address signal line 44Z. The vertical scanning circuit 52 is connected to the counter electrode power line 21X, the counter electrode power line 21Y, and the counter electrode power line 21Z. The vertical scanning circuit 52 is connected to the reset signal line 47X, the reset signal line 47Y, and the reset signal line 47Z.

[0163] In this embodiment, the vertical signal line 45X, the address signal line 44X, the counter electrode power line 21X, the reset signal line 47X, the signal detection circuit 60X, the photoelectric conversion unit 12X, and the charge accumulation region FDX are associated in the same manner as the vertical signal line 45, the address signal line 44, the counter electrode power line 21, the reset signal line 47, the signal detection circuit 60, the photoelectric conversion unit 12, and the charge accumulation region FD in the first embodiment. The same is true for the vertical signal line 45Y, the address signal line 44Y, the counter electrode power line 21Y, the reset signal line 47Y, the signal detection circuit 60Y, the photoelectric conversion unit 12Y, and the charge accumulation region FDY. The same is true for the vertical signal line 45Z, the address signal line 44Z, the counter electrode power line 21Z, the reset signal line 47Z, the signal detection circuit 60Z, the photoelectric conversion unit 12Z, and the charge accumulation region FDZ.

[0164] For example, in this embodiment, the photoelectric conversion unit 12X is connected to a counter electrode power line 21X. The photoelectric conversion unit 12Y is connected to a counter electrode power line 21Y. The photoelectric conversion unit 12Z is ​​connected to a counter electrode power line 21Z.

[0165] Specifically, the counter electrode 15X is connected to a counter electrode power line 21X. The counter electrode 15Y is connected to a counter electrode power line 21Y. The counter electrode 15Z is connected to a counter electrode power line 21Z.

[0166] A gate electrode 26eX of the reset transistor 26X is connected to the reset signal line 47X. A gate electrode 26eY of the reset transistor 26Y is connected to the reset signal line 47Y. A gate electrode 26eZ of the reset transistor 26Z is connected to the reset signal line 47Z.

[0167] In this embodiment as well, the same positional relationships as those in the first embodiment in plan view can be established.

[0168] 11, in the first combination memX, in a plan view, a distance L1X between the charge storage region FDX and the through electrode 81X is greater than a distance L2X between the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26X, which is the first transistor, and the through electrode 81X. In the present embodiment, the first transistor corresponds to the reset transistor 26X.

[0169] In the present embodiment, with respect to the second combination memY, in a plan view, a distance L1Y between the charge storage region FDY and the through electrode 81Y is greater than a distance L2Y between the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26Y, which is the first transistor, and the through electrode 81Y. In the present embodiment, the first transistor corresponds to the reset transistor 26Y.

[0170] In the present embodiment, with respect to the third combination memZ, in a plan view, a distance L1Z between the charge storage region FDZ and the through electrode 81Z is greater than a distance L2Z between the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26Z, which is the first transistor, and the through electrode 81Z. In the present embodiment, the first transistor corresponds to the reset transistor 26Z.

[0171] In this embodiment, with respect to the first combination memX, the gate electrode 26eX of the first transistor 26X is located between the through electrode 81X and the charge storage region FDX in plan view.

[0172] In one example, the control performed by the imaging device 100 includes a first negative bias control. The first negative bias control is a control for maintaining a state in which a voltage is applied to the gate electrode 26eX of the reset transistor 26X, which is the first transistor. The first negative bias control can set a portion of the region along the second main surface 1B of the semiconductor substrate 1 that overlaps with the gate electrode 26eX in a plan view and a portion that overlaps with a part of the charge accumulation region FDX to an accumulation state. The first negative bias control is performed, for example, when the operation mode of the imaging device 100 is a mode in which signal charges are accumulated in the charge accumulation region FD.

[0173] In one specific example, the first transistor is a reset transistor 26X. The control performed by the imaging device 100 includes a first reset control. The first reset control is a control for turning on the reset transistor 26X by applying a positive voltage to the gate electrode 26eX of the reset transistor 26X, thereby resetting the potential of the charge storage region FDX. The absolute value of the voltage applied to the gate electrode 26eX during the first negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26eX during the first negative bias control.

[0174] In this embodiment, with regard to the second combination memY, the gate electrode 26eY of the reset transistor 26Y, which is the first transistor, is located between the through electrode 81Y and the charge storage region FDY in plan view.

[0175] In one example, the control performed by the imaging device 100 includes a second negative bias control. The second negative bias control is a control for maintaining a state in which a voltage is applied to the gate electrode 26eY of the reset transistor 26Y, which is the first transistor. The second negative bias control can set a portion of the region along the second main surface 1B of the semiconductor substrate 1 that overlaps with the gate electrode 26eY in a plan view and a portion that overlaps with a part of the charge accumulation region FDY to an accumulation state. The second negative bias control is performed, for example, when the operation mode of the imaging device 100 is a mode in which signal charges are accumulated in the charge accumulation region FD.

[0176] In one specific example, the first transistor is a reset transistor 26Y. The control performed by the imaging device 100 includes a second reset control. The second reset control is a control for turning on the reset transistor 26Y by applying a positive voltage to a gate electrode 26eY of the reset transistor 26Y to reset the potential of the charge storage region FDY. The absolute value of the voltage applied to the gate electrode 26eY during the second negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26eY during the second negative bias control.

[0177] In this embodiment, with regard to the third combination memZ, the gate electrode 26eZ of the reset transistor 26Z, which is the first transistor, is located between the through electrode 81Z and the charge storage region FDZ in plan view.

[0178] In one example, the control performed by the imaging device 100 includes a third negative bias control. The third negative bias control is a control for maintaining a state in which a voltage is applied to the gate electrode 26eZ of the reset transistor 26Z, which is the first transistor. The third negative bias control can set a portion of the region along the second main surface 1B of the substrate 1 that overlaps with the gate electrode 26eZ in a plan view and a portion that overlaps with a part of the charge accumulation region FDZ to an accumulation state. The third negative bias control is performed, for example, when the operation mode of the imaging device 100 is a mode in which signal charges are accumulated in the charge accumulation region FD.

[0179] In one specific example, the first transistor is a reset transistor 26Z. The control performed by the imaging device 100 includes a third reset control. The third reset control is a control for turning on the reset transistor 26Z by applying a positive voltage to the gate electrode 26eZ of the reset transistor 26Z, thereby resetting the potential of the charge storage region FDZ. The absolute value of the voltage applied to the gate electrode 26eZ during the third negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26eZ during the third negative bias control.

[0180] In this embodiment, with respect to the first combination memX, in a plan view, a distance L1X between the charge storage region FDX and the through electrode 81X is greater than a distance L3X between the gate electrode 22eX of the signal detection transistor 22X, which is the second transistor, and the through electrode 81X. In this embodiment, the second transistor corresponds to the signal detection transistor 22X.

[0181] In the present embodiment, with respect to the second combination memY, in a plan view, a distance L1Y between the charge storage region FDY and the through electrode 81Y is greater than a distance L3Y between the gate electrode 22eY of the signal detection transistor 22Y, which is the second transistor, and the through electrode 81Y. In the present embodiment, the second transistor corresponds to the signal detection transistor 22Y.

[0182] In the present embodiment, with respect to the third combination memZ, in a plan view, a distance L1Z between the charge storage region FDZ and the through electrode 81Z is greater than a distance L3Z between the gate electrode 22eZ of the signal detection transistor 22Z, which is the second transistor, and the through electrode 81Z. In the present embodiment, the second transistor corresponds to the signal detection transistor 22Z.

[0183] In this embodiment, with respect to the first combination memX, in a plan view, the area S1X of the charge storage region FDX is smaller than the area S2X of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26X, which is the first transistor. The ratio S1X / S2X of the area S1X to the area S2X may be 4 / 5 or less, 2 / 3 or less, or 1 / 2 or less. However, the area S1X and the area S2X may be the same. Also, the area S1X may be larger than the area S2X.

[0184] In this embodiment, for the second combination memY, in a plan view, the area S1Y of the charge storage region FDY is smaller than the area S2Y of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26Y, which is the first transistor. The ratio S1Y / S2Y of the area S1Y to the area S2Y may be 4 / 5 or less, 2 / 3 or less, or 1 / 2 or less. However, the area S1Y and the area S2Y may be the same. Also, the area S1Y may be larger than the area S2Y.

[0185] In this embodiment, with respect to the third combination memZ, in a plan view, the area S1Z of the charge storage region FDZ is smaller than the area S2Z of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26Z, which is the first transistor. The ratio S1Z / S2Z of the area S1Z to the area S2Z may be 4 / 5 or less, 2 / 3 or less, or 1 / 2 or less. However, the area S1Z and the area S2Z may be the same. Also, the area S1Z may be larger than the area S2Z.

[0186] The first electrical path 83, the through electrode 81X, and the charge storage region FDX for the first combination memX can be associated in the same manner as the first electrical path 83, the through electrode 81, and the charge storage region FD in the first embodiment.

[0187] The first electrical path 83, the through electrode 81Y, and the charge storage region FDY for the second combination memY can be associated in the same manner as the first electrical path 83, the through electrode 81, and the charge storage region FD in the first embodiment.

[0188] The first electrical path 83, the through electrode 81Z, and the charge storage region FDZ for the third combination memZ can be associated in the same manner as the first electrical path 83, the through electrode 81, and the charge storage region FD in the first embodiment.

[0189] The gate wiring 26w for the first combination memX may be electrically connected to the gate electrode 26eX of the first transistor. In an example in which the first transistor is the reset transistor 26X, the gate wiring 26wX for the first combination memX may correspond to the reset signal line 47X.

[0190] The gate wiring 26w for the second combination memY may be electrically connected to the gate electrode 26eY of the first transistor. In an example in which the first transistor is the reset transistor 26Y, the gate wiring 26wY for the first combination memX may correspond to the reset signal line 47Y.

[0191] The gate wiring 26w for the third combination memZ may be electrically connected to the gate electrode 26eZ of the first transistor. In an example in which the first transistor is the reset transistor 26Z, the gate wiring 26wZ for the first combination memX may correspond to the reset signal line 47Z.

[0192] In one example, in a plan view, the first electrical path 83 for the first combination memX bypasses the second electrical path 26m for the first combination memX. Here, the second electrical path 26m for the first combination memX refers to the combination of the gate electrode 26eX of the first transistor and the gate wiring 26w for the first combination memX.

[0193] In one example, in a plan view, the first electrical path 83 for the second combination memY bypasses the second electrical path 26m for the second combination memY. Here, the second electrical path 26m for the second combination memY refers to the combination of the gate electrode 26eY of the first transistor and the gate wiring 26w for the second combination memY.

[0194] In one example, in a plan view, the first electrical path 83 for the third combination memZ bypasses the second electrical path 26m for the third combination memZ. Here, the second electrical path 26m for the third combination memZ refers to the combination of the gate electrode 26eZ of the first transistor and the gate wiring 26w for the third combination memZ.

[0195] In one example, in a plan view, at least a portion of the first electrical path 83 for the first combination memX and the second electrical path 26m for the first combination memX overlap.

[0196] In one example, in a plan view, at least a portion of the first electrical path 83 for the second combination memY and the second electrical path 26m for the second combination memY overlap each other.

[0197] In one example, in a plan view, at least a portion of the first electrical path 83 for the third combination memZ and the second electrical path 26m for the third combination memZ overlap.

[0198] In this embodiment, in a plan view, at least a part of the pixel electrode 13X, which is the first electrode related to the first combination memX, and at least a part of the charge storage region FDX, which is the first electrode related to the first combination memX, overlap. In a plan view, the entire charge storage region FDX may overlap a part of the pixel electrode 13X, which is the first electrode.

[0199] In this embodiment, in a plan view, at least a part of the pixel electrode 13Y, which is the first electrode related to the second combination memY, and at least a part of the charge storage region FDY, which is the second combination memY, overlap. In a plan view, the entire charge storage region FDY may overlap a part of the pixel electrode 13Y, which is the first electrode.

[0200] In this embodiment, in a plan view, at least a part of the pixel electrode 13Z, which is the first electrode of the third combination memZ, and at least a part of the charge storage region FDZ, which is the third combination memZ, overlap. In a plan view, the entire charge storage region FDZ may overlap a part of the pixel electrode 13Z, which is the first electrode.

[0201] In this embodiment, the optical transparency of pixel electrode 13X, which is the first electrode for the first combination memX, may be lower than the optical transparency of substrate 1, pixel electrode 13Y, which is the first electrode for the second combination memY, and pixel electrode 13Z, which is the first electrode for the third combination memZ.

[0202] (Third embodiment) Fig. 13 is a diagram showing an exemplary circuit configuration of pixel 10C. Fig. 15 is a diagram showing an example of a device structure of pixel 10C. Fig. 14 is a diagram showing an arrangement of elements formed on semiconductor substrate 1 when pixel 10C shown in Fig. 15 is viewed along the normal direction of semiconductor substrate 1. If pixel 10C is cut along dashed line XV-XV in Fig. 14 and developed, the cross section shown in Fig. 15 is obtained.

[0203] In the third embodiment, unlike the second embodiment, two photoelectric conversion layers are stacked. Typically, these two photoelectric conversion layers exhibit sensitivity to light in wavelength regions of different colors. Specifically, these two photoelectric conversion layers exhibit sensitivity to light in the red (R) and blue (B) wavelength regions. In the third embodiment, it is possible to use an optimal photoelectric conversion layer exhibiting sensitivity to light in these wavelength regions. The third embodiment is advantageous from the viewpoint of improving the degree of freedom in designing photoelectric conversion film materials.

[0204] Moreover, in the third embodiment, unlike the second embodiment, a photodiode is provided in the semiconductor substrate 1. Typically, this photodiode photoelectrically converts light in a wavelength range that is not absorbed by the above two photoelectric conversion layers. Specifically, this photodiode photoelectrically converts light in a green (G) wavelength range.

[0205] In this way, in the third embodiment, sensitivity to light in three different wavelength ranges can be obtained by using two photoelectric conversion layers and one photodiode. This configuration can be realized without using a color filter.

[0206] The third embodiment will be described in detail below.

[0207] 13, the pixel 10C includes a first combination memX and a third combination memZ, similar to the second embodiment. On the other hand, the pixel 10C includes a second combination pdY, unlike the second embodiment.

[0208] The second combination pdY includes a signal detection circuit 60Y, similar to the second combination memY. On the other hand, the second combination pdY differs from the second combination memY in that it includes a photodiode 27Y and a transfer transistor 28Y.

[0209] In this embodiment, the insulating layer 71, the insulating layer 70, the semiconductor substrate 1, the photoelectric conversion unit 12X, the insulating layer 31X, the photoelectric conversion unit 12Z, the insulating layer 31Z, and the microlens 30 are laminated in this order. Specifically, these are laminated in the thickness direction of the semiconductor substrate 1.

[0210] In this embodiment, the outer contour of the pixel electrode 13X is located inside the outer contour of the pixel electrode 13Z in a plan view.

[0211] The photodiode 27Y exhibits sensitivity to light. Specifically, the photodiode 27Y is provided in the semiconductor substrate 1. The photodiode 27Y photoelectrically converts light in the green (G) wavelength range that is not absorbed by the photoelectric conversion units 12X and 12Z.

[0212] When light is irradiated onto the photodiode 27Y, charges are generated in the photodiode 27Y. The generated charges are accumulated as signal charges in the photodiode 27Y. In this embodiment, unlike the previously described embodiment, the signal charges are negative charges. Specifically, the signal charges are electrons. The photodiode 27Y is an N-type impurity layer.

[0213] The adjustment of each element in accordance with the difference in the positive and negative polarities of the signal charges, such as changing the conductivity type of the impurity regions, can be appropriately performed. Furthermore, the interpretation of terms in accordance with the difference in the positive and negative polarities of the signal charges can be appropriately performed.

[0214] The transfer transistor 28Y is provided on the semiconductor substrate 1. Specifically, the transfer transistor 28Y is provided on the second main surface 1B.

[0215] The transfer transistor 28Y is a MOSFET. Specifically, the transfer transistor 28Y is an N-channel MOSFET.

[0216] The transfer transistor 28Y transfers the signal charge accumulated in the photodiode 27Y to the charge accumulation region FDY. In the third embodiment, similarly to the second embodiment, the charge accumulation region FDY is the first diffusion region 67n which is one of the source and drain of the reset transistor 26Y which is the first transistor.

[0217] A transfer signal line 49Y connected to the vertical scanning circuit 52 is connected to the gate electrode 28eY of the transfer transistor 28Y. The transfer signal line 49Y is provided for each row of the pixels 10C, similar to the address signal line 44Y. The vertical scanning circuit 52 can turn on the transfer transistor 28Y by applying a transfer signal that controls the on / off of the transfer transistor 28Y to the gate electrode 28eY of the transfer transistor 28Y via the transfer signal line 49Y. When the transfer transistor 28Y is turned on, the signal charge accumulated in the photodiode 27Y is transferred to the charge accumulation region FDY.

[0218] (Fourth embodiment) Fig. 16 is a diagram showing an exemplary circuit configuration of pixel 10D. Fig. 18 is a schematic diagram showing an example of a device structure of pixel 10D. Fig. 17 is a schematic diagram showing the arrangement of each element formed on semiconductor substrate 1 when pixel 10D shown in Fig. 18 is viewed along the normal direction of semiconductor substrate 1. If pixel 10D is cut along dashed line XVIII-XVIII in Fig. 17 and developed, the cross section shown in Fig. 18 is obtained.

[0219] In the fourth embodiment, unlike the second and third embodiments, one photoelectric conversion layer is provided. The photoelectric conversion layer exhibits sensitivity to light. Specifically, the photoelectric conversion layer exhibits sensitivity to light in the green (G) wavelength region.

[0220] In the fourth embodiment, unlike the second and third embodiments, two photodiodes are stacked in the semiconductor substrate 1. Typically, these two photodiodes perform photoelectric conversion on light in a wavelength range not absorbed by the photoelectric conversion layer. Typically, these two photodiodes perform photoelectric conversion on light in wavelength ranges of different colors. Specifically, photodiode 27X performs photoelectric conversion on light in the red (R) wavelength range. Photodiode 27Z performs photoelectric conversion on light in the blue (B) wavelength range.

[0221] In this way, in the fourth embodiment, sensitivity to light in three different wavelength ranges is obtained by one photoelectric conversion layer and two photodiodes. This configuration can be realized without using color filters.

[0222] The fourth embodiment will be described in detail below.

[0223] 16, the pixel 10D includes the second combination memY, similar to the second embodiment. On the other hand, the pixel 10D includes the first combination pdX and the third combination pdZ, unlike the second and third embodiments.

[0224] The first combination pdX includes a signal detection circuit 60X, similar to the first combination memX. On the other hand, the first combination pdX includes a photodiode 27X and a transfer transistor 28X, unlike the first combination memX.

[0225] The third combination pdZ includes a signal detection circuit 60Z, similar to the third combination memZ. On the other hand, the third combination pdZ includes a photodiode 27Z and a transfer transistor 28Z, unlike the third combination memZ.

[0226] In this embodiment, the insulating layer 71, the insulating layer 70, the semiconductor substrate 1, the photoelectric conversion unit 12Y, the insulating layer 31Y, and the microlens 30 are stacked in this order. Specifically, these are stacked in the thickness direction of the semiconductor substrate 1.

[0227] The photodiode 27X and the photodiode 27Z are provided in the semiconductor substrate 1. Specifically, the photodiode 27X and the photodiode 27Z are stacked in the semiconductor substrate 1. Specifically, they are stacked in the thickness direction of the semiconductor substrate 1. More specifically, the photodiode 27X is provided at a depth in the semiconductor substrate 1 that allows photoelectric conversion of light in the red (R) wavelength region. The photodiode 27Z is provided at a depth in the semiconductor substrate 1 that allows photoelectric conversion of light in the blue (B) wavelength region.

[0228] The photodiode 27X and the photodiode 27Z are sensitive to light. Specifically, the photodiodes 27X and 27Z photoelectrically convert light in a wavelength range that is not absorbed by the photoelectric conversion unit 12Y. More specifically, the photodiode 27X photoelectrically converts light in a red (R) wavelength range. The photodiode 27Z photoelectrically converts light in a blue (B) wavelength range.

[0229] When the photodiode 27X is irradiated with light, an electric charge is generated in the photodiode 27X. The generated electric charge is accumulated as a signal charge in the photodiode 27X. In this embodiment, the signal charge is a negative electric charge. Specifically, the signal charge is an electron. The photodiode 27X is an N-type impurity layer.

[0230] The transfer transistor 28X is provided on the semiconductor substrate 1. Specifically, the transfer transistor 28X is provided on the second main surface 1B.

[0231] When the photodiode 27Z is irradiated with light, an electric charge is generated in the photodiode 27Z. The generated electric charge is accumulated as a signal charge in the photodiode 27Z.

[0232] The transfer transistor 28Z is provided on the semiconductor substrate 1. Specifically, the transfer transistor 28Z is provided on the second main surface 1B.

[0233] The transfer transistor 28X and the transfer transistor 28Z are MOSFETs. Specifically, the transfer transistor 28X and the transfer transistor 28Z are N-channel MOSFETs.

[0234] The transfer transistor 28X transfers the signal charge accumulated in the photodiode 27X to the charge storage region FDX. In the fourth embodiment, similarly to the second and third embodiments, the charge storage region FDX is the first diffusion region 67n which is one of the source and drain of the reset transistor 26X which is the first transistor.

[0235] The transfer transistor 28Z transfers the signal charge accumulated in the photodiode 27Z to the charge storage region FDZ. In the fourth embodiment, similarly to the second and third embodiments, the charge storage region FDZ is the first diffusion region 67n which is one of the source and drain of the reset transistor 26Z which is the first transistor.

[0236] A transfer signal line 49X connected to the vertical scanning circuit 52 is connected to the gate electrode 28eX of the transfer transistor 28X. The transfer signal line 49X is provided for each row of the pixels 10D, similar to the address signal line 44X. The vertical scanning circuit 52 can turn on the transfer transistor 28X by applying a transfer signal that controls on and off of the transfer transistor 28X to the gate electrode 28eX of the transfer transistor 28X via the transfer signal line 49X. When the transfer transistor 28X is turned on, the signal charge accumulated in the photodiode 27X is transferred to the charge accumulation region FDX.

[0237] A transfer signal line 49Z connected to the vertical scanning circuit 52 is connected to the gate electrode 28eZ of the transfer transistor 28Z. The transfer signal line 49Z is provided for each row of the pixels 10D, similar to the address signal line 44Z. The vertical scanning circuit 52 can turn on the transfer transistor 28Z by applying a transfer signal that controls the on / off of the transfer transistor 28Z to the gate electrode 28eZ of the transfer transistor 28Z via the transfer signal line 49Z. When the transfer transistor 28Z is turned on, the signal charge accumulated in the photodiode 27Z is transferred to the charge accumulation region FDZ.

[0238] Fifth embodiment Fig. 19 is a diagram showing an exemplary circuit configuration of the pixel 10E. Fig. 21 is a diagram showing an example of a device structure of the pixel 10E. Fig. 20 is a diagram showing an arrangement of each element formed on the semiconductor substrate 1 when the pixel 10E shown in Fig. 21 is viewed along the normal direction of the semiconductor substrate 1. If the pixel 10E is cut along the dashed line XXI-XXI in Fig. 20 and developed, the cross section shown in Fig. 21 is obtained.

[0239] In the fifth embodiment, the photoelectric conversion section 12 includes a pixel electrode 13, a photoelectric conversion laminate 29, and a counter electrode 15.

[0240] A first flat film portion 32A of the dielectric layer 32, a pixel electrode 13, an insulating layer 17A, a photoelectric conversion stack 29, an insulating layer 17B, and a counter electrode 15 are laminated in this order. Specifically, these are laminated in the thickness direction of the semiconductor substrate 1.

[0241] Fig. 22 shows the configuration of the photoelectric conversion stack 29. As shown in Fig. 22, the photoelectric conversion stack 29 has an oxide semiconductor layer 11A and a photoelectric conversion layer 14. Specifically, in the photoelectric conversion stack 29, the oxide semiconductor layer 11A and the photoelectric conversion layer 14 are stacked in this order from the pixel electrode 13 toward the counter electrode 15. The oxide semiconductor layer 11A is in contact with the photoelectric conversion layer 14.

[0242] The oxide semiconductor layer 11A contains, for example, at least one selected from the group consisting of indium oxide, gallium oxide, zinc oxide, and tin oxide.

[0243] The pixel electrode 13 has a storage electrode 13a and a readout electrode 13b that are spaced apart from each other. Specifically, the storage electrode 13a and the readout electrode 13b are spaced apart from each other via an insulating layer 17A.

[0244] In addition to the storage electrode 13a and the readout electrode 13, a connection portion 19a, a connection portion 19b, a pad portion 18a, and a pad portion 18b are provided in the insulating layer 17A.

[0245] The insulating layer 17B is provided on the insulating layer 17A. The insulating layer 17B has a through hole.

[0246] A part of the oxide semiconductor layer 11A penetrates the through hole of the insulating layer 17B and contacts the read electrode 13b. Another part of the oxide semiconductor layer 11A contacts the insulating layer 17B in a region that does not overlap with the storage electrode 13a in a plan view. Yet another part of the oxide semiconductor layer 11A contacts the insulating layer 17B in a region that overlaps with the storage electrode 13a in a plan view.

[0247] The storage electrode 13a and the pad portion 18a are electrically connected via a connection portion 19a. The readout electrode 13b and the through electrode 81 are electrically connected via a connection portion 19b and a pad portion 18b in this order.

[0248] In this embodiment, the vertical scanning circuit 52 is connected to the pixel electrode power supply line 41. A voltage can be applied from the vertical scanning circuit 52 to the storage electrode 13a via the pixel electrode power supply line 41. Also, a voltage can be applied from the vertical scanning circuit 52 to the counter electrode 15 via the counter electrode power supply line 21.

[0249] In this embodiment, the accumulation period and the transfer period are realized by adjusting the voltage of the counter electrode 15 and the voltage of the storage electrode 13a. During the accumulation period, the charge generated by the photoelectric conversion layer 14 is attracted to the storage electrode 13a and remains in the oxide semiconductor layer 11A, etc. In this manner, the charge is accumulated in the oxide semiconductor layer 11A, etc. During the transfer period, the charge in the oxide semiconductor layer 11A, etc. is transferred to the charge accumulation region FD via the readout electrode 13b and the through electrode 81.

[0250] In one specific example, after the accumulation period and before the transfer period, the potential of the charge accumulation region FD is reset by a reset control.

[0251] A transfer control electrode spaced apart from the storage electrode 13a and the readout electrode 13b may be provided between the storage electrode 13a and the readout electrode 13b in plan view. Adjusting the voltage of the transfer control electrode together with the voltage of the counter electrode 15 and the voltage of the storage electrode 13a makes it easier to prevent the charge generated by the photoelectric conversion layer 14 from moving toward the readout electrode 13b during the accumulation period.

[0252] A light-shielding film 39 is provided in the insulating layer 31. The light-shielding film 39 is provided so as to overlap with the readout electrode 13b in a plan view. The light-shielding film 39 can suppress photoelectric conversion in a portion of the photoelectric conversion layer 14 that overlaps with the readout electrode 13b in a plan view. This makes it easier to reset all the pixels at once, and makes it easier to realize a global shutter function.

[0253] As shown in FIG. 23, the photoelectric conversion stack 29 may have an oxide film 11B in addition to the oxide semiconductor layer 11A and the photoelectric conversion layer 14. Specifically, in the example of FIG. 23, in the photoelectric conversion stack 29, the oxide semiconductor layer 11A, the oxide film 11B, and the photoelectric conversion layer 14 are stacked in this order from the pixel electrode 13 toward the counter electrode 15. The oxide semiconductor layer 11A is in contact with the oxide film 11B. The oxide film 11B is in contact with the photoelectric conversion layer 14. The oxide film 11B can stabilize the oxide semiconductor layer 11A. In this example, the oxide film 11B is sufficiently thin. Therefore, charges can be moved via the oxide film 11B by the tunnel effect.

[0254] The oxide film 11B includes at least one of a tunnel oxide film and a metal oxide, for example. The tunnel oxide film is, for example, SiO X , SiON, SiOC and AlO Y The metal oxide includes at least one selected from the group consisting of, for example, tantalum oxide, titanium oxide, vanadium oxide, niobium oxide, tungsten oxide, zirconium oxide, hafnium oxide, scandium oxide, yttrium oxide, lanthanum oxide, gallium oxide, and magnesium oxide.

[0255] The technique of this embodiment can be applied to all of the embodiments described above.

[0256] As described above, according to the embodiments of the present disclosure, the effects of leakage current can be suppressed, and therefore an imaging device capable of capturing images with high image quality is provided.

[0257] In the above embodiment, a back-illuminated imaging device has been described as an example, but the present disclosure is also applicable to a front-illuminated imaging device. [Industrial Applicability]

[0258] According to an embodiment of the present disclosure, an imaging device capable of capturing high-quality images while suppressing the effects of leakage current is provided. The imaging device of the present disclosure is useful for, for example, image sensors, digital cameras, etc. The imaging device of the present disclosure can be used for medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc. [Explanation of symbols]

[0259] 1. Semiconductor substrate 1A,1B main surface 1i impurity region 10, 10A, 10B, 10C, 10D, 10E pixels 12,12X,12Y,12Z Photoelectric conversion section 13, 13X, 13Y, 13Z pixel electrodes 13a Storage electrode 13b Readout electrode 14, 14X, 14Y, 14Z Photoelectric conversion layer 15, 15X, 15Y, 15Z Counter electrodes 17A, 17B, 31, 70, 71 Insulating layer 21 Counter electrode power supply line 22, 22X, 22Y, 22Z Signal detection transistor 24, 24X, 24Y, 24Z Address transistor 26, 26X, 26Y, 26Z Reset transistor 22e, 22eX, 22eY, 22eZ, 24e, 24eX, 24eY, 24eZ, 26e, 26eX, 26eY, 26eZ Gate electrodes 26w gate wiring 26m,83 Electrical route 27X, 27Y, 27Z Photodiodes 28X, 28Y, 28Z Transfer transistor 29 Photoelectric conversion laminate 30 Micro Lenses 32 Dielectric layer 33 Fixed charge layer 32A,33A Flat membrane part 32B, 33B Cylindrical section 41 Pixel electrode power line 42 Power wiring 44, 44X, 44Y, 44Z Address signal lines 45,45X,45Y,45Z Vertical signal line 47, 47X, 47Y, 47Z Reset signal line 48 Voltage Line 52 Vertical scanning circuit 54 Horizontal signal readout circuit 56 Control circuit 58 Voltage supply circuit 60 Signal detection circuit 67n, 68an, 68bn, 68cn, 68dn Diffusion area 80 Wiring structure 80a,80b,80c wiring layer 81 Through electrode 82 Through hole 83c,83j,83k part 83s Line 100 Imaging device cp1, cp2, cp3 contact plugs FD,FDX,FDY,FDZ Charge storage area memX, memY, memZ, pdX, pdY, pdZ combination R1 Imaging area R2 Surrounding Area

Claims

1. A substrate; A first electrode; A second electrode; a photoelectric conversion layer located between the first electrode and the second electrode and configured to convert light into electric charges; a first transistor including a first impurity region which is one of a source and a drain, a second impurity region which is the other of the source and the drain, and a first gate electrode; a through electrode penetrating the substrate and electrically connecting the first electrode and the first impurity region; Equipped with The charge is accumulated in the first impurity region, In a plan view, a distance between the first impurity region and the through electrode is longer than a distance between the second impurity region and the through electrode; a first electrical path electrically connecting the through electrode and the first impurity region; a gate wiring connected to the first gate electrode; When a combination of the first gate electrode and the gate wiring is defined as a second electrical path, the first electrical path bypasses the second electrical path in a plan view. Imaging device.

2. A substrate, A first electrode; A second electrode; a photoelectric conversion layer located between the first electrode and the second electrode and configured to convert light into electric charges; a first transistor including a first impurity region which is one of a source and a drain, a second impurity region which is the other of the source and the drain, and a first gate electrode; a through electrode penetrating the substrate and electrically connecting the first electrode and the first impurity region; Equipped with The charge is accumulated in the first impurity region, In a plan view, a distance between the first impurity region and the through electrode is longer than a distance between the second impurity region and the through electrode; a first electrical path electrically connecting the through electrode and the first impurity region; a gate wiring connected to the first gate electrode; When a combination of the first gate electrode and the gate wiring is defined as a second electrical path, at least a part of the first electrical path and at least a part of the second electrical path overlap each other in a plan view. Imaging device.

3. The first gate electrode is located between the through electrode and the first impurity region in a plan view. The imaging device according to claim 1 .

4. a second transistor including a second gate electrode electrically connected to the first impurity region; In a plan view, a distance between the first impurity region and the through electrode is longer than a distance between the second gate electrode and the through electrode. The imaging device according to claim 1 .

5. In a plan view, an area of ​​the first impurity region is smaller than an area of ​​the second impurity region. The imaging device according to claim 1 .

6. a first electrical path electrically connecting the through electrode and the first impurity region; At least a portion of the first electrical path is curved in a plan view. The imaging device according to claim 1 .

7. At least a portion of the first electrode and at least a portion of the first impurity region overlap in a plan view. The imaging device according to claim 1 .

8. the first transistor is a reset transistor that resets the potential of the first impurity region; The imaging device according to claim 1 .

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