Electrode Structure of Semiconductor Element

Abstract

An object of the present invention is to provide an electrode structure capable of preventing a yield decrease even when a semiconductor element is miniaturized. 【Solution means】The electrode structure according to the present invention includes a pad mesa 13 in which a semiconductor layer is laminated in a mesa shape on an element substrate 10, an electrode layer 14 formed on the upper surface of the pad mesa 13, a dielectric layer 12 having an opening A1 that exposes the electrode layer 14 on the pad mesa 13, an insulating material 23 that covers the dielectric layer 12, a contact metal 22 formed on the surface of the insulating material 23, and a pedestal metal 21 that penetrates the insulating material 23 and connects the electrode layer 14 exposed from the opening A1 of the dielectric layer 12 and the contact metal 22.

Description

Technical Field

[0001] The present disclosure relates to a structure of an electrode included in a semiconductor element formed by laminating a semiconductor layer on a substrate.

Background Art

[0002] As the operating speed of semiconductor light-receiving elements increases, the light-receiving surface becomes smaller to reduce the element capacitance, and the light absorption layer becomes thinner to shorten the carrier transit time. On the other hand, in order to prevent sensitivity degradation, a structure in which light is incident from the back surface of the chip has become mainstream, and it has a chip form in which the chip is flip-chip mounted on a carrier substrate with wiring (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Furthermore, optical components are becoming smaller as a whole, and as the light-receiving element is miniaturized, the pad size for mounting is also becoming smaller. As a result, the inspection and mounting margins are reduced, the difficulty of these processes is increased, and this contributes to a decrease in yield.

[0005] FIG. 1 is a cross-sectional view for explaining a conventional electrode structure of a semiconductor element to be flip-chip mounted. In a conventional semiconductor element to be flip-chip mounted, it is necessary to prevent a metal wiring connecting the top of the element mesa and the electrode from contacting a layer on the element substrate 10 side or the like. For this reason, on the electrode side as well, the same semiconductor layer as the element mesa is laminated to form a pad mesa 13, and a metal electrode layer 14 is disposed on the top thereof as an electrode. By adopting such a structure, the electrode can also be separated from the element substrate, and the electrode layer 14 having a wiring function can be prevented from contacting a layer on the element substrate 10 side or the like.

[0006] The entire semiconductor element is covered with a dielectric layer 12 which is passivation, and only the top of this pad mesa 13 is open. That is, an electrode layer 14 disposed on the top of the pad mesa 13 appears in the opening A1. The electrode layer 14 appearing in the opening A1 becomes a semiconductor bump connection region when the semiconductor element is flip-chip mounted. Note that the area of the opening A1 is narrower than the area of the top of the pad mesa 13.

[0007] This semiconductor bump connection region is also an area where a contact probe for inspection is pressed against when inspecting the semiconductor element. If the contact probe hits the dielectric layer 12 and the dielectric layer 12 is damaged during inspection, it will not serve as a protective film and will become a defective product.

[0008] When the inspection is performed automatically, it is necessary to keep the contact position of the contact probe within the opening A1 from the start to the end of the inspection. As the semiconductor element is miniaturized, the opening A1 becomes smaller, the margin for deviation of the contact position is small, and a high-level adjustment technique is required for the inspection process.

[0009] Furthermore, during flip-chip mounting, if the position of the solder bump formed on the substrate side where the semiconductor element is mounted is misaligned with the position of the opening A1, the bonding area becomes smaller and the strength also decreases. As the semiconductor element is miniaturized, the opening A1 becomes smaller and the misalignment margin also decreases, so a high-level position adjustment technique is also required during mounting.

[0010] As described above, the miniaturization of the semiconductor element leads to a reduction in the area of the opening A1, and high-level position adjustment (high alignment accuracy) is required during inspection and mounting, resulting in the problem that it is difficult to maintain the yield. Therefore, an object of the present invention is to provide an electrode structure that can prevent a decrease in yield even when the semiconductor element is miniaturized in order to solve the above problems.

Means for Solving the Problems

[0011] To achieve the above object, the electrode structure according to the present invention covers the surface of the semiconductor element with a thick film insulating material and forms a contact metal thereon having a larger area than the conventional pad opening A1.

[0012] Specifically, the electrode structure according to the present invention a pad mesa in which a semiconductor layer is laminated in a mesa shape on an element substrate, an electrode layer formed on the upper surface of the pad mesa, a dielectric layer having an opening for exposing the electrode layer on the pad mesa, an insulating material covering the dielectric layer, a contact metal formed on the surface of the insulating material, a pedestal metal that penetrates the insulating material and connects the electrode layer exposed from the opening of the dielectric layer and the contact metal, and includes.

[0013] By covering the surface of the semiconductor element with a new insulating material, it is possible to avoid the passivation dielectric layer from being damaged by the contact probe. Therefore, the present invention can provide an electrode structure that can prevent a reduction in yield even when the semiconductor element is miniaturized.

[0014] Furthermore, the electrode structure according to the present invention is characterized in that the area of the contact metal is larger than the area of the electrode layer exposed from the opening. This electrode structure can make the area of the contact metal wider than the pad opening A1. Therefore, it is possible to increase the margin for position adjustment of the contact probe in automatic inspection and position adjustment during mounting (relax the alignment accuracy). Therefore, the present invention can provide an electrode structure that can prevent a reduction in yield even when the semiconductor element is miniaturized.

[0015] Also, the semiconductor element according to the present invention is a semiconductor element including the electrode structure, comprising an element mesa in which the semiconductor layer is laminated in a mesa shape on the element substrate, It is characterized in that the upper surface of the element mesa and the upper surface of the pad mesa are connected by the electrode layer.

[0016] In addition, the electrode manufacturing method according to the present invention is as follows. A pad mesa step of laminating a semiconductor layer in a mesa shape on an element substrate to form a pad mesa; An organic material forming step of covering the pad mesa with an organic material; An electrode layer forming step of forming an electrode layer on the upper surface of the pad mesa; A dielectric layer forming step of covering the electrode layer with a dielectric layer; An insulating material forming step of covering the dielectric layer with an insulating material; A contact metal forming step of forming a contact metal on the surface of the insulating material; It has, and between the insulating material forming step and the contact metal forming step A pedestal metal forming step of forming a pedestal metal that penetrates the insulating material and connects the electrode layer exposed from the opening of the dielectric layer and the contact metal is performed.

[0017] Note that the above inventions can be combined as much as possible.

Effects of the Invention

[0018] The present invention can provide an electrode structure that can prevent a decrease in yield even when a semiconductor element is miniaturized.

Brief Description of the Drawings

[0019]

Figure 1

Figure 2

Figure 3

Embodiments for Carrying Out the Invention

[0020] Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, components having the same reference numerals indicate the same components as each other.

[0021] [Comparative Example] FIG. 1 is a diagram for explaining the electrode structure of the comparative example. The area of the opening A1 formed in the dielectric layer 12 which is passivation is smaller than the area of the top of the pad mesa 13. When the semiconductor element is miniaturized, the pad mesa 13 also becomes smaller, and the opening A1 becomes even smaller. For this reason, it becomes difficult to bring the contact probe into contact with the electrode layer 14 in the opening A1 without destroying the dielectric layer 12 during inspection. Furthermore, the reduction of the opening A1 also results in a smaller solder bump connection area when flip-chip mounting on a wired substrate, and high alignment accuracy is required.

[0022] [Embodiment] FIG. 2 is a cross-sectional view for explaining the electrode structure of the present embodiment. This electrode structure includes a pad mesa 13 in which a semiconductor layer is laminated in a mesa shape on an element substrate 10, an electrode layer 14 formed on the upper surface of the pad mesa 13, a dielectric layer 12 having an opening A1 that exposes the electrode layer 14 on the pad mesa 13, an insulating material 23 covering the dielectric layer 12, a contact metal 22 formed on the surface of the insulating material 23, a pedestal metal 21 that penetrates the insulating material 23 and connects the electrode layer 14 exposed from the opening A1 of the dielectric layer 12 and the contact metal 22, and comprises.

[0023] In the present embodiment, the case where the semiconductor element is a back-illuminated light receiving element will be described as an example. The element substrate 10 is a semi-insulating InP substrate. The pad mesa 13 is formed in a mesa shape with a plurality of semiconductor layers stacked thereon. For example, in the pad mesa 13, three InGaAs layers are stacked in the order of n-type, intrinsic, and p-type from the element substrate 10 side. As will be described later, this plurality of semiconductor layers is the same as the semiconductor layers constituting the element mesa formed on the left side of FIG. 2. The periphery of the pad mesa 13 is filled with a passivation 11 of an organic material such as BCB (Benzocyclobutene) or polyimide. The electrode layer 14 serves as a wiring that covers the upper surface of the pad mesa and is electrically connected to the element mesa formed on the left side of FIG. 2. The electrode layer 14 is, for example, copper (Cu). The dielectric layer 12 is, for example, SiN. The insulating material 23 is an organic material such as BCB or polyimide, for example. The pedestal metal 21 and the contact metal 22 are, for example, gold (Au). Note that the size A2 of the contact metal 22 is preferably larger than the size A1 of the opening, that is, the area of the contact metal 22 is preferably larger than the area of the electrode layer 14 exposed from the opening A1.

[0024] FIG. 3 is a process diagram for explaining a method of manufacturing a light receiving element having the electrode structure of FIG. 2. Semiconductor stacking step S01: Using an epitaxial layer growth technique such as MOCVD or MBE, three InGaAs layers are stacked on the element substrate 10 in the order of n-type, intrinsic, and p-type. Mesa formation step S02: Using wet etching and dry etching techniques, the InGaAs layer in the region other than the element mesa and the pad mesa is removed down to the element substrate 10. Organic material formation step S03: An organic material 11 such as BCB or polyimide is applied so as to cover the element mesa and the pad mesa. Then, using techniques such as photolithography and dry etching, the upper organic material is processed to expose the tops of the element mesa and the pad mesa. Electrode layer formation step S04: As a method of forming the tops of the element mesa and the pad mesa and the wiring portion connecting them, after patterning by photolithography using a two-layer resist or a negative resist, the metal of the electrode layer 14 is vapor-deposited and the lift-off method is used. Dielectric layer formation step S05: Using CVD technology, the dielectric layer 12 is laminated over the entire surface. Opening formation step S06: Using lithography technology and etching technology, the portion that will become the opening A1 is removed from the dielectric layer 12 to expose the electrode layer 14. Pedestal metal formation step S07: As a method of forming the pedestal metal inside the opening A1, after patterning by photolithography using a two-layer resist or a negative resist, the pedestal metal 21 is vapor-deposited and the lift-off method is used. Insulating material lamination step S08: An insulating material 23 such as BCB or polyimide is applied so as to cover the dielectric layer 12 and the pedestal metal 21. Contact hole formation step S09: Using lithography technology and etching technology, the top surface of the pedestal metal 21 is exposed. Contact metal formation step S10: As a method of forming the contact metal, after patterning by photolithography using a two-layer resist or a negative resist, the metal of the contact metal 22 is vapor-deposited and the lift-off method is used.

[0025] The "pad mesa step" described in the claims is from the semiconductor lamination step S01 to the organic material formation step S03. The "electrode layer formation step" described in the claims is the electrode layer formation step S04. The "dielectric layer formation step" described in the claims is the dielectric layer formation step S05 and the opening formation step S06. The "pedestal metal formation step" described in the claims is the pedestal metal formation step S07. The "insulating material formation step" described in the claims is the insulating material lamination step S08 and the contact hole formation step S09. The "contact metal formation step" described in the claims is the contact metal formation step S10.

[0026] According to this manufacturing method, it is possible to make the area of the contact metal larger than the area of the top of the pad mesa when viewed from above. Therefore, the accuracy margin for probe contact during inspection and position adjustment during flip chip mounting can be increased.

[0027] (Other embodiments) In the above embodiment, the electrode structure of the light receiving element has been described, but the present invention is not limited to the electrode structure of the light receiving element. The electrode structure of the present invention can also be applied to a semiconductor element (for example, a semiconductor laser, etc.) in which a plurality of semiconductor layers are stacked in a mesa shape.

Explanation of reference numerals

[0028] 10: Element substrate 11: Passivation (organic material) 12: Dielectric layer 13: Pad mesa 14: Electrode layer 21: Pedestal metal 22: Contact metal 23: Insulating material

Claims

1. a pad mesa in which a semiconductor layer is laminated in a mesa shape on an element substrate; an element mesa is formed on the element substrate by laminating the semiconductor layers in a mesa shape on the element substrate so as to be separated from the pad mesa; and an organic material is provided around the pad mesa and filling the gap between the pad mesa and the element mesa; an electrode layer that is wired on an upper surface of the organic material so as to connect an upper surface of the element mesa and an upper surface of the pad mesa; a dielectric layer having an opening exposing the electrode layer on the pad mesa; an insulating material covering the dielectric layer; a contact metal formed on a surface of the insulating material; a base metal that penetrates the insulating material and connects the electrode layer exposed from the opening of the dielectric layer to the contact metal; Equipped with an area of ​​the contact metal is larger than an area of ​​the electrode layer exposed from the opening, and the contact metal is sized so as not to cover the element mesa;

2. a pad mesa process in which a semiconductor layer is laminated in a mesa shape on an element substrate, and a portion of the semiconductor layer is removed down to the element substrate to form a pad mesa on the element substrate, the pad mesa being separated from the element mesa; an organic material forming step of filling a space between the pad mesa and the element mesa with an organic material; an electrode layer forming step of wiring an electrode layer on the upper surface of the organic material so as to connect the upper surface of the element mesa and the upper surface of the pad mesa; a dielectric layer forming step of covering the electrode layer with a dielectric layer; an insulating material forming step of covering the dielectric layer with an insulating material; a contact metal forming step of forming a contact metal on a surface of the insulating material; between the insulating material forming step and the contact metal forming step, performing a base metal forming step of forming a base metal that penetrates the insulating material and connects the electrode layer exposed from the opening of the dielectric layer to the contact metal; The area of ​​the contact metal is larger than the area of ​​the electrode layer exposed from the opening, and the contact metal is sized so as not to cover the element mesa. The electrode manufacturing method according to the present invention is characterized in that

Images