Method for manufacturing semiconductor device and semiconductor device

Abstract

A method for producing a semiconductor device according to one embodiment of the present disclosure comprises: forming a multilayer body by alternately stacking insulating films and sacrificial films on a substrate; forming a through hole in the multilayer body, the through hole extending in the stacking direction of the multilayer body; forming a block insulating film, a charge collecting film, a tunnel insulating film and a channel film in this order on the inner surface of the through hole; providing the multilayer body with a slit that is different from the through hole and extends in the stacking direction of the multilayer body; removing the sacrificial films via the slit so as to form a cavity between insulating films that are adjacent thereto; forming a first metal oxide film on the inner surface of the cavity; forming a second metal oxide film on the first metal oxide film, the second metal oxide film being crystallized at a lower temperature than the first metal oxide film; and burying an electrode layer in the cavity.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.

Background Art

[0002] A semiconductor device having a stacked structure in which a tunnel oxide film, a charge trap film, a blocking oxide film, and a gate electrode are formed in this order from the bottom on a silicon substrate is known (see, for example, Patent Document 1). In the semiconductor device described in Patent Document 1, the blocking oxide film includes a crystalline film provided on the side of the charge trap film and an amorphous film provided on the upper layer of the crystalline film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a technique capable of thinning a block oxide film and improving etching resistance.

Means for Solving the Problems

[0005] A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes forming a laminate by alternately laminating an insulating film and a sacrificial film on a substrate; forming a through hole extending in the lamination direction of the laminate in the laminate; forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film in this order on the inner surface of the through hole; forming a slit extending in the lamination direction of the laminate in the laminate separately from the through hole; forming a cavity between adjacent insulating films by removing the sacrificial film through the slit; forming a first metal oxide film on the inner surface of the cavity; and So as to cover the first metal oxide film forming a second metal oxide film that crystallizes at a temperature lower than that of the first metal oxide film on the first metal oxide film. [Effect of the Invention]

[0006] According to the present disclosure, the block oxide film can be thinned and the etching resistance can be improved. [Brief Description of the Drawings]

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0008] Hereinafter, non-limiting exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In all the accompanying drawings, the same or corresponding members or components are denoted by the same or corresponding reference numerals, and redundant descriptions are omitted.

[0009] 〔3D NAND Memory〕 In a 3D NAND memory, for example, AlO is used as a block oxide film, and tungsten is used as a control gate (word line). The block oxide film is crystallized by heat treatment after film formation in order to have high etching resistance against an etching agent used in a later process, for example, a mixed solution of PAN (H 3 PO 4 , HNO 3 , CH 3 COOH).

[0010] In a 3D NAND memory, as the device is miniaturized, when the control gate becomes thinner, the resistance value increases, which may cause a decrease in the operation speed and an increase in power consumption. Therefore, it has been studied to reduce the resistance value of the control gate and improve the operation speed or reduce the power consumption by reducing the film thickness of the block oxide film and increasing the film thickness of the control gate instead.

[0011] However, when the film thickness of the block oxide film is reduced, the temperature of the heat treatment for crystallizing the block oxide film increases. Further reducing the film thickness of the block oxide film may prevent the block oxide film from crystallizing. Thus, when the heat treatment temperature increases, the films constituting the 3D NAND memory, such as the block insulating film, the charge trapping film, and the tunnel insulating film, may be affected by heat, and the memory characteristics may deteriorate.

[0012] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment capable of thinning a block oxide film and improving etching resistance will be described.

[0013] 〔First Embodiment〕 With reference to FIGS. 1 to 6, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described. Hereinafter, a method for manufacturing a 3D NAND memory as a semiconductor device will be described.

[0014] First, as shown in FIG. 1(a), an insulating film 12 and a sacrificial film 13 are alternately laminated on a substrate 11 by, for example, an atomic layer deposition (ALD) method or a chemical vapor deposition (CVD) method to form a laminate 14. The substrate 11 is a semiconductor substrate such as a single crystal silicon substrate, for example. The insulating film 12 is formed of, for example, silicon oxide. The sacrificial film 13 is formed of, for example, silicon nitride.

[0015] Next, as shown in FIG. 1(b), a memory hole 15 is formed in the laminate 14 by, for example, a reactive ion etching (RIE) method. The memory hole 15 is formed so as to penetrate the laminate 14 and reach the substrate 11.

[0016] Next, as shown in FIG. 1(c), a block insulating film 16, a charge trapping film 17, and a tunnel insulating film 18 are formed in this order on the inner surface of the memory hole 15 by, for example, the ALD method or the CVD method. The block insulating film 16 is formed of, for example, silicon oxide. The charge trapping film 17 is formed of, for example, silicon nitride. The charge trapping film 17 has trap sites for trapping (trapping) charges. The tunnel insulating film 18 is formed of, for example, silicon oxide.

[0017] Next, as shown in FIG. 2(a), for example, by an ALD method or a CVD method, a channel film 19 is formed on the tunnel insulating film 18 in the memory hole 15. The channel film 19 is formed of, for example, amorphous silicon. Subsequently, the channel film 19, the tunnel insulating film 18, the charge trapping film 17, and the block insulating film 16 located on the bottom surface of the memory hole 15 are removed, and a part of the substrate 11 exposed by the removal is removed. Subsequently, the channel film 19 is formed again on the substrate 11 in the memory hole 15 and on the tunnel insulating film 18, the charge trapping film 17, and the block insulating film 16. Subsequently, the channel film 19 is crystallized by an annealing process.

[0018] Next, as shown in FIG. 2(b), for example, by an ALD method or a CVD method, a core film 20 is formed on the channel film 19 in the memory hole 15, and the inside of the memory hole 15 is filled with the core film 20. The core film 20 is formed of, for example, silicon oxide.

[0019] Next, as shown in FIG. 2(c), for example, by RIE, a slit (not shown) extending in the stacking direction of the laminate 14 is formed separately from the memory hole 15. Subsequently, by wet etching, the sacrificial film 13 of the laminate 14 is selectively removed through the slit. Thereby, a cavity 21 is formed between the adjacent insulating films 12.

[0020] Next, as shown in FIG. 3(a), for example, by an ALD method or a CVD method, a block oxide film 22 is formed on the inner surface of the cavity 21. The block oxide film 22 is formed of, for example, aluminum oxide (AlO). The film thickness of the block oxide film 22 is, for example, 2 nm to 3 nm. When forming the block oxide film 22, it is preferable to use an inorganic raw material such as AlCl 3 etc. Thereby, the block oxide film 22 can be uniformly formed on the inner surface of the narrow and deep cavity 21 in a fishbone shape. The block oxide film 22 is amorphous immediately after being formed on the inner surface of the cavity 21.

[0021] Next, as shown in FIG. 3(b), a template film 23 is formed on the block oxide film 22 in the cavity 21 by, for example, the ALD method or the CVD method. The template film 23 crystallizes at a temperature lower than that of the block oxide film 22 and has an etching selectivity ratio with the material forming the block oxide film 22. For example, when the block oxide film 22 is formed of AlO, the template film 23 is formed of ZrO, MgO, TiO, NiO, SrTiO 3 or a combination thereof. The film thickness of the template film 23 is, for example, 0.5 nm to 1.0 nm. The template film 23 is preferably formed of MgO, TiO, SrTiO 3 or a combination thereof. Thereby, the lattice mismatch with AlO forming the block oxide film 22 is reduced, so that the template film 23 can be formed without causing strain or the like. Further, the template film 23 is more preferably formed of SrTiO 3 . This is because SrTiO 3 crystallizes by heat treatment at about 600° C. and has a lattice constant close to that of AlO forming the block oxide film 22 (the lattice mismatch is about 1.3%).

[0022] Next, as shown in FIG. 3(c), the block oxide film 22 is crystallized by subjecting the substrate 11 to a heat treatment. The crystallized block oxide film 22a has high etching resistance to an etchant used for etching the electrode layer 24 described later. At this time, since the template film 23 that crystallizes at a temperature lower than that of the block oxide film 22 is formed on the block oxide film 22, by heating the substrate 11 to a temperature equal to or higher than the temperature at which the template film 23 crystallizes, the template film 23 and the block oxide film 22 are crystallized. For this reason, the block oxide film 22 crystallizes at a temperature lower than when the template film 23 is not formed on the block oxide film 22. In other words, by forming the template film 23 on the block oxide film 22, the temperature at which the block oxide film 22 is crystallized can be lowered. Thereby, when the block oxide film 22 is crystallized, it is possible to suppress the memory characteristics from deteriorating due to the heat influence on the block insulating film 16, the charge trapping film 17, the tunnel insulating film 18, etc. For example, when the film thickness is 2.5 nm, the crystallization temperature of AlO is 950 ° C, that of ZrO is 500 ° C, that of TiO is less than 400 ° C, and that of SrTiO 3 is 600 ° C. Therefore, for example, when the block oxide film 22 is formed of AlO and the template film 23 is formed of any of ZrO, TiO, SrTiO 3 , by performing a heat treatment at a temperature lower than 800 ° C, the AlO which is the block oxide film 22 can be crystallized.

[0023] Next, as shown in FIG. 4(a), the crystallized template film 23a is removed by, for example, wet cleaning. As a result, only the block oxide film 22a with a thin film thickness and crystallized remains on the inner surface of the cavity 21. As the cleaning liquid used for wet cleaning, HPM (Hydrochloric hydrogen Peroxide Mixture: HCl, H 2 O 2 , H 2 O mixture), BHF (Buffered HF: NH 4 F, HF, H 2A mixture of O) etc. can be used. By the way, when the template film 23 is formed on the block oxide film 22 in the fishbone-shaped cavity 21, as shown in FIG. 6, the template film 23 may not be conformally formed on the inner surface of the cavity 21. However, the template film 23 is removed after crystallizing the block oxide film 22. Therefore, even when the template film 23 is not conformally formed, only the thinly crystallized block oxide film 22a can remain on the inner surface of the cavity 21.

[0024] Next, as shown in FIG. 4(b), for example, by the ALD method or the CVD method, an electrode layer 24 is formed on the block oxide film 22 in the cavity 21. At this time, since the crystallized block oxide film 22a is thinly formed on the inner surface of the cavity 21, the thickness of the electrode layer 24 formed in the cavity 21 can be increased. As a result, the resistance of the electrode layer 24 can be lowered, so that the operating speed of the memory can be increased. Also, the electrode layer 24 can be formed outside the cavity 21. The electrode layer 24 is formed of, for example, a laminate of titanium nitride and tungsten.

[0025] Next, as shown in FIG. 4(c), for example, by wet etching, the electrode layer 24 formed outside the cavity 21 is removed. As the etching agent used for wet etching, for example, PAN (H 3 PO 4 , HNO 3 , CH 3 COOH mixture) can be used. At this time, the insulating film 12 is covered with the crystallized block oxide film 22a, and the crystallized block oxide film 22a has high etching resistance to the etching agent. Therefore, the insulating film 12 is prevented from being etched by the etching agent.

[0026] Next, as shown in FIG. 5, for example, by the RIE method or the CMP method, the block insulating film 16, charge trapping film 17, tunnel insulating film 18, channel film 19, and core film 20 located on the laminate 14 are removed, and the upper surface of the laminate 14 is planarized. As a result, a columnar portion 25 having a core film 20, a channel film 19, a tunnel insulating film 18, a charge trapping film 17, and a block insulating film 16 is formed. Subsequently, for example, by the CVD method, an insulating layer 26 is formed on the upper surface of the laminate 14. The insulating layer 26 is formed of, for example, silicon oxide. Subsequently, contacts and bit lines connected to the channel film 19 are formed. Thus, a 3D NAND memory is manufactured.

[0027] As described above, according to the first embodiment, after forming the template film 23 that crystallizes at a temperature lower than that of the block oxide film 22 on the block oxide film 22, the substrate 11 is heat-treated to crystallize the block oxide film 22, and then the template film 23 is removed. In this way, since the template film 23 is formed on the block oxide film 22, the temperature at which the block oxide film 22 is crystallized can be lowered, and the block oxide film 22 can be thinned. Further, since the block oxide film 22 is crystallized, the etching resistance against the etching agent used for etching the electrode layer 24 can be improved.

[0028] 〔Second Embodiment〕 With reference to FIGS. 7 and 8, an example of a method for manufacturing a semiconductor device according to the second embodiment will be described. The method for manufacturing a semiconductor device according to the second embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in that a capping film 31 is formed on the block oxide film 22, the capping film 31 is crystallized, and an electrode layer 24 is formed on the crystallized capping film 31a. Hereinafter, the description will focus on the differences from the method for manufacturing a semiconductor device according to the first embodiment.

[0029] First, the steps up to the step of forming the block oxide film 22 on the inner surface of the cavity 21 are performed by the same method as described with reference to FIGS. 1(a) to 1(c), FIGS. 2(a) to 2(c), and FIG. 3(a). In the second embodiment, the film thickness of the block oxide film 22 is, for example, 1.5 nm.

[0030] Next, as shown in FIG. 7(a), for example, by the ALD method or the CVD method, a capping film 31 is formed on the block oxide film 22 in the cavity 21. The capping film 31 is a film that crystallizes at a temperature lower than that of the block oxide film 22. For example, when the block oxide film 22 is formed of AlO, the capping film 31 is formed of ZrO, HfO, or a combination thereof. Further, the capping film 31 may be formed of HfSiO obtained by adding Si to HfO. The film thickness of the capping film 31 is, for example, 0.5 nm to 1.5 nm. The capping film 31 is formed, for example, by alternately supplying a metal raw material and an oxidizing agent (e.g., O 3 ) to the substrate 11 and repeating the adsorption of the metal raw material to the substrate 11 and the oxidation of the adsorbed metal raw material. Thereby, the capping film 31 is conformally formed on the block oxide film 22 in the cavity 21. As the metal material, for example, tetrakisethylmethylaminozirconium (TEMAZ), trisdimethylaminocyclopentadienyl zirconium ((C 5 H 5 )Zr[N(CH 3 ) 2 3 )), tetrakisdimethylaminohafnium (TDMAH), trisdimethylaminocyclopentadienyl hafnium (HfCp(NMe 2 ) 3 ) can be used.

[0031] ​Next, as shown in FIG. 7(b), by subjecting the substrate 11 to heat treatment, the capping film 31 is crystallized. The crystallized capping film 31a has high etching resistance to the etching agent used for etching the electrode layer 24 described later. At this time, a capping film 31 that crystallizes at a temperature lower than that of the block oxide film 22 is formed on the block oxide film 22, and the capping film 31 is not removed in the process described later. Therefore, since it is not necessary to crystallize the block oxide film 22, the heat treatment temperature may be equal to or higher than the temperature at which the capping film 31 crystallizes. Further, even if ZrO, HfO, and HfSiO are amorphous, they have etching resistance to the etching agent used for etching the electrode layer 24 described later. Therefore, the heat treatment temperature may be lower than the temperature at which the capping film 31 crystallizes, or the heat treatment may not be performed. However, when ZrO, HfO, and HfSiO are crystallized, the etching resistance to the etching agent used for etching the electrode layer 24 becomes particularly high. Therefore, it is preferable to subject the capping film 31 to heat treatment at a temperature equal to or higher than the temperature at which the capping film 31 crystallizes. Thus, since the capping film 31 is formed on the block oxide film 22, the heat treatment temperature can be lowered. Thereby, it is possible to suppress the memory characteristics from deteriorating due to the heat influence on the block insulating film 16, the charge trapping film 17, the tunnel insulating film 18, and the like.

[0032] Next, as shown in FIG. 7(c), for example, by the ALD method or the CVD method, the electrode layer 24 is formed on the capping film 31 in the cavity 21. At this time, since the block oxide film 22 and the crystallized capping film 31a are thinly formed on the inner surface of the cavity 21, the thickness of the electrode layer 24 formed in the cavity 21 can be increased. As a result, the resistance of the electrode layer 24 can be lowered, so that the operating speed of the memory can be increased. Further, the electrode layer 24 can also be formed outside the cavity 21. The electrode layer 24 is formed by laminating, for example, titanium nitride and tungsten.

[0033] Next, as shown in FIG. 8(a), for example, by wet etching, the electrode layer 24 formed outside the cavity 21 is removed. As the etching agent used for wet etching, for example, a mixed solution of PAN (H 3 PO 4 , HNO 3 , CH 3 COOH) can be used. At this time, the insulating film 12 and the block oxide film 22 are covered with the crystallized capping film 31a, and the crystallized capping film 31a has high etching resistance to the etching agent. Therefore, the insulating film 12 and the block oxide film 22 are prevented from being etched by the etching agent.

[0034] Next, as shown in FIG. 8(b), for example, by the RIE method or the CMP method, the block insulating film 16, the charge trapping film 17, the tunnel insulating film 18, the channel film 19, and the core film 20 located on the laminate 14 are removed, and the upper surface of the laminate 14 is planarized. Thereby, the columnar portion 25 having the core film 20, the channel film 19, the tunnel insulating film 18, the charge trapping film 17, and the block insulating film 16 is formed. Subsequently, for example, by the CVD method, an insulating layer 26 is formed on the upper surface of the laminate 14. The insulating layer 26 is formed of, for example, silicon oxide. Subsequently, a contact connected to the channel film 19 and a bit line are formed. Thus, a 3D NAND memory is manufactured.

[0035] As described above, according to the second embodiment, after forming the capping film 31 that crystallizes at a temperature lower than that of the block oxide film 22 on the block oxide film 22, the substrate 11 is heat-treated to crystallize the capping film 31. Then, without removing the crystallized capping film 31a in a subsequent process, the electrode layer 24 is formed on the crystallized capping film 31a. As a result, since the crystallized capping film 31a functions as an etching stop film for the etching agent used for etching the electrode layer 24, it is not necessary to crystallize the block oxide film 22. Therefore, the block oxide film 22 can be thinned. Further, since the crystallized capping film 31a has high etching resistance against the etching agent used for etching the electrode layer 24, the etching resistance against the etching agent can be improved.

[0036] In addition, it is known that non-crystallized AlO (amorphous AlO) exhibits better erasure characteristics than crystalline AlO. Therefore, according to the second embodiment in which the block oxide film 22 can be formed of amorphous AlO, the erasure characteristics can be improved.

[0037] In the above embodiment, the memory hole 15 is an example of a through hole, the block oxide film 22 is an example of a first metal oxide film, and the template film 23 and the capping film 31 are examples of a second metal oxide film.

[0038] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The above embodiments may be omitted, substituted, or changed in various forms without departing from the scope and spirit of the appended claims.

[0039] This international application claims the priority of U.S. Application No. 17 / 331,813 filed with the United States Patent and Trademark Office on May 27, 2021, the entire contents of which are incorporated herein by reference.

Description of Reference Numerals

[0040] 11 Substrate 12 Insulating film 13 Sacrificial film 14 Laminate 15 Memory hole 16 Block insulating film 17 Charge trapping film 18 Tunnel insulating film 19 Channel film 21 Cavity 22 Block oxide film 23 Template film 24 Electrode layer 31 Capping film

Claims

1. Forming a laminate by alternately laminating an insulating film and a sacrificial film on a substrate; Forming a through hole extending in the lamination direction of the laminate in the laminate; Forming a block insulating film, a charge trapping film, a tunnel insulating film, and a channel film in this order on the inner surface of the through hole; Forming a slit extending in the lamination direction of the laminate in the laminate separately from the through hole; Removing the sacrificial film through the slit to form a cavity between adjacent insulating films; Forming a first metal oxide film on the inner surface of the cavity; Forming a second metal oxide film that crystallizes at a temperature lower than that of the first metal oxide film so as to cover the first metal oxide film on the first metal oxide film; Embedding an electrode layer in the cavity; A method for manufacturing a semiconductor device, comprising:

2. After forming the second metal oxide film, heat-treating the substrate to crystallize the first metal oxide film; After crystallizing the first metal oxide film, removing the second metal oxide film; A method for manufacturing a semiconductor device according to claim 1, comprising:

3. The first metal oxide film is formed of AlO; The second metal oxide film is formed of ZrO, MgO, TiO, NiO, SrTiO ３ or a combination thereof, A method for manufacturing a semiconductor device according to claim 2.

4. After forming the second metal oxide film, heat-treating the substrate to crystallize the second metal oxide film, comprising: A method for manufacturing a semiconductor device according to claim 1.

5. The temperature during heat-treating the substrate is higher than the temperature at which the second metal oxide film crystallizes and lower than the temperature at which the first metal oxide film crystallizes; A method for manufacturing a semiconductor device according to claim 4.

6. The first metal oxide film is formed of AlO; The second metal oxide film is formed of ZrO, HfO, or a combination thereof; A method for manufacturing a semiconductor device according to claim 4.

7. Si is added to the ZrO and / or the HfO; A method for manufacturing a semiconductor device according to claim 6.

8. Forming the second metal oxide film comprises: Supplying a metal raw material; Supplying an oxidizing agent for oxidizing the metal raw material; Comprising: A method for manufacturing a semiconductor device according to claim 4.

9. A channel film provided in a laminate having alternately laminated insulating films and electrode layers and extending in the lamination direction of the laminate; A tunnel insulating film, a charge trapping film, a block insulating film, a first metal oxide film, and a second metal oxide film, which are provided in this order from the side of the channel film between the electrode layer and the channel film; having; the second metal oxide film is formed so as to cover the first metal oxide film with a material having a crystallization temperature lower than that of the first metal oxide film; a semiconductor device.

Images