Semiconductor device, semiconductor module, and electronic device

Abstract

Provided is a semiconductor device comprising: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor and bonded to a first surface of the barrier layer; an insulating layer provided on a second surface of the barrier layer opposite the first surface, and having an opening exposing the barrier layer; a gate electrode embedded in the opening; a source electrode and a drain electrode which are provided on the second surface of the barrier layer on both sides sandwiching the gate electrode; and a material layer including a metal material or a semiconductor material and provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and an electronic device.

Background Art

[0002] In recent years, a hetero field effect transistor (HFET) having a two-dimensional electron gas formed at the interface of a hetero-junction of a compound semiconductor as a channel has been proposed (for example, Patent Document 1).

[0003] Since the two-dimensional electron gas has high electron mobility and high sheet electron density, the HFET having the two-dimensional electron gas as a channel is expected to be a transistor capable of low resistance, high breakdown voltage, and high-speed operation. For example, the HFET is expected to be applied to a power device or an RF (Radio Frequency) device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] However, in an HFET using a compound semiconductor, interface traps that trap charges may occur at the interface between the compound semiconductor and the insulator. Since the interface traps may cause a performance degradation of the HFET when a high voltage is applied, it is desirable to suppress the generation of the interface traps in the HFET.

[0006] Therefore, it is desirable to provide a semiconductor device, a semiconductor module, and an electronic device in which a performance degradation due to the application of a high voltage is suppressed.

[0007] A semiconductor device according to an embodiment of the present disclosure includes a barrier layer containing a first compound semiconductor, a channel layer containing a second compound semiconductor and joined to the barrier layer on a first surface, an insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening exposing the barrier layer, a gate electrode provided to fill the opening, a source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode, and a material layer containing a metal material or a semiconductor material and provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode.

[0008] A semiconductor module according to an embodiment of the present disclosure includes a semiconductor device including a barrier layer containing a first compound semiconductor, a channel layer containing a second compound semiconductor and joined to the barrier layer on a first surface, an insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening exposing the barrier layer, a gate electrode provided to fill the opening, a source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode, and a material layer containing a metal material or a semiconductor material and provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode.

[0009] An electronic device according to an embodiment of the present disclosure includes a semiconductor device including a barrier layer containing a first compound semiconductor, a channel layer containing a second compound semiconductor and joined to the barrier layer on a first surface, an insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening exposing the barrier layer, a gate electrode provided to fill the opening, a source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode, and a material layer containing a metal material or a semiconductor material and provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode.

[0010] According to a semiconductor device, a semiconductor module, and an electronic device according to an embodiment of the present disclosure, a material layer including a metal material or a semiconductor material is provided between a gate electrode and a drain electrode on a barrier layer joined to a channel layer. The density of interface traps generated between the material layer and the barrier layer is lower than the density of interface traps generated between the insulating layer and the barrier layer. Thereby, for example, the semiconductor device can reduce the density of interface traps between the gate electrode and the drain electrode.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments in the present disclosure will be described in detail with reference to the drawings. The embodiments described below are a specific example of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Also, the arrangement, dimensions, dimensional ratios, etc. of each component of the present disclosure are not limited to the states shown in the respective drawings.

[0013] Note that the description will be made in the following order. 1. First Embodiment 1.1. Configuration Example 1.2. Operation 1.3. Manufacturing Method 1.4. Modification 2. Second Embodiment 3. Third Embodiment

[0014] <1. First Embodiment> (1.1. Configuration Example) Referring to FIGS. 1 and 2, a configuration example of a semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 1 is a longitudinal sectional view showing the configuration of a semiconductor device 100 according to the present embodiment. FIG. 2 is a top view showing the configuration of the semiconductor device 100 according to the present embodiment.

[0015] As shown in FIGS. 1 and 2, the semiconductor device 100 according to the present embodiment includes a substrate 110, a buffer layer 120, a channel layer 130, a barrier layer 140, a gate electrode 170, a source electrode 150S, a drain electrode 150D, an insulating layer 160, and a material layer 180. The semiconductor device 100 is a HFET having a two-dimensional electron gas 2DEG generated at the hetero-junction interface of the channel layer 130 and the barrier layer 140 due to the polarization of the channel layer 130 and the barrier layer 140 as a channel.

[0016] Although not shown, the gate electrode 170, the source electrode 150S, and the drain electrode 150D may be electrically connected to a wiring layer via contacts provided on top of each electrode, respectively.

[0017] The substrate 110 is a substrate made of a semiconductor material. Specifically, the substrate 110 may be a substrate made of a III-V compound semiconductor. For example, the substrate 110 may be a semi-insulating single crystal GaN substrate having a lattice constant close to that of the channel layer 130 described later. When the semiconductor device 100 includes a buffer layer 120, the substrate 110 may be a substrate made of a material having a lattice constant different from that of the channel layer 130. In such a case, the substrate 110 may be, for example, a SiC substrate, a sapphire substrate, or a Si substrate.

[0018] The buffer layer 120 is a compound semiconductor layer epitaxially grown on the substrate 110. The buffer layer 120 is provided to relieve the lattice mismatch between the substrate 110 and the channel layer 130. By controlling the lattice constant of the surface on which the channel layer 130 is provided, the buffer layer 120 can improve the crystalline state of the channel layer 130 and suppress the warping of the substrate 110. For example, when the substrate 110 is a single-crystalline Si substrate and the channel layer 130 is a GaN layer, the buffer layer 120 may be a layer composed of AlN, AlGaN, or GaN.

[0019] The buffer layer 120 may be provided with a single-layer structure, or may be provided with a multilayer structure in which a plurality of AlN, AlGaN, or GaN are stacked. When the buffer layer 120 is composed of a ternary material, the buffer layer 120 may be provided such that the composition gradually changes in the thickness direction.

[0020] The channel layer 130 is a layer in which carriers are accumulated due to polarization with the barrier layer 140. For example, the channel layer 130 may be an epitaxially grown GaN layer. Also, the channel layer 130 may be an undoped u-GaN layer to which no impurities are added. In such a case, since the channel layer 130 can suppress impurity scattering of carriers, the mobility of carriers can be further increased.

[0021] The barrier layer 140 is a layer in which carriers are accumulated in the channel layer 130 due to polarization with the channel layer 130. For example, the barrier layer 140 may be an epitaxially grown Al1-x-yGaxInyN layer (where 0 ≦ x < 1, 0 ≦ y < 1). Also, the barrier layer 140 may be an undoped u-Al1-x-yGaxInyN layer to which no impurities are added. In such a case, since the barrier layer 140 can suppress impurity scattering of carriers in the channel layer 130, the mobility of carriers can be further increased.

[0022] Note that the barrier layer 140 may be provided with a single-layer structure or a multilayer structure in which a plurality of Al1-x-yGaxInyN layers having different compositions are stacked. Further, the barrier layer 140 may be provided such that the composition gradually changes in the thickness direction.

[0023] Also, as shown in FIG. 2, an active region 140A and an element isolation region 140B are provided in the stacked structure of the substrate 110, the buffer layer 120, the channel layer 130, and the barrier layer 140.

[0024] Specifically, the active region 140A is an island-shaped region where the semiconductor device 100 is provided. In the active region 140A, a source electrode 150S, a gate electrode 170, a material layer 180, and a drain electrode 150D are arranged in the extending direction of the active region 140A.

[0025] The element isolation region 140B is an inactivated region by implanting B (boron) or the like into the channel layer 130 and the barrier layer 140. The element isolation region 140B is provided so as to surround the active region 140A, thereby electrically insulating each of the active regions 140A. Note that the element isolation region 140B may be formed by removing the channel layer 130 and the barrier layer 140 by etching instead of implanting B (boron).

[0026] The insulating layer 160 is provided on the barrier layer 140 so as to cover the source electrode 150S, the drain electrode 150D, and the material layer 180. The insulating layer 160 may be formed of, for example, SiO2, SiN, SION, or Al2O3 having insulating properties with respect to the barrier layer 140. The insulating layer 160 can protect the surface of the barrier layer 140 from impurities such as ions.

[0027] The gate electrode 170 is provided so as to fill the opening 171 provided in the insulating layer 160 from above the insulating layer 160. Specifically, the gate electrode 170 may be provided inside the opening 171 that exposes the barrier layer 140 and on the upper part of the insulating layer 160 so as to have a T-shaped cross-sectional shape. The gate electrode 170 is in contact with the barrier layer 140 at the bottom and can control the number of electrons in the channel layer 130 by an applied voltage. The gate electrode 170 may be provided, for example, in a structure in which Ni and Au are laminated from the barrier layer 140 side.

[0028] Note that a gate insulating film may be provided between the gate electrode 170 and the barrier layer 140. The gate insulating film may be provided, for example, as a single-layer film or a multilayer laminated film such as Al2O3 or HfO2. The gate insulating film can protect the surface of the barrier layer 140 from impurities such as ions and suppress the degradation of the characteristics of the semiconductor device 100 by improving the interface with the barrier layer 140.

[0029] The source electrode 150S and the drain electrode 150D are provided in the active regions 140A on both sides sandwiching the gate electrode 170. The source electrode 150S and the drain electrode 150D are provided so as to form a low-resistance electrical connection with the two-dimensional electron gas 2DEG in the channel layer 130. For example, the source electrode 150S and the drain electrode 150D may be provided on the barrier layer 140, or may be provided by digging (i.e., recessing) the barrier layer 140 to get closer to the two-dimensional electron gas 2DEG. Note that the source electrode 150S and the drain electrode 150D may be provided so as to be in contact with the two-dimensional electron gas 2DEG, or may be provided so as not to be in contact. The source electrode 150S and the drain electrode 150D may be provided, for example, in a structure in which Ti (titanium), Al (aluminum), Ni (nickel), and Au (gold) are sequentially laminated from the barrier layer 140 side.

[0030] Also, an N+ layer containing a high concentration of N-type impurities may be provided below the source electrode 150S and the drain electrode 150D. The N+ layer is provided to electrically connect the source electrode 150S and the drain electrode 150D to the two-dimensional electron gas 2DEG with lower resistance. The N+ layer may be formed, for example, by digging into a region deeper than the vicinity of the barrier layer 140 in the channel layer 130 containing the two-dimensional electron gas 2DEG.

[0031] For example, the N+ layer may be provided by selectively regrowing an n-In1-xGaxN layer so as to fill the etched region after etching the barrier layer 140 and the channel layer 130. Also, the N+ layer may be provided by selectively ion-implanting N-type impurities into the barrier layer 140 and the channel layer 130. The N+ layer may be provided, for example, to contain 1.0×1018 cm-3 or more of Si or Ge which are N-type impurities.

[0032] The material layer 180 contains a metal material or a semiconductor material and is provided on the barrier layer 140 between the opening 171 in which the gate electrode 170 is embedded and the drain electrode 150D. Specifically, the material layer 180 is provided so as to cross the active region 140A in a direction orthogonal to the arrangement direction of the gate electrode 170 and the drain electrode 150D. For example, the material layer 180 may be provided to contain a metal material. More specifically, the material layer 180 may be provided to contain a transition metal material and may be provided to contain Ti (titanium).

[0033] The density of interface traps generated between the material layer 180 containing a metal material or a semiconductor material and the barrier layer 140 is lower than the density of interface traps generated between the insulating layer 160 and the barrier layer 140. This is because the lattice constants are different between the insulating layer 160 and the barrier layer 140, and the dangling bonds that cause interface traps are less likely to occur between the material layer 180 and the barrier layer 140. Therefore, the material layer 180 can reduce the density of interface traps between the gate electrode 170 and the drain electrode 150D, and thus can suppress the degradation of characteristics (especially the decrease in drain current) when a high voltage (for example, 10 V or more) is applied in the semiconductor device 100. Further, since the material layer 180 containing a metal material or a semiconductor material is provided in contact with the barrier layer 140, the material layer 180 can release the charges trapped by the interface traps from the barrier layer 140. Therefore, the material layer 180 can suppress the variation of the characteristics of the semiconductor device 100 during operation.

[0034] The material layer 180 may be provided to have a potential different from that of the gate electrode 170. That is, the material layer 180 may be provided so as not to be electrically connected to the gate electrode 170 by wiring or the like. For example, the material layer 180 may be provided in a floating state. According to this, the material layer 180 can prevent the generation of a parasitic capacitance between the gate electrode 170 and the drain electrode 150D.

[0035] A plurality of the material layers 180 may be provided on the barrier layer 140 between the opening 171 in which the gate electrode 170 is embedded and the drain electrode 150D. Specifically, the material layers 180 may be provided to extend in parallel in a direction orthogonal to the arrangement direction of the gate electrode 170 and the drain electrode 150D.

[0036] Further, the material layer 180 may be provided in a laminated structure of multiple layers. Specifically, the material layer 180 may be provided in a laminated structure including a first layer made of a metal material and a second layer made of an oxide formed by oxidizing the metal material contained in the first layer and provided between the first layer and the barrier layer 140. For example, the material layer 180 may be provided in a laminated structure including a first layer made of Ti and a second layer made of TiO formed by oxidizing Ti contained in the first layer on the barrier layer 140 side.

[0037] Here, with reference to FIGS. 3 and 4, the operation and effect of the semiconductor device 100 according to the above-described embodiment will be described. FIG. 3 is a longitudinal sectional view for explaining the distance X between the opening 171 in which the gate electrode 170 is embedded and the material layer 180.

[0038] FIG. 4 is a graph showing the change in the current degradation rate with respect to the distance X in the semiconductor device 100. The current degradation rate is a value obtained by measuring the reduction rate of the drain current at a drain voltage Vd = 1V before and after applying a high voltage of about 15V to the drain electrode 150D. Further, in FIG. 4, as a comparative example, the current degradation rate of a semiconductor device in which the material layer 180 is not provided is also shown.

[0039] The semiconductor device 100 according to the present embodiment can reduce the density of interface traps generated in the barrier layer 140 by providing the material layer 180, and thus can suppress characteristic degradation during high voltage application and characteristic fluctuations during operation. Specifically, as shown in FIG. 4, it can be seen that the semiconductor device 100 according to the present embodiment has a reduced current degradation rate of the drain current before and after applying a high voltage stress to the drain electrode 150D as compared with the semiconductor device according to the comparative example.

[0040] Also, it can be seen that in the semiconductor device 100 according to the present embodiment, the current degradation rate becomes smaller as the distance X between the opening 171 shown in FIG. 3 and the material layer 180 becomes shorter. This is presumably because as the distance X between the opening 171 and the material layer 180 becomes shorter, the area where interface traps are generated near the gate electrode 170 shrinks. Since the characteristic degradation during high voltage application is greatly affected by the interface traps near the gate electrode 170, it is considered that a greater characteristic improvement effect can be expected by further reducing the interface traps near the gate electrode 170.

[0041] The semiconductor device 100 is preferable because the current degradation rate can be made smaller as the distance X between the opening 171 and the material layer 180 becomes shorter. However, from the viewpoints of manufacturing cost and layout, etc., the semiconductor device 100 is preferably provided such that, for example, the distance X between the opening 171 and the material layer 180 is 0.2 μm or less. In such a case, the semiconductor device 100 can reduce the current degradation rate to a level suitable for a power device or an RF device.

[0042] The semiconductor device 100 according to the present embodiment, whose configuration has been described above, can be used, for example, in a wireless communication device in a mobile communication system or the like. Specifically, the semiconductor device 100 according to the present embodiment can be suitably used as an RF switch or a power amplifier of a wireless communication device. More specifically, the semiconductor device 100 according to the present embodiment can be suitably used as an RF switch or a power amplifier of a wireless communication device whose communication frequency is in the UHF (Ultra High Frequency) band or higher.

[0043] (1.2. Operation) Referring to FIGS. 5 to 7, the operation of the semiconductor device 100 according to the present embodiment will be described. FIG. 5 is a graph showing the energy band configuration below the gate electrode 170 to which the gate voltage Vg is not applied. FIG. 6 is a graph showing the energy band configuration below the gate electrode 170 to which the gate voltage Vg = -10V is applied. FIG. 7 is a longitudinal sectional view showing the configuration of the semiconductor device 100 when a negative gate voltage Vg is applied.

[0044] In FIGS. 5 and 6, as an example, the energy band configuration in the case where the channel layer 130 is made of GaN and the barrier layer 140 is made of an Al0.3-Ga0.7N mixed crystal is shown. Also, Ec represents the energy level at the lower end of the conduction band, Ev represents the energy level at the upper end of the valence band, and Ef represents the Fermi level.

[0045] As shown in FIG. 5, the semiconductor device 100 is configured by joining a channel layer 130 having a narrow bandgap and a barrier layer 140 having a wider bandgap than the channel layer 130. Thereby, in the semiconductor device 100, carriers are accumulated in the channel layer 130 near the junction interface with the barrier layer 140 due to the spontaneous polarization, piezoelectric polarization, or both of the channel layer 130 and the barrier layer 140, and a two-dimensional electron gas 2DEG is formed. Further, the discontinuity amount ΔEc at the lower end of the conduction band between the channel layer 130 and the barrier layer 140 is configured to be sufficiently large (for example, 0.3 eV or more). According to this, the semiconductor device 100 can reduce the number of electrons distributed in the barrier layer 140 to such an extent that it can be ignored with respect to the number of electrons distributed in the channel layer 130.

[0046] Note that it is also possible to provide barrier layers 140 on both sides of the channel layer 130. For example, a second barrier layer having the same configuration as the barrier layer 140 may be provided on the surface of the channel layer 130 opposite to the surface on which the barrier layer 140 is provided (i.e., the surface on the buffer layer 120 side). According to this, the semiconductor device 100 can suppress the spread of the electron distribution in the channel layer 130 toward the buffer layer 120 side, so that it is possible to improve characteristics such as suppressing the short-channel effect.

[0047] Subsequently, with further reference to FIGS. 6 and 7, the operation of the semiconductor device 100 according to the present embodiment will be described. The semiconductor device 100 according to the present embodiment is, for example, a depletion-type transistor having a threshold voltage of about -5V.

[0048] As shown in FIGS. 6 and 7, the semiconductor device 100 can reduce the number of carriers in the carrier depletion region CA below the gate electrode 170 by applying a negative gate voltage Vg of about -10V, for example, to the gate electrode 170. Thereby, the semiconductor device 100 can reduce the number of electrons in the channel layer 130, so that the drain current Id can be made to hardly flow. At this time, the energy band of the semiconductor device 100 is, for example, as shown in FIG. 6.

[0049] On the other hand, the semiconductor device 100 can eliminate the carrier depletion region CA below the gate electrode 170 by applying a positive gate voltage Vg of about 1V, for example, to the gate electrode 170. Thereby, the semiconductor device 100 can increase the number of electrons in the channel layer 130, so that the drain current Id can be modulated. At this time, the energy band of the semiconductor device 100 is, for example, as shown in FIG. 5.

[0050] As described above, the semiconductor device 100 according to the present embodiment can control the flow of the drain current Id by the applied voltage Vg to the gate electrode 170.

[0051] (1.3. Manufacturing method) Referring to FIGS. 8 to 14, an example of a manufacturing method of a semiconductor device 100 according to the present embodiment will be described. FIGS. 8 to 14 are longitudinal sectional views showing each step of the manufacturing method of the semiconductor device 100 according to the present embodiment.

[0052] First, as shown in FIG. 8, for example, a buffer layer 120 is formed by epitaxially growing AlN, AlGaN, or GaN on a substrate 110 made of Si or the like. Next, a channel layer 130 is formed by epitaxially growing GaN on the buffer layer 120. Subsequently, a barrier layer 140 is formed by epitaxially growing u-AlGaN (Al0.3-Ga0.7N mixed crystal) on the channel layer 130.

[0053] Thereafter, although not shown, B (boron) is ion-implanted into the barrier layer 140 and the channel layer 130 to increase the resistance of the barrier layer 140 and the channel layer 130, thereby forming an element isolation region 140B. The element isolation region 140B is formed, for example, so as to surround the periphery of the island-shaped active region 140A and electrically isolate the active regions 140A from each other. Note that the formation of the element isolation region 140B may be performed after the formation of the source electrode 150S and the drain electrode 150D, which will be described later, or after the formation of the gate electrode 170.

[0054] Next, as shown in FIG. 9, source electrodes 150S and drain electrodes 150D are formed by patterning using lithography. Specifically, after sequentially depositing Ti (titanium), Al (aluminum), Ni (nickel), and Au (gold), patterning is performed to form the source electrodes 150S and the drain electrodes 150D.

[0055] Subsequently, as shown in FIG. 10, a material layer 180 is formed by patterning using lithography. Specifically, after depositing a material having a good interfacial state with the barrier layer 140 such as Ti (titanium), patterning is performed to form the material layer 180.

[0056] Next, as shown in FIG. 11, on the barrier layer 140, by depositing SiO2 (silicon dioxide) or the like by CVD (Chemical Vapor Deposition) to cover the source electrode 150S, the drain electrode 150D, and the material layer 180, the insulating layer 160 is formed. Note that the insulating layer 160 may be provided by depositing Al2O3 (aluminum oxide) by ALD (Atomic Vapor Deposition), or may be provided by depositing SiN (silicon nitride) by CVD. Further, the insulating layer 160 may be provided by laminating a plurality of layers formed of the above materials.

[0057] Subsequently, as shown in FIG. 12, by etching the insulating layer 160, an opening 171 is formed to expose the surface of the barrier layer 140. Specifically, the opening 171 is formed by etching and removing the insulating layer 160 in the region corresponding to between the source electrode 150S and the material layer 180.

[0058] Thereafter, as shown in FIG. 13, the gate electrode 170 is formed to fill the opening 171 and spread over the insulating layer 160. Specifically, after sequentially depositing Ni (nickel) and Au (gold), patterning is performed to form the gate electrode 170.

[0059] Through the above steps, the semiconductor device 100 according to the present embodiment can be formed.

[0060] (1.4. Modified Example) With reference to FIGS. 14 to 17, the first and second modified examples of the semiconductor device 100 according to the present embodiment will be described.

[0061] (First Modified Example) First, with reference to FIG. 14, the semiconductor device according to the first modified example will be described. FIG. 14 is a longitudinal sectional view showing the configuration of the semiconductor device 101 according to the first modified example.

[0062] As shown in FIG. 14, the semiconductor device 101 according to the first modification is different from the semiconductor device 100 shown in FIGS. 1 and 2 in that the material layer 180A is made of the same material as the source electrode 150S and the drain electrode 150D.

[0063] Specifically, the material layer 180A may be provided with the same metal material as the source electrode 150S and the drain electrode 150D. For example, when the source electrode 150S and the drain electrode 150D are provided with a structure in which Ti (titanium), Al (aluminum), Ni (nickel), and Au (gold) are sequentially laminated, the material layer 180A may be provided with a structure in which Ti (titanium), Al (aluminum), Ni (nickel), and Au (gold) are sequentially laminated from the barrier layer 140 side. According to this, the material layer 180A can be formed in the same process as the source electrode 150S and the drain electrode 150D.

[0064] Since the semiconductor device 101 according to the first modification can form the material layer 180A, the source electrode 150S, and the drain electrode 150D in the same process, the manufacturing cost can be further reduced. In addition, since the semiconductor device 101 according to the first modification can reduce the number of patterning times in the manufacturing process, the number of times the surface of the semiconductor device 101 is exposed to a resist or the like can be reduced. Therefore, the semiconductor device 101 can suppress the occurrence of defects due to foreign matter adhesion or the like.

[0065] (Second Modification) Next, with reference to FIGS. 15 to 17, a semiconductor device according to the second modification will be described. FIG. 15 is a top view showing the configuration of the semiconductor device 102A according to the second modification. FIG. 16 is a top view showing the configuration of the semiconductor device 102B according to the second modification. FIG. 17 is a top view showing the configuration of the semiconductor device 102C according to the second modification.

[0066] As shown in FIGS. 15 to 17, in the semiconductor devices 102A, 102B, and 102C according to the second modification, the material layer 180 is not in a floating state, but is electrically connected to either the gate electrode 170, the source electrode 150S, or the drain electrode 150D via the resistance portion 190, which is different from the semiconductor device 100 shown in FIGS. 1 and 2.

[0067] Specifically, in FIGS. 15 to 17, the source wiring 153S is electrically connected to the source electrode 150S via the source contact via 152S, the drain wiring 153D is electrically connected to the drain electrode 150D via the drain contact via 152D, and the gate contact via 172 is electrically connected to the gate electrode 170. The source electrode 150S, the drain electrode 150D, and the gate electrode 170 are electrically connected to other elements and the like via the respective contacts and wirings. Note that each contact and wiring can be formed of a conductive material such as metal.

[0068] As shown in FIG. 15, the material layer 180 may be electrically connected to the drain wiring 153D via the contact via 182, the wiring layer 183, the contact via 191, the resistance portion 190, and the contact via 192. According to this, the material layer 180 has the same potential as the drain electrode 150D as direct current (DC). Therefore, since the semiconductor device 102A can discharge the charges that have entered the material layer 180 to the drain electrode 150D, the stability of the device operation can be further enhanced.

[0069] The resistance portion 190 is, for example, a resistor with a resistance of 1 MΩ or more. By suppressing the flow of the RF signal input to the gate electrode 170 through the material layer 180 to the drain electrode 150D, the resistance portion 190 can suppress the degradation of the high-frequency characteristics of the semiconductor device 102A. That is, the semiconductor device 102A electrically connects the material layer 180 and the drain electrode 150D through the resistance portion 190, making the potential of the material layer 180 the same as that of the drain electrode 150D while suppressing the propagation of the RF signal from the material layer 180 to the drain electrode 150D.

[0070] Also, as shown in FIG. 16, the material layer 180 may be electrically connected to the gate wiring 173 through the contact via 182, the wiring layer 183, the contact via 191, the resistance portion 190, and the contact via 192. According to this, the material layer 180 has the same potential as the gate electrode 170 as direct current (DC). Therefore, since the semiconductor device 102B can discharge the charges that have entered the material layer 180 to the gate electrode 170, the stability of device operation can be further enhanced.

[0071] The resistance portion 190 is, as in FIG. 15, a resistor with a resistance of 1 MΩ or more. By suppressing the direct flow of the RF signal input to the gate electrode 170 into the material layer 180, the resistance portion 190 can suppress the degradation of the high-frequency characteristics of the semiconductor device 102B. That is, the semiconductor device 102B electrically connects the material layer 180 and the gate electrode 170 through the resistance portion 190, making the potential of the material layer 180 the same as that of the gate electrode 170 while suppressing the direct flow of the RF signal into the material layer 180.

[0072] Furthermore, as shown in FIG. 17, the material layer 180 may be electrically connected to the source wiring 153S via the contact via 182, the wiring layer 183, the contact via 191, the resistance portion 190, and the contact via 192. According to this, the material layer 180 has the same potential as the source electrode 150S as direct current (DC). Therefore, since the semiconductor device 102C can discharge the charges that have entered the material layer 180 to the source electrode 150S, the stability of device operation can be further enhanced.

[0073] Similar to FIG. 15, the resistance portion 190 is a resistor of 1 MΩ or more. By suppressing the RF signal input to the gate electrode 170 from flowing through the material layer 180 to the source electrode 150S, the resistance portion 190 can suppress the deterioration of the high-frequency characteristics of the semiconductor device 102C. That is, the semiconductor device 102C electrically connects the material layer 180 and the source electrode 150S via the resistance portion 190, so that while making the potential of the material layer 180 the same as the potential of the source electrode 150S, it can suppress the propagation of the RF signal from the material layer 180 to the source electrode 150S.

[0074] Although not shown, the material layer 180 may be electrically connected to a ground line or a power line instead of the gate electrode 170, the source electrode 150S, or the drain electrode 150D. Even in such a case, since the semiconductor device 100 can discharge the charges that have entered the material layer 180 to the outside of the material layer 180, the stability of device operation can be further enhanced.

[0075] <2. Second Embodiment> Subsequently, with reference to FIG. 18, a semiconductor module according to the second embodiment of the present disclosure will be described. FIG. 18 is a schematic perspective view showing the configuration of the semiconductor module 1 according to the present embodiment.

[0076] As shown in FIG. 18, the semiconductor module 1 according to the present embodiment is, for example, an antenna integrated module in which an edge antenna 20 formed in an array shape and front-end components such as a switch 10, a low-noise amplifier 41, a band-pass filter 42, and a power amplifier 43 are implemented as one module. The semiconductor module 1 can be used, for example, as a transceiver for communication.

[0077] The semiconductor module 1 includes, for example, the semiconductor device 100 according to the first embodiment as a transistor constituting the switch 10, the low-noise amplifier 41, or the power amplifier 43 or the like. According to this, the semiconductor module 1 can achieve further high speed, high efficiency, and low power consumption in wireless communication.

[0078] <3. Third Embodiment> Next, with reference to FIG. 19, a wireless communication device according to the third embodiment of the present disclosure will be described. FIG. 19 is a block diagram showing the configuration of the wireless communication device 2 according to the present embodiment.

[0079] As shown in FIG. 19, the wireless communication device 2 includes an antenna ANT, an antenna switch circuit 3, a high-power amplifier HPA, a radio frequency integrated circuit RFIC, a baseband unit BB, a voice output unit MIC, a data output unit DT, and an interface unit I / F (for example, Wireless Local Area Network (W-LAN), or Bluetooth (registered trademark), etc.). The wireless communication device 2 is, for example, a mobile phone system having multiple functions such as voice, data communication, and LAN connection.

[0080] The wireless communication device 2 includes the semiconductor device 100 according to the first embodiment as transistors that constitute an antenna switch circuit 3, a high-power amplifier HPA, a radio frequency integrated circuit RFIC, a baseband section BB, or the like. According to this, the wireless communication device 2 can achieve further high speed, high efficiency, and low power consumption of wireless communication. Therefore, when the wireless communication device 2 is a portable communication terminal, the wireless communication device 2 can further extend the usage time, and thus can further improve portability.

[0081] As described above, the technology according to the present disclosure has been described by way of the first to third embodiments and modification examples. However, the technology according to the present disclosure is not limited to the above-described embodiments and the like, and various modifications are possible. The semiconductor device 100 may be composed of a semiconductor other than the GaN system. For example, the semiconductor device 100 may be composed of a compound semiconductor of the GaAs system, the InP system, or the SiGe system. Further, the semiconductor device 100 may be composed of Si.

[0082] Furthermore, not all of the configurations and operations described in each embodiment are essential as the configurations and operations of the present disclosure. For example, among the components in each embodiment, components not described in the independent claims indicating the most general concept of the present disclosure should be understood as optional components.

[0083] The terms used throughout this specification and the appended claims should be construed as "non-limiting" terms. For example, the terms "including" or "comprised of" should be construed as not being limited to the manner described as being included. The term "having" should be construed as not being limited to the manner described as having.

[0084] The terms used in this specification include terms that are used for the convenience of explanation only and are not used for the purpose of limiting the configuration and operation. For example, terms such as "right", "left", "up", and "down" merely indicate directions on the drawing being referred to. Also, the terms "inside" and "outside" merely indicate the direction towards the center of the element of interest and the direction away from the center of the element of interest, respectively. The same applies to terms similar to these and terms of the same general meaning.

[0085] Note that the technology according to the present disclosure can also adopt the following configurations. According to the technology according to the present disclosure having the following configurations, a semiconductor device can reduce the density of interface traps between a gate electrode and a drain electrode. Therefore, the semiconductor device can suppress the possibility of performance degradation due to the application of a high voltage. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure. (1) A barrier layer including a first compound semiconductor, A channel layer including a second compound semiconductor and joined to the barrier layer on a first surface, An insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening for exposing the barrier layer, A gate electrode provided so as to fill the opening, A source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode, A material layer including a metal material or a semiconductor material and provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode A semiconductor device comprising: (2) The semiconductor device according to (1) above, wherein the material layer contains the metal material. (3) The semiconductor device according to (2) above, wherein the material layer contains a transition metal material as the metal material. (4) The semiconductor device according to (3) above, wherein the material layer contains Ti as the transition metal material. (5) The semiconductor device according to any one of (1) to (4) above, wherein the material layer is provided so as to have a potential different from that of the gate electrode. (6) The semiconductor device according to (5) above, wherein the material layer is in a floating state. (7) The semiconductor device according to (5) above, wherein the material layer is electrically connected to the source electrode or the drain electrode via a resistance portion. (8) The semiconductor device according to any one of (1) to (4) above, wherein the material layer is electrically connected to the gate electrode via a resistance portion. (9) The semiconductor device according to any one of (1) to (8) above, wherein the material layer contains the same conductive material as the conductive material contained in the source electrode or the drain electrode. (10) The semiconductor device according to any one of (1) to (9) above, wherein the distance between the material layer and the opening is 0.2 μm or less. (11) The gate electrode, the source electrode, and the drain electrode are provided in an active region defined by an element isolation region on the second surface of the barrier layer, The semiconductor device according to any one of (1) to (10) above, wherein the material layer extends across the active region in a direction orthogonal to the arrangement direction of the gate electrode and the drain electrode. (12) A barrier layer containing a first compound semiconductor, A channel layer containing a second compound semiconductor and joined to the barrier layer on the first surface, An insulating layer provided on the second surface opposite to the first surface of the barrier layer and having an opening for exposing the barrier layer, A gate electrode provided so as to fill the opening, A source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode A material layer provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode and including a metal material or a semiconductor material A semiconductor device including A semiconductor module (13) A barrier layer including a first compound semiconductor A channel layer including a second compound semiconductor and joined to the barrier layer on a first surface An insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening exposing the barrier layer A gate electrode provided to fill the opening A source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode A material layer provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode and including a metal material or a semiconductor material A semiconductor device including An electronic device

[0086] This application claims priority based on Japanese Patent Application No. 2020-090913 filed with the Japan Patent Office on May 25, 2020, and incorporates all the contents of this application by reference

[0087] Those skilled in the art can conceive various modifications, combinations, sub - combinations, and changes according to design requirements and other factors, and it is understood that they are included within the scope of the appended claims and their equivalents

Claims

1. A barrier layer including a first compound semiconductor, A channel layer including a second compound semiconductor and joined to the barrier layer on a first surface, An insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening for exposing the barrier layer, A gate electrode provided to fill the opening, A source electrode and a drain electrode provided on the second surface of the barrier layer on both sides sandwiching the gate electrode, A material layer including the same conductive material as the conductive material included in the source electrode or the drain electrode and provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode Comprising A semiconductor device.

2. The semiconductor device according to claim 1, wherein the material layer includes a metal material as the conductive material.

3. The semiconductor device according to claim 2, wherein the material layer includes a transition metal material as the metal material.

4. The semiconductor device according to claim 3, wherein the material layer includes Ti as the transition metal material.

5. The semiconductor device according to claim 1, wherein the material layer is provided so as to have a different potential from the gate electrode.

6. The semiconductor device according to claim 5, wherein the material layer is in a floating state.

7. The semiconductor device according to claim 5, wherein the material layer is electrically connected to the source electrode or the drain electrode via a resistance portion.

8. The semiconductor device according to claim 1, wherein the material layer is electrically connected to the gate electrode via a resistance portion.

9. The semiconductor device according to claim 1, wherein the distance between the material layer and the opening is 0.2 μm or less.

10. The gate electrode, the source electrode, and the drain electrode are provided in an active region defined by an element isolation region on the second surface of the barrier layer, The semiconductor device according to claim 1, wherein the material layer extends across the active region in a direction orthogonal to the arrangement direction of the gate electrode and the drain electrode.

11. A barrier layer including a first compound semiconductor, A channel layer including a second compound semiconductor and joined to the barrier layer on a first surface, An insulating layer provided on a second surface opposite to the first surface of the barrier layer and having an opening for exposing the barrier layer, A gate electrode provided to fill the opening, A source electrode and a drain electrode provided on the second surfaces of the barrier layers on both sides sandwiching the gate electrode, A material layer provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode and containing the same conductive material as the conductive material included in the source electrode or the drain electrode A semiconductor device including A semiconductor module.

12. A barrier layer including a first compound semiconductor, A channel layer including a second compound semiconductor and joined to the barrier layer on the first surface, An insulating layer provided on the second surface opposite to the first surface of the barrier layer and having an opening for exposing the barrier layer, A gate electrode provided so as to fill the opening, A source electrode and a drain electrode provided on the second surfaces of the barrier layers on both sides sandwiching the gate electrode, A material layer provided in contact with the second surface of the barrier layer between the gate electrode and the drain electrode and containing the same conductive material as the conductive material included in the source electrode or the drain electrode A semiconductor device including An electronic device.

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