Semiconductor device

Abstract

To provide a semiconductor device having a high breakdown voltage.SOLUTION: A semiconductor device comprises a semiconductor part, first to fourth electrodes, and first and second insulation films. The first and second electrodes are respectively provided on a rear face and at a front face side of the semiconductor part. The third electrode and the fourth electrode extend in the semiconductor part. The fourth electrode encloses a region in which a plurality of third electrodes are provided. The first insulation film is provided between the semiconductor part and the third electrode, and the second insulation film is provided between the semiconductor part and the fourth electrode. The fourth electrode includes first to third portions respectively extending in first to third directions along the rear face. The first direction is orthogonal with the second direction, and the third direction crosses the first direction and the second direction. The plurality of third electrodes are disposed so as to minimize the interval between adjacent two first insulation films between adjacent two third electrodes in the first direction and the third direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] Power control semiconductor devices are required to have a high breakdown voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device having a high breakdown voltage.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, first to fourth electrodes, and first and second insulating films. The semiconductor portion includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first electrode is provided on the back surface of the semiconductor portion, and the second electrode is provided on the surface side of the semiconductor portion. The first semiconductor layer extends between the first electrode and the second electrode, and the second semiconductor layer is provided between the first semiconductor layer and the second electrode and is electrically connected to the second electrode. The third electrode and the fourth electrode extend from the surface side of the semiconductor portion into the first semiconductor layer. A plurality of the third electrodes are provided and are arranged to be spaced apart from each other in a direction along the back surface of the semiconductor portion. The plurality of third electrodes are electrically connected to the second electrode. The fourth electrode surrounds the region where the plurality of third electrodes are provided and is electrically connected to the second electrode. The first insulating film is provided between the semiconductor portion and the plurality of third electrodes, respectively, and electrically insulates the third electrode from the semiconductor portion. The second insulating film is provided between the semiconductor portion and the fourth electrode and electrically insulates the fourth electrode from the semiconductor portion. The fourth electrode includes a first portion extending in a first direction along the back surface of the semiconductor portion, a second portion extending in a second direction along the back surface and orthogonal to the first direction, and a third portion extending in a third direction along the back surface and intersecting the first and second directions and connected to the first and second portions. The plurality of third electrodes are arranged such that the interval between two adjacent first insulating films is minimized between two adjacent third electrodes in the first direction and between another two adjacent third electrodes in the third direction.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiment for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the respective parts, the ratios of the sizes between the parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, the dimensions and ratios thereof may be represented differently depending on the drawings.

[0008] Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X-direction, Y-direction, and Z-direction, respectively. Also, there are cases where the Z-direction is described as upward and the opposite direction as downward.

[0009] FIG. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. FIG. 1 is a cross-sectional view taken along the V-V line shown in FIG. 2(a). The semiconductor device 1 is, for example, a MOSFET.

[0010] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor part 10, a first electrode 20, a second electrode 30, a third electrode 40, a fourth electrode 50, and a control electrode 60. The semiconductor part 10 is, for example, silicon.

[0011] The first electrode 20 is provided on the back surface 10B of the semiconductor part 10. The first electrode 20 is, for example, a drain electrode. The first electrode 20 is, for example, a metal layer containing nickel (Ni), aluminum (Al), etc.

[0012] The second electrode 30 is provided on the surface 10F side of the semiconductor part 10. The second electrode 30 is, for example, a source electrode. The first electrode 20 is, for example, a metal layer containing titanium nitride (TiN), tungsten (W), aluminum (Al), etc.

[0013] The third electrode 40 is disposed inside a first trench TH provided on the surface side of the semiconductor portion 10. The first trench TH has, for example, a circular or polygonal opening, and is provided in a hole shape extending in a direction from the surface side to the back side of the semiconductor portion 10 (for example, the -Z direction). Also, the third electrode 40 is electrically insulated from the semiconductor portion 10 by a first insulating film 45. The first insulating film 45 covers the inner surface of the first trench TH and is provided between the semiconductor portion 10 and the third electrode 40. The first insulating film 45 is, for example, a silicon oxide film.

[0014] The fourth electrode 50 is disposed inside a second trench TG provided on the surface side of the semiconductor portion 10. The second trench TG extends, for example, in a direction from the surface side to the back side of the semiconductor portion 10 (for example, the -Z direction). Also, the second trench TG is provided in a groove shape surrounding a region (active region) where a plurality of third electrodes 40 are disposed (see FIG. 2(a)). That is, the fourth electrode 50 extends along the opening of the second trench TG and is provided so as to surround the active region. The second trench TG is a so-called termination trench.

[0015] The fourth electrode 50 is electrically insulated from the semiconductor portion 10 by a second insulating film 55. The second insulating film 55 covers the inner surface of the second trench TG and is provided between the semiconductor portion 10 and the fourth electrode 50. The second insulating film 55 is, for example, a silicon oxide film.

[0016] The control electrode 60 is provided, for example, between the semiconductor portion 10 and the third electrode 40 inside the first trench TH. The control electrode 60 is, for example, a gate electrode. The control electrode 60 is provided above the first trench TH. The upper surface of the control electrode 60 is located, for example, near the opening of the first trench TH.

[0017] The control electrode 60 is electrically insulated from the semiconductor portion 10 by a third insulating film 63. The third insulating film 63 is, for example, a gate insulating film. The third insulating film 63 covers the upper portion of the inner surface of the first trench TH and is provided between the semiconductor portion 10 and the control electrode 60. The third insulating film 63 is, for example, a silicon oxide film.

[0018] The control electrode 60 is provided, for example, so as to surround the third electrode 40 in a plan view parallel to the surface 10F of the semiconductor portion 10. The control electrode 60 is electrically insulated from the third electrode 40 by the fourth insulating film 65. The fourth insulating film 65 is provided between the third electrode 40 and the control electrode 60. The fourth insulating film 65 is, for example, a silicon oxide film.

[0019] The semiconductor portion 10 includes, for example, a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the first conductivity type, and a fourth semiconductor layer 17 of the first conductivity type. Hereinafter, the first conductivity type will be described as n-type and the second conductivity type will be described as p-type.

[0020] The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30. The first semiconductor layer 11 is, for example, an n-type drift layer. The first trench TH and the second trench TG are each provided so as to extend from the surface side of the semiconductor portion 10 into the first semiconductor layer 11. The third electrode 40 faces the first semiconductor layer 11 via the first insulating film 45. The fourth electrode 50 faces the first semiconductor layer 11 via the second insulating film 55.

[0021] The second semiconductor layer 13 is provided between the first semiconductor layer 11 and the second electrode 30. The second semiconductor layer 13 is, for example, a p-type diffusion layer. The second semiconductor layer 13 is provided so as to face the control electrode 60 via the third insulating film 63.

[0022] The third semiconductor layer 15 is partially provided between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 is provided so as to be in contact with the third insulating film 63. The third semiconductor layer 15 is, for example, an n-type source layer.

[0023] The fourth semiconductor layer 17 is provided, for example, between the first semiconductor layer 11 and the first electrode 20. The fourth semiconductor layer 17 contains a first conductivity type impurity having a higher concentration than the concentration of the first conductivity type impurity in the first semiconductor layer 11. The fourth semiconductor layer 17 is, for example, an n-type buffer layer. The first electrode 20 is electrically connected to the fourth semiconductor layer 17.

[0024] The semiconductor device 1 further includes a fifth insulating film 33, a sixth insulating film 35, a first wiring 47, a second wiring 57, and a third wiring 67.

[0025] The fifth insulating film 33 and the sixth insulating film 35 are provided between the semiconductor portion 10 and the second electrode 30. The fifth insulating film 33 is provided between the semiconductor portion 10 and the sixth insulating film 35. The sixth insulating film 35 is provided between the fifth insulating film 33 and the second electrode 30. The fifth insulating film 33 and the sixth insulating film 35 are, for example, interlayer insulating films. The fifth insulating film 33 and the sixth insulating film 35 are, for example, silicon oxide films.

[0026] The fifth insulating film 33 covers the surface 10F of the semiconductor portion 10, the first trench TH, and the second trench TG. The first wiring 47, the second wiring 57, and the third wiring 67 are provided between the fifth insulating film 33 and the sixth insulating film 35.

[0027] The first wiring 47 is electrically connected to the third electrode 40 through a contact hole provided in the fifth insulating film 33. Connection The second wiring 57 is electrically connected to the fourth electrode 50 through another contact hole provided in the fifth insulating film 33. Connection The third wiring 67 is electrically connected to the control electrode 60 through yet another contact hole provided in the fifth insulating film 33. Connection The first wiring 47 is also electrically connected to the second semiconductor layer 13 and the third semiconductor layer 15 through other contact holes provided in the third insulating film 33. Connection

[0028] The second electrode 30 is connected to the first wiring 47 and the second wiring 57 respectively through contact holes provided in the sixth insulating film 35. Thereby, the second electrode 30 is electrically connected to the third electrode 40 and the fourth electrode 50. Also, the second electrode 30 is electrically connected to the second semiconductor layer 13 and the third semiconductor layer 15.

[0029] ​Figs. 2(a) and (b) are schematic plan views showing the semiconductor device 1 according to the embodiment. Fig. 2(a) is a cross-sectional view taken along the line H-H shown in Fig. 1. Fig. 2(b) is a partial cross-sectional view showing a part of Fig. 2(a).

[0030] As shown in Fig. 2(a), the second trench TG is provided so as to surround a region (active region) where a plurality of third electrodes 40 are arranged. The second trench TG has, for example, an outer edge of a quadrangle with chamfered four corners. The fourth electrode 50 extends along the second trench TG and surrounds the plurality of third electrodes 40.

[0031] The third electrodes 40 are arranged in, for example, the Y direction. A plurality of rows of the third electrodes 40 arranged in the Y direction are arranged in the X direction. One of the third electrodes 40 is arranged, for example, in a space between adjacent third electrodes 40 in the Y direction so as to be adjacent in the X direction.

[0032] Fig. 2(b) is a plan view showing one corner of the second trench TG. As shown in Fig. 2(b), the first trench TH has, for example, a regular hexagonal cross-sectional shape. The third electrode 40 is provided, for example, at the center of the regular hexagon.

[0033] The plurality of third electrodes 40 are arranged such that the interval between two adjacent first insulating films 45 in the Y direction becomes the minimum interval Dmin. Also, the plurality of third electrodes 40 are arranged such that the interval between two adjacent first insulating films 45 in an oblique direction Dd intersecting the X direction and the Y direction becomes, for example, the minimum interval Dmin.

[0034] Also, the first trenches TH arranged along the second trench TG are arranged such that the interval De from the second trench TG is equally spaced. The interval De is, for example, the same as the minimum interval Dmin.

[0035] The second trench TG includes, for example, a first portion TG1, a second portion TG2, and a third portion TG3. The first portion TG1 extends in the Y direction. The second portion TG2 extends in the X direction. The third portion TG3 extends in an oblique direction Dd and is provided so as to connect the first portion TG1 and the second portion TG2. The first portion TG1 is connected to the third portion TG3, for example, with an outer angle of 60°. The second portion TG2 is connected to the third portion TG3, for example, with an outer angle of 30°.

[0036] The fourth electrode 50 provided in the second trench also includes a first portion 50a, a second portion 50b, and a third portion 50c. The first portion 50a extends in the Y direction. The second portion 50b extends in the X direction. The third portion 50c extends in the oblique direction Dd and is provided so as to connect the first portion 50a and the second portion 50b.

[0037] FIG. 3 is a schematic plan view showing the semiconductor device 2 according to the comparative example. FIG. 3 is a plan view corresponding to FIG. 2(b).

[0038] In the semiconductor device 2, one first trench TH is arranged to face the corner portion of the second trench TG. In other words, the second trench TG of the semiconductor device 2 does not have a third portion TG3 (see FIG. 2(b)) that extends in the oblique direction Dd.

[0039] Thus, the second trench TG of the semiconductor device 2 is provided such that the corner portion bends at 90°. The semiconductor device 2 has a shape in which electric field concentration is likely to occur at the corner portion during turn-off.

[0040] FIG. 4 is a graph showing the characteristics of the semiconductor device 1 according to the embodiment. The horizontal axis is the film thickness of the second insulating film 55. The vertical axis is the breakdown voltage. "EB" shown in FIG. 4 indicates the characteristics of the semiconductor device 1. Also, "CE" indicates the characteristics of the semiconductor device 2 as a comparative example.

[0041] For example, by suitably setting the minimum distance Dmin between adjacent first trenches TH, when the breakdown voltage in the active region is increased, the breakdown voltages of semiconductor devices 1 and 2 become dependent on the breakdown voltage of the termination region where the second trench TG is provided.

[0042] As shown in FIG. 4, if the film thickness of the second insulating film 55 in the second trench TG is increased, the electric field value at the interface between the first semiconductor layer 11 and the second insulating film 55 becomes smaller, and the breakdown voltage of the termination region increases.

[0043] The breakdown voltage of the termination region depends, for example, on the electric field concentration at the corner portion of the second trench TG. The second trench TG of semiconductor device 1 has a third portion TG3 at the corner portion (see FIG. 2(b)). Therefore, in semiconductor device 1, the electric field concentration in the second trench TG is alleviated, and the breakdown voltage of semiconductor device 1 becomes higher than the breakdown voltage of semiconductor device 2.

[0044] As described above, in semiconductor device 1 according to the embodiment, by providing the third portion TG3 at the corner portion of the second trench TG, the breakdown voltage can be increased.

[0045] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0046] 1, 2... semiconductor device, 10... semiconductor part, 10B... back surface, 10F... front surface, 11... first semiconductor layer, 13... second semiconductor layer, 15... third semiconductor layer, 17... fourth semiconductor layer, 20... first electrode, 30... second electrode, 33... fifth insulating film, 35... sixth insulating film, 40... third electrode, 45... first insulating film, 47... first wiring, 50... fourth electrode, 55... second insulating film, 57... second wiring, 60... control electrode, 63... third insulating film, 65... fourth insulating film, 67... third wiring, TH... first trench, TG... second trench, TG1, 50a... first part, TG2, 50b... second part, TG3, 50c... third part

Claims

1. A semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; A first electrode provided on the back surface of the semiconductor part; A second electrode provided on the surface side of the semiconductor part, wherein the first semiconductor layer extends between the first electrode and the second electrode, the second semiconductor layer is provided between the first semiconductor layer and the second electrode, and the second electrode is configured to be electrically connected to the second electrode; A plurality of third electrodes extending from the surface side of the semiconductor part into the first semiconductor layer, arranged to be spaced apart from each other in a direction along the back surface of the semiconductor part, and electrically connected to the second electrode; A fourth electrode extending from the surface side of the semiconductor part into the first semiconductor layer, surrounding the region where the plurality of third electrodes are provided, and electrically connected to the second electrode; A first insulating film provided between the semiconductor part and the plurality of third electrodes respectively, for electrically insulating the plurality of third electrodes from the semiconductor part; A second insulating film provided between the semiconductor part and the fourth electrode, for electrically insulating the fourth electrode from the semiconductor part; Comprising; The fourth electrode includes a first portion extending in a first direction along the back surface of the semiconductor part, a second portion extending in a second direction along the back surface, the second direction being perpendicular to the first direction, and a third portion extending in a third direction along the back surface, the third direction intersecting the first direction and the second direction, and connecting the first portion and the second portion; The plurality of third electrodes are arranged such that the distances between two adjacent first insulating films are the same both between two adjacent third electrodes in the first direction and between another two adjacent third electrodes in the third direction; The first portion, the second portion and the third portion do not have a corner portion of 90 degrees or less; The plurality of third electrodes include the plurality of third electrodes belonging to a first group, the plurality of third electrodes belonging to a second group, and the plurality of third electrodes belonging to a third group; The plurality of third electrodes belonging to the first group are arranged along the first direction, The plurality of third electrodes belonging to the second group are arranged along the first direction, The plurality of third electrodes belonging to the third group are arranged along the first direction, The plurality of third electrodes belonging to the second group are, in the second direction, between the plurality of third electrodes belonging to the third group and the first portion, The plurality of third electrodes belonging to the first group are, in the second direction, between the plurality of third electrodes belonging to the second group and the first portion, The plurality of third electrodes belonging to the first group are, in the second direction, the closest to the first portion among the plurality of third electrodes, The number of the plurality of third electrodes belonging to the second group is one greater than the number of the plurality of third electrodes belonging to the first group, The number of the plurality of third electrodes belonging to the third group is one greater than the number of the plurality of third electrodes belonging to the second group, a semiconductor device.

2. The plurality of third electrodes are first trenches provided on the surface side of the semiconductor portion and extending in a fourth direction from the second electrode toward the first electrode, and are provided inside the first trenches having circular or polygonal openings on the surface of the semiconductor portion, The semiconductor device according to claim 1, wherein the fourth electrode is provided inside a groove-shaped second trench extending along the surface of the semiconductor portion.

3. The semiconductor device according to claim 1 or 2, wherein the third direction intersects the first direction so as to have an interior angle of 60° or 30°.

4. A control electrode provided between the second semiconductor layer and the third electrode, A third insulating film provided between the second semiconductor layer and the control electrode, A fourth insulating film provided between the third electrode and the control electrode, and further comprising The third electrode faces the first semiconductor layer through the first insulating film, The semiconductor device according to any one of claims 1 to 3, wherein the control electrode is provided to face the second semiconductor layer through the third insulating film.

5. The semiconductor portion further includes a third semiconductor layer of the first conductivity type, The semiconductor device according to claim 4, wherein the third semiconductor layer is partially provided between the second semiconductor layer and the second electrode and is provided to be in contact with the third insulating film.

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