Semiconductor device and imaging device

Abstract

Provided is a semiconductor device that level-shifts a negative voltage and / or a positive voltage. The semiconductor device comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor and the output terminal. Furthermore, a second terminal of the second transistor is electrically connected to a first terminal of the third transistor. Furthermore, a first terminal of the fourth transistor is electrically connected to the gate of the second transistor and a first terminal of the first capacitor, and a second terminal of the first capacitor is electrically connected to the input terminal. Furthermore, the first transistor, the second transistor, the third transistor, and the fourth transistor are of the same polarity.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification or the like relates to an object, an operation method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited as an example.

Background Art

[0003] In recent years, in electronic devices, there has been a strong demand for reducing power consumption during operation. For example, for the purpose of reducing the power consumption of an electronic device, reduction of the power consumption of individual logic circuits included in the electronic device has been studied.

[0004] Logic circuits can be classified, for example, into static logic circuits, dynamic logic circuits, and pseudo logic circuits. Since a dynamic logic circuit operates by temporarily holding data, compared with a static logic circuit, the leakage current of transistors becomes a problem. If the leakage current of a transistor is large, the data held in the dynamic logic circuit will be destroyed. The leakage current is caused in part by the off-current that flows when the transistor is in the off state. For example, Patent Document 1 and Patent Document 2 disclose that by providing a transistor in which a channel is formed of an oxide semiconductor, the leakage current of a dynamic logic circuit can be reduced.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-9311 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-9313 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] When manufacturing a semiconductor device, the materials included in the channel formation regions of a plurality of transistors included in the semiconductor device may be the same as each other, whereby the manufacturing process of the semiconductor device may be shortened. Specifically, for example, as the material, a metal oxide containing indium, gallium, zinc, or the like can be used.

[0007] However, in a metal oxide containing indium (for example, In oxide) or a metal oxide containing zinc (for example, Zn oxide), an n-type semiconductor can be manufactured, but it is difficult to manufacture a p-type semiconductor in terms of mobility and reliability. Therefore, when manufacturing a semiconductor device, it is preferable to use a unipolar circuit composed of transistors including an n-type semiconductor (n-channel transistors). However, since the unipolar circuit does not include transistors including a p-type semiconductor (p-channel transistors), unlike a CMOS circuit, the circuit area tends to be large.

[0008] Also, consider the case where a level shifter (referred to as a negative voltage level shifter) that shifts the input potential to a lower potential VSSL is configured as a unipolar circuit including an n-channel transistor. When VSSL is input to the source of the n-channel transistor and VSS, which is the input signal, is input to the gate, the gate-source voltage of the n-channel transistor may become higher than the threshold voltage, so the n-channel transistor may not turn off. When the n-channel transistor does not turn off, the negative voltage level shifter has a circuit configuration in which a steady current flows, so the power consumption may increase.

[0009] Further, it is preferable that the level shifter has not only the function of a negative voltage level shifter but also the function of a positive voltage level shifter that shifts the input potential to a higher potential. Also, it is preferable that the level shifter has a circuit configuration that functions as only one of the negative voltage level shifter or the positive voltage level shifter according to the situation.

[0010] One aspect of the present invention is to provide a semiconductor device having a function of shifting an input voltage to a lower voltage or a higher voltage as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with reduced power consumption as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with reduced circuit area as one of the problems.

[0011] Or, one aspect of the present invention is to provide a novel semiconductor device as one of the problems. Or, one aspect of the present invention is to provide an imaging device having the above semiconductor device as one of the problems.

[0012] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this item as described below. Problems not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not necessarily solve all of the problems listed above and other problems.

Means for Solving the Problems

[0013] (1) One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the output terminal. Also, the second terminal of the second transistor is electrically connected to the first terminal of the third transistor. Also, the first terminal of the fourth transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitor, and the second terminal of the first capacitor is electrically connected to the input terminal. Note that each of the first transistor, the second transistor, the third transistor, and the fourth transistor may be a transistor of the same polarity.

[0014] (2) Alternatively, in one aspect of the present invention, in the above (1), when a first potential is input to the input terminal, a second potential is input to the second terminal of the first transistor, and a third potential is input to the second terminal of the third transistor and the second terminal of the fourth transistor, the first transistor preferably has a function of pre-charging the output terminal to the second potential when the first transistor is in an on state, and the second transistor preferably has a function of being turned on or off according to the first potential input to the input terminal when the fourth transistor is in an off state. Further, the semiconductor device preferably has a function of setting the potential of the output terminal to the second potential or the third potential by turning on the third transistor after the output terminal is pre-charged to the second potential and the first transistor is turned off.

[0015] (3) Alternatively, one aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. The first terminal of the first transistor is electrically connected to the first terminal of the third transistor and the output terminal. The second terminal of the third transistor is electrically connected to the first terminal of the second transistor. The first terminal of the fourth transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitor. The second terminal of the first capacitor is electrically connected to the input terminal. Also, a first potential may be input to the input terminal. Note that each of the first transistor, the second transistor, the third transistor, and the fourth transistor may be a transistor of the same polarity.

[0016] (4) Alternatively, in one aspect of the present invention, in the configuration of (3) above, when a first potential is input to the input terminal, a second potential is input to the second terminal of the first transistor, and a third potential is input to the second terminal of the second transistor and the second terminal of the fourth transistor, the first transistor preferably has a function of pre-charging the output terminal to the second potential when the first transistor is in the on state, and the second transistor preferably has a function of turning on or off according to the first potential input to the input terminal when the fourth transistor is in the off state. Further, the semiconductor device preferably has a function of setting the potential of the output terminal to the second potential or the third potential by turning on the third transistor after the output terminal is pre-charged to the second potential and the first transistor is turned off.

[0017] (5) Alternatively, in one aspect of the present invention, in the configuration of (1) or (4) above, a semiconductor device having a second capacitor may be used. The first terminal of the second capacitor is electrically connected to the first terminal of the first transistor, the first terminal of the second transistor, and the output terminal.

[0018] (6) Alternatively, in one aspect of the present invention, in any one of the configurations of (1) to (5) above, each of the first to fourth transistors may have a metal oxide or silicon in the channel formation region.

[0019] (7) Alternatively, in one aspect of the present invention, in any one of the configurations of (1) to (6) above, the first capacitor may include a fifth transistor. The fifth transistor has a metal oxide or silicon in the channel formation region. Also, the gate of the fifth transistor functions as one of the first terminal or the second terminal of the first capacitor, and the first terminal and the second terminal of the fifth transistor function as the other of the first terminal or the second terminal of the first capacitor.

[0020] (8) Alternatively, one aspect of the present invention is an imaging device having any one of the semiconductor devices (1) to (7) described above and a photoelectric conversion element. Further, the photoelectric conversion element is preferably located above the first transistor to the fourth transistor.

[0021] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Further, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc. are semiconductor devices themselves and may have a semiconductor device.

[0022] Also, in this specification and the like, when it is described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected, as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. It is assumed that X and Y are objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0023] As an example of the case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitor elements, inductors, resistor elements, diodes, display devices, light-emitting devices, loads, etc.) that enable electrical connection between X and Y can be connected between X and Y. Note that a switch has a function of controlling on / off. That is, a switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not.

[0024] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is interposed between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0025] Note that when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, when they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, when they are connected without another element or another circuit interposed between X and Y).

[0026] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By using an expression method similar to these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0027] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, one component may have the functions of multiple components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component combined. Therefore, the electrically connected in this specification includes such cases where one conductive film has the functions of multiple components combined within its scope.

[0028] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the "resistive element" includes wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, a coil, and the like. Therefore, the term "resistive element" can be paraphrased as terms such as "resistance", "load", "region having a resistance value", and conversely, terms such as "resistance", "load", "region having a resistance value" can be paraphrased as terms such as "resistive element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0029] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, and the like. Therefore, in this specification and the like, the "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric included between the electrodes, but also parasitic capacitance that appears between wirings, gate capacitance that appears between one of the source or drain of a transistor and the gate, and the like. Also, terms such as "capacitive element", "parasitic capacitance", "gate capacitance" can be paraphrased as terms such as "capacitance", and conversely, the term "capacitance" can be paraphrased as terms such as "capacitive element", "parasitic capacitance", "gate capacitance". Also, the term "pair of electrodes" of "capacitance" can be paraphrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 μF or less.

[0030] Also, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms of the source and the drain are assumed to be interchangeable. Further, in this specification and the like, when explaining the connection relationship of the transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, when the transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0031] Also, in this specification and the like, a node can be equivalently referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on the circuit configuration, the device structure, etc. Also, it is possible to equivalently refer to a terminal, a wiring, etc. as a node.

[0032] Also, in this specification and the like, "voltage" and "electric potential" can be appropriately rephrased. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc., also change.

[0033] Also, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, in two pieces of wiring, if both are described as "functioning as wiring for supplying a high-level potential", the respective high-level potentials provided by the two pieces of wiring do not necessarily have to be equal to each other. Similarly, in two pieces of wiring, if both are described as "functioning as wiring for supplying a low-level potential", the respective low-level potentials provided by the two pieces of wiring do not necessarily have to be equal to each other.

[0034] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers, unless otherwise specified. Carriers here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in wiring, etc., is taken as the direction in which positive carriers move, and is described with a positive current amount. In other words, the direction in which negative carriers move is the opposite of the direction of current, and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), descriptions such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, descriptions such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0035] Also, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0036] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and the like, and can be appropriately rephrased according to the situation. For example, in the expression "insulator located on the upper surface of the conductor", by rotating the orientation of the shown drawing by 180 degrees, it can be rephrased as "insulator located on the lower surface of the conductor".

[0037] Also, the terms "above" or "below" do not limit the positional relationship of components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed directly in contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0038] In addition, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other according to the situation. For example, in some cases, the term "conductive layer" can be changed to the term "conductive film". Or, for example, in some cases, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases, or according to the situation, it is possible to replace the terms such as "film" and "layer" with other terms without using them. For example, in some cases, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, in some cases, the terms "insulating layer" and "insulating film" can be changed to the term "insulator".

[0039] Also, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the term "electrode" or "wiring" also includes cases where a plurality of "electrodes" or "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and for example, a "terminal" can be part of "wiring" or "electrode". Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced by terms such as "region" in some cases.

[0040] Also, in this specification and the like, terms such as "wiring", "signal line", "power supply line", etc. can be interchanged with each other depending on the case or the situation. For example, the term "wiring" may be changed to the term "signal line" in some cases. Also, for example, the term "wiring" may be changed to terms such as "power supply line" in some cases. Also, vice versa, terms such as "signal line" and "power supply line" may be changed to the term "wiring" in some cases. Terms such as "power supply line" may be changed to terms such as "signal line" in some cases. Also, vice versa, terms such as "signal line" may be changed to terms such as "power supply line" in some cases. Also, the term "potential" applied to the wiring may be changed to terms such as "signal" depending on the case or the situation. Also, vice versa, terms such as "signal" may be changed to the term "potential" in some cases.

[0041] In this specification and the like, the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are included, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, oxygen, etc., excluding hydrogen.

[0042] In this specification and the like, a switch refers to something that has a function of controlling whether to conduct (on state) or not to conduct (off state), and thus control whether to allow current to flow or not. Or, a switch refers to something that has a function of selecting and switching the path through which current flows. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control current and is not limited to a specific one.

[0043] As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conducting state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When operating a transistor merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, conduction and non-conduction are controlled for operation.

[0045] In this specification, "parallel" refers to a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "substantially parallel" or "approximately parallel" refers to a state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" refers to a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included. Also, "substantially perpendicular" or "approximately perpendicular" refers to a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

Advantages of the Invention

[0046] According to one aspect of the present invention, a semiconductor device having a function of shifting an input voltage to a lower voltage or a higher voltage can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced circuit area can be provided.

[0047] Or, according to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to one aspect of the present invention, an imaging device having the above semiconductor device can be provided.

[0048] Note that the effects of one aspect of the present invention are not limited to the above-listed effects. The above-listed effects do not prevent the existence of other effects. Other effects are effects not mentioned in this item as described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may, in some cases, not have the above-listed effects.

Brief Description of the Drawings

[0049] FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 2 is a timing chart showing an operation example of a semiconductor device. FIG. 3 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 4A is a circuit diagram showing a configuration example of a capacitor, and FIG. 4B is a circuit diagram showing a configuration example of a semiconductor device. FIG. 5 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 6 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 7 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIGS. 8A to 8C are schematic cross-sectional views showing configuration examples of a transistor. FIG. 9 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIG. 10 is a schematic cross-sectional view showing a configuration example of a semiconductor device. FIGS. 11A and 11B are schematic cross-sectional views showing a configuration example of a transistor. FIGS. 12A and 12B are schematic cross-sectional views showing a configuration example of a transistor. FIG. 13A is a top view showing a configuration example of a capacitor, and FIGS. 13B and 13C are perspective cross-sectional views showing a configuration example of a capacitor. FIG. 14A is a top view showing a configuration example of a capacitor, FIG. 14B is a cross-sectional view showing a configuration example of a capacitor, and FIG. 14C is a perspective cross-sectional view showing a configuration example of a capacitor. FIG. 15 is a schematic cross-sectional view showing a configuration example of an imaging device. FIG. 16 is a schematic cross-sectional view showing a configuration example of an imaging device. FIG. 17A is a diagram for explaining the classification of the crystal structure of IGZO, FIG. 17B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 17C is a diagram for explaining the selected area electron diffraction pattern of crystalline IGZO. FIG. 18A is a perspective view showing an example of a semiconductor wafer, FIG. 18B is a perspective view showing an example of a chip, and FIGS. 18C and 18D are perspective views showing an example of an electronic component. FIGS. 19A to 19F are perspective views of a package and a module containing an imaging device. FIG. 20 is a perspective view showing an example of an electronic device.

DETAILED DESCRIPTION OF THE INVENTION

[0050] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Further, when described as an OSFET or an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0051] In this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0052] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0053] Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with at least one of the content described in another content (even part of the content) described in the same embodiment and the content (even part of the content) described in one or more other embodiments.

[0054] Note that the content described in the embodiments refers to the content described using various figures or the content described using the text described in the specification in each embodiment (or example).

[0055] Note that the figure (which may be only a part) described in one embodiment can be combined with at least one of another part of the figure, another figure (which may be only a part) described in the embodiment, and a figure (which may be only a part) described in one or more other embodiments to form more figures.

[0056] The embodiments described in this specification will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description may be omitted. Also, in perspective views and the like, for the sake of clarity of the drawings, the description of some components may be omitted.

[0057] In this specification and the like, when the same reference numerals are used for a plurality of elements, particularly when it is necessary to distinguish them, an identification symbol such as "_1", "[n]", "[m,n]" may be appended to the reference numerals for description.

[0058] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0059] (Embodiment 1) In this embodiment, a level shifter, which is a semiconductor device according to one aspect of the present invention, will be described.

[0060] Note that the level shifter in this specification and the like is a potential level conversion circuit that converts the input voltage level to another voltage level. At this time, the other voltage may be lower or higher than the input voltage. Note that depending on the input voltage, the level shift may not be performed and the same voltage as the input voltage may be output. For example, the level shifter in this specification and the like may have a function of level shifting the input high-level potential to the first potential and the input low-level potential to the second potential. Note that the first potential may be a potential higher than the high-level potential, the high-level potential, or a potential lower than the high-level potential, and the second potential may be a potential higher than the low-level potential, the low-level potential, or a potential lower than the low-level potential. Therefore, for example, the level shifter in this specification and the like may have a function of level shifting one of the input high-level potential or low-level potential to a potential higher than the high-level potential and the other of the input high-level potential or low-level potential to a potential lower than the low-level potential.

[0061] The level shifter, which is a semiconductor device according to one aspect of the present invention, is a circuit using the architecture of a dynamic logic circuit. The dynamic logic circuit is, for example, a circuit in which circuit driving is performed by operations including temporarily holding data, precharging a potential, evaluating, and the like.

[0062] FIG. 1 shows a configuration example of the level shifter. The level shifter 100 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a capacitor C1, and a capacitor CL.

[0063] Transistors Tr1 to Tr4 are preferably, as an example, OS transistors. In addition, the channel formation regions of transistors Tr1 to Tr4 are more preferably oxides containing at least one of indium, gallium, and zinc. Further, as an alternative to the oxide, an oxide containing at least one of indium, element M (element M includes, for example, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.), and zinc may be used. Transistors Tr1 to Tr4 are more preferably the transistor structures described in Embodiment 2 in particular.

[0064] Alternatively, transistors Tr1 to Tr4 may be, as an example, transistors having silicon in the channel formation region (referred to as Si transistors in this specification). As the silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used.

[0065] Alternatively, as examples other than OS transistors and Si transistors, transistors Tr1 to Tr4 may include transistors in which Ge, etc. is included in the channel formation region, transistors in which compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, SiGe are included in the channel formation region, transistors in which carbon nanotubes are included in the channel formation region, transistors in which organic semiconductors are included in the channel formation region, etc.

[0066] Each of transistors Tr1 to Tr4 has the same structure and materials (for example, materials such as semiconductors, insulators, and conductors included in the channel formation region), so that transistors Tr1 to Tr4 can be manufactured by the same process, thus shortening the manufacturing process of level shifter 100. Note that the semiconductor device according to an aspect of the present invention is not limited thereto. For example, some of transistors Tr1 to Tr4 may be transistors having different structures and materials. For example, transistors Tr1, Tr3, and Tr4 may be OS transistors, and transistor Tr2 may be a Si transistor.

[0067] Also, in FIG. 1, back gates are shown for transistors Tr1 to Tr4, and although the connection configuration of the back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the back gate of transistor Tr1 may be electrically connected, the gate and the back gate of transistor Tr2 may be electrically connected, the gate and the back gate of transistor Tr3 may be electrically connected, or the gate and the back gate of transistor Tr4 may be electrically connected. Further, for example, in a transistor having a back gate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit or the like may be provided, and a configuration may be adopted in which a potential is applied to the back gate of the transistor by the external circuit or the like.

[0068] Note that the threshold voltages of transistors Tr1 to Tr4 are V TH1 , V TH2 , V TH3 , V TH4 respectively. Also, in this specification and the like, unless otherwise specified, VTH1 up to V TH4 Each of them shall be a real number greater than 0.

[0069] Also, although the transistors Tr1 to Tr4 illustrated in FIG. 1 have back gates, the semiconductor device according to one aspect of the present invention is not limited thereto. For example, the transistors Tr1 to Tr4 illustrated in FIG. 1 may be configured not to have a back gate, that is, may be transistors having a single gate structure. Further, some of the transistors may have a configuration with a back gate, and some other transistors may have a configuration without a back gate.

[0070] Also, although the transistors Tr1 to Tr4 illustrated in FIG. 1 are n-channel transistors, the semiconductor device according to one aspect of the present invention is not limited thereto. For example, some or all of the transistors Tr1 to Tr4 may be replaced with p-channel transistors.

[0071] Note that the modification examples regarding the structure and polarity of the above transistors are not limited to only the transistors Tr1 to Tr4. For example, regarding the transistors described in other parts of the specification, the transistors illustrated in other drawings, etc., the structure and polarity of the transistors may be modified in the same manner as above.

[0072] When there is no particular notice, the transistors Tr1 to Tr4 may operate in the saturation region when they are in the on state. That is, when the transistors Tr1 to Tr4 are in the on state, the gate voltage, source voltage, and drain voltage of the transistors Tr1 to Tr4 may be appropriately biased to voltages within the range of operating in the saturation region.

[0073] The first terminal of transistor Tr1 is electrically connected to wiring VDHE, the second terminal of transistor Tr1 is electrically connected to the first terminal of transistor Tr2 and wiring BOTE, and the gate of transistor Tr1 is electrically connected to wiring PRCE. The second terminal of transistor Tr2 is electrically connected to the first terminal of transistor Tr3, and the gate of transistor Tr2 is electrically connected to the first terminal of transistor Tr4 and the first terminal of capacitor C1. The second terminal of transistor Tr3 is electrically connected to wiring VLSE, and the gate of transistor Tr3 is electrically connected to wiring EVE. The second terminal of transistor Tr4 is electrically connected to wiring VLSE, and the gate of transistor Tr4 is electrically connected to wiring CLPE. Also, the second terminal of capacitor C1 is electrically connected to wiring INE. Also, the first terminal of capacitor CL is electrically connected to wiring BOTE, and the second terminal of capacitor CL is electrically connected to wiring VLSE.

[0074] Also, level shifter 100 has, as an example, memory unit AM. Memory unit AM has, as an example, transistor Tr4 and capacitor C1. Also, in this specification and the like, the electrical connection point of the gate of transistor Tr2, the first terminal of capacitor C1, and the first terminal of transistor Tr4 is referred to as node FN.

[0075] Memory unit AM has a function of holding the potential at node FN. Specifically, for example, when a high-level potential is input to wiring CLPE and transistor Tr4 is turned on, the connection between node FN and wiring VLSE becomes conductive, and the potential of node FN becomes the potential provided from wiring VLSE. Here, when a low-level potential is input to wiring CLPE and transistor Tr4 is turned off, memory unit AM can hold the potential given to node FN by wiring VLSE.

[0076] The capacitance CL is provided to stabilize the output signal from the wiring BOTE. Specifically, for example, when a voltage is output to the wiring BOTE and the transistors Tr1 and Tr2 are in the off state, the capacitance CL can hold the voltage. On the other hand, if the capacitance CL is not provided, the voltage of the wiring BOTE may vary due to leakage currents from the transistors Tr1, Tr2, etc. Therefore, it is preferable that the level shifter 100 is provided with the capacitance CL. Note that if the output signal from the wiring BOTE does not change unfavorably due to parasitic capacitance or the like, the capacitance CL may not be provided in the level shifter 100.

[0077] The wiring VDHE functions as a wiring for supplying a constant voltage as an example. Note that the constant voltage is the power supply voltage on the high level side in the level shifter 100. In this specification and the like, the power supply voltage is referred to as VDDH.

[0078] The wiring VLSE functions as a wiring for supplying a constant voltage as an example. Note that the constant voltage is the power supply voltage on the low level side in the level shifter 100. In this specification and the like, the power supply voltage is referred to as VSSL. Also, VSSL is a voltage lower than VDDH.

[0079] The wiring INE is electrically connected to the input terminal of the level shifter 100 as an example, and the wiring INE functions as a wiring for supplying an input voltage to the input terminal. For example, the input voltage can be a voltage output from a logic circuit or the like that is electrically connected to the level shifter 100 via the wiring INE. Note that the input voltage (the output voltage of the logic circuit) can be, for example, a high level potential or a low level potential. In this specification, the high level potential is referred to as VDD, and the low level potential is referred to as VSS. Also, VDD is a voltage higher than VSS and lower than VDDH. Also, VSS is a voltage higher than VSSL.

[0080] In the level shifter 100, when the VDD input to the wiring INE is not level-shifted to VDDH, the fixed voltage provided by the wiring VDHE may be set to VDDH = VDD. Alternatively, in the level shifter 100, when the VSS input to the wiring INE is not level-shifted to VSSL, the fixed voltage provided by the wiring VLSE may be set to VSSL = VSS.

[0081] The wiring PRCE functions as a wiring for controlling the presence or absence of charge of the potential from the wiring VDHE to the wiring BOTE as an example. Specifically, for example, the wiring PRCE can be a wiring that provides VDDH + V TH1 or VSS. Note that V TH1 is the threshold voltage of the transistor Tr1. Also, the high-level potential provided by the wiring PRCE may be VDDH + V TH1 instead of VDDH, or may be a potential exceeding VDDH + V TH1 .

[0082] The wiring EVE functions as a wiring for providing an evaluation signal as an example. Specifically, for example, the wiring EVE can be a wiring that provides VDDH + V TH3 or VSS. Note that V TH3 is the threshold voltage of the transistor Tr3. Also, the high-level potential provided by the wiring EVE may be VDDH + V TH3 instead of VDDH, or may be a potential exceeding VDDH + V TH3 . Also, the high-level potential provided by the wiring EVE may be a potential higher than V TH3 and lower than or equal to VDDH.

[0083] The wiring CLPE functions as a wiring for controlling the switching between the on state and the off state of the transistor Tr4 as an example. Specifically, for example, the wiring CLPE can be a wiring that provides VDD or VSSL. Also, the high-level potential provided by the wiring CLPE may be VDD + V TH4 instead of VDD, or may be a potential exceeding VDD + V TH4 . Note that V TH4Let it be the threshold voltage of transistor Tr4.

[0084] As an example, wiring BOTE is electrically connected to the input terminal of level shifter 100, and wiring BOTE functions as a wiring that outputs the output voltage in level shifter 100. Although it will be described in detail later, when VDD is input to wiring INE, level shifter 100 level-shifts VDD to VDDH, inverts the logic, and outputs VSSL to wiring BOTE. Alternatively, when VSS is input to wiring INE, level shifter 100 level-shifts VSS to VSSL, inverts the logic, and outputs VDDH to wiring BOTE.

[0085] [Operation example] Next, an operation example of level shifter 100 shown in FIG. 1 will be described.

[0086] FIG. 2 is a timing chart showing voltage changes in wiring CLPE, wiring PRCE, wiring EVE, wiring INE, node FN, and wiring BOTE at times T1 to T9 and in the vicinity thereof.

[0087] It is assumed that before time T1, VSS is input to wiring INE, VSSL is input to wiring CLPE, VSSL is input to wiring PRCE, and VSSL is input to wiring EVE. Also, it is assumed that VSSL or VSS is held at node FN of memory unit AM, and VDDH or VSSL is output to wiring BOTE.

[0088] [Period of writing potential to memory unit AM] Between time T1 and time T3, VSSL is written to node FN of memory unit AM. Specifically, between time T1 and time T2, VDD is input to wiring CLPE as a high-level potential. As a result, when VDD is input to the gate of transistor Tr4, the gate-source voltage of transistor Tr4 becomes VDD - VSSL. Here, VDD - VSSL > V TH4 such that V TH4By making a determination, the transistor Tr4 can be turned on.

[0089] When the transistor Tr4 is turned on, the wiring VLSE and the node FN are in a conductive state. As a result, the potential of the node FN of the memory unit AM becomes VSSL.

[0090] Between time T2 and time T3, VSSL is input to the wiring CLPE as a low-level potential. As a result, when VSSL is input to the gate of the transistor Tr4, the gate-source voltage of the transistor Tr4 becomes 0. At this time, 0 < V TH4 Therefore, the transistor Tr4 is turned off.

[0091] When the transistor Tr4 is turned off, the wiring VLSE and the node FN are in a non-conductive state. As a result, VSSL is held at the node FN of the memory unit AM. Specifically, at this time, VSS-VSSL is held between the first terminal and the second terminal of the capacitor C1.

[0092] By the way, since VSSL is input to the gate of the transistor Tr3, the gate-source voltage of the transistor Tr3 becomes 0. At this time, 0 < V TH3 Therefore, the transistor Tr3 is turned off. Since the transistor Tr3 is turned off, no current flows between the source and drain of the transistor Tr2.

[0093] [Precharge period (1), Data input period (1)] Between time T3 and time T4, the potential of the wiring BOTE is precharged. Specifically, between time T3 and time T4, VDDH+V TH1 is input to the wiring PRCE as a high-level potential. As a result, VDDH+V is input to the gate of the transistor Tr1. TH1is input. Also, at this time, since VDDH is input to the first terminal of the transistor Tr1, it is charged until the potential of the second terminal of the transistor Tr1 reaches VDDH. When the second terminal of the transistor Tr1 reaches VDDH, the gate-source voltage of the transistor Tr1 becomes 0, and also 0 < V TH1 so the transistor Tr1 is in the off state. As a result, the potential of the wiring BOTE becomes VDDH.

[0094] Note that after the potential of the wiring BOTE is pre-charged, VSSL is input to the wiring PRCE as a low-level potential.

[0095] Also, between time T3 and time T4, data is input to the level shifter 100. Specifically, between time T3 and time T4, VDD is input to the wiring INE as a high-level potential.

[0096] When VDD is input to the wiring INE, the potential of the node FN fluctuates due to capacitive coupling in the capacitor C1. At this time, for example, the potential of the node FN becomes VSSL + α(VDD - VSS) due to capacitive coupling in the capacitor C1. Note that α is a capacitive coupling coefficient determined by the circuit configuration around the node FN and the like.

[0097] Note that as the timing of data input to the level shifter 100, it is preferably between time T3 and time T4, preferably while VDDH is input to the wiring PRCE. That is, the input of VDD to the wiring INE is preferably performed while the pre-charge of VDDH is being performed on the wiring BOTE.

[0098] [Non-overlap period (1)] The period from time T4 to time T5 is a non-overlap period. The non-overlap period is provided to prevent the pre-charge period from time T3 to time T4 described above and the evaluation period from time T5 to time T6 described below from overlapping. Note that if the pre-charge period and the evaluation period do not overlap, the non-overlap period may not be provided.

[0099] [Evaluation period (1)] During the period from time T5 to time T6, the signal input to the wiring INE is evaluated. Specifically, during the period from time T5 to time T6, for example, a high-level potential of VDDH + V is input to the wiring EVE. TH3 As a result, VDDH + V is input to the gate of the transistor Tr3. TH3 When VDDH + V is input to the gate of the transistor Tr3, TH3 the gate-source voltage of the transistor Tr3 becomes VDDH + V - VSSL. Here, since VDDH + V - VSSL > V, that is, VDDH - VSSL > 0 is satisfied, the transistor Tr3 can be turned on. Therefore, the second terminal of the transistor Tr2 and the wiring VLSE are in a conductive state, and the potential VSSL provided by the wiring VLSE is input to the second terminal of the transistor Tr2. Note that a potential V that is higher than V and lower than or equal to VDDH may be input to the wiring EVE as the high-level potential. In this case, since the gate-source voltage of the transistor Tr3 becomes V - VSSL, the transistor Tr3 can be turned on by setting VSSL so that V - VSSL > V is satisfied. TH3 -VSSL TH3 -VSSL > V TH3 is satisfied, the transistor Tr3 can be turned on. Therefore, the second terminal of the transistor Tr2 and the wiring VLSE are in a conductive state, and the potential VSSL provided by the wiring VLSE is input to the second terminal of the transistor Tr2. Note that a potential V that is higher than V and lower than or equal to VDDH may be input to the wiring EVE as the high-level potential. In this case, since the gate-source voltage of the transistor Tr3 becomes V - VSSL, the transistor Tr3 can be turned on by setting VSSL so that V - VSSL > V is satisfied. TH3 higher than V and lower than or equal to VDDH, EVE V, may be input. EVE -VSSL EVE -VSSL > V TH3 is satisfied, the transistor Tr3 can be turned on.

[0100] At this time, the gate-source voltage of the transistor Tr2 becomes VSSL + α(VDD - VSS) - VSSL = α(VDD - VSS). Here, V TH2when α(VDD - VSS)>V TH2 By satisfying this condition, transistor Tr2 turns on.

[0101] When each of transistor Tr2 and transistor Tr3 turns on, a conductive state is established between wiring BOTE and wiring VLSE. Therefore, the VDDH charged on wiring BOTE is discharged to VSSL provided by wiring VLSE. As a result, wiring BOTE outputs VSSL.

[0102] Note that after VSSL is output from wiring BOTE, VSSL is input to wiring EVE as a low - level potential. Thereby, VSSL is input to the gate of transistor Tr3. When VSSL is input to the gate of transistor Tr3, the gate - source voltage of transistor Tr3 becomes VSSL - VSSL = 0. Also, since 0 < V TH3 transistor Tr3 turns off.

[0103] [Pre - charge period (2), Data input period (2)] Between time T6 and time T7, the potential of wiring BOTE is pre - charged. Specifically, between time T6 and time T7, the operation between time T3 and time T4 is performed in the same manner. For this reason, VDDH + V TH1 is input to wiring PRCE as a high - level potential, and the potential of wiring BOTE becomes VDDH.

[0104] Note that after the potential of wiring BOTE is pre - charged, VSSL is input to wiring PRCE as a low - level potential.

[0105] Also, between time T6 and time T7, data is input to level shifter 100. Specifically, between time T6 and time T7, VSS is input to wiring INE as a low - level potential.

[0106] When VSS is input to the wiring INE, the potential of the node FN fluctuates due to capacitive coupling in the capacitor C1. At this time, since the potential of the wiring INE is VSS, the potential of the node FN returns to the potential of the node FN from time T2 to time T3. That is, the potential of the node FN between time T6 and time T7 becomes VSSL.

[0107] Note that as the timing of data input to the level shifter 100, it is preferable that it is between time T6 and time T7, preferably while VDDH is input to the wiring PRCE. That is, the input of VSS to the wiring INE is preferably performed while the pre-charge of VDDH is being performed on the wiring BOTE.

[0108] [Non-overlap period (2)] The period from time T7 to time T8 is the same non-overlap period as the period from time T4 to time T5. Therefore, for the non-overlap period, refer to the description of the operation between time T4 and time T5.

[0109] [Evaluation period (2)] Between time T8 and time T9, the signal input to the wiring INE is evaluated. Specifically, between time T8 and time T9, VDDH + V is input to the wiring EVE as a high-level potential. TH3 For this reason, similar to the operation between time T5 and time T6, the transistor Tr3 is turned on. Also, thereby, VSSL given by the wiring VLSE is input to the second terminal of the transistor Tr2.

[0110] At this time, the gate-source voltage of the transistor Tr2 becomes VSSL - VSSL = 0. Also, since 0 < V TH2 the transistor Tr2 is turned off. As a result, the potential of the wiring BOTE remains at VDDH charged between time T6 and time T7. As a result, the wiring BOTE outputs VDDH.

[0111] After the output of VDDH is performed from the wiring BOTE, VSSL is input to the wiring EVE as a low-level potential. As a result, the transistor Tr3 is turned off.

[0112] According to the above-described operation example, the input VDD can be level-shifted to VSSL lower than VSS, or the input VSS can be level-shifted to VDDH higher than VDD.

[0113] Note that the semiconductor device according to one aspect of the present invention is not limited to the configuration of FIG. 1. The semiconductor device according to one aspect of the present invention may be one in which the circuit configuration of the level shifter 100 shown in FIG. 1 is changed according to the situation.

[0114] For example, the level shifter 100 shown in FIG. 1 may be changed to the circuit configuration of the level shifter 100A shown in FIG. 3. Specifically, the level shifter 100A has a configuration in which the transistor Tr2 and the transistor Tr3 are interchanged in the level shifter 100.

[0115] Regarding the circuit configuration of the level shifter 100A in FIG. 3, only the points different from the level shifter 100 in FIG. 1 will be described. The first terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr3, the second terminal of the transistor Tr3 is electrically connected to the first terminal of the transistor Tr2, and the second terminal of the transistor Tr2 is electrically connected to the wiring VLSE.

[0116] As an operation example of the level shifter 100A in FIG. 3, for example, it can be the same as the timing chart of FIG. 2 which is the operation example of the level shifter 100 in FIG. 1.

[0117] Also, for example, the level shifter 100 shown in FIG. 1 may be configured such that each of the capacitor C1 and the capacitor CL has a transistor. FIG. 4A shows a configuration in which the capacitor C1 (capacitor CL) includes a transistor Tc1 (transistor TcL). Specifically, the first terminal and the second terminal of the transistor Tc1 (transistor TcL) are used as one of the first terminal or the second terminal of the capacitor C1 (capacitor CL), and the gate of the transistor Tc1 (transistor TcL) is used as the other of the first terminal or the second terminal of the capacitor C1 (capacitor CL). That is, the transistor Tc1 substitutes for the capacitor C1 using the gate capacitance of the transistor Tc1. Similarly, the transistor TcL substitutes for the capacitor CL using the gate capacitance of the transistor TcL. The level shifter 100B shown in FIG. 4B has a configuration in which each of the capacitor C1 and the capacitor CL is replaced with a transistor Tc1 and a transistor TcL. Note that the threshold voltage of the transistor Tc1 (transistor TcL) is preferably lower than the voltage between the gate of the transistor Tc1 (transistor TcL) and the source or drain of the transistor Tc1 (transistor TcL). Also, since the level shifter 100B shown in FIG. 4B can fabricate the transistor Tc1 (transistor TcL) as the capacitor C1 (capacitor CL) in the process of forming the transistor, the process of forming a capacitor such as a planar type or a trench type can be omitted. That is, the time required to fabricate the level shifter 100B can be shortened.

[0118] Further, for example, the level shifter 100 shown in FIG. 1 may be configured such that the second terminal of the capacitor CL is not connected to the wiring VLSE but is electrically connected to another wiring. As such a configuration, for example, the configuration of the level shifter 100C shown in FIG. 5 can be adopted. The level shifter 100C is different from the level shifter 100 in that the second terminal of the capacitor CL is electrically connected to the wiring VAL. The wiring VAL functions as a wiring for supplying a constant voltage, similar to the wiring VLSE. Note that the constant voltage may be VSS, ground potential (GND), etc., instead of VSSL supplied by the wiring VLSE. Alternatively, depending on the situation, the wiring VAL may be a wiring for supplying a voltage such as VDD or VDDH. Or, the wiring VAL may be electrically connected to the wiring VDHE.

[0119] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0120] (Embodiment 2) In this embodiment, a configuration example of the semiconductor device and a configuration example of the transistor applicable to the semiconductor device described in the above embodiment will be described.

[0121] <Configuration Example of Semiconductor Device> The semiconductor device shown in FIG. 6 includes a transistor 300, a transistor 500, and a capacitive element 600. FIG. 8A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 8B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 8C is a cross-sectional view of the transistor 300 in the channel width direction.

[0122] The transistor 500 is a transistor having a metal oxide in the channel formation region (OS transistor). The transistor 500 has characteristics of a small off-current and no change in the field-effect mobility even at high temperatures. By applying the transistor 500 to a semiconductor device, for example, the transistors included in the level shifters 100, 100A, 100B, 100C, etc. described in the above embodiments, a semiconductor device whose operating ability does not deteriorate even at high temperatures can be realized. In particular, by using the characteristic of a small off-current and applying the transistor 500 to the transistor Tr4, the potential written to the node FN of the memory unit AM can be held for a long time.

[0123] In the semiconductor device shown in FIG. 6, the transistor 500 is provided, for example, above the transistor 300, and the capacitor element 600 is provided, for example, above the transistor 300 and the transistor 500. Note that the capacitor element 600 can be a capacitor included in the level shifters 100, 100A, 100B, 100C, etc. described in the above embodiments. Depending on the circuit configuration, the capacitor element 600 shown in FIG. 6 may not necessarily be provided.

[0124] The transistor 300 is provided on a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b. Note that the transistor 300 can be applied to, for example, transistors included in the level shifters 100, 100A, 100B, 100C, etc. described in the above embodiments. Specifically, for example, it can be the transistor Tr2 included in the level shifter 100 of FIG. 1. Note that FIG. 6 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source or drain of the transistor 500 via one of the pair of electrodes of the capacitor element 600. However, depending on the configurations of the level shifter 100, level shifter 100A, level shifter 100B, level shifter 100C, etc., one of the source or drain of the transistor 300 may be electrically connected to one of the source or drain of the transistor 500 via one of the pair of electrodes of the capacitor element 600, or one of the source or drain of the transistor 300 may be electrically connected to the gate of the transistor 500 via one of the pair of electrodes of the capacitor element 600. Also, each terminal of the transistor 300 may not be electrically connected to each terminal of the transistor 500 and each terminal of the capacitor element 600.

[0125] Further, as the substrate 311, it is preferable to use a semiconductor substrate (for example, a single-crystal substrate or a silicon substrate).

[0126] As shown in FIG. 8C, in the transistor 300, the upper surface and the side surface in the channel width direction of the semiconductor region 313 are covered with the conductor 316 via the insulator 315. In this way, by forming the transistor 300 into a Fin type, the effective channel width is increased, so that the on characteristics of the transistor 300 can be improved. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

[0127] Note that the transistor 300 may be either p-channel type or n-channel type.

[0128] In the region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or the drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0129] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0130] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0131] Note that since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0132] Note that the transistor 300 shown in FIG. 6 is an example, and the structure is not limited thereto. An appropriate transistor may be used according to the circuit configuration, driving method, etc. For example, when the semiconductor device is a unipolar circuit of only OS transistors, as shown in FIG. 7, the configuration of the transistor 300 may be the same as that of the transistor 500 using an oxide semiconductor. Details of the transistor 500 will be described later.

[0133] Note that in FIG. 7, the transistor 300 is provided on the substrate 312. In this case, as the substrate 312, a semiconductor substrate may be used in the same manner as the substrate 311 of the semiconductor device in FIG. 6. Further, as the substrate 312, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Or, as an example, there is a synthetic resin such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Or, as an example, there are polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or papers.

[0134] Over the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially laminated and provided.

[0135] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0136] In addition, in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0137] The insulator 322 may have a function as a planarization film that planarizes a step generated by a transistor 300 or the like provided below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0138] In addition, for the insulator 324, it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse from the substrate 311 or the transistor 300 or the like into the region where the transistor 500 is provided.

[0139] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0140] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in the TDS analysis, when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen atoms, per unit area of the insulator 324, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less.

[0141] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0142] In addition, a capacitor element 600, or conductors 328 and 330 connected to the transistor 500, etc. are embedded in the insulators 320, 322, 324, and 326. Note that the conductors 328 and 330 have the function of plugs or wirings. Also, conductors having the function of plugs or wirings may be given the same reference numeral when summarizing a plurality of structures. Also, in this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0143] As the material of each plug and wiring (conductors 328, 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used singly or in a laminated manner. It is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0144] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 6, the insulator 350, the insulator 352, and the insulator 354 are sequentially stacked and provided. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using the same material as the conductor 328 and the conductor 330.

[0145] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350 as in the case of the insulator 324. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0146] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0147] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 6, the insulator 360, the insulator 362, and the insulator 364 are sequentially stacked and provided. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

[0148] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 360. Further, conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 360 having a barrier property against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0149] A wiring layer may be provided on insulator 364 and conductor 366. For example, in FIG. 6, insulators 370, 372, and 374 are sequentially stacked and provided. Further, conductor 376 is formed in insulators 370, 372, and 374. Conductor 376 has a function as a plug or wiring. Note that conductor 376 can be provided using the same materials as conductor 328 and conductor 330.

[0150] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 370. Further, conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 370 having a barrier property against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0151] A wiring layer may be provided on insulator 374 and conductor 376. For example, in FIG. 6, insulators 380, 382, and 384 are sequentially stacked and provided. Further, conductor 386 is formed in insulators 380, 382, and 384. Conductor 386 has a function as a plug or wiring. Note that conductor 386 can be provided using the same materials as conductor 328 and conductor 330.

[0152] Note that, for example, as with the insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 380. Further, the conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by the barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0153] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or may be five or more.

[0154] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked and provided. Any one of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 preferably uses a material having a barrier property against oxygen and hydrogen.

[0155] For example, for the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse from, for example, the substrate 311 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, the same material as that of the insulator 324 can be used.

[0156] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0157] Further, as a film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.

[0158] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable to be used as a protective film for the transistor 500.

[0159] Further, for example, the same materials as those of the insulator 320 can be used for the insulator 512 and the insulator 516. In addition, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, etc. can be used as the insulator 512 and the insulator 516.

[0160] In addition, conductors such as conductor 518 and the conductors (for example, conductor 503) that make up transistor 500 are embedded in insulator 510, insulator 512, insulator 514, and insulator 516. Note that conductor 518 has a function as a plug connected to capacitor element 600 or transistor 300, or as a wiring. Conductor 518 can be provided using the same material as conductor 328 and conductor 330.

[0161] In particular, conductor 518 in the region in contact with insulator 510 and insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0162] A transistor 500 is provided above insulator 516.

[0163] As shown in FIGS. 8A and 8B, transistor 500 includes conductor 503 arranged to be embedded in insulator 514 and insulator 516, insulator 520 arranged on insulator 516 and conductor 503, insulator 522 arranged on insulator 520, insulator 524 arranged on insulator 522, oxide 530a arranged on insulator 524, oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, insulator 580 arranged on conductors 542a and 542b and having an opening formed by overlapping between conductor 542a and conductor 542b, oxide 530c arranged on the bottom surface and side surface of the opening, insulator 550 arranged on the formation surface of oxide 530c, and conductor 560 arranged on the formation surface of insulator 550. In this specification and the like, conductors 542a and 542b are collectively referred to as conductor 542.

[0164] Also, as shown in FIGS. 8A and 8B, it is preferable that an insulator 544 is disposed between the oxides 530a, 530b, the conductors 542a, 542b, and the insulator 580. Further, as shown in FIGS. 8A and 8B, the conductor 560 preferably has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 8A and 8B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550.

[0165] In the following, the oxides 530a, 530b, and 530c may be collectively referred to as the oxide 530.

[0166] In the transistor 500, a configuration in which three layers of the oxides 530a, 530b, and 530c are laminated in a region where a channel is formed and in the vicinity thereof is shown, but one aspect of the present invention is not limited thereto. For example, a single layer of the oxide 530b, a two-layer structure of the oxides 530b and 530a, a two-layer structure of the oxides 530b and 530c, or a laminated structure of four or more layers may be provided. Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated structure, but one aspect of the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers. Also, the transistor 500 shown in FIGS. 6, 8A, and 8B is an example, and the structure is not limited thereto, and an appropriate transistor may be used according to the circuit configuration, driving method, etc.

[0167] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-alignedly selected with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

[0168] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0169] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently without being linked to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made greater than 0V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0170] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and can cover the channel formation region formed in the oxide 530. In this specification etc., the structure of a transistor that electrically surrounds the channel formation region by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0171] Also, the conductor 503 has the same configuration as the conductor 518. The conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside. Note that in the transistor 500, a configuration in which the conductor 503a and the conductor 503b are laminated is shown, but one aspect of the present invention is not limited to this. For example, the conductor 503 may be provided in a single layer or a laminated structure of three or more layers.

[0172] Here, it is preferable to use a conductive material in which the conductor 503a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use a conductive material in which the conductor 503a has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0173] For example, when the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0174] Also, when the conductor 503 also functions as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b. Further, when the conductivity of the wiring can be maintained high, in that case, the conductor 503a does not necessarily have to be provided. Although the conductor 503b is illustrated as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above-described conductive material.

[0175] The insulators 520, 522, and 524 have a function as a second gate insulating film.

[0176] Here, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition for the insulator 524 in contact with the oxide 530. That is, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiency in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved.

[0177] Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which some oxygen desorbs by heating. The oxide that desorbs oxygen by heating is an oxide film in which the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more in the TDS (Thermal Desorption Spectroscopy) analysis. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0178] Further, the insulator having the above-described excess oxygen region and the oxide 530 may be subjected to one or more of heat treatment, microwave treatment, or RF treatment while being in contact with each other. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the bond of VoH is broken, in other words, a reaction of "V O H → V O + H" occurs, and dehydrogenation can be achieved. A part of the hydrogen generated at this time may combine with oxygen to form H2O and be removed from the oxide 530 or the insulator near the oxide 530. Also, a part of the hydrogen may diffuse or be trapped (also referred to as gettering) in the conductors 542a and 542b.

[0179] Further, the above-described microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Also, the above-described microwave treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa or more, more preferably 400 Pa or more. Also, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2 + Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0180] Further, during the manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 530 to create oxygen vacancies (V OReduction of ) can be achieved. Also, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after heat treatment in an atmosphere of nitrogen gas or an inert gas, in order to supplement the desorbed oxygen. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0181] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired with the supplied oxygen. In other words, the reaction of "V O +O→null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide 530 can be prevented from recombining with the oxygen deficiency to form V O H.

[0182] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0183] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., so that the oxygen in the oxide 530 does not diffuse to the insulator 520 side. Also, the conductor 503 can be prevented from reacting with the oxygen in the insulator 524, oxide 530, etc.

[0184] The insulator 522 preferably uses, as a single layer or a laminate, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0185] In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (such that the above oxygen is difficult to permeate). As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0186] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. The above insulators may be laminated with silicon oxide, silicon oxynitride, or silicon nitride and used.

[0187] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity can be obtained.

[0188] In transistors 500 of FIGS. 8A and 8B, insulator 520, insulator 522, and insulator 524 are illustrated as the second gate insulating film having a three-layer stacked structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more stacked structure. In that case, it is not limited to a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0189] For transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for oxide 530 including the channel formation region. For example, as oxide 530, a metal oxide such as In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. In particular, the In-M-Zn oxide applicable as oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). Also, In-Ga oxide, In-Zn oxide, In oxide, etc. may be used as oxide 530.

[0190] Also, for transistor 500, it is preferable to use a metal oxide with a low carrier concentration. When reducing the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be lowered and the density of defect levels may be lowered. In this specification, etc., a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0191] In particular, hydrogen contained in the metal oxide may react with oxygen bonded to the metal atom to form water, thereby forming oxygen vacancies in the metal oxide. Further, when hydrogen enters the oxygen vacancies in the oxide 530, the oxygen vacancies and hydrogen may combine to form V O H. V O V H may function as a donor and electrons that are carriers may be generated. Also, part of the hydrogen may combine with oxygen bonded to the metal atom to generate electrons that are carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the metal oxide is likely to move due to stress such as heat and an electric field, if the metal oxide contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the oxide 530 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, in order to obtain a metal oxide in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the metal oxide (which may be described as dehydration and dehydrogenation treatment), and to supply oxygen to the metal oxide to fill the oxygen vacancies (which may be described as oxygen addition treatment). V O By using a metal oxide in which impurities such as V

[0192] H are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted. Defects in which hydrogen enters oxygen vacancies can function as donors in the metal oxide. However, it is difficult to quantitatively evaluate such defects. Therefore, in the metal oxide, it may be evaluated by the carrier concentration instead of the donor concentration. Thus, in this specification and the like, as a parameter of the metal oxide, the carrier concentration assuming a state where no electric field is applied may be used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration" in some cases.

[0193] Therefore, when using a metal oxide for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 20 atoms / cm 3 less than 1×10 19 atoms / cm 3 preferably less than 1×10 18 atoms / cm 3 more preferably less than 5×10 18 atoms / cm 3 even more preferably less than 1×10 18 atoms / cm 3 By using a metal oxide with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0194] In addition, when using a metal oxide for the oxide 530, the metal oxide is a semiconductor with a high bandgap, intrinsic (also referred to as type I), or substantially intrinsic, and the carrier concentration of the metal oxide in the channel formation region is 18 cm -3 preferably less than 1×10 17 cm -3 more preferably less than 1×10 16 cm -3 even more preferably less than 1×10 13 cm -3 even more preferably less than 1×10 12 cm -3 even more preferably less than 1×10 12 cm -3 even more preferably less than 1×10 12 cm -3 Regarding the lower limit value of the carrier concentration of the metal oxide in the channel formation region, there is no particular limitation, but for example, it can be -9 cm -3 1×10 -9 cm -3 .

[0195] Further, when a metal oxide is used for the oxide 530, oxygen in the oxide 530 may diffuse into the conductors 542a and 542b upon contact therewith, and the conductors 542a and 542b may be oxidized. Oxidation of the conductors 542a and 542b increases the likelihood of a decrease in their conductivity. Note that the diffusion of oxygen in the oxide 530 into the conductors 542a and 542b can be alternatively described as absorption of oxygen in the oxide 530 by the conductors 542a and 542b.

[0196] In addition, when oxygen in the oxide 530 diffuses into the conductors 542a and 542b, a hetero-layer may be formed between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b. Since the hetero-layer contains more oxygen than the conductors 542a and 542b, the hetero-layer is presumed to be insulating. At this time, the three-layer structure of the conductor 542a or 542b, the hetero-layer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be referred to as a MIS (Metal-Insulator-Semiconductor) structure, or may be referred to as a diode junction structure mainly having a MIS structure.

[0197] Note that the formation of the hetero-layer is not limited to the region between the conductors 542a and 542b and the oxide 530b. For example, the hetero-layer may be formed between the conductors 542a and 542b and the oxide 530c, or may be formed between the conductors 542a and 542b and both the oxide 530b and the oxide 530c.

[0198] As the metal oxide that functions as a channel formation region in the oxide 530, a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, is preferably used. By using a metal oxide with a large bandgap in this way, the off-current of the transistor can be reduced.

[0199] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b. Also, by having the oxide 530c on the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b.

[0200] Note that the oxide 530 preferably has a laminated structure with a plurality of oxide layers having different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a. Also, the oxide 530c can use the metal oxide that can be used for the oxide 530a or the oxide 530b.

[0201] Specifically, as the oxide 530a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. Further, as the oxide 530b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 1:1:1 may be used. Further, as the oxide 530c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, or an atomic ratio of Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Further, as a specific example in the case where the oxide 530c has a laminated structure, there may be mentioned a laminated structure of an atomic ratio of In:Ga:Zn = 4:2:3 and In:Ga:Zn = 1:3:4, or a laminated structure of an atomic ratio of Ga:Zn = 2:1 and an atomic ratio of In:Ga:Zn = 4:2:3, or a laminated structure of an atomic ratio of Ga:Zn = 2:5 and an atomic ratio of In:Ga:Zn = 4:2:3, or a laminated structure of gallium oxide and an atomic ratio of In:Ga:Zn = 4:2:3, and the like.

[0202] Further, for example, when the atomic ratio of In to element M in the metal oxide used for the oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for the oxide 530b, as the oxide 530b, an In-Ga-Zn oxide having a composition such as In:Ga:Zn = 5:1:6 or in the vicinity thereof, In:Ga:Zn = 5:1:3 or in the vicinity thereof, In:Ga:Zn = 10:1:3 or in the vicinity thereof may be used.

[0203] Further, as compositions other than those described above, for the oxide 530b, for example, a metal oxide having a composition such as In:Zn = 2:1, In:Zn = 5:1, In:Zn = 10:1, or a composition in the vicinity of any one of these may be used.

[0204] It is preferable to combine these oxides 530a, 530b, and 530c so as to satisfy the above-mentioned relationship of atomic ratios. For example, it is preferable that the oxide 530a and the oxide 530c are metal oxides having a composition of In:Ga:Zn = 1:3:4 and compositions in the vicinity thereof, and the oxide 530b is a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1 and compositions in the vicinity thereof. Note that the above composition indicates the atomic ratio in the oxide formed on the substrate or the atomic ratio in the sputtering target. Also, as the composition of the oxide 530b, increasing the ratio of In is suitable because it can increase the on-current of the transistor, the field-effect mobility, etc.

[0205] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b.

[0206] Here, at the junction of the oxide 530a, the oxide 530b, and the oxide 530c, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is continuously joined. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c.

[0207] Specifically, by having a common element (as the main component) other than oxygen between the oxide 530a and the oxide 530b and between the oxide 530b and the oxide 530c, a mixed layer with a low density of defect energy levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is advisable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a and the oxide 530c.

[0208] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxides 530a and 530c as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0209] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements is preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0210] In FIGS. 8A and 8B, the conductors 542a and 542b are shown as single-layer structures, but they may also have a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0211] Also, a three-layer structure in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film is provided, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, etc. exist. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0212] Also, as shown in FIG. 8A, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0213] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0214] The insulator 544 is provided to cover the conductors 542a and 542b and suppress the oxidation of the conductors 542a and 542b. At this time, the insulator 544 may cover the respective side surfaces of the oxide 530 and the insulator 524 and be provided to contact the insulator 522.

[0215] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Also, as the insulator 544, silicon oxynitride, silicon nitride, etc. can also be used.

[0216] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate), etc., which are insulators containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent process. Note that when the conductors 542a and 542b are made of a material having oxidation resistance or the conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0217] By having the insulator 544, it is possible to suppress impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. Also, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen possessed by the insulator 580.

[0218] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (upper surface and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen upon heating, similar to the insulator 524 described above.

[0219] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0220] By providing an insulator that releases oxygen upon heating as insulator 550 in contact with the upper surface of oxide 530c, oxygen can be effectively supplied from insulator 550, through oxide 530c, to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 550 is reduced. The film thickness of insulator 550 is preferably 1 nm or more and 20 nm or less.

[0221] Further, in order to efficiently supply the excess oxygen possessed by insulator 550 to oxide 530, a metal oxide may be provided between insulator 550 and conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from insulator 550 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 550 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0222] Note that insulator 550 may have a laminated structure similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a laminated structure that is thermally stable and has a high relative dielectric constant can be formed.

[0223] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 8A and 8B, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0224] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Further, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0225] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0226] Insulator 580 is provided on conductor 542a and conductor 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, as insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0227] Insulator 580 preferably has an excess oxygen region. By providing insulator 580 that releases oxygen upon heating in contact with oxide 530c, the oxygen in insulator 580 can be efficiently supplied to oxide 530 through oxide 530c. Note that it is preferable that the concentration of impurities such as water or hydrogen in insulator 580 is reduced.

[0228] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b. Thereby, conductor 560 is formed to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0229] When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of conductor 560 from decreasing. Therefore, if the film thickness of conductor 560 is increased, conductor 560 can have a high aspect ratio shape. In the present embodiment, since conductor 560 is provided to be embedded in the opening of insulator 580, even if conductor 560 has a high aspect ratio shape, it can be formed without collapsing conductor 560 during the process.

[0230] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0231] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0232] In particular, aluminum oxide has high barrier properties, and even a thin film with a thickness of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0233] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0234] Also, the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductors 546 and 548 described later.

[0235] An insulator 582 is provided on an insulator 581. It is preferable to use a material that is barrier - resistant to oxygen, hydrogen, etc. for the insulator 582. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0236] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the entry of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0237] An insulator 586 is provided on the insulator 582. The same material as the insulator 320 can be used for the insulator 586. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, etc. can be used.

[0238] Conductors 546 and 548 are embedded in the insulator 520, insulator 522, insulator 524, insulator 544, insulator 580, insulator 574, insulator 581, insulator 582, and insulator 586.

[0239] The conductor 546 and the conductor 548 have functions as plugs or wirings connecting to the capacitor element 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be provided using the same materials as the conductor 328 and the conductor 330.

[0240] After the formation of the transistor 500, an opening may be formed so as to surround the transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 500 with the above-described insulator having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively wrapped with an insulator having high barrier properties against hydrogen or water. When forming an opening so as to surround the transistor 500, for example, when forming an opening reaching the insulator 514 or the insulator 522 and forming the above-described insulator having high barrier properties so as to be in contact with the insulator 514 or the insulator 522, it also serves as part of the manufacturing process of the transistor 500, which is preferable. As the insulator having high barrier properties against hydrogen or water, for example, the same material as that of the insulator 522 may be used.

[0241] Subsequently, a capacitor element 600 is provided above the transistor 500. The capacitor element 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0242] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor element 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0243] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0244] In FIG. 6, the conductor 612 and the conductor 610 are shown as single-layer structures, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, a conductor having barrier properties and a conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity, and a conductor having high adhesion to the conductor having high conductivity may be formed.

[0245] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when forming simultaneously with other structures such as conductors, Cu (copper), Al (aluminum), or the like, which are low-resistance metal materials, may be used.

[0246] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. Further, the insulator 650 may function as a planarization film that covers the uneven shape below it.

[0247] By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0248] Note that the semiconductor device according to one aspect of the present invention may be configured such that, for example, another semiconductor substrate on which a circuit is formed is bonded below the substrate 311 on which the transistor 300 is formed. FIG. 9 shows a configuration in which a layer SA, which is a part of the semiconductor device of FIG. 6, and a layer SB, in which a circuit is formed on another semiconductor substrate, are bonded together. Specifically, the semiconductor device shown in FIG. 9 has a configuration in which a substrate 211, in which a circuit or the like included in the layer SB is formed, is bonded below the substrate 311 included in the layer SA. Note that in FIG. 9, conductors, insulators, etc. above the insulator 360 in the layer SA are omitted.

[0249] As the substrate 211, for example, a substrate applicable to the substrate 311 of the semiconductor device of FIG. 6 can be used.

[0250] As an example, on the substrate 211, insulators 220, 222, 224, 226, and 230 are sequentially provided so as to cover the transistor 200, similarly to the transistor 300 on the substrate 311.

[0251] In addition, as the insulators 220, 222, 224, 226, 230, and 231, for example, materials applicable to the insulators 320, 322, 324, 326, and 230 can be used. Further, the insulators 220, 222, 224, 226, 230, and 231 can be formed, for example, by the same processes as those for the insulators 320, 322, 324, 326, and 350.

[0252] In addition, conductors 228 and 229 are embedded in the insulators 220, 222, 224, and 226. The conductors 228 and 229 have functions as plugs or wirings, similarly to the conductors 328 and 330. Further, as the conductors 228 and 229, materials applicable to the conductors 328 and 330 can be used.

[0253] The insulator 232 functions as a bonding layer for the insulator 341 provided below the substrate 311 to be described later. Further, a conductor 233 is embedded in the insulator 231 and the insulator 232 so as to be electrically connected to a part of the conductor 229, and the conductor 233 also functions as a part of the bonding layer.

[0254] As the insulator 232, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0255] As the conductor 233, for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold, etc. can be used. From the viewpoint of ease of bonding with the conductor 342 to be described later, it is preferable to use copper, aluminum, tungsten, or gold.

[0256] Note that the conductor 233 may have a multilayer structure including a plurality of layers. For example, a first conductor may be formed on the sidewalls of the openings of the insulator 231 and the insulator 232, and then a second conductor may be formed so as to fill the openings of the insulator 231 and the insulator 232. As the first conductor, for example, a conductor having a barrier property against hydrogen such as tantalum nitride can be used, and as the second conductor, for example, highly conductive tungsten can be used.

[0257] Also, an insulator 341 is formed below the substrate 311. The insulator 341 functions as a bonding layer for the insulator 232 on the substrate 211.

[0258] As the insulator 341, for example, materials applicable to the insulator 232 can be used. In particular, in order to bond the insulator 232 and the insulator 341, it is preferable that the insulator 232 and the insulator 341 are composed of the same components.

[0259] In layer SA, a conductor 342 is embedded in the insulator 341, the substrate 311, the insulator 320, and the insulator 322 so as to be electrically connected to a part of the conductor 330, and the conductor 342 also functions as a part of the bonding layer.

[0260] As the conductor 342, for example, a material applicable to the conductor 233 can be used. In particular, in order to bond the conductor 342 and the conductor 233, it is preferable that the conductor 342 and the conductor 233 use the same metal material.

[0261] Note that the conductor 342 may have a multilayer structure including a plurality of layers. For example, a first conductor may be formed on the sidewalls of the openings of the insulator 341, the substrate 311, the insulator 320, and the insulator 322, and then a second conductor may be formed so as to fill the openings of the insulator 341, the substrate 311, the insulator 320, and the insulator 322. As the first conductor, for example, a conductor having a barrier property against hydrogen such as tantalum nitride can be used, and as the second conductor, for example, highly conductive tungsten can be used.

[0262] Next, the bonding of layer SA and layer SB will be described.

[0263] In the pre-process of bonding layer SA and layer SB, in layer SB, the surfaces of the insulator 232 and the conductor 233 are planarized so that their heights are the same. Similarly, in layer SA, the surfaces of the insulator 341 and the conductor 342 are planarized so that their heights are the same.

[0264] In the bonding process, when bonding the insulator 232 and the insulator 341, that is, bonding the insulating layers, after providing high flatness by polishing or the like, hydrophilic treatment is performed with oxygen plasma or the like, and then the surfaces after the hydrophilic treatment are brought into contact with each other for temporary bonding, and a hydrophilic bonding method such as performing permanent bonding by dehydration by heat treatment can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, a mechanically excellent bond can be obtained.

[0265] Also, for example, when joining the conductor 233 and the conductor 342, that is, joining conductors together, a surface activation bonding method can be used in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact and joined. Alternatively, a diffusion bonding method or the like in which the surfaces are joined using a combination of temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.

[0266] By performing the above-described laminating step, the conductor 342 contained in the layer SA can be electrically connected to the conductor 233 contained in the layer SB. Also, a connection having mechanical strength can be obtained between the insulator 341 contained in the layer SA and the insulator 232 contained in the layer SB.

[0267] When laminating the layer SA and the layer SB, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a combination of a surface activation bonding method and a hydrophilic bonding method may be used.

[0268] For example, a method can be used in which the surface is cleaned after polishing, an antioxidant treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed for bonding. Also, the surface of the metal layer may be made of a metal with low oxidation resistance such as gold, and a hydrophilic treatment may be performed. Note that a bonding method other than the above-described methods may be used.

[0269] By using the above-described laminating step, a circuit can be further added to the semiconductor device. Therefore, an increase in the circuit area of the semiconductor device can be suppressed. Also, by the laminating step, another semiconductor device (for example, a logic circuit, a signal conversion circuit, a potential level conversion circuit, a current source, a voltage source, a switching circuit, an amplifier circuit, a photoelectric conversion circuit, an arithmetic circuit, etc.) can be electrically connected to the semiconductor device. Therefore, a new semiconductor device can be configured.

[0270] On the substrate 211 included in the layer SB, as an example, a transistor 200 is formed. In FIG. 9, as an example, the transistor 200 is shown having the same structure as the transistor 300, but the transistor 200 may have a structure different from that of the transistor 300. For example, as shown in FIG. 10, the transistor 200 may have the structure of the transistor 500 shown in FIGS. 6, 7, 8A, and 8B as an OS transistor. Note that, as the substrate 212 shown in FIG. 10, for example, a substrate applicable to the substrate 312 of the semiconductor device shown in FIG. 7 can be used.

[0271] Next, another configuration example of the OS transistor illustrated in FIGS. 6 and 7 will be described.

[0272] FIGS. 11A and 11B are modified examples of the transistor 500 shown in FIGS. 8A and 8B. FIG. 11A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction. Note that the configurations shown in FIGS. 11A and 11B can also be applied to other transistors included in a semiconductor device of an aspect of the present invention, such as the transistor 300.

[0273] The transistor 500 having the configuration shown in FIGS. 11A and 11B is different from the transistor 500 having the configuration shown in FIGS. 8A and 8B in that it has the insulators 402 and 404. Further, the transistor 500 having the configuration shown in FIGS. 11A and 11B is different from the transistor 500 having the configuration shown in FIGS. 8A and 8B in that the insulator 552 is provided in contact with the side surfaces of the conductors 540a and 540b. Furthermore, the transistor 500 having the configuration shown in FIGS. 11A and 11B is different from the transistor 500 having the configuration shown in FIGS. 8A and 8B in that it does not have the insulator 520.

[0274] In the transistor 500 having the configuration shown in FIGS. 11A and 11B, the insulator 402 is provided on the insulator 512. Also, the insulator 404 is provided on the insulator 574 and on the insulator 402.

[0275] In the transistor 500 configured as shown in FIGS. 11A and 11B, insulators 514, 516, 522, 524, 544, 580, and 574 are provided, and an insulator 404 has a structure covering these. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the upper surface of the insulator 402, respectively. Thereby, the oxide 530 etc. are isolated from the outside by the insulator 404 and the insulator 402.

[0276] The insulators 402 and 404 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. For example, as the insulators 402 and 404, it is preferable to use silicon nitride or silicon oxynitride, which are materials with high hydrogen barrier properties. Thereby, since the diffusion of hydrogen etc. into the oxide 530 can be suppressed, the deterioration of the characteristics of the transistor 500 can be suppressed. Therefore, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0277] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 552, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which are materials with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, the diffusion of impurities such as water or hydrogen from the insulator 580 etc. through the conductors 540a and 540b into the oxide 530 can be suppressed. Also, the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b can be suppressed. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0278] In addition, the transistor 500 shown in FIGS. 11A and 11B may change the configuration of the transistor according to the situation. For example, the transistor 500 in FIGS. 11A and 11B can be changed to the transistor shown in FIGS. 12A and 12B as a modification example. FIG. 12A is a cross-sectional view of the transistor in the channel length direction, and FIG. 12B is a cross-sectional view of the transistor in the channel width direction. The transistors shown in FIGS. 12A and 12B are different from the transistors shown in FIGS. 11A and 11B in that the oxide 530c has a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0279] The oxide 530c1 is in contact with the upper surface of the insulator 524, the side surface of the oxide 530a, the upper surface and the side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 is in contact with the insulator 550.

[0280] As the oxide 530c1, for example, In-Zn oxide can be used. Also, as the oxide 530c2, the same material as the material that can be used for the oxide 530c when the oxide 530c has a single-layer structure can be used. For example, as the oxide 530c2, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, Ga:Zn = 2:1, or Ga:Zn = 2:5 can be used.

[0281] By forming the oxide 530c into a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased compared to the case where the oxide 530c has a single-layer structure. Therefore, the transistor can be applied, for example, as a power MOS transistor. Note that the oxide 530c of the transistor having the configuration shown in FIGS. 8A and 8B can also be formed into a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0282] The transistors configured as shown in FIGS. 12A and 12B can be applied, for example, to the transistor 300 shown in FIGS. 6 and 7. Further, for example, the transistor 300 can be applied to the semiconductor devices described in the above embodiments, such as the transistors included in the level shifters 100, 100A, 100B, and 100C described in the above embodiments. Note that the transistors shown in FIGS. 12A and 12B can also be applied to transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one aspect of the present invention.

[0283] Next, a capacitive element applicable to the semiconductor devices of FIGS. 6 and 7 will be described.

[0284] In FIG. 13, a capacitive element 600A is shown as an example of a capacitive element 600 applicable to the semiconductor devices shown in FIGS. 6 and 7. FIG. 13A is a top view of the capacitive element 600A, FIG. 13B is a perspective view showing a cross section taken along the dashed-dotted line L3-L4 of the capacitive element 600A, and FIG. 13C is a perspective view showing a cross section taken along the dashed-dotted line W3-L4 of the capacitive element 600A.

[0285] The conductor 610 functions as one of a pair of electrodes of the capacitive element 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitive element 600A. Further, the insulator 630 functions as a dielectric sandwiched between the pair of electrodes.

[0286] As the insulator 630, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like can be used, and it can be provided in a laminated or single-layer form.

[0287] Further, for example, the insulator 630 may use a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. With this configuration, the capacitor element 600A can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and can improve the dielectric strength by having an insulator with high dielectric strength, thereby suppressing the electrostatic breakdown of the capacitor element 600A.

[0288] Examples of the insulator of the high dielectric constant (high-k) material (material with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, a oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, a oxynitride having silicon and hafnium, or a nitride having silicon and hafnium.

[0289] Alternatively, the insulator 630 may use, for example, a single layer or a laminate of an insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). For example, when the insulator 630 is a laminate, a three-layer laminate formed in order of zirconium oxide, aluminum oxide, and zirconium oxide, or a four-layer laminate formed in order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide may be used. Further, as the insulator 630, a compound containing hafnium and zirconium may be used. As the semiconductor device becomes more miniaturized and highly integrated, problems such as leakage current of the transistor and / or the capacitor element may occur due to the thinning of the gate insulator and the dielectric used for the capacitor element. By using a high-k material for the gate insulator and the insulator that functions as the dielectric used for the capacitor element, it is possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitor element while maintaining the physical film thickness.

[0290] The capacitive element 600 is electrically connected to the conductor 546 and the conductor 548 below the conductor 610. The conductor 546 and the conductor 548 function as a plug for connecting to another circuit element or as a wiring. Also, in FIGS. 13A to 13C, the conductor 546 and the conductor 548 are collectively described as the conductor 540.

[0291] Also, in FIG. 13, for clarity of the figure, the insulator 586 in which the conductors 546 and 548 are embedded and the insulator 650 covering the conductor 620 and the insulator 630 are omitted.

[0292] Note that although the capacitive element 600 shown in FIGS. 6, 7, 13A, 13B, and 13C is a planar type, the shape of the capacitive element is not limited to this. For example, the capacitive element 600 may be a cylindrical capacitive element 600B shown in FIGS. 14A to 14C.

[0293] FIG. 14A is a top view of the capacitive element 600B, FIG. 14B is a cross-sectional view of the capacitive element 600B taken along the dashed-dotted line L3-L4, and FIG. 14C is a perspective view showing the cross-section of the capacitive element 600B taken along the dashed-dotted line W3-L4.

[0294] In FIG. 14B, the capacitive element 600B includes an insulator 631 on the insulator 586 in which the conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 functioning as one of a pair of electrodes, and a conductor 620 functioning as the other of the pair of electrodes.

[0295] Also, in FIG. 14C, for clarity of the figure, the insulator 586, the insulator 650, and the insulator 651 are omitted.

[0296] As the insulator 631, for example, the same material as the insulator 586 can be used.

[0297] In addition, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. As the conductor 611, for example, the same material as that of the conductor 330 and the conductor 518 can be used.

[0298] As the insulator 651, for example, the same material as that of the insulator 586 can be used.

[0299] In addition, as described above, the insulator 651 has an opening, and the opening overlaps the conductor 611.

[0300] The conductor 610 is formed on the bottom and the side surface of the opening. That is, the conductor 610 overlaps the conductor 611 and is electrically connected to the conductor 611.

[0301] As a method for forming the conductor 610, an opening is formed in the insulator 651 by an etching method or the like, and then the conductor 610 is formed by a sputtering method, an ALD method, or the like. Then, by a CMP (Chemical Mechanical Polishing) method or the like, the conductor 610 formed on the insulator 651 is removed leaving the conductor 610 formed in the opening.

[0302] The insulator 630 is located on the insulator 651 and on the formation surface of the conductor 610. Note that the insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor element.

[0303] The conductor 620 is formed on the insulator 630 so as to fill the opening of the insulator 651.

[0304] The insulator 650 is formed so as to cover the insulator 630 and the conductor 620.

[0305] The cylindrical capacitor element 600B shown in FIG. 14 can have a higher capacitance value than the planar capacitor element 600A.

[0306] In addition, in a semiconductor device according to an aspect of the present invention, a photoelectric conversion element may be provided above the capacitive element 600 of the semiconductor device shown in FIGS. 6 and 7. That is, as an aspect of the present invention, an imaging device including the level shifter described in the above embodiment may be used. The imaging device converts, for example, a current induced by a photoelectric conversion element into a digital signal by a current-voltage conversion circuit, an analog-digital conversion circuit, etc. By providing a level shifter in the imaging device, the digital signal can be level-shifted.

[0307] FIG. 15 shows a configuration example of an imaging device in which a photoelectric conversion element 700 is provided above the capacitive element 600 in the semiconductor device shown in FIG. 7. Note that the photoelectric conversion element 700 may be provided below the transistor 300 instead of above the capacitive element 600.

[0308] The photoelectric conversion element 700 has, as an example, a layer 767a, a layer 767b, a layer 767c, a layer 767d, and a layer 767e.

[0309] The photoelectric conversion element 700 shown in FIG. 15 is an example of an organic photoconductive film. The layer 767a is a lower electrode, the layer 767e is a light-transmissive upper electrode, and the layers 767b, 767c, and 767d correspond to a photoelectric conversion section. Note that, instead of the photoelectric conversion element 700 shown in FIG. 15, for example, a pn junction type photodiode, an avalanche photodiode, or the like may be used.

[0310] The layer 767a, which is the lower electrode, can be either an anode or a cathode, and the layer 767b, which is the upper electrode, can be the other of the anode or the cathode. In the present embodiment, the layer 767a is a cathode and the layer 767b is an anode.

[0311] The layer 767a is preferably, for example, a low-resistance metal layer or the like. Specifically, as the layer 767a, for example, aluminum, titanium, tungsten, tantalum, silver, or a laminate thereof can be used.

[0312] As the layer 767e, it is preferable to use, for example, a conductive layer having high translucency with respect to visible light. Specifically, as the layer 767e, for example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which the layer 767e is omitted can also be adopted.

[0313] Either one of the layers 767b and 767d of the photoelectric conversion unit can be a hole transport layer, and the other can be an electron transport layer. Also, the layer 767c can be a photoelectric conversion layer.

[0314] As the hole transport layer, for example, molybdenum oxide can be used. As the electron transport layer, for example, C 60 、C 70 fullerenes such as, or derivatives thereof can be used.

[0315] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0316] In the imaging device of FIG. 15, the insulator 751 is provided on the insulator 650, and the layer 767a is provided on the insulator 751. Also, the insulator 752 is provided on both the insulator 751 and the layer 767a. The layer 767b is provided on both the insulator 752 and the layer 767a.

[0317] Also, on the layer 767b, the layers 767c, 767d, 767e, and the insulator 753 are laminated and provided in this order.

[0318] The insulator 751 functions as an interlayer insulating film as an example. For the insulator 751, it is preferable to use an insulator having a barrier property against hydrogen, similar to the insulator 324 for example. By using an insulator having a barrier property against hydrogen for the insulator 751, the diffusion of hydrogen into the transistor 500 can be suppressed. Therefore, as the insulator 751, as an example, a material applicable to the insulator 324 can be used.

[0319] The insulator 752 functions as an element isolation layer as an example. Although not shown, the insulator 752 is provided to prevent a short circuit with another photoelectric conversion element located adjacent thereto. As the insulator 752, it is preferable to use an organic insulator or the like for example.

[0320] The insulator 753 functions as a planarization film having translucency as an example. As the insulator 753, materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride can be used for example.

[0321] Above the insulator 753, a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773 are provided as an example.

[0322] The light-shielding layer 771 provided on the insulator 753 can suppress the inflow of light into adjacent pixels. As the light-shielding layer 771, a metal layer such as aluminum or tungsten can be used. Further, a dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0323] A color filter can be used for the optical conversion layer 772 provided on the insulator 753 and on the light-shielding layer 771. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel of the color filter, a color image can be obtained.

[0324] Also, if a wavelength cut filter is used for the optical conversion layer 772, an imaging device capable of obtaining images in various wavelength regions can be achieved.

[0325] For example, if a filter that blocks light with a wavelength equal to or less than that of visible light is used for the optical conversion layer 772, an infrared imaging device can be obtained. Also, if a filter that blocks light with a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 772, a far-infrared imaging device can be obtained. Further, if a filter that blocks light with a wavelength equal to or greater than that of visible light is used for the optical conversion layer 772, an ultraviolet imaging device can be obtained.

[0326] Also, if a scintillator is used for the optical conversion layer 772, an imaging device can be obtained that visualizes the intensity of radiation used in an X-ray imaging device or the like to obtain an image. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light and ultraviolet light by the photoluminescence phenomenon. Then, image data is acquired by detecting the light with the photoelectric conversion element 700. Further, an imaging device having such a configuration may be used for a radiation detector or the like.

[0327] A scintillator includes a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible light or ultraviolet light when irradiated. For example, those obtained by dispersing Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. in resin, ceramics, etc. can be used.

[0328] A microlens array 773 is provided on the light-shielding layer 771 and on the optical conversion layer 772. Light passing through the individual lenses of the microlens array 773 passes through the optical conversion layer 772 directly below and is irradiated onto the photoelectric conversion element 700. By providing the microlens array 773, the condensed light can be incident on the photoelectric conversion element 700, so that photoelectric conversion can be performed efficiently. The microlens array 773 is preferably formed of a resin or glass having high translucency to visible light.

[0329] Incidentally, FIG. 15 shows the configuration of an imaging device provided with a photoelectric conversion element 700 using an organic photoconductive film above transistors 300 and 500. However, the imaging device according to one aspect of the present invention is not limited thereto. For example, the imaging device according to one aspect of the present invention may be configured to provide a back-illuminated pn junction type photoelectric conversion element instead of the photoelectric conversion element 700.

[0330] FIG. 16 shows a configuration example of an imaging device provided with a back-illuminated pn junction type photoelectric conversion element 700A above transistors 300 and 500. The imaging device shown in FIG. 16 has a structure in which a structure SC having a photoelectric conversion element 700A is bonded above a substrate 312 provided with transistors 300, transistors 500, and a capacitive element 600.

[0331] Note that the structure SC includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773. For the description of these, refer to the above description.

[0332] The photoelectric conversion element 700A is a pn junction type photodiode formed on a silicon substrate, and has a layer 765b corresponding to a p-type region and a layer 765a corresponding to an n-type region. The photoelectric conversion element 700A is an embedded type photodiode, and a thin p-type region (a part of the layer 765b) provided on the surface side (current extraction side) of the layer 765a can suppress dark current and reduce noise.

[0333] The insulator 701, the conductor 741, and the conductor 742 have functions as bonding layers. The insulator 754 has functions as an interlayer insulating film and a planarization film. The insulator 755 has a function as an element isolation layer. The insulator 756 has a function of suppressing the outflow of carriers.

[0334] The silicon substrate is provided with grooves for separating pixels, and the insulator 756 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulator 756, it is possible to suppress carriers generated in the photoelectric conversion element 700A from flowing out to adjacent pixels. In addition, the insulator 756 also has a function of suppressing the intrusion of stray light. Therefore, the insulator 756 can suppress color mixing. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulator 756.

[0335] The element isolation layer can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method or the like. As the insulator 756, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used. Note that the insulator 756 may have a multilayer structure.

[0336] The layer 765a (n-type region, corresponding to the cathode) of the photoelectric conversion element 700A is electrically connected to the conductor 741. The layer 765b (p-type region, corresponding to the anode) is electrically connected to the conductor 742. The conductors 741 and 742 have regions embedded in the insulator 701. In addition, the surfaces of the insulator 701, the conductor 741, and the conductor 742 are flattened so that their heights are the same.

[0337] Above the insulator 650, the insulator 691 and the insulator 692 are laminated in order. Also, for example, in FIG. 16, the insulator 692 is provided with an opening, and the conductor 743 is formed so as to fill the opening.

[0338] As the insulator 691, for example, a material applicable to the insulator 751 can be used.

[0339] Also, as the insulator 692, for example, a material applicable to the insulator 650 can be used.

[0340] Each of the insulator 693 and the insulator 701 functions as part of the bonding layer. Also, each of the conductor 741, the conductor 742, and the conductor 743 functions as part of the bonding layer.

[0341] As the insulator 693 and the insulator 701, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used. In particular, in order to bond the insulator 693 and the insulator 701, it is preferable that the insulator 693 and the insulator 701 are composed of the same components.

[0342] As the conductor 741, the conductor 742, and the conductor 743, for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold, etc. can be used. In particular, in order to facilitate bonding between the conductor 741 and the conductor 743, and between the conductor 742 and the conductor 743, it is preferable to use copper, aluminum, tungsten, or gold.

[0343] Note that the conductor 741, the conductor 742, and the conductor 743 may have a multilayer structure including a plurality of layers. For example, a first conductor may be formed on the side surface of the opening where the conductor 741, the conductor 742, or the conductor 743 is provided, and then a second conductor may be formed to fill the opening. As the first conductor, for example, a conductor having a barrier property against hydrogen such as tantalum nitride can be used, and as the second conductor, for example, highly conductive tungsten can be used.

[0344] In the pre-process of bonding the bonding layer on the substrate 312 side and the bonding layer on the structure SC side, on the substrate 312 side, the surfaces of the insulator 693 and the conductor 743 are planarized so that their heights are the same. Similarly, on the structure SC side, the surfaces of the insulator 701, the conductor 741, and the conductor 742 are planarized so that their heights are the same.

[0345] In the bonding process, when bonding the insulator 693 and the insulator 701, that is, bonding the insulating layers, after providing high flatness by polishing or the like, the surfaces that have been hydrophilized with oxygen plasma or the like are brought into contact and temporarily bonded, and a hydrophilic bonding method or the like in which permanent bonding is performed by dehydration through heat treatment can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, a mechanically excellent bond can be obtained.

[0346] Also, for example, when bonding the conductor 741 and the conductor 743, and bonding the conductor 742 and the conductor 743, that is, bonding the conductors, a surface activation bonding method can be used in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact and bonded. Or, a diffusion bonding method or the like in which the surfaces are bonded by using both temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, an excellent bond can be obtained not only electrically but also mechanically.

[0347] By performing the bonding process described above, the conductor 743 on the substrate 312 side can be electrically connected to the conductors 741 and 742 on the structure SC side. Also, a connection having mechanical strength can be obtained between the insulator 693 on the substrate 312 side and the insulator 701 on the structure SC side.

[0348] When bonding the substrate 312 and the structure SC, since the insulating layer and the metal layer are mixed on each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method can be combined and performed.

[0349] For example, a method can be used in which the surface is cleaned after polishing, an antioxidant treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed for bonding. Also, the surface of the metal layer can be made of a metal with poor oxidation resistance such as gold, and a hydrophilic treatment can be performed. Note that bonding methods other than the methods described above may also be used.

[0350] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0351] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0352] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0353] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 17A. FIG. 17A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0354] As shown in FIG. 17A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) are included in "Crystalline" (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, single crystal and poly crystal are included in "Crystal".

[0355] Note that the structure within the thick frame shown in FIG. 17A is an intermediate state between “Amorphous” and “Crystal” and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable “Amorphous” and completely different from “Crystal”.

[0356] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as “Crystalline” is shown in FIG. 17B (the horizontal axis is 2θ [deg.], and the vertical axis represents the intensity (Intensity) in arbitrary units (a.u.)). Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 17B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 17B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 17B is 500 nm.

[0357] As shown in FIG. 17B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. Note that, as shown in FIG. 17B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity (Intensity) is detected.

[0358] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 17C. FIG. 17C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 17C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0359] As shown in FIG. 17C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0360] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from FIG. 17A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0361] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0362] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. Here, the specific direction means the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When considering the atomic arrangement as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor having c-axis orientation and no obvious orientation in the a-b plane direction.

[0363] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0364] Also, in an In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Thus, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0365] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0366] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0367] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0368] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carrier capture. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0369] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities and / or the generation of defects, it can also be said that CAAC-OS is an oxide semiconductor with few impurities and / or defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0370] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Further, nc-OS does not show regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and an amorphous oxide semiconductor. For example, when performing a structural analysis on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the out-of-plane XRD measurement using θ / 2θ scan. Further, when performing electron beam diffraction (also referred to as restricted-view electron beam diffraction) using an electron beam having a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0371] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Further, a-like OS has a higher hydrogen concentration in the film than nc-OS and CAAC-OS.

[0372] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that CAC-OS relates to the material constitution.

[0373] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0374] Furthermore, CAC-OS becomes a mosaic state by separating the material into a first region and a second region, and the first region is a configuration distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0375] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0376] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, or the like. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, or the like. That is, the first region can be rephrased as a region mainly composed of In. The second region can be rephrased as a region mainly composed of Ga.

[0377] Note that there may be cases where a clear boundary cannot be observed between the first region and the second region.

[0378] For example, in CAC-OS of In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0379] When CAC-OS is used in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, thereby enabling the function of switching (turning on / off) to be imparted to CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be realized.

[0380] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0381] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0382] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0383] For the transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, even more preferably 1×10 10 cm -3 or less, and 1×10 -9 cm -3 or more. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0384] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0385] In addition, the charge trapped in the trap level of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0386] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[0387] <Impurity> Here, the effects of various impurities in the oxide semiconductor will be described.

[0388] In an oxide semiconductor, when silicon, carbon, or the like, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon, carbon, or the like in the oxide semiconductor and the concentration of silicon, carbon, or the like near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Hereinafter, preferably 2×10 17 atoms / cm 3 or less.

[0389] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0390] In addition, when nitrogen is contained in the oxide semiconductor, carriers, i.e., electrons, are generated, the carrier concentration increases, and the semiconductor tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm3 Hereinafter, more preferably 5×10 17 atoms / cm 3 or less.

[0391] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, carriers such as electrons may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate carriers such as electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 or less, preferably 1×10 19 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or less, and even more preferably 1×10 18 atoms / cm 3 or less.

[0392] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0393] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0394] (Embodiment 4) This embodiment shows an example of a semiconductor wafer on which a semiconductor device or the like described in the above embodiment is formed, and an example of an electronic component in which the semiconductor device is incorporated.

[0395] <Semiconductor Wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 18A.

[0396] The semiconductor wafer 4800 shown in Fig. 18A has a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion without the circuit portion 4802 is a spacing 4803, which is a dicing area.

[0397] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the opposite side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warping of the wafer 4801 and the like can be reduced, and miniaturization as a component can be achieved.

[0398] As the next process, a dicing process is performed. Dicing is performed along the scribe lines SCL1 and SCL2 (which may be referred to as dicing lines or cutting lines) indicated by the dashed line. Note that, in order to facilitate the dicing process, the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular.

[0399] By performing the dicing process, a chip 4800a as shown in Fig. 18B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately equal to the kerf of the scribe line SCL1 or the kerf of the scribe line SCL2.

[0400] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 18A. For example, a semiconductor wafer having a rectangular shape may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0401] <Electronic component> FIG. 18C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 18C has a chip 4800a in a mold 4711. As shown in FIG. 18C, the chip 4800a may have a configuration in which circuit portions 4802 are stacked. FIG. 18C omits a part to show the inside of the electronic component 4700. The electronic component 4700 has a land 4712 outside the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0402] FIG. 18D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 4730, an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

[0403] The electronic component 4730 includes a semiconductor device 4710. As the semiconductor device 4710, for example, the semiconductor device described in the above embodiment, a wide-band memory (HBM: High Bandwidth Memory), or the like can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device can be used.

[0404] The package substrate 4732 can be made of a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 4731 can be a silicon interposer, a resin interposer, or the like.

[0405] The interposer 4731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits with different terminal pitches. The plurality of wirings can be provided in a single layer or multiple layers. The interposer 4731 also has a function to electrically connect an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be referred to as a "rewiring substrate" or an "intermediate substrate". In some cases, a through electrode is provided on the interposer 4731 and used to electrically connect the integrated circuit and the package substrate 4732. In the case of a silicon interposer, a TSV (Through Silicon Via) can also be used as the through electrode.

[0406] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult for a resin interposer.

[0407] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. Therefore, the interposer for mounting HBM requires the formation of fine and high-density wirings. Thus, it is preferable to use a silicon interposer as the interposer for mounting HBM.

[0408] In addition, in SiP, MCM, etc. that use a silicon interposer, a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer is less likely to occur. Also, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0409] Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to make the heights of the semiconductor device 4710 and the semiconductor device 4735 uniform.

[0410] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 18D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix pattern at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0411] The electronic component 4730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0412] Next, an electronic component having an image sensor chip (imaging device) including a photoelectric conversion element will be described.

[0413] FIG. 19A is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 4510 for fixing an image sensor chip 4550 (see FIG. 19C), a cover glass 4520, an adhesive 4530 for bonding the two, and the like.

[0414] FIG. 19B is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball Grid Array) with solder balls as bumps 4540. Note that, not limited to BGA, it may have an LGA (Land Grid Array), a PGA (Pin Grid Array), or the like.

[0415] FIG. 19C is a perspective view of the package shown with a part of the cover glass 4520 and the adhesive 4530 omitted. An electrode pad 4560 is formed on the package substrate 4510, and the electrode pad 4560 and the bump 4540 are electrically connected via a through hole. The electrode pad 4560 is electrically connected to the image sensor chip 4550 by a wire 4570.

[0416] Further, FIG. 19D is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 4511 for fixing an image sensor chip 4551 (FIG. 19F), a lens cover 4521, a lens 4535, and the like. Also, an IC chip 4590 (FIG. 19F) having functions such as a drive circuit and a signal conversion circuit of the imaging device is provided between the package substrate 4511 and the image sensor chip 4551, and has a configuration as a SiP (System in Package).

[0417] FIG. 19E is a perspective view of the lower surface side of the camera module. The lower surface and side surfaces of the package substrate 4511 have a QFN (Quad Flat No-lead package) configuration with mounting lands 4541. Note that this configuration is an example, and a QFP (Quad Flat Package), the aforementioned BGA, etc. may be provided.

[0418] FIG. 19F is a perspective view of the module shown with a part of the lens cover 4521 and the lens 4535 omitted. The land 4541 is electrically connected to the electrode pad 4561, and the electrode pad 4561 is electrically connected to the image sensor chip 4551 or the IC chip 4590 by a wire 4571.

[0419] By housing the image sensor chip in a package of the form described above, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0420] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0421] (Embodiment 5) In this embodiment, an example of an electronic device having the semiconductor device described in the above embodiment will be described. Note that FIG. 20 illustrates a state in which an electronic component 4700 having the semiconductor device is included in each electronic device.

[0422] [Mobile phone] The information terminal 5500 shown in FIG. 20 is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided in the display unit 5511, and buttons are provided in the housing 5510.

[0423] Also, although not shown in FIG. 20, the information terminal 5500 has semiconductor devices such as a storage device and an imaging device. Here, by applying the semiconductor devices described in the above embodiment to the information terminal 5500, the power consumption of the storage device, the imaging device, the display unit 5511, etc. can be reduced. Further, due to the low power consumption, the heat generation from the circuit can be reduced, so that the influence of the heat generation on the circuit itself, the peripheral circuits, and the modules can be minimized.

[0424] [Wearable Terminal] Also, in FIG. 20, a wristwatch-type information terminal 5900 is shown as an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, etc.

[0425] Similar to the information terminal 5500 described above, the wearable terminal can reduce the power consumption of semiconductor devices such as the storage device, the imaging device, and the display unit 5902 included in the wearable terminal by applying the semiconductor devices described in the above embodiment.

[0426] [Information Terminal] Also, in FIG. 20, a desktop-type information terminal 5300 is shown. The desktop-type information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0427] Similar to the information terminal 5500 described above, the desktop-type information terminal 5300 can reduce the power consumption of the semiconductor devices provided in the desktop-type information terminal 5300 by applying the semiconductor devices described in the above embodiment.

[0428] In the above description, smartphones, desktop information terminals, and wearable terminals are taken as examples of electronic devices and are illustrated in FIG. 20 respectively. However, information terminals other than smartphones, desktop information terminals, and wearable terminals can also be applied. Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0429] [Household Appliance] Also, in FIG. 20, an electric refrigerator-freezer 5800 is illustrated as an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0430] By applying the semiconductor device described in the above embodiment to the electric refrigerator-freezer 5800, the power consumption of the electric refrigerator-freezer 5800 can be reduced.

[0431] In this example, an electric refrigerator-freezer is described as a household appliance. Other household appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH (Induction Heating) cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, audio-visual equipment, and the like.

[0432] [Game Machine] Also, in FIG. 20, a portable game machine 5200, which is an example of a game machine, is illustrated. The portable game machine 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0433] Furthermore, FIG. 20 shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 has a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 20, the controller 7522 can be provided with a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like. Also, the controller 7522 is not limited to the shape shown in FIG. 20, and the shape of the controller 7522 may be changed variously according to the genre of the game. For example, in a shooting game such as FPS (First Person Shooter), a controller in the shape of a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller in the shape of a musical instrument or a music device can be used. Furthermore, the stationary game machine may be configured to be operated by a gesture and / or voice of a game player, instead of using a controller, and may be provided with a camera, a depth sensor, a microphone, and the like.

[0434] In addition, the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.

[0435] By applying the semiconductor device described in the above embodiment to the portable game machine 5200, a portable game machine 5200 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence of the heat on the circuit itself, the peripheral circuit, and the module can be minimized.

[0436] In FIG. 20, a portable game machine is illustrated as an example of a game machine, but the electronic device according to one aspect of the present invention is not limited thereto. Examples of the electronic device according to one aspect of the present invention include, for example, a home stationary game machine, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0437] [Mobile body] The semiconductor device described in the above embodiment can be applied to an automobile, which is a mobile body, and the periphery of the driver's seat of the automobile.

[0438] FIG. 20 shows an automobile 5700, which is an example of a mobile body.

[0439] Around the driver's seat of the automobile 5700, there is an instrument panel capable of displaying a speedometer, a tachometer, the driving distance, a fuel gauge, the gear state, the setting of the air conditioner, etc. Further, a display device for showing such information may be provided around the driver's seat.

[0440] In particular, the display device can supplement the field of view blocked by a pillar or the like and the blind spot of the driver's seat by projecting the video from an imaging device (not shown) provided in the automobile 5700, thereby enhancing safety. That is, by displaying the image from the imaging device provided outside the automobile 5700, the blind spot can be supplemented and safety can be enhanced.

[0441] The semiconductor device described in the above embodiment can be applied to the above-described instrument panel, imaging device, etc. Therefore, the power consumption of the instrument panel, imaging device, etc. provided in the automobile 5700 can be reduced. Further, due to the low power consumption, the heat generation from the circuit can be reduced, so that the influence on the circuit itself, the peripheral circuit, and the module due to the heat generation can be minimized.

[0442] In the above description, an automobile has been described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc. The semiconductor device according to one aspect of the present invention can be applied to these moving bodies to reduce power consumption.

[0443] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0444] FIG. 20 shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0445] By applying the semiconductor device described in the above embodiment to the imaging device included in the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, the peripheral circuit, and the module due to heat generation can be minimized.

[0446] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0447] FIG. 20 shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0448] The video camera 6300 has an imaging device similar to the digital camera 6240. Therefore, by applying the semiconductor device described in the above embodiment to the imaging device included in the video camera 6300, a video camera 6300 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence of the heat generation on the circuit itself, the peripheral circuits, and the modules can be minimized.

[0449] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

Description of Reference Numerals

[0450] AM: Memory unit, Tr1: Transistor, Tr2: Transistor, Tr3: Transistor, Tr4: Transistor, Tc1: Transistor, TcL: Transistor, C1: Capacitance, CL: Capacitance, FN: Node, INE: Wiring, BOTE: Wiring, VDHE: Wiring, VLSE: Wiring, PRCE: Wiring, EVE: Wiring, CLPE: Wiring, VAL: Wiring, SA: Layer, SB: Layer, SC: Structure, 100: Level shifter, 100A: Level shifter, 100B: Level shifter, 100C: Level shifter, 200: Transistor, 211: Substrate, 212: Substrate, 220: Insulator, 222: Insulator, 224: Insulator, 226: Insulator, 228: Conductor, 229: Conductor, 230: Insulator, 231: Insulator, 232: Insulator, 233: Conductor, 300: Transistor, 311: Substrate, 312: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 341: Insulator, 342: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 402: Insulator, 404: Insulator, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530c: Oxide, 530c1: Oxide, 530c2: Oxide, 540: Conductor, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 546: Conductor, 548: Conductor, 550: Insulator, 552: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacitor element, 600A: Capacitor element, 600B: Capacitor element, 610: Conductor, 611: Conductor, 612: Conductor, 620: Conductor,630: Insulator, 631: Insulator, 650: Insulator, 651: Insulator, 691: Insulator, 692: Insulator, 693: Insulator, 701: Insulator, 741: Conductor, 742: Conductor, 743: Conductor, 751: Insulator, 752: Insulator, 753: Insulator, 754: Insulator, 755: Insulator, 756: Insulator, 765a: Layer, 765b: Layer, 767a: Layer, 767b: Layer, 767c: Layer, 767d: Layer, 767e: Layer, 771: Light-shielding layer, 772: Optical conversion layer, 4510: Package substrate, 4511: Package substrate, 4520: Cover glass, 4521: Lens cover, 4530: Adhesive, 4535: Lens, 4540: Bump, 4541: Land, 4550: Image sensor chip, 4551: Image sensor chip, 4560: Electrode pad, 4561: Electrode pad, 4570: Wire, 4571: Wire, 4590: IC chip, 4700: Electronic component, 4702: Printed circuit board, 4704: Mounting substrate, 4710: Semiconductor device, 4711: Mold, 4712: Land, 4713: Electrode pad, 4714: Wire, 4730: Electronic component, 4731: Interposer, 4732: Package substrate, 4733: Electrode, 4735: Semiconductor device, 4800: Semiconductor wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit section, 4803: Spacing, 4803a: Spacing, 5200: Portable game machine, 5201: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main body, 5302: Display, 5303: Keyboard, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation button, 5904: Operator, 5905: Band, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation button, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Housing, 6302: Housing, 6303: Display unit, 6304: Operation key, 6305: Lens, 6306: Connection part, 7500: Console game machine, 7520: Main body, 7522: Controller,

Claims

1. A semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, an input terminal, and an output terminal, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a transistor of the same polarity, a first terminal of the first transistor is electrically connected to a first terminal of the second transistor and the output terminal, a second terminal of the second transistor is electrically connected to a first terminal of the third transistor, a first terminal of the fourth transistor is electrically connected to a gate of the second transistor and a first terminal of the first capacitor, a second terminal of the first capacitor is electrically connected to the input terminal, a first terminal of the second capacitor is electrically connected to the first terminal of the first transistor, the first terminal of the second transistor, and the output terminal. Semiconductor device.

2. The semiconductor device according to claim 1, wherein when a first potential is input to the input terminal, a second potential is input to a second terminal of the first transistor, and a third potential is input to a second terminal of the third transistor and a second terminal of the fourth transistor, the first transistor has a function of pre-charging the output terminal to the second potential when the first transistor is in an on state, the second transistor has a function of being turned on or off according to the first potential input to the input terminal when the fourth transistor is in an off state, after the output terminal is pre-charged to the second potential and the first transistor is turned off, the third transistor is turned on to set the potential of the output terminal to the second potential or the third potential. Semiconductor device.

3. It has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, an input terminal, and an output terminal. Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a transistor of the same polarity. A first terminal of the first transistor is electrically connected to a first terminal of the third transistor and the output terminal. A second terminal of the third transistor is electrically connected to a first terminal of the second transistor. A first terminal of the fourth transistor is electrically connected to a gate of the second transistor and a first terminal of the first capacitor. A second terminal of the first capacitor is electrically connected to the input terminal. A first terminal of the second capacitor is electrically connected to a first terminal of the first transistor, a first terminal of the third transistor, and the output terminal. A semiconductor device.

4. In claim 3, When a first potential is input to the input terminal, a second potential is input to a second terminal of the first transistor, and a third potential is input to a second terminal of the second transistor and a second terminal of the fourth transistor, The first transistor has a function of precharging the output terminal to the second potential when the first transistor is in an on state. The second transistor has a function of being turned on or off according to the first potential input to the input terminal when the fourth transistor is in an off state. After the output terminal is precharged to the second potential and the first transistor is turned off, by turning on the third transistor, it has a function of setting the potential of the output terminal to the second potential or the third potential. A semiconductor device.

5. In any one of claims 1 to 4, Each of the first to fourth transistors has a metal oxide or silicon in a channel formation region. Semiconductor device.

6. In any one of Claims 1 to 5, The first capacitor has a fifth transistor. The fifth transistor has a metal oxide or silicon in a channel formation region. A gate of the fifth transistor functions as one of a first terminal and a second terminal of the first capacitor. A first terminal and a second terminal of the fifth transistor function as the other of the first terminal and the second terminal of the first capacitor. Semiconductor device.

7. A semiconductor device according to any one of Claims 1 to 6 and a photoelectric conversion element. The photoelectric conversion element is located above the first to fourth transistors. Imaging device.

Images