Compound Cathode Contact for Monolithically Integrated Micro-LEDs, Mini-LEDs, and LED Arrays

Abstract

The LED device includes a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having a top surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface. A transparent conductive layer is on the at least one sidewall and in the trench. A cathode layer is in the trench on the transparent conductive layer. A p-type contact is at the top surface of the mesa. In some embodiments, a spacer layer is formed between the transparent conductive layer and the cathode layer. In other embodiments, a distributed Bragg reflector is formed between the transparent conductive layer and the cathode layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to arrays of light-emitting diode (LED) devices and methods of manufacturing the same. More specifically, the present embodiments relate to arrays of LED devices having composite cathode contacts.

Background Art

[0002] A light-emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. In an LED, a P-type semiconductor and an N-type semiconductor are combined. Generally, III-V compound semiconductors are used for LEDs. III-V compound semiconductors provide more stable operation at high temperatures compared to devices using other semiconductors. III-V compounds are typically formed on a substrate made of sapphire, silicon (Si), or silicon carbide (SiC).

Summary of the Invention

Problems to be Solved by the Invention

[0003] Inorganic light-emitting diodes (i-LEDs) are widely used in constructing different types of displays, LED matrices, and light engines, including automotive adaptive headlights, augmented reality, virtual reality, mixed reality (AR / VR / MR) headsets, smart glasses, and displays for mobile phones, smart watches, monitors, and televisions. Individual LED pixels in these architectures can have areas ranging from several square millimeters to several square micrometers, depending on the size of the matrix or display and the pixel requirements per inch. One common approach is to form a monolithic array of LED pixels on an EPI wafer and then transfer and hybridize these LED arrays to a backplane to control individual pixels.

[0004] Monolithic arrays require metal side contacts, which function as the electrical cathode for each pixel and provide reflective sidewalls between the pixels, reducing lateral light scattering and propagation. In these architectures, the substrate (e.g., sapphire, silicon) is removed after the LED array is integrated with the backplane controller, and light extraction and beam profiling need to be enhanced. The standard method for removing the sapphire substrate is by a laser lift-off process, in which a laser beam (UV laser in the case of a sapphire substrate) is used to separate the substrate from the epitaxial layer (in this case, the LED array grown on the substrate). Since the cathodes are etched down to the surface of the substrate, they interact with the laser beam from the laser lift-off process, generating metal-rich droplets or other metal-containing by-products, which are generally absorptive and reduce the light output. Also, damage to the sidewall contacts can affect the electrical characteristics of the pixels, resulting in unstable V f or the occurrence of electrical leakage. Such effects can also raise concerns about long-term reliability.

[0005] Therefore, there is a need for a monolithic LED array and manufacturing process in which the interaction between the laser and the metal layer is eliminated during laser lift-off of the substrate.

Means for Solving the Problem

[0006] Embodiments of the present disclosure relate to a light-emitting diode (LED) device and a method of manufacturing the LED device. In one embodiment, the light-emitting diode (LED) device includes a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, the mesa, a transparent conductive layer on at least one sidewall and within the trench, a cathode layer within the trench on the transparent conductive layer, and a p-type contact on the upper surface of the mesa.

[0007] Another embodiment of the present disclosure relates to a method of manufacturing an LED device. In one embodiment, a method of manufacturing a light emitting diode (LED) device comprises: depositing a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate; etching a portion of the semiconductor layer to form at least one trench and at least one mesa defining a pixel, the at least one mesa having the semiconductor layer, an upper surface, and at least one sidewall; depositing a transparent conductive layer on at least one sidewall, the upper surface of at least one mesa, and in the trench; depositing a cathode layer in the trench and on the transparent conductive layer; forming a p-type contact on at least one of the upper surfaces; and having.

[0008] Another embodiment relates to a light emitting diode (LED) device, which comprises: a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface; a dielectric layer on at least one sidewall and on an upper portion of the upper surface of the at least one mesa; a zinc oxide layer on the dielectric, on at least one sidewall of the mesa, and in the trench; a cathode layer on the zinc oxide layer; a p-contact on the upper surface of the mesa; and having.

[0009] In another embodiment, a light emitting diode (LED) device comprises: a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface; a transparent conductive layer on at least one of the sidewalls and in the trench; a spacer layer on the transparent conductive layer; a cathode layer on the dielectric spacer layer; a p-type contact on the upper surface of the mesa; and has.

[0010] Another embodiment of the present disclosure relates to a method of manufacturing an LED device. In one embodiment, a method of manufacturing a light emitting diode (LED) device includes: depositing a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate; etching a portion of the semiconductor layer to form at least one trench and at least one mesa defining a pixel, the at least one mesa including the semiconductor layer, an upper surface, and at least one sidewall; depositing a transparent conductive layer on the at least one sidewall, the upper surface of the at least one mesa, and in the trench; depositing a spacer layer on the transparent conductive layer; depositing a cathode layer on the transparent conductive layer; forming a p-type contact on the upper surface of the at least one mesa; and has.

[0011] Another embodiment relates to a light emitting diode (LED) device, the LED device including: a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface; a dielectric layer on at least the one sidewall of the mesa and on an upper portion of the upper surface of the mesa; a zinc oxide layer on the dielectric layer, on at least the one sidewall of the mesa, and in the trench; a spacer layer on the zinc oxide layer; a cathode layer on the spacer layer; the p-contact of the upper surface of the mesa, and has.

[0012] In another embodiment, a light-emitting diode (LED) device includes a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, a transparent conductive layer on the at least one sidewall and within the trench, a distributed Bragg reflector (DBR) on the transparent conductive layer, a cathode layer on the dielectric spacer layer, a p-type contact on the upper surface of the mesa, and has.

[0013] Another embodiment of the present disclosure relates to a method of manufacturing an LED device. In one embodiment, a method of manufacturing a light-emitting diode (LED) device includes depositing a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate, etching a portion of the semiconductor layer to form at least one trench and at least one mesa defining a pixel, the at least one mesa having the semiconductor layer, an upper surface, and at least one sidewall, depositing a transparent conductive layer on the at least one sidewall, the upper surface of the at least one mesa, and within the trench, depositing a distributed Bragg reflector (DBR) on the transparent conductive layer, depositing a cathode layer on the transparent conductive layer, forming a p-type contact on the upper surface of the at least one mesa, and has.

[0014] Another embodiment relates to a light-emitting diode (LED) device. The LED device includes A mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, the mesa; A dielectric layer on an upper portion of the at least one sidewall of the mesa and a portion of the upper surface of the mesa; The dielectric layer, the at least one sidewall of the mesa, and a zinc oxide layer in the trench; A distributed Bragg reflector (DBR) on the zinc oxide layer; A cathode layer on the spacer layer; A p-contact on the upper surface of the mesa; having.

[0015] By referring to the embodiments, a more specific description of the present disclosure, briefly summarized above, can be obtained so that the foregoing features of the present disclosure can be understood in detail, and a part of which is shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure, and thus the present disclosure is not intended to limit the scope of the present disclosure and allows other equally effective embodiments. The embodiments described in the present application are shown by way of example and not by way of limitation in the figures of the accompanying drawings, and like reference numerals represent like elements.

Brief Description of the Drawings

[0016]

Figure 1A

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Figure 7

[0017] Before describing some exemplary embodiments of the present disclosure, it is understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. In the present disclosure, other embodiments are possible and can be implemented or realized in various ways.

[0018] As used in this application in one or more embodiments, the term "substrate" refers to a structure, intermediate, or end product having a surface or a portion of a surface on which a process acts. Also, in some embodiments, a reference to a substrate refers to only a portion of the substrate, unless the context clearly indicates otherwise. Further, in some embodiments, a reference to depositing a film on a substrate includes depositing a film on a bare substrate or on a substrate on which one or more layers, films, features, or materials have been previously deposited or formed.

[0019] In one or more embodiments, "substrate" means any substrate on which a film process is performed during a manufacturing process, or the surface of a material formed on a substrate. In an exemplary embodiment, the substrate surface on which the process is performed can be made of materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable materials such as metals, metal nitrides, group-III nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials. The substrate includes, but is not limited to, having a light-emitting diode (LED) device. In some embodiments, the substrate is exposed to a pretreatment process and the substrate surface is polished, etched, reduced, oxidized, hydroxylated, annealed, UV cured, electron beam cured, and / or fired. In addition to direct film processing on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps are performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such underlying layers when the context indicates so. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0020] In this disclosure, the terms "wafer" and "substrate" are used interchangeably. Thus, as used in this application, a wafer functions as the substrate on which the LED device described in this application is formed.

[0021] In the embodiments described in the present application, an LED device and a method of forming the LED device are described. In particular, the present disclosure describes an improved, more uniform, and reproducible manufacturing process for monolithic LED arrays that require laser lift-off for substrate removal by eliminating the interaction of the laser with the metal layer. In the LED devices of one or more embodiments, the light output is significantly improved, the electrical characteristics are improved, and the reliability is improved. In one or more embodiments, an improved uniformity / coverage of the sidewall cathode contact, as well as better optical and electrical characteristics, are described.

[0022] In one or more embodiments, an optically transparent conductive layer having a bandgap close to the bandgap of the epitaxial layer is incorporated at the bottom of the epitaxial structure. In some embodiments, the optically transparent layer may function as a protective layer for the metal contact layer and prevent the interaction of the laser with the metal layer. In one or more embodiments, the optically transparent layer includes zinc oxide (ZnO). Zinc oxide has a high light transmittance at visible wavelengths and a bandgap of 3.37 eV, which is close to the bandgap of gallium nitride (GaN, 3.4 eV). By having a bandgap close to GaN, ZnO can absorb the laser beam in the same manner as GaN and thus be separated from the sapphire substrate during the laser lift-off step, protecting the metal layer from the laser beam. In one or more embodiments, the thickness of the transparent layer may range from several tens of nanometers to several hundreds of nanometers, which is a sufficient thickness to ensure that the laser beam is completely absorbed by the bottom section of this layer and does not reach the metal layer.

[0023] Embodiments of the present disclosure are illustrated by the figures. The figures show devices (e.g., LEDs) and processes for forming the devices according to one or more embodiments of the present disclosure. The processes shown are merely exemplary uses contemplated for the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the uses shown.

[0024] One or more embodiments of the present disclosure are described with reference to the drawings. FIGS. 1A through 1I show cross-sectional views of an apparatus 100 according to one or more embodiments. One aspect of the present disclosure relates to a method of manufacturing an LED array. FIG. 5 shows a process flow diagram of a method 500 for manufacturing an LED device. Referring to FIGS. 1A through 1I and FIG. 5, an LED device 100 is manufactured that includes an optically transparent conductive layer having a bandgap close to the bandgap of the epitaxial layer.

[0025] Referring to FIGS. 1A and 5, in one or more embodiments, a first portion of the epitaxy (operation 502) includes the growth of an n-type layer 106, which may be the same as a conventional LED growth run using a sapphire or other applicable growth substrate 102. The substrate 102 may be any substrate known to those skilled in the art configured for use in forming an LED device. In one or more embodiments, the substrate 102 includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 102 is a transparent substrate. In a particular embodiment, the substrate 102 includes sapphire. In one or more embodiments, the substrate 102 is not patterned prior to the formation of the LED. Thus, in some embodiments, the substrate 102 may be considered unpatterned and flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0026] In one or more embodiments, the n-type layer 106 may include any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), which is also referred to as a group-III nitride material. Thus, in some embodiments, the n-type layer 106 includes one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a particular embodiment, the n-type layer 106 includes gallium nitride (GaN). In one or more embodiments, the n-type layer 106 is doped with an n-type dopant such as silicon (Si) or germanium (Ge). The n-type layer 106 may have a dopant concentration sufficient for lateral current transport through the layer.

[0027] In one or more embodiments, the n-type layer 106 is formed by one or more of sputtering, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0028] As used herein, "sputtering" refers to a physical vapor deposition (PVD) method for forming a thin film by sputtering. In sputtering, a material, such as a group-III nitride, is ejected from a target, which is the source, onto a substrate. This technique is based on ion bombardment of the source material, the target. As a result of the ion bombardment, vapor is generated by a purely physical process, namely sputtering of the target material.

[0029] "Atomic layer deposition" (ALD) or "cyclic deposition" as used in some embodiments of the present application represents a vapor phase technique used to deposit a thin film on a substrate surface. The process of ALD involves exposing the substrate surface or a portion of the substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to the alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into the reaction zone of the processing chamber, and the substrate or a portion of the substrate is separately exposed to the precursors.

[0030] In some embodiments, "chemical vapor deposition" as used in the present application represents a process in which a film of material is deposited from the vapor phase by decomposition of a chemical substance on the substrate surface. In CVD, the substrate surface is exposed to the precursor and / or co-ligand simultaneously or substantially simultaneously. A particular subset of CVD processes commonly used in the manufacture of LEDs uses organometallic precursor chemicals and is referred to as metalorganic chemical vapor deposition (MOCVD) or metalorganic vapor phase epitaxy (MOVPE). "Substantially simultaneously" as used in the present application refers to either co-flow or cases where there is overlap for most of the exposure of the precursors.

[0031] In some embodiments, "plasma enhanced atomic layer deposition" (PEALD) as used in the present application represents a technique for depositing a thin film on a substrate. In some examples of the PEALD process, compared to the thermal ALD process, the material can be formed from the same chemical precursors but at a higher deposition rate and a lower temperature. In the PEALD process, generally, a reactive gas and a reactive plasma are sequentially introduced into a process chamber containing the substrate within the chamber. The first reactive gas is pulsed within the processing chamber and adsorbed onto the substrate surface. Then, the reactive plasma is pulsed into the processing chamber and reacts with the first reactive gas to form a film-forming material, e.g., a thin film, on the substrate. Similar to the thermal ALD process, a purge step may be performed between each supply of the reactants.

[0032] In one or more embodiments, "Plasma Enhanced Chemical Vapor Deposition (PECVD)" as used in the present application represents a technique for forming a thin film on a substrate. In the PECVD process, a source material in the gas phase or liquid phase, such as a vapor of a group III-nitride material in the gas phase co-transported with a carrier gas or a vapor of a group III-nitride material in the liquid phase, is introduced into the PECVD chamber. Also, a plasma initiation gas is introduced into the chamber. By generating plasma in the chamber, excited radicals are generated. The excited radicals chemically bond to the surface of the substrate disposed in the chamber, and a desired film is formed thereon.

[0033] In one or more embodiments, the LED device 100 is manufactured by disposing the substrate 102 in a Metal-Organic Vapor Phase Epitaxy (MOVPE) reactor such that an LED device layer grows epitaxially.

[0034] In one or more embodiments, after the growth of the n-type layer 106, the active region 116 and the p-type layer 104 are grown using a film-forming technique known to those skilled in the art. In one or more embodiments, the p-type layer 104 contains gallium nitride (GaN).

[0035] Referring to FIGS. 1B through 1D and FIG. 5, in operation 504, a plurality of mesas are formed by etching a first mesa 122a and a second mesa 122b into the wafer. In one or more embodiments, the first mesa 122a and the second mesa 122b are separated by a trench 120. In some embodiments, the trench 120 may be formed using a conventional directional etching process such as dry etching. The trench 120 may be any suitable depth and may extend from the upper surface of the dielectric layer 108 through the n-type layer 106 to the substrate 102. The trench 120 may have at least one sidewall 121 and a bottom surface 123.

[0036] In one or more embodiments, the first mesa 122a may have a height (thickness) substantially the same as the height (thickness) of the second mesa 122b. In other embodiments, the first mesa 122a may have a height (thickness) different from the height (thickness) of the second mesa 122b.

[0037] In one or more embodiments, the etching surface (trench 120) may have a maximum tilt angle of 45. In some embodiments, the etching surface (trench 120) may be completely vertical.

[0038] Figures 1C and 5 show that in operation 506, a dielectric layer 108 is formed on the plurality of mesas 122a, 122b and within the trench 120. The dielectric layer 108 may be formed using conventional film-forming techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0039] As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer 108 may include any suitable dielectric material known to those skilled in the art. In some embodiments, the dielectric layer 108 includes a low refractive index material. In some embodiments, the dielectric material is silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum nitride (AlN), silicon oxide (SiO x ), hafnium-doped silicon dioxide (HfSiO x) includes one or more of them. The term "silicon oxide" may be used to describe the dielectric layer 108, but those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" may be used to represent a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. In one or more embodiments, the dielectric layer 108 has a thickness greater than about 300 nm, or greater than about 500 nm, or greater than about 1000 nm.

[0040] In one or more embodiments, the dielectric layer 108 is substantially conformal. A layer that is "substantially conformal" as used herein represents a layer having a thickness that is substantially the same throughout (e.g., on the upper surface of each mesa, on at least one sidewall 121, and on the bottom surface 123 of the trench 120). A substantially conformal layer varies in thickness by about 5%, 2%, 1%, or 0.5%, or less.

[0041] In one or more embodiments, the dielectric layer 108 is formed on the entire at least one sidewall 121 and the bottom surface 123 of the trench 120. Referring to FIGS. 1C and 5, in operation 508, a portion of the dielectric layer 108 may be removed from the bottom surface 123 of the trench 120 and at least one sidewall 121. A portion of the dielectric layer 108 may be removed using a conventional directional etching process such as dry etching. In one or more embodiments, when a portion of the dielectric layer 108 is removed from the bottom surface 123 of the trench 120 and at least one sidewall 121, an exposed portion 125 of the sidewall is formed. The exposed portion 125 may include a portion of the n-type layer 106, and the substrate 102 may be exposed within the trench 120.

[0042] Referring to FIG. 1D, after the dielectric layer 108 is formed, the device 100 is etched to complete the formation of the plurality of mesas 122a, 122b, and the upper surface of the substrate 102 is exposed. In some embodiments, the upper surface of the substrate 102 forms the bottom of the trench 120.

[0043] Referring to FIGS. 1E and 5, in one or more embodiments, in operation 510, a transparent conductive layer 114 is formed on a plurality of mesas 122a, 122b on the dielectric layer 108 and exposed portions 125 of the sidewalls of the plurality of mesas 122a, 122b. In one or more embodiments, the transparent conductive layer 114 is formed on the bottom surface 123 of the trench 120. In some embodiments, the transparent conductive layer 114 is a conformal layer.

[0044] The transparent conductive layer 114 may be formed using conventional film formation techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0045] In one or more embodiments, the transparent conductive layer 114 may include any suitable material known to those skilled in the art. In some embodiments, the transparent conductive layer 114 includes zinc oxide (ZnO). ZnO has a high light transmittance at visible light wavelengths and a bandgap of 3.37 eV, which is close to the bandgap of GaN (3.4 eV). Having a bandgap close to that of GaN means that ZnO absorbs the laser beam during subsequent laser lift-off of the substrate in a manner similar to GaN, and thus is separated from the sapphire substrate 102 during the same laser lift-off step used for separating the GaN layers 106, 104, protecting the metal contact layer 110 from the laser lift-off laser beam. The thickness of the ZnO layer ranges from tens of nanometers to hundreds of nanometers, thick enough that the laser beam is completely absorbed by the bottom section of this layer and does not reach the metal contact layer 110 for sure.

[0046] The term "zinc oxide" may be used to describe the transparent conductive layer 114, but it will be understood by those skilled in the art that the present disclosure is not limited to a particular stoichiometry. In one or more embodiments, the transparent conductive layer 114 has a thickness greater than about 10 nm, or greater than about 20 nm, or greater than about 100 nm. In other embodiments, the transparent conductive layer 114 has a thickness in the range of 10 nm to 500 nm. Without intending to be bound by theory, it is believed that the optimal thickness of the transparent conductive layer 114 depends on laser lift-off parameters such as laser wavelength and energy.

[0047] Referring to FIGS. 1F and 5, in one or more embodiments, in operation 512, a cathode layer 110 or an n-type contact is formed on the exposed portion 125 within the trench 120. In one or more embodiments, the cathode layer 110 may have any suitable material known to those skilled in the art. In one or more embodiments, the cathode layer 110 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0048] FIG. 1G shows that in operation 514 of FIG. 5, a contact hole 124 is formed in the dielectric layer 108, exposing the upper surface of the n-type layer 104. In some embodiments, a first contact hole 124a is formed in the dielectric layer 108 of the first mesa 122a, exposing the upper surface of the n-type layer 104. A second contact hole 124b is formed in the dielectric layer 108 of the second mesa 122b, exposing the upper surface of the n-type layer 104. The contact holes 124a, 124b are formed using a conventional directional etching process such as dry etching.

[0049] Referring to FIGS. 1H and 5, in operation 516, an anode contact metal 112 (or p-type contact) is formed within contact hole 124. In one or more embodiments, the p-type contact metal 112 may include any suitable material known to those skilled in the art. In one or more embodiments, the p-type contact metal 112 includes a p-type contact material selected from one or more of aluminum (Al), silver (Ag), gold (Au), platinum (Pt), and palladium (Pd). In a particular embodiment, the p-type contact metal 112 includes silver (Ag). In some embodiments, a small amount of an additional metal may be added to the anode contact metal 112 as an adhesion promoter. Such adhesion promoters may include, but are not limited to, one or more of nickel (Ni), titanium (Ti), and chromium (Cr).

[0050] In one or more embodiments, the anode contact metal 112 and the cathode contact 110 may be composed of the same metal in the same film formation and lift-off steps.

[0051] Referring to FIGS. 1I and 5, in operation 518, at a later stage of the process, the space between the mesas 122a, 122b may be filled with a conductive material 146, which may be, for example, electroplated copper (Cu), and the entire wafer 100 or a portion of the wafer 100 is bonded to a system substrate, such as a display backplane, to form a system. An array of landing pads may be disposed on the system substrate with dimensions aligned with the bonding pads on the LED wafer 100. The landing pads may be connected to a display driver circuit in the system substrate.

[0052] In one or more embodiments, when the substrate is a UV-transmissive material such as sapphire, after bonding, the growth substrate 102 is removed using a process such as laser lift-off. In one or more embodiments, by incorporating an optically transparent conductive layer 114, problems of interaction with the laser beam from the laser lift-off process are solved. The transparent conductive layer 114 functions as a protective layer for the metal contact layer 110 and prevents interaction of the laser with the metal contact layer 110. In one or more embodiments, the laser lift-off laser power is absorbed within the transparent conductive layer 114 before reaching the contact layer 110. Without being bound by theory, the transparent conductive layer 114 enables a thin conformal coating of a laser lift-off separable layer that covers the sapphire at the bottom of the trench, which protects the metal contact layer 110 but is still thought to be able to provide good optical contrast between pixels. Also, the risk of cracks occurring in this thin transparent conductive layer 114 and propagating to the pixel active region is reduced.

[0053] FIG. 2 shows an alternative embodiment of the LED device. FIG. 6 shows a process flow diagram of a method 600 for forming an LED device. The epitaxial growth shown in FIG. 2 in operation 602 is slightly different from the epitaxial growth of FIGS. 1A - 1H. Referring to FIG. 2, in one or more embodiments, a transparent conductive oxide layer 230 (e.g., indium tin oxide (ITO)) is grown before the p-type layer 204. In operation 604, then, as shown with respect to FIG. 1B, the semiconductor layer is etched to form a plurality of mesas. Next, in operation 606, a dielectric layer 208 is deposited over the plurality of mesas, and in operation 608, a portion of the dielectric layer may be removed as shown with respect to FIG. 1C above. In operation 610, a transparent conductive layer 214 is deposited over the plurality of mesas 222a, 222b of the dielectric layer 208 and on the exposed portions of the sidewalls of the trench. In one or more embodiments, the transparent conductive layer 214 is formed on the bottom surface of the trench. In some embodiments, the transparent conductive layer 214 is a conformal layer.

[0054] The transparent conductive layer 214 may be formed using conventional film-forming techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0055] In one or more embodiments, the transparent conductive layer 214 may include any suitable material known to those skilled in the art. In some embodiments, the transparent conductive layer 214 includes zinc oxide (ZnO). ZnO has a high light transmittance at visible light wavelengths and a bandgap of 3.37 eV, which is close to the bandgap of GaN (3.4 eV). Having a bandgap close to GaN means that ZnO absorbs the laser beam during subsequent laser lift-off of the substrate in a manner similar to GaN, and thus can be separated from the sapphire substrate during the same laser lift-off step used to separate the GaN layers 206, 204, protecting the metal contact layer 210 from the laser lift-off laser beam. The thickness of the ZnO layer ranges from several tens of nanometers to several hundreds of nanometers, thick enough such that the laser beam is completely absorbed by the bottom section of this layer and does not reach the metal contact layer 210.

[0056] Although the term "zinc oxide" may be used to describe the transparent conductive layer 114, it will be understood by those skilled in the art that the present disclosure is not limited to a specific stoichiometry. In one or more embodiments, the transparent conductive layer 214 has a thickness greater than about 10 nm, or greater than about 20 nm, or greater than about 100 nm. In other embodiments, the transparent conductive layer 214 has a thickness in the range of 10 nm to 500 nm. Without intending to be bound by theory, the optimal thickness of the transparent conductive layer 214 is thought to depend on laser lift-off parameters such as the laser wavelength and energy.

[0057] Referring to FIGS. 2 and 6, in one or more embodiments, in operation 612, a spacer layer 218 is formed in the trench adjacent to the transparent conductive layer 214. The spacer layer 218 may be formed using conventional film-forming techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0058] In one or more embodiments, the spacer layer 218 may comprise any suitable dielectric material known to those skilled in the art. In some embodiments, the spacer layer 218 comprises a dielectric material. In one or more embodiments, the spacer layer 218 comprises silicon oxide. In one or more embodiments, the spacer layer 218 has a thickness greater than about 10 nm, or greater than about 20 nm, or greater than about 100 nm. In other embodiments, the spacer layer 218 has a thickness in the range of 10 nm to 500 nm. Thereby, the spacer layer 281 provides total internal reflection (TIR) means and enhances the sidewall reflectivity.

[0059] In one or more embodiments, in operation 614, a cathode layer 210, or an n-type contact, is formed in the trench directly adjacent to the spacer layer 218 / directly above the spacer layer 310. In one or more embodiments, the cathode layer 210 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the cathode layer 210 comprises an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0060] At the bottom of the trench between the cathode layer 210 and the transparent conductive layer 214, a necessary electrical metal-ZnO (210-214) contact is formed. Current injection into the semiconductor is ensured by lateral current diffusion through the transparent conductive layer 214.

[0061] FIG. 3 shows an alternative embodiment of the LED device. FIG. 6 shows a process flow diagram of a method 600 for forming an LED device. In operation 602, the epitaxial growth shown in FIG. 3 is slightly different from the epitaxial growth of FIGS. 1A-1H. Referring to FIG. 3, in one or more embodiments, a transparent conductive oxide layer 330 (e.g., indium tin oxide (ITO)) is grown before the p-type layer 304. Next, in operation 604, as shown with respect to FIG. 1B above, the semiconductor layer is etched to form a plurality of mesas. Next, in operation 606, a dielectric layer 308 is deposited over the plurality of mesas, and in operation 608, a portion of the dielectric layer may be removed as shown with respect to FIG. 1C above. In operation 610, a transparent conductive layer 314 is deposited on the exposed portions of the sidewalls of the plurality of mesas 322a, 322b, and trenches on the dielectric layer 308. In one or more embodiments, the transparent conductive layer 314 is on the bottom surface of the trench and the upper surface 314t of the trench. In some embodiments, the transparent conductive layers 314, 314t are conformal layers.

[0062] The transparent conductive layer 314 may be formed using conventional film deposition techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0063] In one or more embodiments, the transparent conductive layer 314 may comprise any suitable material known to those skilled in the art. In some embodiments, the transparent conductive layer 314 comprises zinc oxide (ZnO). ZnO has a high light transmittance at visible light wavelengths and a bandgap of 3.37 eV, which is close to the bandgap of GaN (3.4 eV). Having a bandgap close to that of GaN means that ZnO absorbs the laser beam during subsequent laser lift-off of the substrate in a similar manner to GaN, and thus ZnO can be separated from the sapphire substrate during the same laser lift-off step used to separate the GaN layers 306, 304, protecting the metal contact layer 310 from the laser lift-off laser beam. The thickness of the ZnO layer ranges from several tens of nanometers to several hundreds of nanometers and is thick enough that the laser beam is completely absorbed by the bottom section of this layer and does not reach the metal contact layer 310.

[0064] In one or more embodiments, the transparent conductive layer 314 has a thickness greater than about 10 nm, or greater than about 20 nm, or greater than about 100 nm. In other embodiments, the transparent conductive layer 314 has a thickness in the range of 10 nm to 500 nm. Without intending to be bound by theory, the optimal thickness of the transparent conductive layer 314 is believed to depend on laser lift-off parameters such as laser wavelength and energy.

[0065] Referring to FIGS. 3 and 6, in one or more embodiments, in operation 612, a spacer layer 318 is formed in the trench adjacent to the transparent conductive layer 314. The spacer layer 318 may be formed using conventional film-forming techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0066] In one or more embodiments, the spacer layer 318 may include any suitable dielectric material known to those skilled in the art. In some embodiments, the spacer layer 318 includes a dielectric material. In one or more embodiments, the spacer layer 318 includes silicon oxide. In one or more embodiments, the spacer layer 318 has a thickness greater than about 10 nm, or greater than about 20 nm, or greater than about 100 nm. In other embodiments, the spacer layer 318 has a thickness in the range of 10 nm to 500 nm. Thereby, the spacer layer 318 provides total internal reflection (TIR) means for increasing the sidewall reflectivity.

[0067] In one or more embodiments, in operation 614, the cathode layer 310 or the n-type contact is formed in the trench directly adjacent to the spacer layer 318 / on the spacer layer 310. In one or more embodiments, the cathode layer 310 may include any suitable material known to those skilled in the art. In one or more embodiments, the cathode layer 310 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0068] The required electrical metal-ZnO (310 - 314) contact is formed at the bottom of the trench and at the upper part (310t - 314t) of the trench between the cathode layer 310 and the transparent conductive layer 314. Lateral current diffusion through the transparent conductive layer 314 ensures current injection into the semiconductor.

[0069] FIG. 4 shows another embodiment of the LED device. FIG. 7 shows a process flow diagram of a method 700 for forming an LED device. The epitaxial growth shown in operation 702 of FIG. 4 is slightly different from the epitaxial growth of FIGS. 1A-1H. Referring to FIG. 4, in one or more embodiments, a transparent conductive oxide layer 430 (e.g., indium tin oxide (ITO)) is formed before the p-type layer 404. In operation 704, as shown with respect to FIG. 1B, the semiconductor layer is then etched to form a plurality of mesas. Next, in operation 706, a dielectric layer 408 is formed over the plurality of mesas, and in operation 708, a portion of the dielectric layer 408 may be removed as shown with respect to FIG. 1C. In operation 710, a transparent conductive layer 414 is formed over the plurality of mesas 422a, 422b on the dielectric layer 408 and on the exposed portions of the sidewalls of the trenches. In one or more embodiments, the transparent conductive layer 414 is on the bottom surface of the trench and the upper surface 414t of the trench. In some embodiments, the transparent conductive layers 414, 414t are conformal layers.

[0070] The transparent conductive layer 414 may be formed using conventional film-forming techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0071] In one or more embodiments, the transparent conductive layer 414 may include any suitable material known to those skilled in the art. In some embodiments, the transparent conductive layer 414 includes zinc oxide (ZnO). ZnO has a high light transmittance at visible light wavelengths and a bandgap of 3.37 eV, which is close to the bandgap of GaN (3.4 eV). Having a bandgap close to that of GaN means that ZnO absorbs the laser beam during subsequent laser lift-off of the substrate in a manner similar to GaN, and thus ZnO can be separated from the sapphire substrate during the same laser lift-off step used to separate the GaN layers 406, 404, protecting the metal contact layer 410 from the laser lift-off laser beam. The thickness of the ZnO layer ranges from several tens of nanometers to several hundreds of nanometers and is thick enough that the laser beam is completely absorbed by the bottom section of this layer and does not reach the metal contact layer 410.

[0072] In one or more embodiments, the transparent conductive layer 414 has a thickness greater than about 10 nm, or greater than about 20 nm, or greater than about 100 nm. In other embodiments, the transparent conductive layer 414 has a thickness in the range of 10 nm to 500 nm. Without intending to be bound by theory, the optimal thickness of the transparent conductive layer 414 is thought to depend on laser lift-off parameters such as laser wavelength and energy.

[0073] In one or more embodiments, referring to FIGS. 4 and 7, in operation 712, adjacent to the transparent conductive layer 414, a distributed Bragg reflector (DBR) 436 is formed in the trench. The distributed Bragg reflector (DBR) 436 may be formed using conventional film formation techniques such as, for example, CVD, PECVD, ALD, evaporation, sputtering, chemical solution deposition, spin-on deposition, or other similar processes.

[0074] A distributed Bragg reflector is typically composed of a multi-layer of alternating thin film materials with different refractive indices, and high reflectivity is one of the important attributes. A distributed Bragg reflector or mirror is a structure formed from a multi-layer stack of alternating thin film materials with varying refractive indices, such as alternating layers of a high refractive index film and a low refractive index film. The Bragg reflector needs to have a high reflectivity. In some embodiments, the distributed Bragg reflector 436 has a thickness of at least 0.2 microns.

[0075] In one or more embodiments, the distributed Bragg reflector (DBR) 436 may include any suitable dielectric material known to those skilled in the art. In some embodiments, the distributed Bragg reflector (DBR) 436 includes, but is not limited to, a series of alternating layers of group-III nitride materials with different refractive indices, such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN), or aluminum indium nitride (AlInN), or mixtures thereof. In one or more embodiments, the DBR 436 includes silicon oxide.

[0076] In one or more embodiments, the distributed Bragg reflector (DBR) 436 has a thickness of at least 0.2 microns. In other embodiments, the distributed Bragg reflector (DBR) 436 has a thickness in the range of 0.2 microns to 5 microns. In other embodiments, the distributed Bragg reflector (DBR) 436 has a thickness in the range of 10 nm to 500 nm. The distributed Bragg reflector (DBR) 436 thereby provides total internal reflection (TIR) means for increasing the sidewall reflectivity.

[0077] In one or more embodiments, in operation 714, a cathode layer 410 or an n-type contact is formed in the trench directly adjacent to / on top of the distributed Bragg reflector (DBR) 436. In one or more embodiments, the cathode layer 410 may include any suitable material known to those skilled in the art. In one or more embodiments, the cathode layer 410 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0078] The necessary electrical metal-ZnO (410-414) contact is formed at the bottom of the trench and also at the upper part (410t-414t) of the trench between the cathode layer 410 and the transparent conductive layer 414. The lateral current diffusion through the transparent conductive layer 314 ensures current injection into the semiconductor.

[0079] (Embodiment) The following are various embodiments. It is understood that the embodiments described below may be combined with all aspects and other embodiments in accordance with the scope of the present invention.

[0080] (Embodiment a) A light-emitting diode (LED) device, A mesa having a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, a mesa, A transparent conductive layer on the at least one sidewall and within the trench, A cathode layer within the trench on the transparent conductive layer, A p-type contact on the upper surface of the mesa, An LED device having.

[0081] (Embodiment b) The LED device according to Embodiment a, wherein the transparent conductive layer contains zinc oxide.

[0082] (Embodiment c) The LED element according to Embodiment (a) or (b), wherein the thickness of the transparent conductive layer ranges from 10 nm to 500 nm.

[0083] (Embodiment d) The LED device according to Embodiments (a) to (c), further having a dielectric layer on a part of the mesa.

[0084] (Embodiment e) The LED device according to Embodiments (a) to (d), wherein the dielectric layer contains a low refractive index material.

[0085] (Embodiment f) The low refractive index material is silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum nitride (AlN), silicon oxide (SiO x ), and hafnium-doped silicon dioxide (HfSiO x ), and the LED device according to Embodiments (a) to (e) includes a material selected from the group consisting of.

[0086] (Embodiment g) The transparent conductive layer is a CVD transparent conductive layer or a sputtering transparent conductive layer, and the LED device according to Embodiments (a) to (f).

[0087] (Embodiment h) The cathode layer includes one or more of silver (Ag) and aluminum (Al), and the LED device according to Embodiments (a) to (g).

[0088] (Embodiment i) The semiconductor layer is an epitaxial semiconductor layer having a thickness of at least 1 micron, and the LED device according to Embodiments (a) to (h).

[0089] (Embodiment j) A method for manufacturing a light-emitting diode (LED) device, a step of forming a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate; etching a part of the semiconductor layer to form at least one trench and at least one mesa defining a pixel, wherein the at least one mesa contains the semiconductor layer, an upper surface, and at least one side wall; forming a transparent conductive layer on the at least one side wall, the upper surface of the at least one mesa, and in the trench; forming a cathode layer in the trench and on the transparent conductive layer; forming a p-type contact on the upper surface of the at least one mesa; A method comprising:

[0090] (Embodiment k) The method according to embodiment (j), wherein the transparent conductive layer contains zinc oxide.

[0091] (Embodiment l) The method according to any one of embodiments (j) to (k), wherein the thickness of the transparent conductive layer ranges from 10 nm to 500 nm.

[0092] (Embodiment m) The method according to any one of embodiments (j) to (l), further comprising depositing a dielectric layer on a part of the mesa.

[0093] (Embodiment n) The method according to any one of embodiments (j) to (m), wherein the dielectric layer contains a low refractive index material.

[0094] (Embodiment o) The method according to any one of embodiments (j) to (n), wherein the low refractive index material contains silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum nitride (AlN), silicon oxide (SiO x ), or a material selected from the group consisting of hafnium-doped silicon dioxide (HfSiO x ).

[0095] (Embodiment p) The method according to any one of embodiments (j) to (o), wherein the transparent conductive layer is a CVD transparent conductive layer or a sputtering transparent conductive layer.

[0096] (Embodiment q) The method according to any one of embodiments (j) to (p), wherein the cathode layer contains one or more of silver (Ag) and aluminum (Al).

[0097] (Embodiment r) The method according to Embodiments (j) to (q), wherein the semiconductor layer is an epitaxial semiconductor layer having a thickness of at least 1 micron.

[0098] (Embodiment s) A light-emitting diode (LED) device, a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, the mesa; a dielectric layer on the at least one sidewall of the mesa and on a part of the upper surface of the mesa; a zinc oxide layer on the dielectric layer, on the at least one sidewall of the mesa, and in the trench; a cathode layer on the zinc oxide layer; a p-contact on the upper surface of the mesa; The LED device having the above.

[0099] (Embodiment t) The LED device according to Embodiment (s), wherein the cathode layer includes one or more of silver (Ag) and aluminum (Al).

[0100] (Embodiment u) A light-emitting diode (LED) device, a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, the mesa; a transparent conductive layer on the at least one sidewall and in the trench; a spacer layer on the transparent conductive layer; a cathode layer on the dielectric spacer layer; a p-type contact on the upper surface of the mesa; The LED device having the above.

[0101] (Embodiment v) The LED device according to Embodiment (u), wherein the transparent conductive layer includes zinc oxide.

[0102] (Embodiment w) The LED device according to Embodiment (u) to Embodiment (v), wherein the transparent conductive layer has a thickness in the range of 10 nm to 500 nm.

[0103] (Embodiment x) The LED device according to Embodiment (u) to Embodiment (w), wherein the spacer layer contains silicon oxide.

[0104] (Embodiment y) The LED device according to Embodiment (u) to Embodiment (x), wherein the spacer layer has a thickness in the range of 10 nm to 500 nm.

[0105] (Embodiment z) The LED device according to Embodiment (u) to Embodiment (y), further having a dielectric layer on a part of the mesa.

[0106] (Embodiment aa) The LED device according to Embodiment (u) to Embodiment (z), further having the transparent conductive layer on the upper surface of the dielectric layer and having the cathode layer on the upper surface of the transparent conductive layer.

[0107] (Embodiment bb) The LED device according to Embodiment (u) to Embodiment (aa), wherein the transparent conductive layer is a CVD transparent conductive layer or a sputtered transparent conductive layer.

[0108] (Embodiment cc) The LED device according to Embodiment (u) to Embodiment (bb), wherein the cathode layer contains one or more of silver (Ag) and aluminum (Al).

[0109] (Embodiment dd) The LED device according to Embodiment (u) to Embodiment (cc), wherein the semiconductor layer is an epitaxial semiconductor layer having a thickness of at least 1 micron.

[0110] (Embodiment ee) A method for manufacturing a light emitting diode (LED) device, a step of forming a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate; Etching a part of the semiconductor layer to form at least one trench and at least one mesa that define pixels, wherein the at least one mesa includes the semiconductor layer, an upper surface, and at least one sidewall; Depositing a transparent conductive layer on the at least one sidewall, the upper surface of the at least one mesa, and within the trench; Depositing a spacer layer on the transparent conductive layer; Depositing a cathode layer on the transparent conductive layer; Forming a p-type contact on the upper surface of the at least one mesa; A method comprising the above steps.

[0111] (Embodiment ff) The method according to embodiment (ee), wherein the transparent conductive layer contains zinc oxide.

[0112] (Embodiment gg) The method according to embodiments (ee) to (ff), wherein the transparent conductive layer has a thickness in the range of 10 nm to 500 nm.

[0113] (Embodiment hh) The method according to embodiments (ee) to (gg), wherein the spacer layer contains silicon oxide.

[0114] (Embodiment ii) The method according to embodiments (ee) to (hh), wherein the spacer layer has a thickness in the range of 10 nm to 500 nm.

[0115] (Embodiment jj) The method according to embodiments (ee) to (ii), further comprising depositing a dielectric layer on a part of the mesa.

[0116] (Embodiment kk) Further, Forming a transparent conductive layer on the upper surface of the dielectric layer; Forming the cathode layer on the upper surface of the transparent conductive layer; The method according to embodiments (ee) to (jj), comprising the above steps.

[0117] (Embodiment ll) The method according to Embodiments (ee) to (kk), wherein the cathode layer contains one or more of silver (Ag) and aluminum (Al).

[0118] (Embodiment mm) A light-emitting diode (LED) device, a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, a mesa; a dielectric layer on the at least one sidewall of the mesa and on a part of the upper surface of the mesa; a zinc oxide layer on the dielectric layer, on the at least one sidewall of the mesa, and in the trench; a spacer layer on the zinc oxide layer; a cathode layer on the spacer layer; a p-contact on the upper surface of the mesa; An LED device having

[0119] (Embodiment nn) The LED device according to Embodiment (mm), wherein the spacer layer contains silicon oxide.

[0120] (Embodiment oo) A light-emitting diode (LED) device, a mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, a mesa; a transparent conductive layer on the at least one sidewall and in the trench; a distributed Bragg reflector (DBR) on the transparent conductive layer; a cathode layer on the dielectric spacer layer; a p-type contact on the upper surface of the mesa; An LED device having

[0121] (Embodiment pp) The LED device according to Embodiment (oo), wherein the transparent conductive layer contains zinc oxide.

[0122] (Embodiment qq) The LED device according to Embodiments (oo) to (pp), wherein the transparent conductive layer has a thickness in the range of 10 nm to 500 nm.

[0123] (Embodiment rr) The LED device according to Embodiments (oo) to (qq), wherein the distributed Bragg reflector (DBR) contains silicon oxide.

[0124] (Embodiment ss) The LED device according to Embodiments (oo) to (rr), wherein the distributed Bragg reflector (DBR) has a thickness of at least 0.2 microns.

[0125] (Embodiment tt) The LED device according to Embodiments (oo) to (ss), further having a dielectric layer on a part of the mesa.

[0126] (Embodiment uu) The dielectric layer is made of silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum nitride (AlN), silicon oxide (SiO x ), and hafnium-doped silicon oxide (HfSiO x ). The LED device according to Embodiments (oo) to (tt) contains a material selected from the group consisting of.

[0127] (Embodiment vv) The LED device according to Embodiments (oo) to (uu), wherein the transparent conductive layer is a CVD transparent conductive layer or a sputtered transparent conductive layer.

[0128] (Embodiment ww) The LED device according to Embodiments (oo) to (vv), wherein the cathode layer contains one or more of silver (Ag) and aluminum (Al).

[0129] (Embodiment xx) The LED device according to Embodiments (oo) to (ww), wherein the semiconductor layer is an epitaxial semiconductor layer having a thickness of at least 1 micron.

[0130] (Embodiment yy) A method for manufacturing a light-emitting diode (LED) device, comprising: Depositing a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate; Etching a part of the semiconductor layer to form at least one trench and at least one mesa defining a pixel, wherein the at least one mesa has the semiconductor layer, an upper surface, and at least one sidewall; Depositing a transparent conductive layer on the at least one sidewall, the upper surface of the at least one mesa, and in the trench; Depositing a distributed Bragg reflector (DBR) on the transparent conductive layer; Depositing a cathode layer on the transparent conductive layer; Forming a p-type contact on the upper surface of the at least one mesa; A method having the above steps.

[0131] (Embodiment zz) The method according to Embodiment (yy), wherein the transparent conductive layer contains zinc oxide.

[0132] (Embodiment aaa) The method according to Embodiments (yy) to (zz), wherein the transparent conductive layer has a thickness in the range of 10 nm to 500 nm.

[0133] (Embodiment bbb) The method according to Embodiments (yy) to (aaa), wherein the distributed Bragg reflector (DBR) contains silicon oxide.

[0134] (Embodiment ccc) The distributed Bragg reflector (DBR) has a thickness in the range of 10 nm to 500 nm, and the method described in Embodiment (yy) to Embodiment (bbb).

[0135] (Embodiment ddd) Further, the method described in Embodiment (yy) to Embodiment (ccc), which includes a step of forming a dielectric layer on a part of the mesa.

[0136] (Embodiment eee) The dielectric layer is silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum nitride (AlN), silicon oxide (SiO x ), and hafnium-doped silicon dioxide (HfSiO x ), and the method described in Embodiment (yy) to Embodiment (ddd) includes a material selected from the group consisting of these.

[0137] (Embodiment fff) The cathode layer includes one or more of silver (Ag) and aluminum (Al), and the method described in Embodiment (yy) to Embodiment (eee).

[0138] (Embodiment ggg) A light-emitting diode (LED) device, A mesa including a semiconductor layer, the semiconductor layer includes an N-type layer, an active layer, and a P-type layer, the mesa has an upper surface and at least one side wall, and the at least one side wall defines a trench having a bottom surface, a mesa, A dielectric layer on the at least one side wall of the mesa and on a part of the upper surface of the mesa, A zinc oxide layer on the dielectric layer, on the at least one side wall of the mesa, and in the trench, A distributed Bragg reflector (DBR) on the zinc oxide layer, A cathode layer on the spacer layer, A p-contact on the upper surface of the mesa, An LED device having

[0139] (Embodiment hhh) The LED device according to embodiment (ggg), wherein the cathode layer contains one or more of silver (Ag) and aluminum (Al).

[0140] In the context of describing the materials and methods described in this application (in particular, in the context of the following claims), the terms "a", "an", and "the" and similar references are to be construed as encompassing both the singular and the plural, unless otherwise indicated in this application or clearly contradicted by the context. The description of a range of values in this application is merely intended to serve as an abbreviation for individually representing each separate value included within that range, and each separate value is incorporated into this application as if it were individually recited herein. All methods described in this application can be performed in any suitable order, unless otherwise indicated in this application or clearly contradicted by the context. The use of any and all examples, or exemplary terms (e.g., "such as") in this application is merely intended to make the materials and methods more clear and is not limiting of the scope, unless otherwise claimed. No term in this application should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0141] Throughout this application, references to terms such as first, second, third, etc. are used to describe various elements, and these elements should not be limited by these terms. These terms can be used to distinguish one element from another.

[0142] Throughout this application, references to a layer, region, or substrate that is "above" or "extends above" another element mean that it may be directly above the other element, or directly extend above the other element, or intervening elements may be present. When an element is referred to as being "directly above" or "extending directly above" another element, intervening elements may not be present. Further, when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected or coupled to the other element, and / or may be connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected to" or "directly coupled to" another element, no intervening elements are present between the element and the other element. It is understood that these terms are intended to encompass different orientations of the elements in addition to any orientation shown in the figures.

[0143] Relative terms such as "under", "above", "upper", "lower", "horizontal", or "vertical" as used in this application may be used to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0144] Throughout this application, references to "one embodiment", "an embodiment", "one or more embodiments", or "embodiments" mean that the particular features, structures, materials, or characteristics described in connection with the embodiments are included in at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in embodiments" throughout this application are not necessarily all referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0145] In the disclosure of the present application, although the description is made with reference to specific embodiments, it is understood that these embodiments are merely examples of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode (LED) device, A mesa having a semiconductor layer, the semiconductor layer including an N-type layer, an active layer, and a P-type layer, the mesa having an upper surface and at least one sidewall, the at least one sidewall defining a trench having a bottom surface, the mesa; A transparent conductive layer on the at least one sidewall and within the trench, the transparent conductive layer continuously extending from the at least one sidewall across the bottom surface of the trench, the transparent conductive layer; A cathode layer within the trench on the transparent conductive layer; A p-type contact on the upper surface of the mesa; and having The transparent conductive layer includes zinc oxide, The N-type layer and the P-type layer include GaN, the LED device.

2. Further, having a spacer layer on the transparent conductive layer, The spacer layer includes silicon oxide, and the spacer layer has a thickness in the range of 10 nm to 500 nm, the LED device according to claim 1.

3. Further, having a distributed Bragg reflector (DBR) on the transparent conductive layer, The distributed Bragg reflector (DBR) includes silicon oxide and has a thickness of at least 0.2 microns, the LED device according to claim 1.

4. The transparent conductive layer has a thickness in the range of 10 nm to 500 nm, the LED device according to claim 1.

5. Further, having a dielectric layer on a part of the mesa, The dielectric layer is silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x), aluminum nitride (AlN), silicon oxide (SiO x ), and a low refractive index material selected from the group consisting of hafnium-doped silicon oxide (HfSiO x ), the LED device according to claim 1.

6. The LED device according to claim 1, wherein the transparent conductive layer is a CVD transparent conductive layer or a sputtered transparent conductive layer.

7. The LED device according to claim 1, wherein the cathode layer includes one or more of silver (Ag) and aluminum (Al).

8. A method of manufacturing a light-emitting diode (LED) device, comprising: forming a plurality of semiconductor layers including an N-type layer, an active layer, and a P-type layer on a substrate, wherein the N-type layer and the P-type layer include GaN; etching a part of the semiconductor layer to form at least one trench and at least one mesa that define pixels, wherein the at least one mesa includes the semiconductor layer, an upper surface, and at least one sidewall; forming a transparent conductive layer on the at least one sidewall, the upper surface of the at least one mesa, and in the trench, wherein the transparent conductive layer includes zinc oxide and continuously extends from the upper surface of the at least one mesa to the bottom surface of the trench; forming a cathode layer in the trench and on the transparent conductive layer; forming a p-type contact on the upper surface of the at least one mesa; A method having the above steps.

9. The method according to claim 8, further comprising forming a spacer layer on the transparent conductive layer.

10. The method according to claim 9, wherein the spacer layer includes silicon oxide and has a thickness in the range of 10 nm to 500 nm.

11. The method according to claim 8, further comprising a step of forming a distributed Bragg reflector (DBR) on the transparent conductive layer.

12. The method according to claim 11, wherein the distributed Bragg reflector (DBR) contains silicon oxide and has a thickness of at least 0.2 microns.

13. Further comprising a step of forming a dielectric layer on a part of the mesa, The dielectric layer contains a low refractive index material selected from the group consisting of silicon nitride (SiN), titanium oxide (TiO x ), niobium oxide (NbO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum nitride (AlN), silicon oxide (SiO x ), and hafnium-doped silicon dioxide (HfSiO x ). The method according to claim 8.

14. A light-emitting diode (LED) device, A mesa including a semiconductor layer, the semiconductor layer includes an N-type layer, an active layer, and a P-type layer, the N-type layer and the P-type layer contain GaN, the mesa has an upper surface and at least one side wall, and the at least one side wall defines a trench having a bottom surface, a mesa; A dielectric layer on a part of the at least one side wall of the mesa and on the upper surface of the mesa; A zinc oxide layer on the dielectric, on the at least one side wall of the mesa, and in the trench, the zinc oxide layer continuously extends from at least one side wall of the mesa to the bottom surface of the trench, a zinc oxide layer; A cathode layer on the zinc oxide layer; A p-contact on the upper surface of the mesa; An LED device having.

15. Furthermore, the LED device according to claim 14, having one or more of a spacer layer or a distributed Bragg reflector (DBR) on the zinc oxide layer.

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