Semiconductor device

Abstract

To provide a semiconductor device capable of achieving high breakdown voltage.SOLUTION: A semiconductor device 1 includes: a first semiconductor region 2: first grooves 3 formed in the first semiconductor region; first insulation films 4 formed in respective first grooves; conductors 5 formed in the insides of the first grooves; a second groove 31 formed in the first semiconductor region; a second insulation film 41 formed in the second groove; third grooves 32 formed in the first semiconductor region separately on the outside of the second groove; a second semiconductor region 21 formed between the first groove and the second groove; third semiconductor regions 22 formed between the second groove and the third grooves; a first field electrode 13 formed on the second insulation film in the second groove separately from the second semiconductor region; and a second field electrode 14 formed on the second insulation film in the second groove separately from the third semiconductor region. The first field electrode is electrically connected to the first main electrode and the second field electrode is electrically floating.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In order to improve breakdown voltage, there is a method of using a termination trench that divides an active region and an inactive region. Also, it is known to provide field electrodes on the left and right side surfaces in the termination trench and relax the electric field by setting both field electrodes to an anode potential or a floating potential.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, even if both field electrodes provided in the termination trench are set to an anode potential or a floating potential, the electric field may concentrate near the oxide film at the corner bottom on the outer peripheral side of the termination trench, resulting in deterioration of the breakdown voltage or deterioration of the oxide film formed on the termination trench.

[0005] In view of the above problems, an object of the present invention is to provide a semiconductor device capable of achieving high breakdown voltage.

Means for Solving the Problems

[0006] According to one aspect of the present invention, a semiconductor device includes a first semiconductor region, a first groove provided in the first semiconductor region, a first insulating film formed in the first groove, a conductor provided inside the first groove, a second groove provided in the first semiconductor region, a second insulating film formed in the second groove, a third groove provided in the first semiconductor region spaced apart from the outside of the second groove, a second semiconductor region provided between the first groove and the second groove, a third semiconductor region provided between the second groove and the third groove, a first field electrode formed spaced apart from the second semiconductor region on the second insulating film inside the second groove, and a second field electrode formed spaced apart from the third semiconductor region on the second insulating film inside the second groove. The first field electrode is electrically connected to the first main electrode, and the second field electrode is electrically floating. and the second semiconductor region is electrically floating is. According to another aspect of the present invention, a semiconductor device includes a first semiconductor region of a first conductivity type having an active region and an inactive region, a first groove provided so as to reach the first semiconductor region in the active region, a first insulating film formed in the first groove, a conductor provided inside the first groove, a second groove provided so as to reach the first semiconductor region in the inactive region, a second insulating film formed in the second groove, a third groove provided in the inactive region and separated from the second groove and reaching the first semiconductor region, a second semiconductor region of a second conductivity type provided on the first semiconductor region between the first groove and the second groove, a third semiconductor region of a second conductivity type provided on the first semiconductor region between the second groove and the third groove, a first field electrode disposed on the second insulating film of the second groove and separated from the second semiconductor region, and a second field electrode disposed on the second insulating film of the second groove and separated from the third semiconductor region. The first field electrode is electrically connected to a first main electrode, the second field electrode is electrically floating, and a distance between the second semiconductor region and the first field electrode is larger than a distance between the second semiconductor region and the conductor.

Advantages of the Invention

[0007] According to the present invention, a semiconductor device capable of achieving a high breakdown voltage can be provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0009] Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, etc. are different from the actual ones. Therefore, specific dimensions should be determined with reference to the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0010] Also, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the shape, structure, arrangement, etc. of the components as the following. Various modifications can be made to the embodiments of the present invention within the scope of the claims.

[0011] FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 2 is an enlarged view of the periphery X1 of the second groove 31 in FIG. 1.

[0012] As shown in FIG. 1, the semiconductor device 1 according to the embodiment includes a semiconductor substrate having an active region 101 and an inactive region 102 in the remaining region of the active region 101. The semiconductor substrate has one main surface 2a and the other main surface 2b. Here, an example in which a fast recovery diode (FRD) is disposed in the active region 101 of the semiconductor device 1 according to the embodiment will be described. Note that, in the semiconductor device 1 according to the embodiment, an RFC diode (Relaxed Field of Cathode Diode) or a reverse conducting insulated gate bipolar transistor (RC-IGBT) may be disposed in the active region 101. In the following description, a region having a breakdown voltage structure in the inactive region 102 is also referred to as a junction termination region.

[0013] As shown in FIGS. 1 and 2, the semiconductor device 1 according to the embodiment includes a first semiconductor region 2 of a first conductivity type, a second semiconductor region 21 of a second conductivity type different from the first conductivity type, a third semiconductor region 22 of the second conductivity type, a fourth semiconductor region 23 of the second conductivity type, a fifth semiconductor region 24 of the first conductivity type, a sixth semiconductor region 25 of the first conductivity type, a first trench 3, a second trench 31, and a third trench 32.

[0014] The first semiconductor region 2 is continuously disposed in common in the active region 101 and the inactive region 102.

[0015] The second semiconductor region 21 is disposed in the inactive region 102, contacts the upper surface of the first semiconductor region 2, and is partially exposed on one main surface 2a.

[0016] The third semiconductor region 22 is disposed in the inactive region 102 in contact with the second trench 31, contacts the upper surface of the first semiconductor region 2, and is partially exposed on one main surface 2a.

[0017] The fourth semiconductor region 23 is disposed in the active region 101, contacts the upper surface of the first semiconductor region 2, and is partially exposed on one main surface 2a.

[0018] The first groove 3 is disposed in the active region 101, penetrates the fourth semiconductor region 23 from one main surface 2a, and reaches the first semiconductor region 2 at the bottom surface.

[0019] The second groove 31 is disposed in the inactive region 102 in contact with the second semiconductor region 21, penetrates the second semiconductor region 21 from one main surface 2a, and reaches the first semiconductor region 2 at the bottom surface.

[0020] The third groove 32 is disposed in the inactive region 102, penetrates the third semiconductor region 22 from one main surface 2a, and reaches the first semiconductor region 2 at the bottom surface.

[0021] The fifth semiconductor region 24 is disposed in contact with the third groove 32, contacts the upper surface of the first semiconductor region 2, and is partially exposed on one main surface 2a.

[0022] The sixth semiconductor region 25 is disposed continuously in common with the active region 101 and the inactive region 102, contacts the lower surface of the first semiconductor region 2, and is exposed on the other main surface 2b.

[0023] The first conductivity type and the second conductivity type are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. Here, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplarily described. Also, in the following description, the second semiconductor region 21 of the second conductivity type is referred to as the floating p - region 21, the third semiconductor region 22 of the second conductivity type is referred to as the floating p region 22, the fourth semiconductor region 23 of the second conductivity type is referred to as the anode p - region 23, the fifth semiconductor region 24 of the first conductivity type is referred to as the channel stopper n + region 24, and the sixth semiconductor region 25 of the first conductivity type is referred to as the cathode n + region 25.

[0024] The impurity concentration of the first semiconductor region 2 is, for example, 1x10 14 cm -3 ~1x10 15 cm -3It is formed to such an extent. Note that the thickness of the first semiconductor region 2 may be about 60 to 70 μm when the breakdown voltage is 600 V, and may be about 90 to 120 μm when the breakdown voltage is 1200 V.

[0025] Floating p - As shown in FIGS. 1 and 2, the region 21 is disposed between the first groove 3 and the second groove 31. Floating p - As shown in FIG. 2, an interlayer insulating film 50 is disposed so as to cover the upper part of the region 21.

[0026] Floating p - As shown in FIG. 2, the depth D2 of the region 21 is deeper than half of the depth D1 of the second groove 31 and shallower than the depth D1 of the second groove 31.

[0027] As shown in FIGS. 1 and 2, a first insulating film 4 is provided on the side surface and the bottom surface of the first groove 3. Further, a conductor 5 is filled inside the first groove 3.

[0028] The conductor 5 may be, for example, polysilicon. The conductor 5 is electrically connected to the first main electrode 11.

[0029] As shown in FIG. 1, the first main electrode 11 is electrically connected to the anode terminal A. In the following description, the first main electrode 11 is also referred to as the anode electrode 11. As shown in FIGS. 1 and 2, the anode electrode 11 is anode p - It is formed on the interlayer insulating film 50 that extends from the region 23 across the second groove 31 to the floating p region 22 and above the third groove 32.

[0030] As shown in FIGS. 1 and 2, a second insulating film 41 is provided on the side surface and the bottom surface of the second groove 31. A first field electrode 13 and a second field electrode 14 are disposed inside the second groove 31. For example, the first field electrode 13 and the second field electrode 14 may be made of polysilicon. Further, as shown in FIG. 2, an interlayer insulating film 50 is disposed to cover the second groove 31. That is, an interlayer insulating film 50 and an anode electrode 11 thereon are disposed above the first field electrode 13 and the second field electrode 14.

[0031] As shown in FIG. 2, the first field electrode 13 is formed separated from the floating p - region 21. Further, the first field electrode 13 is formed separated from the first semiconductor region 2. That is, the first field electrode 13 is disposed in contact with the side surface and the bottom surface of the second insulating film 41. The first field electrode 13 is electrically connected to the anode electrode 11. The first field electrode 13 is electrically connected to the anode electrode 11 through a conductor 5, for example. That is, the first field electrode 13 has the same potential as the anode electrode 11. Details of the connection example will be described with reference to FIG. 4, which is a plan view.

[0032] As shown in FIG. 2, the second field electrode 14 is formed separated from the floating p region 22 and the first field electrode 13. Further, the second field electrode 14 is formed separated from the first semiconductor region 2. That is, the second field electrode 14 is disposed in contact with the side surface and the bottom surface of the second insulating film 41. That is, the second field electrode 14 is sandwiched between the second insulating film 41 and the interlayer insulating film 50, is not electrically connected to other electrodes, and has a floating potential.

[0033] floating p - The distance between the region 21 and the first field electrode 13 is the floating p - region 21 and the conductor 5. Here, as shown in FIG. 2, the floating p -The distance between the region 21 and the first field electrode 13 is substantially equal to the thickness N1 of the second insulating film 41 formed on the side surface and the bottom surface of the second groove 31. Also, the float p - The distance between the region 21 and the conductor 5 is substantially equal to the thickness N2 of the first insulating film 4 formed on the side surface and the bottom surface of the first groove 3. That is, as shown in FIG. 2, it is desirable that the thickness N1 of the second insulating film 41 formed on the side surface and the bottom surface of the second groove 31 is thicker than the thickness N2 of the first insulating film 4 formed on the side surface and the bottom surface of the first groove 3.

[0034] The pitch (L1, L2, L3, ··· Ln) between adjacent grooves in the float p region 22 corresponds to the width L1 of the adjacent second groove 31 and the third groove 32 or the widths (L2, L3, ···, Ln) of the third grooves 32 as shown in FIG. 1. Also, from the second groove 31 to the channel stopper n + As it goes toward the region 24 of the float p, the pitch (L1, L2, L3, ··· Ln) between adjacent grooves in the float p region 22 is arranged to become narrower. In the following description, the width between adjacent grooves is also referred to as the pitch between adjacent grooves.

[0035] On the upper part of the float p region 22, as shown in FIG. 2, it is arranged so as to be covered by the interlayer insulating film 50.

[0036] Anode p - The impurity concentration of the anode p region 23 is set to be lower than the impurity concentration of the float p region 22. Specifically, the anode p - The impurity concentration of the region 23 is, for example, 1x10 15 cm -3 ~1x10 17 cm -3 and is formed to that extent.

[0037] Anode p - The anode p region 23 is electrically connected at the contact region 30 between the first main electrode 11 and the active region 101. The contact region 30 is, as shown in FIG. 1, the region where the anode p - region 23 and the first groove 3 are exposed on one main surface 2a. As shown in FIG. 1, the anode p- The pitch M1 between adjacent first grooves in region 23 corresponds to the width between adjacent first grooves 3 in the active region 101.

[0038] The pitch L1 between adjacent second groove 31 and third groove 32 is the anode p - The pitch M1 between adjacent first grooves 3 in region 23 is wider than the pitch between adjacent first grooves 3 in region 23. Specifically, the pitch L1 between adjacent second groove 31 and third groove 32 is the anode p - About 50 times the pitch M1 between adjacent first grooves in region 23. For example, the anode p - The pitch M1 between adjacent first grooves in region 23 is about 4 to 5 μm. The pitch L1 between adjacent second groove 31 and third groove 32 is wider than the pitch between adjacent second groove 31 and first groove 3.

[0039] As shown in FIG. 1, a third insulating film 42 is provided on the side surface and the bottom surface of the third groove 32. Further, a conductor 52 is filled inside the third groove 32. The conductor 52 is electrically connected to the anode electrode 11 or has a floating potential.

[0040] The conductor 52 may be, for example, polysilicon. As shown in FIG. 2, an interlayer insulating film 50 is disposed so as to cover the upper portion of the conductor 52.

[0041] Cathode n + Region 25 is electrically connected to the second main electrode 12.

[0042] As shown in FIG. 1, the second main electrode 12 is electrically connected to the first cathode terminal K1. In the following description, the second main electrode 12 is also referred to as the first cathode electrode 12. The first cathode electrode 12 is the cathode n + It is disposed on the other main surface 2b where region 25 is exposed.

[0043] Channel stopper n + Region 24 is electrically connected to the third main electrode 15.

[0044] As shown in FIG. 1, the third main electrode 15 is electrically connected to the second cathode terminal K2. In the following description, the third main electrode 15 is also referred to as the second cathode electrode 15. The second cathode electrode 15 is disposed on the channel stopper n + region 24.

[0045] FIG. 3 is a schematic plan view showing the structure of the semiconductor device 1 according to the embodiment.

[0046] As shown in FIG. 3, in the active region 101a, in a plan view, the first groove 3 surrounds the anode p - region 23. Here, the anode p - region 23 is formed in a block shape as shown in FIG. 3. That is, in the extending direction of the first groove 3 (Y direction in FIG. 3), adjacent first grooves 3 are connected at a plurality of locations, and similarly, adjacent conductors 5 in the first groove 3 are connected at a plurality of locations. In the active region 101a, the pattern configuration of the first groove 3 and the anode p - region 23 may be a stripe pattern, a lattice pattern, a staggered lattice pattern, or a dot pattern in addition to the illustrated block shape. Here, the "plan view" is the normal direction of one main surface 2a, that is, the case of viewing from the vertical direction (Z direction) of the paper surface in FIG. 3. In FIG. 3, a plane perpendicular to the Z direction is defined as the XY plane, the left-right direction of the paper surface is the Y direction, and the up-down direction of the paper surface is the X direction.

[0047] Outside the active region 101a (corner side of the semiconductor device) 101b, the first groove 3 is in an arc shape, and the first groove 3 on the center side of the arc and the first groove 3 on the outside are connected at a plurality of locations, and the conductors 5 in the first groove 3 on the center side and the conductors 5 in the first groove 3 on the outside are electrically connected through the conductors provided therein. The active region 101 is disposed inside and surrounded by the second groove 31 as shown in FIG. 3. The inactive region 102 is disposed outside the second groove 31. The third groove 32 and the like of the inactive region 102 are formed so as to surround the second groove 31, but are omitted in FIG. 3.

[0048] Further, FIG. 4 is an enlarged view of the periphery X2 of the second groove 31 in FIG. 3. In FIG. 4, illustration of the anode electrode 11, the second cathode electrode 15, and the interlayer insulating film 50 is omitted. A cross-sectional view taken along the line V-V in FIG. 4 corresponds to FIG. 2. The dashed line CB in FIG. 4 represents the contact boundary.

[0049] As shown in FIG. 4, the second groove 31 is formed with connection grooves to the first groove 3 from a plurality of locations substantially uniformly in the plane, and through a conductor provided in the connection groove, the conductor 5 is electrically connected to the first field electrode 13.

[0050] FIG. 5 is a schematic diagram of the result of a potential distribution simulation when, in the semiconductor device 1 according to the embodiment of the present invention, the first field electrode 13 is set to the same potential as the anode electrode 11 and the second field electrode 14 is set to a floating potential.

[0051] That is, in FIG. 5, by setting the first field electrode 13 to the same potential as the anode electrode 11 and the second field electrode 14 to a floating potential, a field relaxation effect is obtained at the periphery P1 of the bottom surface of the first groove 3, and at the peripheries P2 and P3 of the bottom surface of the first field electrode 13. For this reason, in the embodiment, a semiconductor device with high breakdown voltage can be obtained. In FIG. 5, each line is shown at 10 V per line.

[0052] Next, FIG. 6 is a schematic diagram of the result of a potential distribution simulation when, as a first comparative example, the first field electrode 13 is set to a floating potential and the second field electrode 14 is set to a floating potential.

[0053] When the first field electrode 13 and the second field electrode 14 are set to a floating potential, the electric field lines are the float p -It rises upward within the region 21, and the electric field is concentrated in the electric field P3 near the bottom surface of the first groove 3. Therefore, there is a possibility of breakdown voltage degradation or degradation of the first insulating film 4 formed in the first groove 3. In the following description, the concentration of the electric field may also be referred to as electric field concentration.

[0054] Next, FIG. 7 is a schematic diagram of the potential distribution simulation result when the first field electrode 13 is set to the same potential as the anode electrode 11 and the second field electrode 14 is set to the same potential as the anode electrode 11 as a second comparative example.

[0055] When the first field electrode 13 and the second field electrode 14 are set to the same potential as the anode electrode 11, the electric field is concentrated in the oxide film periphery P4 on the bottom surface and the side surface of the second field electrode 14. Therefore, there is a possibility of breakdown voltage degradation or degradation of the second insulating film 41 formed in the second groove 31.

[0056] As described above, in the semiconductor device 1 according to the embodiment, by setting the first field electrode 13 disposed inside the second groove 31 to the same potential as the anode electrode 11 and the second field electrode 14 to a floating potential, it is possible to suppress the entry of electric lines of force into the second semiconductor region 21 provided between the second groove 31 and the first groove 3 adjacent to the second groove 31, and the electric lines of force can be made flatter. Therefore, the electric field in the junction termination region can be relaxed, and a high breakdown voltage can be achieved. In order to make the electric lines of force flatter, it is desirable that the second groove 31 be formed wider than the first groove 3.

[0057] Also, by setting the second field electrode 14 to a floating potential, some of the electric lines of force enter the second groove 31, thereby relaxing the electric field concentration around the corner portion on the second field electrode 14 side at the bottom of the second groove 31.

[0058] A float p - region 21 is disposed, and the float p -By arranging the depth D2 of the region 21 to be deeper than half of the depth D1 of the second groove 31 and shallower than the depth D1 of the second groove 31, the float p - In the region 21, some of the electric lines of force do not extend in the direction of one main surface 2a (the float p - Some of the electric lines of force in the region 21 do not rise upward), so the influence on the breakdown voltage reduction can be reduced.

[0059] float p - By setting the region 21 to a floating potential, the electric field concentration near the bottom of the first groove 3 and the second groove 31 can be alleviated, making it difficult for the electric lines of force to reach the anode electrode 11 and improving the breakdown voltage.

[0060] By making the thickness N1 of the second insulating film 41 thicker than the thickness N2 of the first insulating film 4, the leakage current around the bottom surface of the second groove 31 can be reduced.

[0061] (Other embodiments) As described above, although the present invention has been described by way of embodiments, it should not be understood that the descriptions and drawings forming a part of this disclosure limit the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0062] Thus, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specific matters according to the reasonable claims based on the above description.

Explanation of reference numerals

[0063] 1... Semiconductor device 2... First semiconductor region 3... First groove 4... First insulating film 5... Conductor 11... First main electrode, anode electrode 12... Second main electrode, first cathode electrode 13... First field electrode 14…Second Field Electrode 15…Third Main Electrode, Second Cathode Electrode 21…Second Semiconductor Region, Floating p - Region 22…Third Semiconductor Region, Floating p Region 23…Fourth Semiconductor Region, Anode p - Region 24…Fifth Semiconductor Region, Channel Stopper n + Region 25…Sixth Semiconductor Region, Cathode n + Region 30…Contact Region 31…Second Groove 32…Third Groove 41…Second Insulating Film 42…Third Insulating Film 50…Interlayer Insulating Film 52…Conductor 101…Active Region 102…Inactive Region 2a…One Main Surface 2b…The Other Main Surface A…Anode Terminal K1…First Cathode Terminal K2…Second Cathode Terminal N1…Thickness of the Second Insulating Film N2…Thickness of the First Insulating Film

Claims

1. A first semiconductor region of a first conductivity type having an active region and an inactive region, a first groove provided to reach the first semiconductor region in the active region, a first insulating film formed in the first groove, a conductor provided inside the first groove, a second groove provided to reach the first semiconductor region in the inactive region, a second insulating film formed in the second groove, a third groove provided in the inactive region, separated from the second groove, and provided to reach the first semiconductor region, a second semiconductor region of a second conductivity type provided on the first semiconductor region between the first groove and the second groove, a third semiconductor region of a second conductivity type provided on the first semiconductor region between the second groove and the third groove, a first field electrode disposed on the second insulating film of the second groove, separated from the second semiconductor region, and a second field electrode disposed on the second insulating film of the second groove, separated from the third semiconductor region, wherein the first field electrode is electrically connected to a first main electrode, the second field electrode is electrically floating, and the second semiconductor region is electrically floating. A semiconductor device.

2. A first semiconductor region of a first conductivity type having an active region and an inactive region, a first groove provided to reach the first semiconductor region in the active region, a first insulating film formed in the first groove, a conductor provided inside the first groove, a second groove provided to reach the first semiconductor region in the inactive region, a second insulating film formed in the second groove, A third groove that is separated from the second groove in the inactive region and is provided so as to reach the first semiconductor region. A second semiconductor region of a second conductivity type provided on the first semiconductor region between the first groove and the second groove. A third semiconductor region of a second conductivity type provided on the first semiconductor region between the second groove and the third groove. A first field electrode disposed on the second insulating film of the second groove and separated from the second semiconductor region. A semiconductor device comprising a second field electrode disposed on the second insulating film of the second groove and separated from the third semiconductor region. The first field electrode is electrically connected to the first main electrode, and the second field electrode is electrically floating. A semiconductor device in which the distance between the second semiconductor region and the first field electrode is greater than the distance between the second semiconductor region and the conductor.

3. The semiconductor device according to claim 2, wherein the second semiconductor region is electrically floating.

4. Furthermore, a fourth semiconductor region of a second conductivity type disposed on the first semiconductor region of the active region is provided. The semiconductor device according to any one of claims 1 to 3, wherein the impurity concentration of the fourth semiconductor region is lower than the impurity concentration of the third semiconductor region.

5. The semiconductor device according to any one of claims 1 to 4, wherein the pitch between the second groove and the third groove is wider than the pitch between the first grooves.

6. The semiconductor device according to any one of claims 1 to 5, wherein the depth of the second semiconductor region is deeper than half of the depth of the second groove and shallower than the depth of the second groove.

7. The semiconductor device according to any one of claims 1 to 6, wherein the thickness of the first insulating film is thinner than the thickness of the second insulating film.

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