Light emitting diode device having a defined hard mask opening

Abstract

A light emitting diode (LED) device is described, the LED device comprising: a plurality of mesas defining pixels, each mesa including a semiconductor layer; an N-contact material in a space between each of the plurality of mesas, and a dielectric material insulating a P-type layer and sidewalls of an active region from metal; a hard mask layer over the semiconductor layer, the hard mask layer having a plurality of openings, each opening being partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; a passivation film over the hard mask layer, the passivation film having a plurality of passivation film openings defining a width, the width of each passivation film opening being less than the width of the P-metal material plug and the liner layer combined.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to light emitting diode (LED) devices and methods of manufacturing the same. More specifically, the embodiments are directed to light emitting diode devices comprising a multilayer composite film including an opening defined in a hard mask layer.

Background Art

[0002] A light emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. An LED is a combination of a P-type semiconductor and an N-type semiconductor. LEDs generally use III-V compound semiconductors. III-V compound semiconductors operate stably at higher temperatures than devices using other semiconductors. III-V compounds are usually formed on a substrate made of sapphire aluminum oxide (Al2O3) or silicon carbide (SiC).

[0003] In various emerging display applications such as wearable devices, head-mounted displays, and large-area displays, there is a need for small chips composed of an array of high-density micro light-emitting diodes (μLEDs or uLEDs) with a lateral dimension of less than 100 μm × 100 μm. Micro light-emitting diodes (uLEDs) typically have dimensions with a diameter or width smaller than about 50 μm, and micro light-emitting diodes including red, blue, and green wavelengths are arranged in proximity to be used in the manufacture of color displays. Generally, two approaches have been utilized to assemble displays constructed from individual micro LED dies. The first is the pick-and-place approach, where individual micro LEDs of blue, green, and red wavelengths are picked up, aligned, and attached to a backplane, and then the backplane is electrically connected to a driver integrated circuit. Due to the small size of each micro LED, this assembly sequence is slow and susceptible to manufacturing errors. Furthermore, as the die size decreases to meet the high-resolution requirements of the display, more and more dies need to be transferred in each pick-and-place operation to arrange a display of the required dimensions. The second approach is to bond a group of LEDs, such as a monolithic die or an array or a matrix, to the backplane, which eliminates the handling of individual LEDs associated with pick-and-place. Therefore, it is necessary to develop a method for efficiently preparing a group of LEDs that may be used subsequently for bonding to the LED backplane.

Summary of the Invention

[0004] Embodiments of the present disclosure are directed to light-emitting diode (LED) devices, where the LED devices include a plurality of mesas defining pixels, each of the mesas including a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each of the mesas having a height less than its width; a plurality of mesas N-contact material within the space between each mesa, providing optical separation between each of the mesas and electrically contacting the N-type layer of each of the mesas along the sidewalls of the N-type layer; N-contact material A dielectric material that insulates the sidewalls of the P-type layer and the active region from the N-contact material; A hard mask layer above the semiconductor layer, the hard mask layer having a plurality of openings therein, each of the plurality of openings being partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width, the hard mask layer; A passivation film on the hard mask layer, the passivation film having a plurality of passivation film openings defining a width, the width of each passivation film opening being less than the width of the combination of the P-metal material plug and the liner layer, the passivation film; comprising.

[0005] Embodiments of the present disclosure are directed to light-emitting diode (LED) devices, the LED devices comprising: A plurality of mesas defining pixels, each mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each mesa having a height less than its width, the plurality of mesas; Metal within the space between each of the mesas, the metal providing optical isolation between each mesa and making electrical contact with the N-type layer of each mesa along the sidewall of the N-type layer; A dielectric material that insulates the sidewalls of the P-type layer and the active region from the metal; A current diffusion layer on the P-type layer, the current diffusion layer having a first portion and a second portion; A P-contact layer on the first portion of the current diffusion layer; A dielectric layer on the second portion of the current diffusion layer; A guard layer covering the P-contact layer; A hard mask layer on a first section of the guard layer above a second section of the current diffusion layer, the hard mask layer having an opening, the opening being partially filled with a liner layer and partially filled with a P-metal material plug, the hard mask layer; A combination of a P-metal material plug having a width and a liner layer; A passivation film on a hard mask layer, the passivation film having a passivation film opening defining a width, the width of the passivation film opening being less than the width of a combination of a P-metal material plug and a liner layer, the passivation film covering a part of the P-metal material plug and the surface of the liner layer, the passivation film and, comprising.

[0006] Further embodiments are directed to a method of manufacturing a light emitting diode device (LED device), the method comprising: Depositing a plurality of semiconductor layers having an N-type layer, an active region and a P-type layer on a substrate; Depositing a hard mask layer over the P-type layer; Etching the hard mask layer and a part of the semiconductor layer to form a plurality of mesas and trenches defining pixels, each of the plurality of mesas having a semiconductor layer, each of the mesas having a height less than its width; Depositing a dielectric material in the trenches; Forming an opening in the hard mask layer and etching the semiconductor layer to expose the surface of the substrate and the sidewalls of the N-type layer; Depositing a liner layer on the substrate including on the surface of the substrate, the N-type layer, the dielectric material, and the opening in the hard mask layer; Depositing an electrode metal on the liner layer; Planarizing the substrate to form a P-metal material plug on the liner layer within the opening of the hard mask layer and an N-contact material that electrically contacts the N-type layer of each mesa along the sidewalls of the N-type layer, the combination of the liner layer and the P-metal material within the opening of the hard mask layer having a width; Forming a passivation layer on the substrate and forming an opening in the passivation layer defining a width, the width of each opening film opening in the passivation layer being less than the width of a combination of a P-metal material plug and a liner layer, and.

Brief Description of the Drawings

[0007] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the disclosure briefly summarized above can be obtained by referring to some embodiments illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure and, therefore, are not considered to limit the scope thereof, as the present disclosure may admit other equally effective embodiments. The embodiments described herein are shown by way of example and not limitation in the figures of the accompanying drawings, and like references indicate like elements.

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[0008] For ease of understanding, the same reference numbers are used, if possible, to indicate the same elements common to the drawings. The drawings are not drawn to scale. For example, the height and width of the mesa are not drawn to scale.

DETAILED DESCRIPTION OF THE INVENTION

[0009] Before describing some exemplary embodiments of the disclosure, it should be understood that the disclosure is not limited to the details of the structures or process steps described in the following description. The methods and apparatuses are realizable in other embodiments, practicable, or executable in various ways.

[0010] According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process acts. Further, references to a substrate in some embodiments may, unless the context clearly indicates otherwise, refer to only a portion of the substrate. Further, references to deposition on a substrate according to some embodiments include deposition on a bare substrate or on a substrate on which one or more films, features or materials have been deposited or formed thereon.

[0011] In one or more embodiments, "substrate" means any substrate or the surface of a material formed on a substrate on which film processing is performed during the manufacturing process. In an exemplary embodiment, the substrate surface to be processed may include, depending on the application, silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and other suitable materials such as metals, metal nitrides, group III nitrides (e.g., GaN, AlN, InN, alloys), metal alloys, and other conductive materials. The substrate includes, but is not limited to, light-emitting diode (LED) devices. The substrate in some embodiments is exposed to a pretreatment process of polishing, etching, reducing, oxidizing, hydroxiding, annealing, UV curing, electron beam curing, and / or firing the substrate surface. In addition to performing the film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0012] The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, as used herein, a wafer functions as a substrate for the formation of the LED devices described herein.

[0013] A micro-LED (uLED) refers to a light-emitting diode having one or more characteristic dimensions (e.g., dimensions such as height, width, depth, thickness, etc.) of less than 100 micrometers. In one or more embodiments, one or more of the dimensions of height, width, depth, and thickness have values in the range of 2 to 25 micrometers.

[0014] FIG. 1A is a cross-sectional view of a stack of a semiconductor layer, a metal layer (e.g., a p-contact layer), and a dielectric layer (e.g., a hard mask layer) deposited on a substrate during steps of manufacturing an LED device according to one or more embodiments. Referring to FIG. 1A, a semiconductor layer 104 is growing on a substrate 102. The semiconductor layer 104 according to one or more embodiments includes an epitaxial layer, a group III nitride layer, or an epitaxial group III nitride layer.

[0015] The substrate may be any substrate known to those skilled in the art. In one or more embodiments, the substrate includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate is not patterned prior to the growth of the (one or more) epitaxial layers. Thus, in some embodiments, the substrate can be considered unpatterned, flat, or substantially flat. In other embodiments, the substrate can be patterned, for example, a patterned sapphire substrate (PSS).

[0016] In one or more embodiments, the semiconductor layer 104 comprises a group III nitride material, and in certain embodiments, an epitaxial group III nitride material. In some embodiments, the group III nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layer 104 consists of one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), and the like. In one or more specific embodiments, the semiconductor layer 104 comprises a p-type layer, an active region, and an n-type layer. In one or more embodiments, the semiconductor layer 104 comprises a group III nitride material, and in certain embodiments, an epitaxial group III nitride material. In some embodiments, the group III nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layer 104 consists of one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), and the like. In one or more specific embodiments, the semiconductor layer 104 comprises a p-type layer, an active region, and an n-type layer.

[0017] In one or more embodiments, the substrate 102 is placed in a metalorganic vapor phase epitaxy (MOVPE) reactor, and an LED device layer is epitaxially grown to form the semiconductor layer 104.

[0018] In one or more embodiments, the semiconductor layer 104 comprises a stack of an undoped group III nitride material and a doped group III nitride material. The group III nitride material can be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg) depending on whether a p-type or n-type group III nitride material is required. In a particular embodiment, the semiconductor layer 104 comprises an N-type layer 104n, an active region 106, and a P-type layer 104p.

[0019] In one or more embodiments, the semiconductor layer 104 has a combined thickness in the range of about 2 μm to about 10 μm, the range including about 2 μm to about 9 μm, 2 μm to about 8 μm, 2 μm to about 7 μm, 2 μm to about 6 μm, 2 μm to about 5 μm, 2 μm to about 4 μm, 2 μm to about 3 μm, 3 μm to about 10 μm, 3 μm to about 9 μm, 3 μm to about 8 μm, 3 μm to about 7 μm, 3 μm to about 6 μm, 3 μm to about 5 μm, 3 μm to about 4 μm, 4 μm to about 10 μm, 4 μm to about 9 μm, 4 μm to about 8 μm, 4 μm to about 7 μm, 4 μm to about 6 μm, 4 μm to about 5 μm, 5 μm to about 10 μm, 5 μm to about 9 μm, 5 μm to about 8 μm, 5 μm to about 7 μm, 5 μm to about 6 μm, 6 μm to about 10 μm, 6 μm to about 9 μm, 6 μm to about 8 μm, 6 μm to about 7 μm, 7 μm to about 10 μm, 7 μm to about 9 μm, or 7 μm to about 8 μm.

[0020] In one or more embodiments, the active region 106 is formed between the n-type layer 104n and the p-type layer 104p. The active region 106 can be composed of any suitable material known to those skilled in the art. In one or more embodiments, the active region 106 is composed of a multiple quantum well (MQW) of a group III nitride material and a group III nitride electron blocking layer.

[0021] In one or more embodiments, the P contact layer 105 and the hard mask layer 108 are deposited on the p-type layer 104p. As shown in the figure, the P contact layer is deposited on the p-type layer 104p, and the hard mask layer 108 is on the P contact layer. In some embodiments, the P contact layer 105 is deposited directly on the p-type layer 104p. In other embodiments, although not shown, one or more additional layers may be present between the p-type layer 104p and the P contact layer 105. In some embodiments, the hard mask layer 108 is deposited directly on the P contact layer 105. In other embodiments, although not shown, one or more additional layers may be present between the hard mask layer 108 and the P contact layer 105. The hard mask layer 108 and the P contact layer 105 can be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the hard mask layer 108 and the P contact layer 105 are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0022] As used herein, "sputter deposition" refers to the physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material such as a metal is emitted from a target, which is the source, onto a substrate. This technique is based on ion bombardment of the target, which is the source material. The ion bombardment is a purely physical process, i.e., the sputtering of the target material into vapor.

[0023] When used in accordance with some embodiments of this specification, "atomic layer deposition" (ALD) or "cyclical deposition" refers to a vapor-phase technique used to deposit a thin film on a substrate surface. The process of ALD involves exposing the surface of the substrate or a portion of the substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to the alternating precursors, those precursors are introduced sequentially or simultaneously. Those precursors are introduced into the reaction zone of the processing chamber, and the substrate or a portion of the substrate is separately exposed to those precursors.

[0024] In some embodiments, as used herein, "chemical vapor deposition" (CVD) refers to a process in which a film of material is deposited from the gas phase by decomposition of a chemical substance on the surface of a substrate. In CVD, the surface of the substrate is exposed to the precursor and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either a co-flow or a location where most of the exposure of the precursors overlaps.

[0025] As used herein in some embodiments, "plasma enhanced atomic layer deposition" (PEALD) refers to a technique for depositing a thin film on a substrate. In some examples of the PEALD process compared to the thermal ALD process, the material can be formed from the same chemical precursors, but at a higher deposition rate and at a lower temperature. The PEALD process generally involves sequentially introducing a reaction gas and a reaction plasma into a process chamber having a substrate therein. The first reaction gas is pulsed in the process chamber and adsorbed on the substrate surface. Thereafter, the reaction plasma is pulsed into the process chamber and reacts with the first reaction gas to form a deposited material, such as a thin film, on the substrate. Similar to the thermal ALD process, a purge step can be performed during the delivery of each reactant.

[0026] As used herein in one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing a thin film on a substrate. In the PECVD process, a source material that is in the gas phase or liquid phase, such as the vapor of a liquid phase group III nitride material incorporated in a carrier gas or a gas phase group III nitride material, is introduced into the PECVD chamber. A plasma ignition gas is also introduced into the chamber. When plasma is generated in the chamber, excited radicals are generated. The excited radicals chemically bond to the surface of the substrate disposed in the chamber and form a desired film thereon.

[0027] In one or more embodiments, the hard mask layer 108 can be fabricated using materials and patterning techniques known in the art. In some embodiments, the hard mask layer 108 includes a metal or a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that using a formula such as SiO to represent silicon oxide does not imply a specific stoichiometric relationship between the elements. The formula simply identifies the basic constituents of the film.

[0028] In one or more embodiments, the P contact layer 105 can include any suitable metal known to those skilled in the art. In one or more embodiments, the P contact layer 105 includes silver (Ag).

[0029] FIG. 1B is a cross-sectional view of the stack after one step in the manufacturing stage of the LED device 100 according to one or more embodiments. Referring to FIG. 1B, the hard mask layer 108 and the P contact layer 105 are patterned to form at least one opening 110 in the hard mask layer 108 and the P contact layer 105, exposing the top surface 104t of the semiconductor layer 104 and the sidewalls 108s, 105s of the hard mask layer 108 and the P contact layer 105, respectively.

[0030] In one or more embodiments, the hard mask layer 108 and the P-contact layer 105 are patterned by suitable patterning techniques known to those skilled in the art. In one or more embodiments, the hard mask layer 108 and the P-contact layer 105 are patterned by etching. According to one or more embodiments, conventional masking, wet etching and / or dry etching processes can be used to pattern the hard mask layer 108 and the P-contact layer 105.

[0031] In other embodiments, nanoimprint lithography is used to transfer the pattern to the hard mask layer 108 and the P-contact layer 105. In one or more embodiments, the substrate 102 is etched in a reactive ion etching (RIE) tool using conditions that effectively etch the hard mask layer 108 and the P-contact layer 105 but very slowly or not at all etch the p-type layer 104p. In other words, the etching is selective to the P-contact layer 105 and the hard mask layer 108 over the p-type layer 104p. It is understood that masking techniques can be used in the patterning step to achieve the desired pattern.

[0032] FIG. 1C is a cross-sectional view of the stack after one step in the manufacturing stage of the LED device 100 according to one or more embodiments. Referring to FIG. 1C, an inner spacer 112 is deposited on the top surface 104t of the semiconductor layer 104 and on the sidewalls 108s, 105s of the hard mask layer 108 and the P-contact layer 105. The inner spacer 112 can comprise any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer 112 comprises a dielectric material. Deposition of the material forming the inner spacer is typically performed conformally with respect to the substrate surface, followed by etching to obtain the inner spacer on the sidewalls 108s, 105s rather than on the top surface 104b of the semiconductor layer 104.

[0033] As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the inner spacer 112 includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides such as silicon nitride (Si3N4), etc. In one or more embodiments, the dielectric inner spacer 112 includes silicon nitride (Si3N4). In other embodiments, the inner spacer 112 includes silicon oxide (SiO2). In some embodiments, the inner spacer 112 composition is non-stoichiometric with respect to the ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxynitrides (e.g., silicon oxynitride (SiON)), oxicarbides (e.g., silicon oxycarbide (SiOC)), and oxynitrocarbides (e.g., silicon oxynitrocarbide (SiNCO)).

[0034] In some embodiments, the inner spacer 112 can be a distributed Bragg reflector (DBR). As used herein, "distributed Bragg reflector" refers to a structure (e.g., a mirror) formed from an alternating thin film material with a change in refractive index, such as a multi-layer stack of high and low refractive indices.

[0035] In one or more embodiments, the inner spacer 112 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0036] In one or more embodiments, the inner spacer 112 has a thickness in the range of about 200 nm to about 1 μm, such as about 300 nm to about 1 μm, about 400 nm to about 1 μm, about 500 nm to about 1 μm, about 600 nm to about 1 μm, about 700 nm to about 1 μm, about 800 nm to about 1 μm, about 900 nm to about 1 μm, about 200 nm to about 900 nm, about 300 nm to about 900 nm, about 400 nm to about 900 nm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 200 nm to about 800 nm, about 300 nm to about 800 nm, about 400 nm to about 800 nm, about 500 nm to about 800 nm, about 600 nm to about 800 nm, about 700 nm to about 800 nm, about 200 nm to about 700 nm, about 300 nm to about 700 nm, about 400 nm to about 700 nm, about 500 nm to about 700 nm, about 600 nm to about 700 nm, about 200 nm to about 600 nm, about 300 nm to about 600 nm, about 400 nm to about 600 nm, about 500 nm to about 600 nm, about 200 nm to about 500 nm, about 300 nm to about 500 nm, about 300 nm to about 400 nm, about 200 nm to about 400 nm, or about 300 nm to about 400 nm.

[0037] FIG. 1D is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to FIG. 1D, the semiconductor layer 104 is etched to form at least one mesa, such as a first mesa 150a and a second mesa 150b. In the embodiment shown in FIG. 1D, the first mesa 150a and the second mesa 150b are separated by a trench 111 referred to as trench 111. Each trench 111 has sidewalls 113.

[0038] Figure 1E is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1E, an outer spacer 114 is deposited on sidewall 113 of trench 111. The outer spacer 114 can be composed of any suitable material known to those skilled in the art. In one or more embodiments, the outer spacer 114 includes a dielectric material. As will be described below with reference to Figure 1I, the dielectric material insulates the sidewalls of the P-type layer 104p (sidewall 104s) and the sidewalls of the active region 106 (sidewall 106s) from the metal deposited in the trench 111. Deposition of the material forming the outer spacer is typically performed conformally with respect to the substrate surface and is then etched to obtain the outer spacer on the sidewalls of the trench rather than on the sides of the trench or the top of the hard mask layer.

[0039] In one or more embodiments, the outer spacer 114 can include oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides such as silicon nitride (Si3N4), etc. In one or more embodiments, the outer spacer 114 includes silicon nitride (Si3N4). In other embodiments, the outer spacer 114 includes silicon oxide (SiO2). In some embodiments, the outer spacer 114 can be a distributed Bragg reflector (DBR).

[0040] In one or more embodiments, the outer spacer 114 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD).

[0041] Figure 1N is an enlarged view showing a part of the stack of Figure 1E indicated by the dotted line edge 1N in Figure 1E.

[0042] In one or more embodiments, as shown in FIGS. 1B, 1E, and 1N, a dark space or dark space gap 117 is formed between adjacent edges 105e of the P contact layer 105 on the first mesa 150a and the second mesa 150b. In one or more embodiments, the dark space gap 117 formed between adjacent edges 105e of the P contact layer 105 on the first mesa 150a and the second mesa 150b is in the range of 10 μm to 0.5 μm, or in the range of 9 μm to 0.5 μm, or in the range of 8 μm to 0.5 μm, or in the range of 7 μm to 0.5 μm, or in the range of 6 μm to 0.5 μm, or in the range of 5 μm to 0.5 μm, or in the range of 4 μm to 0.5 μm, or in the range of 3 μm to 0.5 μm. In other embodiments, the dark space gap 117 formed between adjacent edges 105e of the P contact layer 105 on the first mesa 150a and the second mesa 150b is in the range of 10 μm to 4 μm, for example, in the range of 8 μm to 4 μm. In embodiments of the LED device 100, each of the plurality of spaced-apart mesas 150a, 150b includes a conductive and reflective P contact layer 105 that extends across portions of each of the plurality of mesas 150a, 150 and includes the edges 105e, and trenches 11 between each of the plurality of spaced-apart mesas, resulting in a pixel pitch in the range including 1 μm to 100 μm, 40 μm to 100 μm, 41 μm to 100 μm, and all values and sub-ranges therebetween, and a dark space gap 117 between adjacent edges of the P contact layer that is less than 20% of the pixel pitch. In some embodiments, the pixel pitch is in the range of 5 μm to 100 μm, 10 μm to 100 μm, or 15 μm to 100 μm. In some embodiments, when the pixel pitch is in the range of 10 μm to 100 μm, the dark space gap 117 between adjacent edges of the P contact layer exceeds 1% of the pixel pitch and is less than 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, or 5% of the pixel pitch.

[0043] In one or more embodiments, each of the spaced-apart mesas 150a, 150b includes sidewalls 104s, and each sidewall has a first segment 104s1 and a second segment 104s2 (shown in FIG. 1M). The first segment 104s1 defines an angle "a" (as shown in FIG. 1N) in the range of 60 degrees to 90 degrees from a horizontal plane 129 parallel to the N-type layer 104n and the P-type layer 104p. In some embodiments, the angle "a" is in the range of 60 degrees to 85 degrees, 60 degrees to 80 degrees, 60 degrees to 75 degrees, 60 degrees to 70 degrees, 65 degrees to 90 degrees, 65 degrees to 85 degrees, 65 degrees to 80 degrees, 65 degrees to 75 degrees, 65 degrees to 70 degrees, 70 degrees to 90 degrees, 70 degrees to 85 degrees, 70 degrees to 80 degrees, 70 degrees to 75 degrees, 75 degrees to 90 degrees, 75 degrees to 85 degrees, 75 degrees to 80 degrees, 80 degrees to 90 degrees, or 80 degrees to 85 degrees. In one or more embodiments, the second segment 104s2 of the sidewall forms an angle in the range of 75° to less than 90° with the top surface of the substrate on which the mesa is formed.

[0044] FIG. 1F is a cross-sectional view of a stack after one step in the manufacturing stage of an LED device 100 according to one or more embodiments. Referring to FIG. 1F, the semiconductor layer 104 is etched to expand the trench 111 (i.e., increase the depth of the trench) to expose the top surface 102t of the substrate 102. In one or more embodiments, the etching is selective, and thus the outer spacer 114 remains on the sidewalls of the trench 111. In one or more embodiments, the trench 111 has a bottom 111b and sidewalls 113. In one or more embodiments, the trench 111 has a depth in the range of about 0.5 μm to about 2 μm from the top surface 104t of the semiconductor layer forming the mesa.

[0045] Figure 1G is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1G, the first mesa 150a and the second mesa 150b are patterned, via openings 116 are formed in the top surfaces of the mesas, and the top surface of the semiconductor layer 104 and / or the top surface of the P-contact layer 105 are exposed. In one or more embodiments, the first mesa 150a and the second mesa 150b can be patterned by any suitable technique known to those skilled in the art, such as masking and etching processes used in semiconductor processing.

[0046] Figure 1H is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1H, the reflective liner 130 is deposited on the substrate, along the sidewalls 113 and the bottom 111b of the trench 111, on the sidewalls of the outer spacer 114, and on the surface of the hard mask layer 108 and the top surface of the semiconductor layer 104 and / or the top surface of the P-contact layer 105. The reflective liner 130 can be composed of any suitable material known to those skilled in the art. In one or more examples, the reflective liner 130 is composed of aluminum (Al).

[0047] In one or more embodiments, the reflective liner 130 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, the deposition of the reflective liner 130 is selective, and thus the reflective liner 130 is deposited only on the sidewalls 113 of the trench 111 and the sidewalls of the outer spacer 114.

[0048] Figure 1I is a cross-sectional view of a stack after one step in the manufacturing process of an LED device according to one or more embodiments. Referring to Figure 1I, for example, an electrode metal 118 for obtaining an N contact material 118n and / or a P metal material plug 118p and / or a conductive metal 118c in a final product is deposited on a substrate and includes the tops of mesas 150a, 150b, via openings 116, and trenches 111. The electrode metal 118 can include any suitable material known to those skilled in the art. In one or more embodiments, the electrode metal 118 includes copper, and the electrode metal material 118 is deposited by electrochemical deposition (ECD) of copper.

[0049] Figure 1J is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1J, the electrode metal 118 is planarized, etched, or polished. An N contact material 118n and a P metal material plug 118p are obtained from the electrode metal 118. The term "planarized" as used herein refers to a process of smoothing a surface and includes, but is not limited to, chemical mechanical polishing / planarization (CMP), etching, etc.

[0050] Figure 1K is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1K, a passivation layer 120 is deposited on a substrate. In some embodiments, the passivation layer 120 is deposited directly on the planarized N-contact material 118n, the planarized P-metal material plug 118p, the top surface of the inner spacer 112, the top surface of the outer spacer 114, and the top surface of the hard mask layer 108. In other embodiments, one or more additional layers can be present between the passivation layer 120 and the planarized N-contact material 118n, the planarized P-metal material plug 118p, the top surface of the inner spacer 112, the top surface of the outer spacer 114, and the top surface of the hard mask layer 108. In some embodiments, the passivation material includes the same material as the hard mask layer 108. In other embodiments, the passivation layer 120 includes a material different from the hard mask layer 108.

[0051] In one or more embodiments, the passivation layer 120 can be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the passivation layer 120 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0052] In one or more embodiments, the passivation layer 120 can include any suitable material known to those skilled in the art. In one or more embodiments, the passivation layer 120 includes a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof.

[0053] Figure 1L is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1L, the passivation layer 120 is patterned to form at least one opening 122, exposing the top surface of the P-metal material plug 118p. Two openings 122 are shown. The passivation layer 120 can be patterned using any suitable technique known to those skilled in the art, including but not limited to lithography, wet etching, or dry etching.

[0054] Figure 1M is a cross-sectional view of a stack after one step in the manufacturing process of an LED device 100 according to one or more embodiments. Referring to Figure 1M, the under-bump metallization (UBM) material forms an under-bump metallization (UBM) layer 124a, which is deposited within the opening 122. As used herein, "under-bump metallization (UBM)" refers to the metal layers necessary to connect a die to a substrate having solder bumps for a flip-chip package. In one or more embodiments, the UBM layer 124a can be a thin film stack of patterned material that provides an electrical connection from the die to the solder bump, provides a barrier function to limit unwanted diffusion from the bump to the die, and provides a mechanical interconnection of the solder bump to the die through adhesion to the die passivation and attachment to the solder bump pad. The UBM layer 124a can include any suitable metal known to those skilled in the art. In one or more embodiments, the UBM layer 124a can include gold (Au).

[0055] In one or more embodiments, the under-bump metallization (UBM) can be achieved by any technique known to those skilled in the art, including but not limited to dry vacuum sputtering combined with electroplating. In one or more embodiments, the dry vacuum sputtering combined with electroplating consists of a multi-metal layer sputtered in a high-temperature vapor phase system.

[0056] In FIG. 1M, the UBM layer 124a is patterned (e.g., by masking and etching). The UBM layer 124a can be patterned using any suitable techniques known to those skilled in the art, including but not limited to lithography, wet etching, or dry etching. The patterning of the UBM layer 124a provides anode pads that contact the P-metal material plug 118p across the P-contact layer 105 in the first mesa 150a and the second mesa 150b.

[0057] FIG. 1O is a cross-sectional view of a completed LED device according to one or more embodiments. Referring to FIG. 1O, the completed LED device 100 includes the features shown in FIG. 1M and further includes a common electrode (common cathode) 140 formed at the end of the device 100 as seen in cross-section. In the first mesa 150a and the second mesa 150b, the UBM material is patterned to provide anode pads 124a that contact the P-metal material plug 118p across the P-contact layer 105. The common cathode 140 includes a conductive metal 118c. Also, the under bump metallization (UBM) material provides cathode pads 124c that contact the common cathode 140 and are patterned in the same manner as the UBM layer 124a. In one or more embodiments, the plurality of spaced mesas 150a, 150b define a matrix of pixels, and the matrix of pixels is surrounded by the common electrode 140.

[0058] In one or more embodiments, the common electrode 140 is a pixelated common cathode that includes a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stack includes a semiconductor layer 104, which, according to one or more embodiments, includes an epitaxial layer, a group III nitride layer, or an epitaxial group III nitride layer. In certain embodiments, one or more of the semiconductor layers include GaN.

[0059] To fabricate the pixelated common electrode, the process proceeds according to FIGS. 1A through 1F. At this point, instead of providing the via opening 116 as shown in FIG. 1G, a portion of the mesa is etched to expose the top surface of the semiconductor layer. Referring to FIG. 5A, the third mesa 150c and the fourth mesa 150d are etched to expose the top surface 104t of the semiconductor layer 104, and semiconductor stacks 151c and 151d are respectively formed. That is, the inner spacers 112, hard mask layer 108, and P contact layer 105 on the third mesa 150c and the fourth mesa 150d are removed. The sidewalls of the third mesa 150c and the fourth mesa 150d are exposed by etching the outer spacers 114. Thereafter, the processing of the third mesa 150c and the fourth mesa 150d proceeds as follows: FIG. 1H Add the reflective liner layer 130, FIG. 1I Deposit the electrode material 118, FIGS. 1J-1M Form the pixelated common cathode as shown in FIG. 5B.

[0060] In the embodiment of FIG. 5B, the completed LED device 101 comprises the features shown in FIG. 5A and is then processed according to FIGS. 1H-1M and includes a common electrode (common cathode) 141 formed at the end of the device 101 as seen in cross-section in FIG. 1M. The UBM material is patterned to provide an anode pad 124a that contacts the P-metal material plug 118p across the P contact layer 105 in the first mesa 150a and the second mesa 150b. The third mesa 150c and the fourth mesa 150d respectively define or form semiconductor stacks 151c and 151d surrounded by the conductive metal 118c. The semiconductor stacks 151c and 151d are inactive in that they do not generate light. Also, the under bump metallization (UBM) material provides a cathode pad 124c patterned similarly to the UBM layer 124a that contacts the common cathode 141.

[0061] FIG. 2 shows a plan view of an LED monolithic array 200 including a plurality of pixels 155 (155a and 155b among them are examples) defined or formed by a plurality of spaced mesas as described herein with respect to FIGS. 1A - 1O. For example, the first mesa 150a defines or forms the first pixel 155a, and the second mesa 150b defines or forms the second pixel 155b. The third mesa 150c and the fourth mesa 150d form or provide inactive pixels or semiconductor stacks 151c and 151d. The pixels 155 are arranged in a grid and are connected by a common cathode 140. In one or more embodiments, the array of spaced mesas includes an array of mesas in two directions. For example, the array can include an arrangement of 2×2 mesas, 4×4 mesas, 20×20 mesas, 50×50 mesas, 100×100 mesas, or n1×n2 mesas, where each of n1 and n2 is a number in the range of 2 to 1000, and n1 and n2 can be equal or not equal.

[0062] One or more embodiments provide a light-emitting diode (LED) device 100 including a plurality of spaced-apart mesas 150a, 150b that define pixels 155a, 155b, each of the plurality of spaced-apart mesas including a semiconductor layer 104, the semiconductor layer including an N-type layer 104n, an active region 106, and a P-type layer 104p, the spaced-apart mesas 150a, 150b having a height H and a width W, the height H being less than or equal to the width W. The LED device 100 further includes metal 118 within trenches 111 in the form of trenches 111 between each of the plurality of spaced-apart mesas 150a, 150b, the metal 118 providing optical separation between each of the spaced-apart mesas 150a, 150b and being in electrical contact with the N-type layer 104n of each of the spaced-apart mesas 150a, 150b along sidewalls of the N-type layer 104n. In one or more embodiments, the LED device 100 includes a first dielectric material 114 that insulates sidewalls of the P-type layer 104p (sidewalls 104s) and the active region 106 (sidewalls 106s) from an N-contact material 118n. A P-metal material plug 118p is in electrical communication with a p-contact layer 105. In embodiments of the LED device 100, each of the plurality of spaced-apart mesas 150a, 150b includes a conductive p-contact layer 105, the p-contact layer 105 extending across portions of each of the plurality of mesas 150a, 150b and including an edge 105e, the trenches 111 between each of the plurality of spaced-apart mesas resulting in a pixel pitch in the range of 1 μm to 100 μm, including the range of 51 μm to 100 μm, and all values and sub-ranges therebetween, and a dark space gap 117 between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In some examples, the pixel pitch is in the range of 5 μm to 100 μm, 10 μm to 100 μm, or 15 μm to 100 μm. In other embodiments, the dark space gap 117 is in the range of 10 μm to 0.5 μm, such as in the range of 10 μm to 4 μm, such as in the range of 8 μm to 4 μm. As used herein in accordance with one or more embodiments and as shown in FIG. 1O, "pixel pitch" means the distance or spacing 119 between centers "C" of adjacent pixels provided or formed by the mesas 150a, 150b. That is, the pixel pitch means the center-to-center spacing 119 of adjacent pixels.In one or more embodiments, the center-to-center spacing of the LED array as shown in FIG. 2 is the same for all adjacent pixels 155a, 155b and all adjacent pixels of the array 200. In one or more embodiments, the pixel pitch is in the range of 5 μm to 100 μm, for example, 5 μm to 90 μm, 5 μm to 80 μm, 5 μm to 70 μm, 5 μm to 60 μm, 5 μm to 50 μm, 5 μm to 40 μm, 5 μm to 30 μm, 10 μm to 90 μm, 10 μm to 80 μm, 10 μm to 70 μm, 10 μm to 60 μm, 10 μm to 50 μm, 10 μm to 40 μm, 10 μm to 30 μm, 20 μm to 90 μm, 20 μm to 80 μm, 20 μm to 70 μm, 20 μm to 60 μm, 20 μm to 50 μm, 20 μm to 40 μm, 20 μm to 30 μm, 30 μm to 90 μm, 30 μm to 80 μm, 30 μm to 70 μm, 30 μm to 60 μm, 30 μm to 50 μm, 30 μm to 40 μm, 40 μm to 90 μm, 40 μm to 80 μm, 40 μm to 70 μm, 40 μm to 60 μm, 40 μm to 50 μm, 50 μm to 90 μm, 50 μm to 80 μm, 50 μm to 70 μm, or 50 μm to 60 μm.

[0063] In one or more embodiments, a light-emitting diode (LED) device includes: a plurality of mesas that define pixels, each of the plurality of mesas having a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each mesa having a height that is less than or equal to its width; an N-contact material within the space between each of the plurality of mesas, the N-contact material providing optical separation between each mesa and electrically contacting the N-type layer of each mesa along the sidewalls of the N-type layer; a dielectric material that insulates the sidewalls of the P-type layer and the active region from the N-contact material. Each of the plurality of mesas has a p-contact layer that extends across a portion of each of the plurality of mesas and includes an edge. The space between each of the plurality of mesas provides a pixel pitch in the range of 10 μm to 100 μm and provides a dark space gap between adjacent edges of the p-contact layer that is less than 20% of the pixel pitch. In one or more embodiments, the P-contact layer 105 includes a reflective metal. The LED device of claim 1 has a pixel pitch in the range of 4 to 100 μm. In one or more embodiments, the dark space gap between adjacent edges of the p-contact layer is less than 10% of the pixel pitch. Therein, in the LED device of claim 1, the semiconductor layer is an epitaxial semiconductor layer having a thickness in the range of 2 μm to 10 μm. In one or more embodiments, the dielectric material is in the form of an outer spacer including a material selected from the group including SiO2, AlO x and SiN having a thickness in the range of 200 nm to 1 μm. In one or more embodiments, the N-contact material has a depth in the range of 0.5 μm to 2 μm from the top surface of the mesa. In one or more embodiments, each mesa includes a sidewall having a first segment and a second segment, respectively, the first segment of the sidewall defining an angle in the range of 60° to 90° from a horizontal plane parallel to the N-type layer and the P-type layer, and the second segment of the sidewall forming an angle in the range of 75° to less than 90° with the top surface of the substrate on which the mesa is formed.

[0064] In one or more embodiments, a light emitting diode (LED) device includes: a plurality of mesas defining pixels, each of the plurality of mesas having a semiconductor layer including an N-type layer, an active region, and a P-type layer, each mesa having a height less than or equal to its width; a metal within the space between each of the plurality of mesas, the metal providing optical separation between each mesa and making electrical contact with the N-type layer of each mesa along the sidewall of the N-type layer; a dielectric material insulating the sidewalls of the P-type layer and the active region from an N-contact material; each of the plurality of mesas having a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, the space between each of the plurality of mesas providing a pixel pitch in the range of 10 μm to 100 μm and a dark space gap between adjacent edges of the p-contact layer in the range of 4 μm to 10 μm. The plurality of mesas includes an array of mesas. In one or more embodiments, the dark space gap is in the range of 4 μm to 8 μm. In one or more embodiments, the pixel pitch is in the range of 40 μm to 100 μm.

[0065] One or more embodiments of the present disclosure provide a method of manufacturing an LED device. FIGS. 3A-3F illustrate process flow diagrams according to various embodiments. Referring to FIG. 3A, method 200 includes manufacturing a substrate at operation 202. Manufacturing the substrate includes depositing a plurality of semiconductor layers on the substrate, the semiconductor layers including, but not limited to, an N-type layer, an active region, and a P-type layer. When the semiconductor layers are deposited on the substrate, a portion of the semiconductor layers is etched to form trenches and a plurality of spaced-apart mesas. At operation 204, dies are manufactured. Manufacturing the dies includes depositing a (first) dielectric material to insulate sidewalls of the epitaxial layers (e.g., the N-type layer, the active region, and the P-type layer), and then depositing electrode metal in the trenches, e.g., in the space between each of the plurality of spaced-apart mesas. In some embodiments, manufacturing the dies further includes depositing a P contact layer and a hard mask, forming a current spreading film, plating a p-metal material plug, and subsequent under bump metallization (UBM). At operation 204, dies are manufactured. At operation 206, any microbumping can occur on a complementary metal oxide semiconductor (CMOS) backplane. At operation 208, back-end processing occurs, whereupon, optionally, the dies are connected to the CMOS backplane, underfill is provided, laser lift-off occurs, and then optionally a phosphor is integrated.

[0066] Referring to FIG. 3B, in one embodiment, method 210 includes depositing, at 212, a plurality of semiconductor layers including an N-type layer, an active region, and a P-type layer on a substrate. At 214, the method further includes etching a portion of the semiconductor layers to form a plurality of spaced-apart mesas that define trenches and pixels, each of the plurality of spaced-apart mesas includes a semiconductor layer, and each spaced-apart mesa has a height that is less than or equal to its width. At 216, the method includes depositing a dielectric material that insulates the sidewalls of the P-type layer and the active region from metal. At 218, the method includes depositing an electrode metal in the space between each of the plurality of spaced-apart mesas, the metal provides optical separation between each of the spaced-apart mesas and electrically contacts the N-type layer of each of the spaced-apart mesas along the sidewalls of the N-type layer. In one or more embodiments, each of the plurality of spaced-apart mesas includes a conductive p-contact layer that extends across a portion of each of the plurality of mesas and includes an edge, and the space between each of the plurality of spaced-apart mesas is a dark space gap between adjacent edges of the p-contact layer that has a pixel pitch in the range of 1 μm to 100 μm and is less than 20% of the pixel pitch. In some examples, the pixel pitch is in the range of 5 μm to 100 μm, 10 μm to 100 μm, or 15 μm to 100 μm. In other embodiments, the dark space gap is in the range of 10 μm to 0.5 μm, or in the range of 10 μm to 4 μm, such as in the range of 8 μm to 4 μm. As used herein, according to one or more embodiments, the term "dark space gap" refers to the space between adjacent edges of the p-contact layer where light is not reflected.

[0067] In some embodiments, the method includes forming an array of spaced-apart mesas. In some embodiments, the metal includes a reflective metal. In some embodiments, the dark space gap is in the range of 10 μm to 0.5 μm, or in the range of 10 μm to 4 μm. In some embodiments, a plurality of spaced-apart mesas are disposed within a pixel, and the pixel pitch is in the range of 5 μm to 100 μm or 30 μm to 50 μm. In some examples, the thickness of the semiconductor layer 104 is in the range of 2 μm to 10 μm.

[0068] Referring to FIG. 3C, method 220 further includes forming a common electrode at operation 222 in addition to operations 212 through 218 of FIG. 3B. In one or more embodiments, the common electrode includes a plurality of semiconductor stacks surrounded by a conductive metal. In one or more embodiments, the semiconductor stack includes one or more layers of GaN.

[0069] Referring to FIG. 3D, method 224 further includes depositing a current diffusion layer at operation 226 in addition to operations 212 through 218 of FIG. 3B. Some method embodiments include forming a multilayer composite film on a P-type layer, the multilayer composite film including a current diffusion layer, a P-contact layer on a first portion of the current diffusion layer, and a (second) dielectric layer on a second portion of the current diffusion layer below a hard mask layer. In one or more embodiments, the multilayer composite film has a current diffusion layer on the P-type layer, a current diffusion layer having a first portion and a second portion, a dielectric layer on the second portion of the current diffusion layer, a via opening defined by sidewalls of the dielectric layer and the first portion of the current diffusion layer, and a P-contact layer within the via opening on at least a portion of the first portion of the current diffusion layer, sidewalls of the dielectric layer, and surface of the dielectric layer. In one or more embodiments, the multilayer composite film is formed directly on the P-type layer. In other embodiments, one or more additional layers may be formed between the multilayer composite film and the P-type layer. In one or more embodiments, the multilayer composite layer includes a guard layer on the P-contact layer.

[0070] Some embodiments include depositing a current diffusion layer over the P-type layer. Embodiments of other methods include depositing a current diffusion layer over the P-type layer; depositing a dielectric layer over the current diffusion layer; forming a via opening in the dielectric layer; conformally depositing a P-contact layer within the via opening and on top of the dielectric layer; depositing a guard layer over the P-contact layer; depositing a hard mask layer over the guard layer; forming an opening in the hard mask layer; depositing a liner layer in the opening of the hard mask layer; and depositing a P-metal material plug over the liner layer, the P-metal material plug having a width; and forming a passivation layer over the P-metal material plug, the passivation layer having an opening defining a width, the width of the opening within the passivation layer being less than the combined width of the liner layer and the P-metal material plug within the opening.

[0071] Referring to FIG. 3E, method 230 includes, at operation 232, depositing a hard mask layer above or over the P-type layer. At operation 234, an opening is formed in the hard mask layer. At operation 236, in one or more embodiments, a liner layer is deposited in the opening of the hard mask layer. At operation 238, in one or more examples, a P-metal material plug is deposited over the liner layer, the P-metal material plug having a width, and at operation 240, a passivation layer is formed over the P-metal material plug, the passivation layer having an opening defining a width, the width of the opening of the passivation layer being smaller than the width of the P-metal material plug.

[0072] In one or more embodiments, a method of manufacturing a light-emitting diode (LED) device, the method comprising: depositing a plurality of semiconductor layers having an N-type layer, an active region, and a P-type layer on a substrate; depositing a hard mask layer over the P-type layer; partially etching the hard mask layer and the semiconductor layers to form a plurality of mesas and trenches defining pixels, each of the plurality of mesas having a semiconductor layer and each mesa having a height less than its width; depositing a dielectric material in the trenches; forming an opening in the hard mask layer and etching the semiconductor layers to expose a surface of the substrate and sidewalls of the N-type layer; depositing a liner layer on the substrate, where on the substrate includes on the substrate, the N-type layer, the dielectric material, and on a surface of the opening in the hard mask layer; depositing an electrode metal on the liner layer; planarizing the substrate to form a P-metal material plug on the liner layer within the opening of the hard mask layer and an N-contact material that electrically contacts the N-type layer of each mesa along the sidewalls of the N-type layer, where a combination of the liner layer within the opening of the hard mask layer and the P-metal material plug has a width; forming a passivation layer on the substrate and forming an opening in the passivation layer defining a width. In one or more embodiments, the width of each opening in the passivation layer is less than the width of the combination of the P-metal material plug and the liner layer.

[0073] Referring to FIG. 3F, embodiments of some methods include method 240, which includes depositing a semiconductor layer in operation 212, as described with respect to FIG. 1A. Method 240 further includes depositing a current spreading film or layer and / or a P-contact layer in operation 213, as described with respect to FIG. 1A. Method 240 further includes depositing and patterning a hard mask layer in operation 231, as described with respect to FIGS. 1A-C. In operation 233, trenches are formed in the semiconductor layer and a dielectric material is deposited, as described with respect to FIGS. 1D-G. In operation 234, an opening is formed in the hard mask layer, as described with respect to FIG. 1H. In operation 236, in one or more embodiments, a liner layer is deposited within the opening of the hard mask layer, as described with respect to FIG. 1H. In operation 237, metal is deposited in the trenches and a P-metal material plug is deposited, as described with respect to FIG. 1I. In operation 239, planarization is performed, as described with respect to FIG. 1J. In operation 241, a passivation layer is formed and patterned, as described with respect to FIGS. 1K and 1L. In operation 243, an under bump metallization layer is formed and patterned, as described with respect to FIG. 1M. The operations of method 240 can be utilized according to one or more embodiments to form a device, as shown in FIG. 1O or FIG. 4.

[0074] Another aspect of the present disclosure relates to an electronic system. In one or more embodiments, the electronic system comprises the LED monolithic devices and arrays described herein and a driver circuit configured to provide an independent voltage to one or more p-contact layers. In one or more embodiments, the electronic system is selected from the group consisting of LED-based lighting fixtures, light emitting strips, light emitting sheets, optical displays, and micro-LED displays.

[0075] FIG. 4 is a cross-sectional view of an LED device 300 showing a single mesa 350 of an LED device according to one or more embodiments. The device 300 is similar to the first mesa 15a or the second mesa 150b of the device 100 shown in FIG. 1O. The device 300 includes a semiconductor layer 304 including an n-type layer 304n, a p-type layer 304p, and an active region 306 between the n-type layer 304n and the p-type layer 304p.

[0076] In the illustrated embodiment, there is a multilayer composite film 317 on the P-type layer 304. As shown, the multilayer composite film 317 has a current diffusion layer 311 on the P-type layer 304p. The multilayer composite film further includes a dielectric layer 307 on the current diffusion layer 311. In one or more embodiments, the current diffusion layer 311 has a first portion 311y and a second portion 311z. The first portion 311y and the second portion 311z are lateral portions of the current diffusion layer 311. The P-contact layer 305 is on the first portion 311y of the current diffusion layer 311 and within the via opening 319. The dielectric layer 307 is on the second portion 311z of the current diffusion layer 311. In one or more embodiments, the dielectric layer 307 is separated by the via opening 319. The via opening 319 has at least one sidewall 319s and a bottom 319b, and the bottom 319b exposes the current diffusion layer 311. In the illustrated embodiment, the via opening 319 is defined by the opposing sidewalls 319s of the dielectric layer 307 and the bottom 319b defined by the current diffusion layer 311. In the embodiment shown in FIG. 4, the via opening 319 is filled with the P-contact layer 305 and the guard layer 309. As shown in FIG. 4, the P-contact layer 305 is present on the top surface of the dielectric layer 307, the sidewall 319s and the lower part 31b of the via opening 319, and directly above the first portion 311y of the current diffusion layer 311. As shown in the embodiment of FIG. 4, the P-contact layer 305 is substantially conformal with the via opening 319. As used herein, "substantially conformal" refers to a layer that has substantially the same thickness throughout (e.g., on the hard mask layer 308, on the sidewall 319s, and on the bottom 319b of the via opening 319). The variation in the thickness of a substantially conformal layer is about 5%, 2%, 1%, or 0.5% or less. In one or more embodiments, the guard layer 309 is on the P-contact layer 305. Without intending to be bound by theory, according to one or more embodiments, the guard layer 309 can prevent metal ions from the P-contact layer 305 from moving and shorting the device 300. In one or more embodiments, the guard layer 309 covers the entire P-contact layer 305. In one or more embodiments, the guard layer 309 directly covers the entire P-contact layer 305.

[0077] In one or more embodiments, the current diffusion layer includes a transparent material. The current diffusion layer is separated from the reflective layer. In this way, the function of current diffusion is realized by a layer different from the function of reflection. In one or more embodiments, the current diffusion layer 311 includes indium tin oxide (ITO) or other suitable conductive transparent materials, such as transparent conductive oxides (TCOs) such as indium zinc oxide (IZO), and the current diffusion layer has a thickness in the range of 5 nm to 100 nm. In some embodiments, the dielectric layer 307 includes any suitable dielectric material, such as silicon dioxide (SiO2) or silicon oxynitride (SiON). In some embodiments, the guard layer 309 includes titanium-platinum (TiPt), titanium-tungsten (TiW), or titanium-tungsten nitride (TiWN). In one or more embodiments, the P-contact layer 305 includes a reflective metal. In one or more embodiments, the P-contact layer 305 includes a suitable reflective material such as nickel (Ni) or silver (Ag), but is not limited thereto.

[0078] Without intending to be bound by theory, according to some embodiments, the multilayer composite film 317 on the P-type layer 304p can achieve a balance of absorption, reflection, and conductivity. In some embodiments, the P-contact layer 305 is a high-reflection layer. At angles close to and greater than the critical angle, the dielectric layer 307 is a better reflector than the P-contact layer 305, especially when there may be no conductivity. In some embodiments, the dielectric layer 307 includes a plurality of dielectric layers and can form a DBR (distributed Bragg reflector). In one or more embodiments, the current diffusion layer 311 is optimized to minimize absorption and increase conductivity.

[0079] In one or more embodiments, the P-contact layer 305 spreads over a mesa width smaller than the width over which the current diffusion layer 311 spreads.

[0080] In the illustrated embodiment, there is a hard mask layer 308 on the first section of the guard layer 309 above the second portion 311z of the current diffusion layer 311, and the hard mask layer 308 has a mask opening 347 defined therein. The hard mask layer 308 can include any suitable material including a dielectric material. The hard mask layer 308 is masked and etched as described with respect to FIGS. 1A-1N above.

[0081] The hard mask opening 347 is partially filled with the liner layer 325 and partially filled with the P-metal material plug 318p, and the P-metal material plug 318p has a width 339. As shown in the embodiment of FIG. 4, the liner layer 325 is substantially conformal to the hard mask opening 347. As used herein, "substantially conformal" refers to a layer that is substantially the same thickness throughout (e.g., on the sidewalls 347s and bottom 347b of the hard mask opening 347). The variation in the thickness of a substantially conformal layer is about 5%, 2%, 1% or less than 0.5%. In one or more embodiments, the hard mask opening 347 has at least one sidewall 347s and a bottom surface 347b. In some embodiments, the bottom surface 347b exposes the guard layer 309. In one or more embodiments, the liner layer 325 is on at least one sidewall 347s and the bottom 347b of the hard mask opening 347. In a particular embodiment, the liner layer 325 is substantially conformal to at least one sidewall 347s and the lower portion 347b of the hard mask opening 347. In the illustrated embodiment, there are two sidewalls 347s, which are opposing sidewalls 347s that define the hard mask opening 347. In one or more embodiments, the thickness of the liner layer 325 ranges from about 5 nm to about 2 μm. In one or more embodiments, the liner layer 325 includes a seed material, and the liner layer 325 can include any suitable material including, but not limited to, aluminum (Al), titanium nitride, Ag, indium tin oxide (ITO), titanium tungsten (TiW), and / or titanium platinum (TiP). The seed material of the liner layer 325 according to some embodiments can promote the plating of the P-metal material plug 318p. In one or more examples, the liner layer 325 functions as an electrical bridge. The liner layer 325 can be formed by any means known to those skilled in the art, such as sputtering deposition.

[0082] As shown in FIG. 4, there is a passivation film 321 on the hard mask layer 308. In one or more embodiments, the passivation film 321 includes a first passivation layer 320 and a second passivation layer 322. The first passivation layer 320 and the second passivation layer 322 can include any suitable materials. In one or more examples, the first passivation layer 320 includes silicon oxide (SiO2), and the second passivation layer includes silicon nitride (SiN). In one or more embodiments, the passivation film 321 has a passivation film opening 348 that defines a width 349 therein, and the width 349 of the passivation film opening 348 is less than the width 339 of the combination of the P-metal material plug 318p and the liner layer 325. In one or more embodiments, the passivation film 321 is sized to cover the surface 325f of the liner layer 325 and a portion of the P-metal material plug 318p. Thus, the passivation film opening 348, which is less than the width 339 of the P-metal material plug 318p and the liner layer 325, is effective to protect the liner layer 325 while allowing access to the P-metal material plug 318p. In one or more embodiments, each passivation film opening 348 is disposed at the center of the P-metal material plug 318p.

[0083] As shown in FIG. 4, a layer of P-metal material, also referred to as the P-metal material plug 318p, is formed on the liner layer 325. The P-metal material plug 318p can include any suitable material. In one or more embodiments, the P-metal material plug 318p includes copper (Cu). In one or more embodiments, the inner spacer 312 contacts the outer edges of the P-contact layer 305, the guard layer 309, and the hard mask layer 308. An outer spacer 314 is formed adjacent to the inner spacer 312.

[0084] In one or more embodiments, a reflective liner 330 is formed at the ends of the semiconductor layers 304n, 306, and 304p, separating from the N contact material 318n. The difference between the LED device 300 of FIG. 4 and the LED device of FIG. 10 is a first passivation layer 320 corresponding to the passivation layer 120 shown in FIG. 1M and a second passivation layer 322 that can include silicon nitride (SiN) in some embodiments. In some embodiments, only the first passivation layer 320 is present, while in other examples, both the first passivation layer 320 and the second passivation layer 322 are present. The first passivation layer 320 and the second passivation layer 322 have a passivation film opening 348 therein. FIG. 4 also shows an anode pad including an under bump metallization 324a, the configuration of which will be described with respect to FIG. 1M. The P metal material plug 318p has a width 339 defined by the distance from the outer edge of the liner layer 325, and the passivation film opening 348 in the passivation layer is filled with the under bump metallization 324a forming the anode pad. In one or more embodiments, the opening 348 has a width 349 smaller than the width 339 of the P metal material plug 318p. In some embodiments, the width of the P metal material plug 318p ranges from 2 μm to 30 μm, for example, from 10 μm to 20 μm.

[0085] Use The LED devices disclosed herein can be monolithic arrays or matrices. For use in end applications, the LED devices can be attached to a backplane. Illumination arrays and lens systems can incorporate the LED devices disclosed herein. Uses include, but are not limited to, beam steering and other uses that benefit from fine intensity, spatial, and temporal control of light distribution. These uses include, but are not limited to, precise spatial patterning of light emitted from pixel blocks or individual pixels. Depending on the application, the emitted light can be spectrally discriminated and be adaptive overtime and / or responsive to the environment. The light-emitting pixel array can provide a pre-programmed light distribution in various intensity, spatial, or temporal patterns. The associated optical system can vary at the pixel, pixel block, or device level. An example light-emitting pixel array can include a device having a common control central block of high-brightness pixels with an associated common optical system, although the edge pixels can have individual optical systems. In addition to flashlights, common applications supported by the light-emitting pixel array include video lighting, automotive headlights, architectural and area lighting, and street lighting. Embodiments

[0086] Various examples are listed below. It will be understood that the embodiments listed below can be combined with all aspects and other embodiments according to the scope of the present invention.

[0087] Embodiment (a) A light-emitting diode device (LED device) comprising: A plurality of mesas defining pixels, each mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each mesa having a height less than its width; N-contact material within the space between each mesa, providing optical separation between each of the mesas, and electrically contacting the N-type layer of each mesa along the sidewalls of the N-type layer; A dielectric material insulating the sidewalls of the P-type layer and the active region from the N-contact material; A hard mask layer above the semiconductor layer, the hard mask layer having a plurality of openings therein, each of the plurality of openings being partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; A passivation film on a hard mask layer, the passivation film having a plurality of passivation film openings defining a width, the width of each passivation film opening being less than the width of a combination of a P metal material plug and a liner layer, the passivation film, and comprising.

[0088] Embodiment (b) The LED device of embodiment (a), wherein the passivation film covers a part of the P metal material plug and the surface of the liner layer.

[0089] Embodiment (c) The LED device of embodiments (a) to (b), wherein the passivation film opening is disposed at the center of the P metal material plug.

[0090] Embodiment (d) One of the LED devices of embodiments (a) to (c), wherein the P metal material plug contains copper.

[0091] Embodiment (e) One of the LED devices of embodiments (a) to (d), The width of the combination of the P metal material plug and the liner layer is in the range of 2 μm to 30 μm.

[0092] Embodiment (f) One of the LED devices of embodiment (e), wherein the width of the combination of the P metal material plug and the liner layer is in the range of 10 μm to 20 μm.

[0093] Embodiment (g) One of the LED devices of embodiments (a) to (f), wherein the pixel pitch of the plurality of mesas is in the range of 5 μm to 100 μm,

[0094] Embodiment (h) The LED device of embodiment (g), wherein the pixel pitch is in the range of 30 μm to 50 μm,

[0095] Embodiment (i) One of the LED devices according to embodiments (a) to (h), wherein the thickness of the semiconductor layer ranges from 2 μm to 10 μm.

[0096] Embodiment (j) One of the LED devices according to embodiments (a) to (i), wherein the dielectric material is in the form of an external spacer including a material selected from the group consisting of SiO2, AlO having a thickness in the range of 200 nm to 1 μm. x and SiN.

[0097] Embodiment (k) One of the LED devices according to embodiments (a) to (j), wherein the space between each mesa includes a trench having a depth in the range of 0.5 μm to 2 μm from the top surface of each mesa.

[0098] Embodiment (l) One of the LED devices according to embodiments (a) to (k). Each mesa includes sidewalls of a semiconductor layer having a first segment and a second segment, respectively. The first segment of the sidewall defines an angle in the range of 60° to 90° from a horizontal plane parallel to the N-type layer and the P-type layer. The second segment of the sidewall forms an angle in the range of 75° to less than 90° with the top surface of the substrate on which the mesa is formed.

[0099] Embodiment (m) One of the LED devices according to embodiments (a) to (j), wherein the plurality of mesas includes an array of mesas.

[0100] Embodiment (n) A light-emitting diode device (LED device), comprising: A plurality of mesas defining pixels, each mesa including a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, and an N-contact material that electrically contacts the N-type layer of each mesa along the sidewall of the N-type layer; A dielectric material that insulates the sidewalls of the P-type layer and the active region from the metal; A current diffusion layer on a P-type layer, the current diffusion layer having a first portion and a second portion; A P-contact layer on the first portion of the current diffusion layer; A dielectric layer on the second portion of the current diffusion layer; A guard layer covering the P-contact layer; a hard mask layer on a first section of the guard layer above a second section of the current diffusion layer, the hard mask layer having an opening, the opening being partially filled with a liner layer and partially filled with a P-metal material plug, the hard mask layer; A combination of a P-metal material plug having a width and a liner layer; A passivation film on the hard mask layer, the passivation film having a passivation film opening defining a width, the width of the passivation film opening being less than the width of the combination of the P-metal material plug and the liner layer, the passivation film covering a portion of the P-metal material plug and the surface of the liner layer, the passivation film, comprising.

[0101] Embodiment (o) A method of manufacturing a light-emitting diode device (LED device), Depositing a plurality of semiconductor layers having an N-type layer, an active region, and a P-type layer on a substrate; Depositing a hard mask layer over the P-type layer; Etching a portion of the hard mask layer and the conductor layer to form a plurality of mesas and trenches defining pixels, each of the plurality of mesas having a semiconductor layer, each of the mesas having a height less than its width, the step; Depositing a dielectric material in the trenches; Forming an opening in the hard mask layer and etching the semiconductor layer to expose the surface of the substrate and the sidewalls of the N-type layer, the step; Depositing a liner layer on the substrate including on the surface of the substrate, the N-type layer, the dielectric material, and the opening in the hard mask layer; Depositing an electrode metal on the liner layer; A step of planarizing a substrate and forming a P-metal material plug on a liner layer within an opening of a hard mask layer and an N-contact material that electrically contacts the N-type layer of each mesa along the sidewalls of the N-type layer, wherein the combination of the liner layer and the P-metal material within the opening of the hard mask layer has a width; A step of forming a passivation layer on a substrate and forming an opening within the passivation layer that defines a width, wherein the width of each opening membrane opening within the passivation layer is less than the width of the combination of the P-metal material plug and the liner layer, and including:

[0102] Example (p) Before depositing a hard mask layer over the P-type layer: A step of depositing a current diffusion layer on the P-type layer, wherein the current diffusion layer has a first portion and a second portion; A step of depositing a dielectric layer on the current diffusion layer; A step of forming a via within the dielectric layer by the sidewalls of the dielectric layer and the first portion of the current diffusion layer such that the dielectric layer is only on the section portion of the current diffusion layer; A step of depositing a P-contact layer on the substrate such that the P-contact layer is on the surface of the dielectric layer, the sidewalls of the dielectric layer, and the first portion of the current diffusion layer; A step of depositing a guard layer that covers the P-contact layer, wherein the hard mask layer and the liner layer within the opening of the hard mask layer are in direct contact with the P-contact layer, and including:

[0103] Embodiment (q) One of the methods of embodiments (o)-(p), wherein the P-metal material plug includes copper.

[0104] Embodiment (r) One of the methods of embodiments (o)-(n), wherein the width of the combination of the P-metal material plug and the liner layer is in the range of 2 μm to 30 μm.

[0105] Embodiment (s) One of the methods of embodiments (o)-(n), The pixel pitch of the plurality of mesas is in the range of 5 μm to 100 μm.

[0106] Embodiment (t) One of the methods of Embodiments (o) to (n), wherein the thickness of the semiconductor layer is in the range of 2 μm to 10 μm.

[0107] The use of the terms "a" and "an" and "the" and similar designations in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) is to be construed to cover both the singular and the plural forms unless specifically indicated otherwise herein or clearly contradicted by the context. The recitation of a range of values herein is merely intended to serve as a shorthand method of referring individually to each value falling within the range unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless specifically indicated otherwise herein or clearly contradicted by the context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is merely for the purpose of better illuminating the materials and methods and does not impose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0108] References throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in certain embodiments", "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0109] Although the disclosure herein has been described with reference to particular embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and devices of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode device (LED device), comprising: A plurality of mesas defining pixels, each of the mesas comprising a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each of the mesas having a height less than its width; a plurality of mesas; An N-contact material within the space between each mesa, providing optical isolation between each of the mesas, and electrically contacting the N-type layer of each of the mesas along the sidewalls of the N-type layer; an N-contact material; A dielectric material insulating the sidewalls of the P-type layer and the active region from the N-contact material; A hard mask layer above the semiconductor layer, the hard mask layer having a plurality of openings therein, each of the plurality of openings being partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; a hard mask layer; A passivation film on the hard mask layer, the passivation film having a plurality of passivation film openings defining a width, the width of each passivation film opening being less than the combined width of the P-metal material plug and the liner layer within the opening of the hard mask layer; a passivation film, An LED device comprising.

2. The passivation film covers a part of the P-metal material plug and the surface of the liner layer. The LED device according to claim 1.

3. The passivation film opening is disposed at the center of the P-metal material plug. The LED device according to claim 1.

4. The P-metal material plug contains copper. The LED device according to claim 1.

5. The plurality of mesas includes an array of mesas. The LED device according to claim 1.

6. The width of the combination of the P-metal material plug and the liner layer is in the range of 2 μm to 30 μm. The LED device according to claim 1.

7. The width of the combination of the P-metal material plug and the liner layer is in the range of 10 μm to 20 μm. The LED device according to claim 6.

8. The pixel pitch of the plurality of mesas is in the range of 5 μm to 100 μm. The LED device according to claim 1.

9. The pixel pitch is in the range of 30 μm to 50 μm. The LED device according to claim 8.

10. The thickness of the semiconductor layer is in the range of 2 μm to 10 μm. The LED device according to claim 1.

11. The dielectric material is in the form of an external spacer including a material selected from the group consisting of SiO2, AlOx, and SiN having a thickness in the range of 200 nm to 1 μm. The LED device according to claim 1.

12. The space between each mesa includes a trench having a depth in the range of 0.5 μm to 2 μm from the top surface of the mesa. The LED device according to claim 1.

13. Each of the mesas includes sidewalls of the semiconductor layer each having a first segment and a second segment. The first segment of the sidewall defines an angle in the range of 60° to 90° from a horizontal plane parallel to the N-type layer and the P-type layer. The second segment of the sidewall forms an angle in the range of 75° to less than 90° with the top surface of the substrate on which the mesa is formed. The LED device according to claim 1.

14. A light-emitting diode device (LED device), comprising: A plurality of mesas defining pixels, each of the mesas including a semiconductor layer, the semiconductor layer including an N-type layer, an active region, and a P-type layer, each of the mesas having a height less than its width; A metal within the space between each of the mesas, the metal providing optical isolation between each mesa and being in electrical contact with the N-type layer of each mesa along the sidewalls of the N-type layer; an N-contact material; A dielectric material insulating the sidewalls of the P-type layer and the active region from the metal; A current diffusion layer on the P-type layer, the current diffusion layer having a first portion and a second portion; A P-contact layer on the first portion of the current diffusion layer; A dielectric layer on the second portion of the current diffusion layer; A guard layer covering the P-contact layer; A hard mask layer on a first section of the guard layer above the second portion of the current diffusion layer, the hard mask layer having an opening, the opening being partially filled with a liner layer and partially filled with a P-metal material plug, the combination of the P-metal material plug and the liner layer having a width; a hard mask layer; A passivation film on the hard mask layer, the passivation film having a passivation film opening defining a width, the width of the passivation film opening being less than the width of the combination of the P-metal material plug and the liner layer within the opening of the hard mask layer, the passivation film covering a portion of the P-metal material plug and the surface of the liner layer; a passivation film; An LED device comprising.

15. A method of manufacturing a light-emitting diode device (LED device), comprising: Depositing a plurality of semiconductor layers having an N-type layer, an active region, and a P-type layer on a substrate; Depositing a hard mask layer over the P-type layer; Etching the hard mask layer and a part of the semiconductor layer to form a plurality of mesas and trenches that define pixels, wherein each of the plurality of mesas has a semiconductor layer, and each of the mesas has a height less than its width; Depositing a dielectric material in the trenches; Forming an opening in the hard mask layer and etching the semiconductor layer to expose the surface of the substrate and the sidewalls of the N-type layer; Depositing a liner layer on the substrate, including on the surface of the substrate, the N-type layer, the dielectric material, and the opening in the hard mask layer; Depositing an electrode metal on the liner layer; Planarizing the substrate to form a P-metal material plug on the liner layer within the opening of the hard mask layer and an N-contact material that electrically contacts the N-type layer of each mesa along the sidewalls of the N-type layer, wherein the combination of the liner layer and the P-metal material plug within the opening of the hard mask layer has a width; Forming a passivation layer on the substrate and forming an opening in the passivation layer that defines a width, wherein the width of the film opening in the passivation layer is less than the width of the combination of the P-metal material plug and the liner layer within the opening of the hard mask layer; A method comprising.

16. Before depositing the hard mask layer over the P-type layer: Depositing a current diffusion layer on the P-type layer, the current diffusion layer having a first portion and a second portion; Depositing a dielectric layer on the current diffusion layer; Forming a via in the dielectric layer by the sidewalls of the dielectric layer and the first portion of the current diffusion layer such that the dielectric layer is only on the second portion of the current diffusion layer; Depositing a P contact layer on the substrate such that the P contact layer is on the surface of the dielectric layer, the sidewalls of the dielectric layer, and the first portion of the current diffusion layer; Depositing a guard layer covering the P contact layer, wherein the hard mask layer and the liner layer within the opening are in direct contact with the P contact layer; The method according to claim 15, further comprising.

17. The P metal material plug contains copper. The method according to claim 15.

18. The width of the combination of the P metal material plug and the liner layer is in the range of 2 μm to 30 μm. The method according to claim 15.

19. The pixel pitch of the plurality of mesas is in the range of 5 μm to 100 μm. The method according to claim 15.

20. The thickness of the semiconductor layer is in the range of 2 μm to 10 μm. The method according to claim 15.

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