Semiconductor device

Abstract

In this semiconductor device, an edge termination structure portion includes: one or more guard rings of a second conductivity type provided between a well region and a terminal side of a semiconductor substrate, and exposed on an upper surface of the semiconductor substrate; a first conductivity-type region provided between the well region and a first guard ring among the one or more guard rings that is closest to the well region; and a first field plate provided over the upper surface of the semiconductor substrate and connected to the first guard ring. The first field plate overlaps 90% or more of the first conductivity-type region between the first guard ring and the well region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device including an edge termination structure portion including a guard ring has been known (see, for example, Patent Document 1). In the edge termination structure portion, an insulating film is provided on the upper surface of the semiconductor substrate. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open No. 8-306937Problems to be Solved

[0003] It is preferable to suppress a decrease in breakdown voltage when charges are accumulated in the insulating film. General Disclosure

[0004] In order to solve the above problems, in one aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type provided therein. The semiconductor device may include an active portion provided in the semiconductor substrate. The semiconductor device may include an edge termination structure portion provided between the active portion and the edge of the semiconductor substrate in the semiconductor substrate. The semiconductor device may include a well region of a second conductivity type provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate. One or more edge termination structure portions may be provided between the well region and the edge of the semiconductor substrate, and may have a guard ring of the second conductivity type exposed on the upper surface of the semiconductor substrate. The edge termination structure portion may include a first guard ring closest to the well region among the one or more guard rings, and a first conductivity type region provided between the first guard ring and the well region. The edge termination structure portion may be provided above the upper surface of the semiconductor substrate and may have a first field plate connected to the first guard ring. The first field plate may have an upper portion overlapping the first guard ring above the first guard ring. The first field plate may have an extending portion extending from the upper portion in the direction of the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region.

[0005] The first field plate may include polysilicon.

[0006] The semiconductor device may include a well plate provided above the well region. In the direction connecting the well region and the first guard ring, the length by which the extension of the first field plate overlaps the first conductivity type region may be greater than the length by which the well plate overlaps the first conductivity type region.

[0007] In the direction connecting the well region and the first guard ring, the first conductivity type region may have a portion that does not overlap with either the first field plate or the well plate.

[0008] The first field plate may be provided up to a position overlapping the well region.

[0009] The first field plate may be provided up to a position overlapping the well plate.

[0010] An insulating film that separates the first field plate and the well plate may be provided between the first field plate and the well plate.

[0011] A part of the first field plate may be provided between the well plate and the semiconductor substrate.

[0012] The semiconductor device may be provided above the upper surface of the semiconductor substrate and may include one or more second field plates connected to guard rings other than the first guard ring. At least one second field plate may be provided from above one guard ring to above an adjacent other guard ring.

[0013] At least one second field plate may cover a part of an adjacent other guard ring.

[0014] The semiconductor device may be provided above the upper surface of the semiconductor substrate and include two or more second field plates connected to guard rings other than the first guard ring. Two second field plates provided on two adjacent guard rings may have a portion overlapping with each other.

[0015] Of the two second field plates overlapping with each other, the second field plate disposed farther from the well region may be disposed below the other second field plate.

[0016] Each of the two second field plates overlapping with each other may have an upper portion overlapping with the guard ring above the guard ring. Of the two second field plates overlapping with each other, the second field plate disposed farther from the well region may have an inner extension portion extending in the direction of the well region from the upper portion. Of the two second field plates overlapping with each other, the other second field plate may have an outer extension portion extending in the direction opposite to the well region from the upper portion. In the direction connecting the well region and the edge of the semiconductor substrate, the inner extension portion may be longer than the outer extension portion.

[0017] The semiconductor device may include an insulating film provided between the first field plate and the semiconductor substrate. At least a part of the insulating film may be disposed inside the semiconductor substrate. At least a part of the insulating film may be disposed above the upper surface of the semiconductor substrate.

[0018] The thickness of the insulating film provided below the first field plate may satisfy the following formula. (φ0 - φ1) / E C <t However, φ0 is the potential of the well region, φ1 is the potential of the first field plate, t is the thickness of the insulating film, and E C is the critical electric field strength of the insulating film.

[0019] The extension of the first field plate may be connected to the upper part and have a first portion that extends from the upper part in the direction of the well region. The extension may be connected to the first portion, extend from the first portion in the direction of the well region, and have a second portion at least a part of which is disposed above the first portion.

[0020] Note that the above summary of the invention does not enumerate all the necessary features of the present invention. Also, sub-combinations of these feature groups may also be inventions.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Mode for Carrying Out the Invention

[0022] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0023] The unit system in this specification is the SI unit system unless otherwise specified. Although the unit of length may be expressed in cm, various calculations may be performed after converting to meters (m). In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0024] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without indicating positive or negative, it means directions parallel to the +Z-axis and -Z-axis.

[0025] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis. Further, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Also, in this specification, a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction. When referred to as the upper surface side of the semiconductor substrate in this specification, it refers to the region from the center in the depth direction of the semiconductor substrate to the upper surface. When referred to as the lower surface side of the semiconductor substrate, it refers to the region from the center in the depth direction of the semiconductor substrate to the lower surface.

[0026] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0027] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. N-type and P-type are examples of the first conductivity type and the second conductivity type. The N-type may be the first conductivity type and the P-type may be the second conductivity type, or the P-type may be the first conductivity type and the N-type may be the second conductivity type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be described as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to obtain a semiconductor showing an N-type conductivity type or a semiconductor showing a P-type conductivity type.

[0028] In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charges. As an example, when the donor concentration is N D , and the acceptor concentration is N A , the net net doping concentration at any position is |N D - N A |.

[0029] The donor has a function of supplying electrons to the semiconductor. The acceptor has a function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the impurities themselves. For example, a VOH defect in which a hole (V), oxygen (O), and hydrogen (H) present in the semiconductor are combined functions as a donor that supplies electrons.

[0030] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0031] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the electrically activated state. The chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry. The net doping concentration described above can be measured by a voltage-capacitance measurement method (CV method). Also, the carrier density measured by a spreading resistance measurement method (SR method) may be used as the net doping concentration. The carrier density measured by the CV method or the SR method may be a value in the thermal equilibrium state. Also, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier density in the region may be used as the donor concentration. Similarly, in a P-type region, the carrier density in the region may be used as the acceptor concentration.

[0032] Also, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in the region. In cases where the concentration of the donor, acceptor, or net doping is substantially uniform, etc., the average value of the concentration of the donor, acceptor, or net doping in the region may be used as the concentration of the donor, acceptor, or net doping.

[0033] The carrier density measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility is caused by scattering of carriers due to disorder in the crystal structure, such as lattice defects.

[0034] The concentration of donors or acceptors calculated from the carrier density measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic acting as a donor, or the acceptor concentration of boron acting as an acceptor, is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen acting as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0035] FIG. 1 is an example of a top view of the semiconductor device 100. In FIG. 1, the positions where each member is projected onto the upper surface of the semiconductor substrate 10 are shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.

[0036] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In the semiconductor substrate 10 of this example, N-type bulk donors are distributed throughout. The bulk donors are donors by dopants that were contained substantially uniformly in the ingot when the ingot from which the semiconductor substrate 10 originated was manufactured. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, elements of Group V or Group VI, such as phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also included in the P-type regions. The semiconductor substrate 10 may be a chip obtained by singulating a wafer cut out from a semiconductor ingot. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0037] The oxygen chemical concentration contained in a substrate manufactured by the MCZ method is, as an example, 1×10 17 ~7×10 17 atoms / cm 3 . The oxygen chemical concentration contained in a substrate manufactured by the FZ method is, as an example, 1×10 15 ~5×10 16 atoms / cm 3 . The bulk donor concentration may use the chemical concentration of the bulk donors distributed throughout the semiconductor substrate 10, and may be a value between 90% and 100% of the chemical concentration. In a semiconductor substrate doped with Group V or Group VI dopants such as phosphorus, the bulk donor concentration may be 1×10 11 / cm 3 or more and 3×10 13 / cm 3 or less. The bulk donor concentration of a semiconductor substrate doped with Group V or Group VI dopants is preferably 1×10 12 / cm 3 or more and 1×10 13 / cm 3The following applies. Also, as the semiconductor substrate 10, a non-doped substrate that does not substantially contain a bulk dopant such as phosphorus may be used. In that case, the bulk donor concentration of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration of the non-doping substrate is preferably 5×10 12 / cm 3 or less.

[0038] Also, a P-type bulk acceptor may be distributed throughout the semiconductor substrate 10. The bulk acceptor may be an acceptor by a dopant contained substantially uniformly in the ingot during the production of the ingot that is the source of the semiconductor substrate 10, or may be an acceptor implanted throughout the wafer or chip-shaped semiconductor substrate 10. The bulk acceptor may be boron. The bulk acceptor concentration may be lower than the bulk donor concentration. That is, the bulk of the ingot or semiconductor substrate 10 is N-type. As an example, the bulk acceptor concentration is 5×10 11 ( / cm 3 ) to 8×10 14 ( / cm 3 ), and the bulk donor concentration is 5×10 12 ( / cm 3 ) to 1×10 15 ( / cm 3 ). The bulk acceptor concentration may be 1% or more, 10% or more, or 50% or more of the bulk donor concentration. The bulk acceptor concentration may be 99% or less, 95% or less, or 90% or less of the bulk donor concentration. The bulk acceptor concentration and the bulk donor concentration may be the chemical concentrations of impurities such as boron or phosphorus distributed throughout the semiconductor substrate 10. The bulk acceptor concentration and the bulk donor concentration may also be the values at the center in the depth direction of the semiconductor substrate 10 of the chemical concentrations of impurities such as boron or phosphorus distributed throughout the semiconductor substrate 10.

[0039] The semiconductor substrate 10 has an upper surface and a lower surface. The upper surface and the lower surface are two main surfaces of the semiconductor substrate 10. The semiconductor substrate 10 has an edge 102 in a top view. When simply referred to as a top view in this specification, it means looking from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edges 102 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to any one of the edges 102. Also, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0040] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160 but is omitted in FIG. 1.

[0041] At least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD) is provided in the active portion 160. In the example of FIG. 1, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In other examples, only one of the transistor portion 70 and the diode portion 80 may be provided in the active portion 160.

[0042] In FIG. 1, the region where the transistor portion 70 is arranged is marked with the symbol "I", and the region where the diode portion 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extending direction (the Y-axis direction in FIG. 1). The transistor portion 70 and the diode portion 80 may each have a longitudinal dimension in the extending direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.

[0043] The diode portion 80 has an N+-type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region that overlaps the cathode region in a top view. A P+-type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10. In this specification, the extension region 81 obtained by extending the diode portion 80 in the Y-axis direction up to the gate wiring described later may also be included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0044] The transistor portion 70 has a P+-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor portion 70, a gate structure including an N+-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10.

[0045] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 in this example has a gate pad 112. The semiconductor device 100 may have an anode pad and a cathode pad connected to a temperature detection diode, and may also have a current detection pad. Each pad is arranged in the vicinity of the end side 102. The vicinity of the end side 102 refers to the region between the end side 102 in a top view and the emitter electrode. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0046] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0047] The gate wiring in this example has an outer peripheral gate wiring 130 and an active side gate wiring 131. The outer peripheral gate wiring 130 is disposed between the active portion 160 and the edge 102 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the outer peripheral gate wiring 130 in a top view may be regarded as the active portion 160. Further, the outer peripheral gate wiring 130 is connected to the gate pad 112. The outer peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring may be a metal wiring containing aluminum or the like, may be a wiring formed of polysilicon, or may be a laminated wiring in which these wirings are laminated.

[0048] The active side gate wiring 131 is provided in the active portion 160. By providing the active side gate wiring 131 in the active portion 160, for each region of the semiconductor substrate 10, the variation in the wiring length from the gate pad 112 can be reduced.

[0049] The active side gate wiring 131 is connected to the gate trench portion of the active portion 160. The active side gate wiring 131 is disposed above the semiconductor substrate 10. The active side gate wiring 131 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0050] The active side gate wiring 131 may be connected to the outer peripheral gate wiring 130. The active side gate wiring 131 in this example is provided to extend in the X-axis direction so as to cross the active portion 160 from one outer peripheral gate wiring 130 to the other outer peripheral gate wiring 130 at substantially the center in the Y-axis direction. When the active portion 160 is divided by the active side gate wiring 131, in each divided region, the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction.

[0051] Further, the semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detection portion (not shown) which simulates the operation of the transistor portion provided in the active portion 160.

[0052] In the semiconductor device 100 of this example, an edge termination structure portion 90 is provided between the active portion 160 and the side edge 102. The edge termination structure portion 90 is provided outside the active portion 160 in the semiconductor substrate 10. The outside in the semiconductor substrate 10 refers to the side closer to the side edge 102. The edge termination structure portion 90 of this example is disposed between the outer peripheral gate wiring 130 and the side edge 102. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 has a plurality of guard rings 92. The guard ring 92 is a P+-type region in contact with the upper surface of the semiconductor substrate 10. The guard ring 92 may surround the active portion 160 in a top view. The plurality of guard rings 92 are arranged at a predetermined interval between the outer peripheral gate wiring 130 and the side edge 102. The guard ring 92 disposed on the outside may surround the guard ring 92 disposed one inside. The outside refers to the side closer to the side edge 102, and the inside refers to the side closer to the center in a top view of the upper surface of the semiconductor substrate 10. By providing the plurality of guard rings 92, the depletion layer on the upper surface side of the active portion 160 can be extended to the outside, and the breakdown voltage of the semiconductor device 100 can be improved. The edge termination structure portion 90 may further include at least one of a field plate and RESURF provided annularly surrounding the active portion 160.

[0053] Figure 2 is a diagram showing an example of the A-A cross section in Figure 1. The A-A cross section is the XZ plane passing through the transistor portion 70 and the diode portion 80. In the semiconductor device 100 of this example, in the cross section, it has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as a silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, a nitride film, and other insulating films. The interlayer insulating film 38 is provided with a contact hole 54 connecting the emitter electrode 52 and the semiconductor substrate 10.

[0054] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The emitter electrode 52 may be in contact with the emitter region 12, the contact region, and the base region 14, which will be described later. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0055] The semiconductor substrate 10 has an N--type drift region 18. The doping concentration of the drift region 18 may coincide with the bulk donor concentration, or may coincide with the bulk net doping concentration, which is the difference between the bulk donor concentration and the bulk acceptor concentration. In other examples, the doping concentration of the drift region 18 may be higher than the bulk donor concentration or the bulk net doping concentration. The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.

[0056] On the upper surface side of the semiconductor substrate 10, one or more gate trench portions 40 and dummy trench portions 30 are provided. The gate trench portion 40 functions as a gate electrode when a gate voltage is applied, and the dummy trench portion 30 does not function as a gate electrode when a gate voltage is not applied. In this specification, the gate trench portion 40 and the dummy trench portion 30 may be referred to as trench portions. The trench portions are provided in the depth direction from the upper surface 21 of the semiconductor substrate 10 to the drift region 18. Also, the trench portions extend in the extending direction (Y-axis direction) on the upper surface 21 of the semiconductor substrate 10.

[0057] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the array direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the array direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the array direction. The diode section 80 of this example is not provided with a gate trench section 40.

[0058] In the array direction, a mesa section is provided between each trench section. The mesa section refers to a region sandwiched by the trench sections inside the semiconductor substrate 10. As an example, the upper end of the mesa section is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa section is the same as the depth position of the lower end of the trench section. The mesa section of this example is provided so as to extend in the extending direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10. In this example, a mesa section 60 is provided in the transistor section 70, and a mesa section 61 is provided in the diode section 80. When simply referred to as a mesa section in this specification, each of the mesa section 60 and the mesa section 61 is indicated.

[0059] In the mesa section 60 of the transistor section 70, an N+-type emitter region 12 and a P-type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N-type accumulation region 16 may be provided in the mesa section 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0060] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench section 40. The emitter region 12 may be in contact with the trench sections on both sides of the mesa section 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0061] The base region 14 is provided below the emitter region 12. The base region 14 of this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench sections on both sides of the mesa section 60.

[0062] The storage region 16 is provided below the base region 14. The storage region 16 is an N-type region with a doping concentration higher than that of the drift region 18. By providing the high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0063] In the mesa portion 61 of the diode portion 80, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, a storage region 16 may be provided below the base region 14.

[0064] At least one of the mesa portion 60 and the mesa portion 61 may be provided with a P+-type contact region exposed on the upper surface 21 of the semiconductor substrate 10. For example, in the mesa portion 60, the contact region and the emitter region 12 may be alternately arranged along the Y-axis direction.

[0065] In each of the transistor portion 70 and the diode portion 80, an N-type buffer region 20 may be provided on the lower surface 23 side than the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 has one or a plurality of donor concentration peaks with a higher donor concentration than the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+-type collector region 22 and the N+-type cathode region 82.

[0066] In the transistor section 70, a P+-type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0067] In the diode section 80, an N+-type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements serving as donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0068] Each trench section reaches the drift region 18 through the base region 14 from the upper surface 21 of the semiconductor substrate 10. In the region where at least any one of the emitter region 12, the contact region, and the accumulation region 16 is provided, each trench section also penetrates these doping regions and reaches the drift region 18. The fact that the trench section penetrates the doping region is not limited to the case where the trench section is formed in the order of forming the doping region first and then the trench section. Even in the case where the doping region is formed between the trench sections after the trench sections are formed, it is included in the case where the trench section penetrates the doping region.

[0069] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30 and is not provided with the gate trench section 40. In this example, the boundary in the X-axis direction between the diode section 80 and the transistor section 70 is the boundary between the cathode region 82 and the collector region 22.

[0070] The gate trench portion 40 has a groove-shaped gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the upper surface 21 of the semiconductor substrate 10. The gate trench portion 40 is an example of a gate structure. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0071] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.

[0072] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross-section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 may be connected to an electrode different from the gate pad. For example, the dummy conductive portion 34 may be connected to a dummy pad (not shown) connected to an external circuit different from the gate pad, and different control may be performed from the gate conductive portion 44. Also, the dummy conductive portion 34 may be electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0073] In the cross-section, the gate trench portion 40 and the dummy trench portion 30 are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. As described above, the gate trench portion 40 may be connected to the gate wiring at any location, and the dummy trench portion 30 may be connected to the emitter electrode 52 at any location.

[0074] FIG. 3 is a diagram showing an example of the B-B cross-section in FIG. 1. The B-B cross-section is the XZ plane passing through the outer peripheral gate wiring 130 and the edge termination structure portion 90. In FIG. 3, a part of the transistor portion 70 in the vicinity of the outer peripheral gate wiring 130 is also shown.

[0075] The outer peripheral gate wiring 130 is disposed above the upper surface 21 of the semiconductor substrate 10. In this example, the outer peripheral gate wiring 130-1 and the outer peripheral gate wiring 130-2 are stacked and disposed in the Z-axis direction. The outer peripheral gate wiring 130-1 is formed of a metal material such as aluminum, and the outer peripheral gate wiring 130-2 is formed of polysilicon doped with impurities.

[0076] Note that the outer peripheral gate wiring 130-2 and the semiconductor substrate 10 are insulated from each other by an insulating film such as a thermal oxide film, which is omitted in FIG. 3. The outer peripheral gate wiring 130-2 is connected to the gate conductive portion 44 at any position.

[0077] The outer peripheral gate wiring 130-1 is disposed above the outer peripheral gate wiring 130-2. An interlayer insulating film 38 is disposed between the outer peripheral gate wiring 130-1 and the outer peripheral gate wiring 130-2. A contact hole 132 for connecting the outer peripheral gate wiring 130-1 and the outer peripheral gate wiring 130-2 is provided in the interlayer insulating film 38. The contact hole 132 may be provided along the outer peripheral gate wiring 130 so as to surround the active portion 160. The outer peripheral gate wiring 130-1 is connected to the outer peripheral gate wiring 130-2 through the contact hole 132.

[0078] A well region 11 is provided in the semiconductor substrate 10 below the outer peripheral gate wiring 130. The well region 11 is provided deeper than the base region 14 from the upper surface 21 of the semiconductor substrate 10. The well region 11 is exposed on the upper surface 21. In this specification, when it is described that a predetermined region is exposed on the upper surface 21, it includes not only the case where the region is exposed on the upper surface 21 but also the case where the region is exposed on the bottom surface of the groove formed on the upper surface 21. The region exposed on the upper surface 21 comes into contact with a member different from the semiconductor substrate, such as an insulating member or a conductive member.

[0079] The well region 11 is preferably provided deeper than the trench portion (see FIG. 2). The well region 11 is a P+-type region having a higher concentration than the base region 14. An interlayer insulating film 38 may be formed between the emitter electrode 52 and the well region 11. The well region 11 may be connected to the emitter electrode 52 through one or more contact holes formed in the interlayer insulating film 38. That is, the well region 11 may be electrically connected to the emitter electrode 52.

[0080] The well region 11 is provided overlapping with the outer peripheral gate wiring 130. The well region 11 may be provided to extend with a predetermined width also in a range where it does not overlap with the outer peripheral gate wiring 130. Further, the well region 11 may be provided along the outer peripheral gate wiring 130 so as to surround the active portion 160. The well region 11 may also be disposed below the active side gate wiring 131. By providing the well region 11, it becomes easier to extend the depletion layer spreading from the active portion 160 to the edge termination structure portion 90, and breakdown in the active portion 160 can be suppressed.

[0081] Above the well region 11, a well plate formed of a conductive member is provided. The outer peripheral gate wiring 130 is an example of the well plate. The well plate may be insulated from the well region 11 like the outer peripheral gate wiring 130, or may be electrically connected to the well region 11.

[0082] In this example, the region surrounded by the well region 11 is taken as the active portion 160. Also, the region outside the well region 11 is taken as the edge termination structure portion 90. The well region 11 may be connected to the base region 14 of the active portion 160.

[0083] The edge termination structure portion 90 has one or more guard rings 92, one or more regions 84 of the first conductivity type, and one or more field plates 93. The edge termination structure portion 90 of this example further has a plurality of insulating films 95, a plurality of field electrodes 94, an outer electrode 97, an outer plate 96, and a channel stopper 98.

[0084] The guard ring 92 is a P+-type region provided in contact with the upper surface 21 of the semiconductor substrate 10. One or more guard rings 92 are provided between the well region 11 and the edge 102 of the semiconductor substrate 10 and are exposed on the upper surface 21 of the semiconductor substrate 10. Among the one or more guard rings 92, the guard ring 92 closest to the well region 11 is defined as the first guard ring 92-1. Also, among the one or more guard rings 92, the guard rings 92 other than the first guard ring 92-1 are defined as the second guard rings 92-2. One or more second guard rings 92-2 may be provided in the edge termination structure portion 90. When referring to the guard ring 92 in this specification, it refers to each of the first guard ring 92-1 and the second guard ring 92-2.

[0085] As shown in FIG. 1, each guard ring 92 surrounds the active portion 160. The lower end of the guard ring 92 may be disposed closer to the lower surface 23 side than the lower end of the base region 14. The lower end of the guard ring 92 may be disposed closer to the lower surface 23 side than the lower end of the trench portion (see FIG. 2). The lower end of the guard ring 92 may be disposed closer to the lower surface 23 side than the lower end of the well region 11, may be disposed closer to the upper surface 21 side than the lower end of the well region 11, or may be disposed at the same depth position as the lower end of the well region 11. In this example, the lower end of the guard ring 92 is disposed at the same depth position as the lower end of the well region 11.

[0086] The first conductivity type region 84 is a first conductivity type region provided between the first guard ring 92-1 and the well region 11. The first conductivity type region 84 may be exposed on the upper surface 21 of the semiconductor substrate 10. In this example, the first conductivity type region 84 is the drift region 18, but the first conductivity type region 84 may have the same concentration as the drift region 18, may be a region with a higher concentration than the drift region 18, or may be a region with a lower concentration. The first conductivity type region 84 may also be provided between two adjacent guard rings 92 in a top view. In this example, the first conductivity type region 84 is provided between each guard ring 92. The first conductivity type region 84 may also be provided between the second guard ring 92-2 and the channel stopper 98.

[0087] The insulating film 95 is provided so as to cover each of the first conductivity type regions 84. In this example, the insulating film 95 is provided so as to cover the first conductivity type regions 84 between the first guard ring 92-1 and the well region 11, between two adjacent guard rings 92, and between the second guard ring 92-2 and the channel stopper 98. The insulating film 95 may be provided so as to surround the active portion 160 along the guard ring 92.

[0088] At least a part of the insulating film 95 in this example is embedded inside the semiconductor substrate 10. That is, at least a part of the insulating film 95 is disposed below the upper surface 21 of the semiconductor substrate 10. The upper surface 21 of the semiconductor substrate 10 may refer to the uppermost surface among the surfaces made of a semiconductor material such as silicon. The thickness of the portion of the insulating film 95 below the upper surface 21 of the semiconductor substrate 10 may be greater than the thickness of the portion above the upper surface 21. The entire insulating film 95 may be provided at the same position as or below the upper surface 21 of the semiconductor substrate 10. The upper surface of the insulating film 95 in this example is at the same position as the upper surface 21 of the semiconductor substrate 10, and the entire insulating film 95 is provided from the same position as the upper surface 21 of the semiconductor substrate 10 to a position below the upper surface 21.

[0089] The insulating film 95 may have an insulating film obtained by oxidizing or nitriding the semiconductor substrate 10, may have an insulating film deposited by CVD or the like, or may have other insulating films. The insulating film 95 may be a single-layer insulating film or may be an insulating film in which a plurality of films formed by different methods are laminated. The insulating film 95 in this example is a LOCOS film formed by forming a recess in the upper surface 21 of the semiconductor substrate 10 and thermally oxidizing the semiconductor material exposed in the recess.

[0090] By providing the insulating film 95, it is possible to prevent the semiconductor substrate 10 from being exposed between the guard rings 92. That is, it is possible to prevent the semiconductor substrate 10 between the guard rings 92 from coming into contact with the conductive member. Further, by disposing at least a part of the insulating film 95 inside the semiconductor substrate 10, the unevenness on the upper surface 21 of the semiconductor substrate 10 can be reduced. As a result, it becomes easier to form a member disposed above the upper surface 21 of the semiconductor substrate 10. For example, the step of the field plate 93 can be reduced, so that it becomes easier to form the field plate 93.

[0091] The field plate 93 is a conductive member provided above the upper surface 21 of the semiconductor substrate 10. The field plate 93 in this example is formed of polysilicon doped with impurities. The field plate 93 is disposed above the guard ring 92. In this example, a field plate 93 is provided for all the guard rings 92. Each field plate 93 is electrically connected to the corresponding guard ring 92. Each field plate 93 may be in direct contact with the corresponding guard ring 92 or may be electrically connected via the corresponding field electrode 94.

[0092] Each field plate 93 is provided so as to surround the active portion 160 in a top view along the corresponding guard ring 92. The field plate 93 is disposed so as to cover at least a part of the corresponding guard ring 92. At least one field plate 93 may be disposed so as to cover the entire corresponding guard ring 92. At least one field plate 93 may be provided so as to extend to a position where it does not overlap with the corresponding guard ring 92. An insulating film such as a thermal oxide film may be provided between the field plate 93 and the semiconductor substrate 10 (or the insulating film 95).

[0093] Among the one or more field plates 93, the field plate 93 connected to the first guard ring 92-1 is defined as the first field plate 93-1. Also, among the one or more field plates 93, the field plates 93 other than the first field plate 93-1 are defined as the second field plates 93-2. One or more second field plates 93-2 may be provided in the edge end structure portion 90. When referring to the field plate 93 in this specification, it refers to each of the first field plate 93-1 and the second field plate 93-2.

[0094] The field electrode 94 in this example is formed of a metal material such as aluminum. The field electrode 94 is disposed above the field plate 93. The field electrode 94 is provided for at least one field plate 93. The field electrode 94 may be provided one by one for all the field plates 93.

[0095] An interlayer insulating film 38 is disposed between the field electrode 94 and the field plate 93. The interlayer insulating film 38 is also provided between the outer peripheral gate wiring 130-2 and the first field plate 93-1, between two field plates 93, and between the second field plate 93-2 and the outer plate 96. The interlayer insulating film 38 may be connected to the insulating film 95.

[0096] The field electrode 94 and the field plate 93 are connected through a contact hole provided in the interlayer insulating film 38. Although the contact hole is not shown in the cross section shown in FIG. 3, in other cross sections, the contact hole is provided in the interlayer insulating film 38. As an example, contact holes may be provided at the four corners of the semiconductor substrate 10 in the edge termination structure portion 90, and the field electrode 94 and the field plate 93 may be connected through the contact holes. Thus, the field electrode 94 and the field plate 93 are electrically connected and can have the same potential as each other. Further, the interlayer insulating film 38 may be provided with a contact hole for connecting the field electrode 94 and the guard ring 92. Each field electrode 94 is electrically floating. For example, when a voltage V CE is applied to the collector electrode 24 with the gate of the semiconductor device 100 off, a predetermined voltage lower than the voltage V CE is applied to each field electrode 94.

[0097] The channel stopper 98 is provided in contact with the edge 102 and the upper surface 21 of the semiconductor substrate 10. The channel stopper 98 is of P-type having the same or higher concentration than the base region 14, or of N-type having a higher concentration than the drift region 18. The outer plate 96 is disposed above the channel stopper 98 and is electrically connected to the channel stopper 98. The outer plate 96 is formed of polysilicon doped with impurities. The outer plate 96 and the channel stopper 98 may be provided on an insulating film (not shown), may be connected through a contact hole provided in the insulating film, or may be in direct contact. The channel stopper 98 may be connected to the outer electrode 97 through a contact hole.

[0098] The outer electrode 97 is disposed above the outer plate 96. The outer electrode 97 is formed of a metal material such as aluminum. An interlayer insulating film 38 is provided between the outer electrode 97 and the outer plate 96. The outer electrode 97 and the outer plate 96 are connected via a contact hole provided in the interlayer insulating film 38. The contact hole may be provided in the vicinity of the corner of the semiconductor substrate 10. A predetermined voltage is applied to the outer electrode 97. The potential of the channel stopper 98 is the potential of the collector electrode 24. By setting the potential of the channel stopper 98 to the potential of the collector electrode 24, the depletion layer extending from the active portion 160 is suppressed from spreading by the outer electrode 97, preventing it from reaching the side surface of the semiconductor substrate 10. Thereby, the breakdown voltage of the semiconductor device 100 is improved. Note that the outer plate 96 may be omitted. In this case, the channel stopper 98 is connected to the outer electrode 97 via a contact hole provided in the interlayer insulating film 38.

[0099] In addition to the configuration described with reference to FIG. 3, the semiconductor device 100 may include a protective member formed of a gel or a resin. The protective member may be formed of polyimide. The protective member covers at least a part of the periphery of the semiconductor substrate 10. For example, the interlayer insulating film 38, the field electrode 94, and the outer electrode 97 provided on the upper surface 21 of the edge termination structure portion 90 are covered with the protective member.

[0100] FIG. 4 is an enlarged view of the vicinity of the well region 11 and the first guard ring 92-1. In FIG. 4, the insulating film 195 omitted in FIG. 3 is also shown. The insulating film 195 in this example is a thermal oxide film formed on the upper surface 21 of the semiconductor substrate 10 and the insulating film 95. In FIG. 4, the interlayer insulating film 38 and the like are omitted.

[0101] In this example, the well region 11 and the first guard ring 92-1 are provided down to below the insulating film 95. That is, the X-axis direction ends of the well region 11 and the first guard ring 92-1 overlap the insulating film 95 below the insulating film 95. A first conductivity type region 84 is provided in a portion sandwiched between the well region 11 and the first guard ring 92-1 in a top view. Let the length of the first conductivity type region 84 be L1. The length L1 may be the length of the first conductivity type region 84 at a position in contact with the insulating film 95. The length L1 may be the shortest distance between the well region 11 and the first guard ring 92-1 in a top view.

[0102] The first field plate 93-1 has an upper portion 86, an inner extension portion 88, and an outer extension portion 89. The upper portion 86, the inner extension portion 88, and the outer extension portion 89 in this example are formed of the same material. The upper portion 86 is disposed above the first guard ring 92-1 and is a portion that overlaps the first guard ring 92-1 in a top view. The upper portion 86 may be connected to the first guard ring 92-1. The upper portion 86 in this example is connected to the first guard ring 92-1 through a contact hole provided in the insulating film 195.

[0103] The outer extension portion 89 is a portion that extends from the upper portion 86 in a direction opposite to the well region 11 in a top view. That is, the outer extension portion 89 is a portion that extends from the upper portion 86 toward the edge 102 of the semiconductor substrate 10. The first guard ring 92-1 may not have the outer extension portion 89.

[0104] The inner extension portion 88 is provided to extend from the upper portion 86 in the direction of the well region 11 in a top view. FIG. 4 shows the inner extension portion 88 that extends in a direction parallel to the X-axis from the upper portion 86. An insulating film 95 and an insulating film 195 are provided between the inner extension portion 88 and the semiconductor substrate 10. Let the length of the inner extension portion 88 in a top view be L2. The length L2 is the length in the same direction as the length L1.

[0105] The inner extension 88 is provided to overlap with 90% or more of the first conductivity type region 84 between the first guard ring 92-1 and the well region 11. The overlapping ratio of the inner extension 88 and the first conductivity type region 84 may be the area ratio in top view or the length ratio in any cross-section. That is, the inner extension 88 may cover 90% or more of the area of the first conductivity type region 84 in top view. Or, in any cross-section perpendicular to the XY plane, the length L2 of the inner extension 88 may be 90% or more of the length L1 of the first conductivity type region 84.

[0106] The overlapping ratio of the inner extension 88 and the first conductivity type region 84 may be 95% or more, or may be 100% or more. The inner extension 88 may be provided to the position overlapping with the well region 11 in top view. The overlapping ratio of the inner extension 88 and the first conductivity type region 84 may be 120% or less, may be 110% or less, or may be 105% or less. By covering most or all of the first conductivity type region 84 with the inner extension 88, the breakdown voltage of the semiconductor device 100 can be improved.

[0107] FIG. 5 is a diagram for explaining a comparative example. In the comparative example, the first field plate 93-1 hardly or does not cover the first conductivity type region 84 at all. When the semiconductor device 100 is used, charges 72 may be accumulated on the upper surface of the interlayer insulating film 38. The charges 72 in this example are positive charges. For example, charged particles such as ions contained in the protective member covering the semiconductor device 100 may gather at the edge termination structure portion 90 where a voltage is applied. Since the electrodes such as the field plate 93 of the edge termination structure portion 90 are floating electrodes, these charged particles remain in the edge termination structure portion 90 without being drawn out through the electrodes of the edge termination structure portion 90. These charged particles pass through the protective member and are distributed at the interface between the protective member and the interlayer insulating film 38 (that is, the upper surface of the interlayer insulating film 38).

[0108] When charges 72 accumulate on the upper surface of the interlayer insulating film 38, opposite-polarity charges 74 are induced on the upper surface 21 of the semiconductor substrate 10 disposed with a dielectric such as an insulating film interposed therebetween. The charge 74 in this example is a negative charge. When the charge 74 is induced, the way the depletion layer extends in the edge termination structure portion 90 changes, and the breakdown voltage may decrease. In particular, when a first conductivity type region 84 having a relatively low doping concentration, such as the drift region 18, is exposed on the upper surface 21 of the semiconductor substrate 10, the ratio of the density of the charge 74 induced on the upper surface of the first conductivity type region 84 becomes relatively large with respect to the doping concentration of the first conductivity type region 84. For this reason, even a small amount of the charge 74 affects the breakdown voltage. In particular, when the charge 74 is induced in the first conductivity type region 84 between the well region 11 and the first guard ring 92-1, the influence on the breakdown voltage becomes large.

[0109] In contrast, in the example described with reference to FIGS. 1 to 4, the first field plate 93-1 covers 90% or more of the first conductivity type region 84 between the well region 11 and the first guard ring 92-1. For this reason, the induction of the charge 74 in the first conductivity type region 84 can be inhibited, and a decrease in the breakdown voltage can be suppressed.

[0110] FIG. 6 is a diagram showing another structural example of the inner extension portion 88 of the first field plate 93-1. The structure other than the inner extension portion 88 is the same as any of the examples described in this specification and the drawings. The inner extension portion 88 in this example is arranged so as not to overlap the well region 11. That is, the length L2 of the inner extension portion 88 is smaller than the length L1 of the first conductivity type region 84. However, as described above, the length L2 is 90% or more of the length L1.

[0111] In the example of FIG. 6, the outer peripheral gate wiring 130-2 is provided in a range overlapping with the well region 11. In other examples, the outer peripheral gate wiring 130-2 may extend to a position overlapping with the first conductivity type region 84 between the well region 11 and the first guard ring 92-1. However, the first conductivity type region 84 in this example has a portion 83 that does not overlap with either the first field plate 93-1 or the outer peripheral gate wiring 130-2 in the direction (for example, the X-axis direction) connecting the well region 11 and the first guard ring 92-1. The distance between the portion 83 and the well region 11 is smaller than the distance between the portion 83 and the first guard ring 92-1.

[0112] FIG. 7 is a diagram for explaining the change in the breakdown voltage of the semiconductor device 100. FIG. 7 shows a charge amount - breakdown voltage characteristic with the amount of charge accumulated on the upper surface of the interlayer insulating film 38 between the well region 11 and the first guard ring 92-1 on the horizontal axis and the breakdown voltage of the semiconductor device 100 on the vertical axis. The positive and negative on the horizontal axis indicate the positive and negative of the charge, and the value on the horizontal axis indicates the relative value of the charge amount. The value on the vertical axis indicates the relative value of the breakdown voltage.

[0113] Characteristic 205 shows the characteristics of an example where the length L2 of the first field plate 93-1 is 0 μm, that is, an example where the first field plate 93-1 is provided only in a range overlapping with the first guard ring 92-1. Characteristic 204 is the characteristic of an example where the length L1 - L2 is 2.0 μm, that is, the length of the portion 83 (see FIG. 6) is 2.0 μm. Characteristic 203 is the characteristic of an example where the length L1 - L2 of the portion 83 is 1.0 μm. Note that in characteristic 203, the ratio of the length L2 to the length L1 is 90% or more. Characteristic 202 is the characteristic of an example where the length L1 - L2 is 0 μm, that is, an example where the end position of the first field plate 93-1 coincides with the end position of the well region 11. Characteristic 201 is the characteristic of an example where the length L1 - L2 is -1.0 μm, that is, an example where the length of the overlapping portion between the first field plate 93-1 and the well region 11 is 1.0 μm.

[0114] As shown in characteristic 205, when the first field plate 93-1 does not completely cover the first conductivity type region 84, charges accumulate on the upper surface of the interlayer insulating film 38, resulting in a large variation in breakdown voltage. In characteristic 204, the first field plate 93-1 covers the first conductivity type region 84, but the portion 83 is relatively large. In this case, charges accumulate on the upper surface of the interlayer insulating film 38, causing the breakdown voltage to vary.

[0115] On the other hand, as shown in characteristics 201, 202, and 203, when the first field plate 93-1 covers 90% or more of the first conductivity type region 84, even if charges accumulate on the upper surface of the interlayer insulating film 38, the breakdown voltage hardly varies. That is, by having the first field plate 93-1 cover 90% or more of the first conductivity type region 84, a significant reduction in the breakdown voltage of the semiconductor device 100 can be suppressed.

[0116] FIG. 8 is a diagram showing another structural example of the edge termination structure portion 90. The structure of the edge termination structure portion 90 in this example, except for the second field plate 93-2, is the same as any of the examples described in this specification and the drawings.

[0117] In this example, at least one second field plate 93-2 is provided from above the corresponding second guard ring 92-2 to above the other adjacent guard ring 92 in a top view. That is, the first conductivity type region 84 between each guard ring 92 is covered by the second field plate 93-2. In other examples, the ratio of the second field plate 93-2 covering the first conductivity type region 84 may be 90% or more, or may be 95% or more. In this example, the second field plate 93-2 connected to the outer (edge 102 side) second guard ring 92-2 extends toward the inner (well region 11 side) guard ring 92.

[0118] The second field plate 93-2 may cover a part of another adjacent guard ring 92. However, the second field plate 93-2 does not cover the whole of the other guard ring 92. In this case, above the other guard ring 92, a field plate 93 connected to the guard ring 92 and a second field plate 93-2 extending from the adjacent guard ring 92 are arranged.

[0119] As shown in FIG. 8, all the second field plates 93-2 may extend toward the adjacent guard ring 92. Each second field plate 93-2 may cover 90% or more, 95% or more, or even 100% of the first conductivity type region 84.

[0120] Also, the second field plate 93-2 connected to the second guard ring 92-2 adjacent to the channel stopper 98 may be provided to extend toward the channel stopper 98. The second field plate 93-2 may cover a part of the first conductivity type region 84 between the second guard ring 92-2 and the channel stopper 98, or may cover the whole. In the example of FIG. 8, the second field plate 93-2 covers a part of the first conductivity type region 84. The second field plate 93-2 may extend to a position overlapping with the outer plate 96 or the outer electrode 97. Thereby, the entire first conductivity type region 84 can be covered by the second field plate 93-2, the outer plate 96, and the outer electrode 97.

[0121] FIG. 9 is a diagram showing another example of the semiconductor device 100. The structure of the semiconductor device 100 in this example is the same as any of the examples described in this specification and the drawings except for the insulating film 95. At least a part of the insulating film 95 in this example is disposed above the upper surface 21 of the semiconductor substrate 10. The upper surface 21 in this case refers to the uppermost surface among the surfaces of the semiconductor substrate 10. That is, when a groove is formed in the upper surface 21, the bottom surface of the groove does not correspond to the upper surface 21 in this example.

[0122] The insulating film 95 may have 50% or more of its thickness in the Z-axis direction disposed above the upper surface 21, may have 80% or more of its thickness disposed above the upper surface 21, or may have 100% of its thickness disposed above the upper surface 21. The insulating film 95 in this example is a thermal oxide film formed by oxidizing the flat upper surface 21. According to this example, the insulating film 95 can be easily formed. In any of the examples described in this specification and the drawings, the insulating film 95 shown in FIG. 3 may be applied, or the insulating film 95 shown in FIG. 9 may be applied.

[0123] FIG. 10 is a diagram showing another example of the semiconductor device 100. The structure of the semiconductor device 100 in this example, except for the first field plate 93-1 and the outer peripheral gate wiring 130, is the same as any of the examples described in this specification and the drawings. The first field plate 93-1 and the outer peripheral gate wiring 130 in this example are arranged so as to overlap in a top view. In the example of FIG. 10, the first field plate 93-1 and the outer peripheral gate wiring 130-1 overlap, but the first field plate 93-1 and the outer peripheral gate wiring 130-2 may also overlap. The first field plate 93-1 in this example may cover only a part of the first conductivity type region 84 between the well region 11 and the first guard ring 92-1, or may cover the whole.

[0124] FIG. 11 is a diagram for explaining the thickness t of the insulating film provided between the field plate 93 and the semiconductor substrate 10. In FIG. 11, the thickness t of the insulating film below the first field plate 93-1 is explained, but the thickness t of the insulating film below the second field plate 93-2 may be the same. In this example, the sum of the thicknesses of the insulating film 95 and the insulating film 195 below the first field plate 93-1 is defined as t. Also, the insulating film 95 and the insulating film 195 are collectively referred to as the insulating film 95 and the like.

[0125] Since the first field plate 93-1 extends toward the well region 11, the equipotential lines 110 that enter from the first conductivity type region 84 into the insulating film 95 or the like extend in the X-axis direction inside the insulating film 95 or the like. For this reason, when the thickness t of the insulating film 95 or the like is small, the interval between the equipotential lines 110 becomes small inside the insulating film 95 or the like, and the electric field strength applied per unit thickness of the insulating film 95 or the like increases. Therefore, it is preferable that the thickness t (cm) of the insulating film 95 or the like satisfies the following formula. The thickness t may be the thickness in the Z-axis direction. (φ0 - φ1) / E C <t ··· Equation (1) Here, φ0 is the potential of the well region (in this example, the emitter potential, V) when a reverse bias of the rated voltage is applied between the emitter electrode 52 and the collector electrode 24, φ1 is the potential (V) of the first field plate 93-1 when a reverse bias of the rated voltage is applied between the emitter electrode 52 and the collector electrode 24, and E C is the critical electric field strength (V / cm). Also, it is preferable that the thickness t of the insulating film or the like below the second field plate 93-2 satisfies the following formula. (φ n - φ n+1 ) / E C <t ··· Equation (2) Here, φ n+1 is the potential of the second field plate 93-2 when a reverse bias of the rated voltage is applied between the emitter electrode 52 and the collector electrode 24, and φ n is the potential of the field plate 93 disposed one inside from the second field plate 93-2 when a reverse bias of the rated voltage is applied between the emitter electrode 52 and the collector electrode 24.

[0126] The potential difference φ0 - φ1 or φ n - φ n+1The rated voltage described above may be approximated using a value X obtained by dividing the rated voltage by the number of guard rings 92 arranged from the well region 11 to the edge 102. For example, when the rated voltage is 1200V and the number of guard rings 92 is 12, the potential difference described above can be approximated using X = 100V. The potential difference described above may be 0.5 times or more and 2 times or less the value X. The potential difference described above may be 0.7 times or more the value X, may be 0.9 times or more the value X, or may be 1 time the value X. The potential difference described above may be 1.5 times or less the value X, or may be 1.1 times or less the value X. Note that the above potential can be calculated by well-known device simulation.

[0127] FIG. 12 is a diagram showing a structural example of the field plate 93. Although the first field plate 93-1 is shown, the second field plate 93-2 may have a similar structure. The inner extension 88 of the first field plate 93-1 in this example has a first portion 121 and a second portion 122.

[0128] The first portion 121 is connected to the upper portion 86 and extends in the direction from the upper portion 86 toward the well region 11. The first portion 121 is disposed above the first conductivity type region 84. The second portion 122 is connected to the first portion 121 and extends in the direction from the first portion 121 toward the well region 11. The first portion 121 may extend up to above the well region 11 and may be provided so as not to overlap the well region 11.

[0129] At least a part of the second portion 122 is disposed above the first portion 121. Thereby, the thickness of the insulating film 95 below the second portion 122 is larger than the thickness of the insulating film 95 below the first portion 121. The thickness of the insulating film 95 below the second portion 122 may be 1.3 times or more, may be 1.5 times or more, or may be 2 times or more the thickness of the insulating film 95 below the first portion 121.

[0130] As it approaches the tip of the inner extension 88, the number of equipotential lines 110 extending in the X-axis direction inside the insulating film 95 increases, making the electric field prone to concentration. In contrast, according to this example, since the thickness of the insulating film 95 below the vicinity of the tip of the inner extension 88 can be increased, electric field concentration can be alleviated and dielectric breakdown can be suppressed.

[0131] In FIG. 12, the inner extension 88 has been described as an example, but the outer extension 89 may have a first portion 121 and a second portion 122. In this case, the first portion 121 is a portion connected to the upper portion 86 and extending in the direction of the end side 102. Also, the second portion 122 is a portion connected to the first portion 121 and extending in the direction of the end side 102.

[0132] Also, the outer peripheral gate wiring 130 may have a first portion 121 and a second portion 122. In the example of FIG. 12, the outer peripheral gate wiring 130-2 has a first portion 121 and a second portion 122.

[0133] FIG. 13 is a diagram showing another structural example of the inner extension 88. The inner extension 88 of this example has a second portion 122. The second portion 122 of this example is connected to the upper portion 86 and extends toward the well region 11. The second portion 122 is disposed above the upper portion 86. Also according to this example, electric field concentration in the insulating film 95 can be alleviated. Similar to the example described in FIG. 12, the structure shown in FIG. 13 may be applied to the outer extension 89, may be applied to at least one of the inner extension 88 or the outer extension 89 of the second field plate 93-2, and may also be applied to the outer peripheral gate wiring 130.

[0134] FIG. 14 is a diagram showing a structural example of the first field plate 93-1 and the outer peripheral gate wiring 130. The structures other than the first field plate 93-1 and the outer peripheral gate wiring 130 are the same as any of the examples described in this specification and the drawings.

[0135] The first field plate 93-1 in this example is provided up to a position overlapping with the outer peripheral gate wiring 130. In the example of FIG. 14, the first field plate 93-1 overlaps with the outer peripheral gate wiring 130-2. The length L2 of the first field plate 93-1 may be shorter than the length L1 of the first conductivity type region 84, may be the same as the length L1, or may be longer than the length L1.

[0136] The outer peripheral gate wiring 130-2 may be provided to extend up to a position overlapping with the first conductivity type region 84. A part of the inner extension 88 of the first field plate 93-1 in this example is provided between the outer peripheral gate wiring 130-2 and the semiconductor substrate 10. An insulating film 95 that separates the inner extension 88 and the outer peripheral gate wiring 130-2 is provided between the inner extension 88 and the outer peripheral gate wiring 130-2. The equipotential line 110 in FIG. 11 passes through the insulating film 95. It is also preferable that the thickness t2 of the insulating film 95 between the inner extension 88 and the outer peripheral gate wiring 130-2 satisfies the formula (1). Do A part of the inner extension 88 of the first field plate 93-1 is provided between the outer peripheral gate wiring 130-2 and the semiconductor substrate 10. An insulating film 95 that separates the inner extension 88 and the outer peripheral gate wiring 130-2 is provided between the inner extension 88 and the outer peripheral gate wiring 130-2. The equipotential line 110 in FIG. 11 passes through the insulating film 95. It is also preferable that the thickness t2 of the insulating film 95 between the inner extension 88 and the outer peripheral gate wiring 130-2 satisfies the formula (1).

[0137] According to this example, even if charges reach the upper surface of the insulating film 95 between the inner extension 88 and the outer peripheral gate wiring 130-2, they can be drawn out by the outer peripheral gate wiring 130-2, so charge accumulation can be suppressed. Also, by providing the first field plate 93-1 with a higher potential below the outer peripheral gate wiring 130-2, the depletion layer is less likely to extend in the X-axis direction, and the edge termination structure portion 90 can be shortened.

[0138] The length L2 of the inner extension 88 of the first field plate 93-1 overlapping with the first conductivity type region 84 may be larger than the length L3 of the outer peripheral gate wiring 130-2 overlapping with the first conductivity type region 84. The relationship of L2>L3 is the same even when the inner extension 88 does not overlap with the outer peripheral gate wiring 130-2.

[0139] FIG. 15 is a diagram showing an example of the structure of the second field plate 93-2. In FIG. 15, two adjacent second guard rings 92-2a and 92-2b and two adjacent second field plates 93-2a and 93-2b are shown. The second field plate 93-2b is disposed outside the second field plate 93-2a. The second guard ring 92-2b is disposed outside the second guard ring 92-2a.

[0140] The two adjacent second field plates 93-2 in this example have overlapping portions in a top view. Similar to the example of FIG. 14 in this example, among the two second field plates 93-2 that overlap each other, a part of the second field plate 93-2b disposed farther from the well region 11 is disposed below the other second field plate 93-2a.

[0141] Each second field plate 93-2 has an upper portion 86, an inner extension 88, and an outer extension 89, similar to the first field plate 93-1. The inner extension 88 of the outer second field plate 93-2b is provided to a position overlapping the outer extension 89 of the inner second field plate 93-2a. The length L4 of each inner extension 88 may be shorter than the length L1 of the first conductivity type region 84, may be the same as the length L1, or may be longer than the length L1.

[0142] Each outer extension 89 may be extended and provided to a position overlapping the first conductivity type region 84. In this example, a part of the inner extension 88 of the outer second field Do plate 93-2b is provided between the outer extension 89 of the inner second field plate 93-2a and the semiconductor substrate 10. An insulating film 95 for separating the inner extension 88 and the outer extension 89 is provided between the inner extension 88 and the outer extension 89. The thickness t4 of the insulating film 95 for separating the inner extension 88 and the outer extension 89 preferably satisfies Equation (2). Also, the thickness t3 of the insulating film 95 or the like below the inner extension 88 preferably satisfies Equation (2).

[0143] The length L4 of the inner extension 88 of the outer second field plate 93-2b overlapping the first conductivity type region 84 may be greater than the length L5 of the outer extension 89 of the inner second field plate 93-2a overlapping the first conductivity type region 84. That is, in the direction connecting the well region 11 and the edge 102 of the semiconductor substrate 10, the inner extension 88 is longer than the outer extension 89. The relationship of L4>L5 is the same even when the inner extension 88 does not overlap the outer extension 89.

[0144] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0145] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the specification, and the drawings is not explicitly indicated as "earlier" or "preceding" etc., and unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Explanation of Reference Numerals

[0146] 10 ··· Semiconductor substrate, 11 ··· Well region, 12 ··· Emitter region, 14 ··· Base region, 16 ··· Accumulation region, 18 ··· Drift region, 20 ··· Buffer region, 21 ··· Upper surface, 22 ··· Collector region, 23 ··· Lower surface, 24 ··· Collector electrode, 30 ··· Dummy trench portion, 32 ··· Dummy insulating film, 34 ··· Dummy conductive portion, 38 ··· Interlayer insulating film, 40 ··· Gate trench portion, 42 ··· Gate insulating film, 44 ··· Gate conductive portion, 52 ··· Emitter electrode, 54 ··· Contact hole, 60, 61 ··· Mesa portion, 70 ··· Transistor portion, 72 ··· Charge, 74 ··· Charge, 80 ··· Diode portion, 81 ··· Extension region, 82 ··· Cathode region, 83 ··· Portion, 84 ··· First conductivity type region, 90 ··· Edge termination structure portion, 92 ··· Guard ring, 93 ··· Field plate, 86 ··· Upper portion, 88 ··· Inner extension portion, 89 ··· Outer extension portion, 94 ··· Field electrode, 95 ··· Insulating film, 96 ··· Outer plate, 97 ··· Outer electrode, 98 ··· Channel stopper, 100 ··· Semiconductor device, 102 ··· Edge side, 110 ··· Iso-potential line, 112 ··· Gate pad, 121 ··· First portion, 122 ··· Second portion, 130 ··· Outer peripheral gate wiring, 131 ··· Active side gate wiring, 132 ··· Contact hole, 160 ··· Active portion, 195 ··· Insulating film, 201, 202, 203, 204, 205 ··· Characteristics

Claims

1. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type; An active portion provided on the semiconductor substrate and including a transistor portion that operates in response to a gate voltage; An edge termination structure portion provided between the active portion and an edge of the semiconductor substrate in the semiconductor substrate; A well region of a second conductivity type provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate; A well plate provided entirely above the well region and to which the gate voltage is applied and comprising; The edge termination structure portion is One or more guard rings of a second conductivity type provided between the well region and the edge of the semiconductor substrate and exposed on the upper surface of the semiconductor substrate; A first guard ring closest to the well region among the one or more guard rings, and a first conductivity type region provided between the first guard ring and the well region; A first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring and having; The first field plate is An upper portion overlapping the first guard ring above the first guard ring; An extending portion extending from the upper portion in the direction of the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region A semiconductor device including.

2. The semiconductor device according to claim 1, wherein the first field plate contains polysilicon.

3. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type; An active portion provided on the semiconductor substrate; An edge termination structure portion provided between the active portion and the edge of the semiconductor substrate in the semiconductor substrate; A second conductivity type well region provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate; Comprising: The edge termination structure portion: One or more second conductivity type guard rings provided between the well region and the edge of the semiconductor substrate and exposed on the upper surface of the semiconductor substrate; A first conductivity type region provided between the first guard ring closest to the well region among the one or more guard rings and the well region; A first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring; Having: The first field plate: An upper portion overlapping the first guard ring above the first guard ring; An extending portion extending from the upper portion in the direction of the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region; Including: The extending portion does not overlap with the well region in top view; A semiconductor device.

4. The semiconductor device according to claim 3, further comprising an outer peripheral gate wiring insulated from the extending portion by an insulating film, wherein an outer peripheral side end portion of the outer peripheral gate wiring is provided above the extending portion so as to overlap with the extending portion in top view. The semiconductor device according to claim 3.

5. A semiconductor substrate having an upper surface and a lower surface and provided with a first conductivity type drift region; An active portion provided on the semiconductor substrate; An edge termination structure portion provided between the active portion and the edge of the semiconductor substrate in the semiconductor substrate; A second conductivity type well region provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate; is provided with The edge end structure portion is provided with one or more between the well region and the end side of the semiconductor substrate, and a guard ring of the second conductivity type exposed on the upper surface of the semiconductor substrate, a first guard ring closest to the well region among the one or more guard rings, and a first conductivity type region provided between the first guard ring and the well region, a first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring and has The first field plate has an upper portion overlapping the first guard ring above the first guard ring, and an extension portion extending from the upper portion in the direction of the well region and overlapping 90% or more of the first conductivity type region between the first guard ring and the well region and includes further includes a well plate provided above the well region, In the direction connecting the well region and the first guard ring, the length of the extension portion of the first field plate overlapping the first conductivity type region is larger than the length of the well plate overlapping the first conductivity type region semiconductor device.

6. In the direction connecting the well region and the first guard ring, the first conductivity type region has a portion that does not overlap with either the first field plate or the well plate The semiconductor device according to claim 5.

7. The first field plate is provided up to a position overlapping the well region The semiconductor device according to claim 1.

8. The first field plate is provided up to a position overlapping the well plate The semiconductor device according to claim 5.

9. An insulating film for separating the first field plate and the well plate is provided between the first field plate and the well plate. The semiconductor device according to claim 8.

10. A part of the first field plate is provided between the well plate and the semiconductor substrate. The semiconductor device according to claim 8.

11. Further provided with one or more second field plates provided above the upper surface of the semiconductor substrate and connected to the guard rings other than the first guard ring, At least one of the second field plates is provided from above one of the guard rings to above another adjacent guard ring. The semiconductor device according to any one of claims 1 to 10.

12. At least one of the second field plates covers a part of another adjacent guard ring. The semiconductor device according to claim 11.

13. Further provided with two or more second field plates provided above the upper surface of the semiconductor substrate and connected to the guard rings other than the first guard ring, Two second field plates provided on two adjacent guard rings have overlapping portions with each other. The semiconductor device according to any one of claims 1 to 10.

14. A semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, An active portion provided on the semiconductor substrate, An edge termination structure portion provided between the active portion and the edge of the semiconductor substrate in the semiconductor substrate, A well region of a second conductivity type provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate is provided with The edge termination structure part One or more are provided between the well region and the end side of the semiconductor substrate, and a guard ring of the second conductivity type exposed on the upper surface of the semiconductor substrate A first guard ring closest to the well region among the one or more guard rings, and a first conductivity type region provided between the first guard ring and the well region A first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring has The first field plate An upper part overlapping the first guard ring above the first guard ring, and An extension part extending from the upper part in the direction of the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region includes Further provided above the upper surface of the semiconductor substrate, and two or more second field plates connected to guard rings other than the first guard ring Two second field plates provided on two adjacent guard rings have a portion overlapping with each other Among the two second field plates overlapping with each other, the second field plate arranged farther from the well region is arranged below the other second field plate Semiconductor device.

15. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of the first conductivity type An active part provided on the semiconductor substrate An edge termination structure part provided between the active part and the end side of the semiconductor substrate on the semiconductor substrate A well region of the second conductivity type provided between the active part and the edge termination structure part on the semiconductor substrate and exposed on the upper surface of the semiconductor substrate is provided with The edge end structure part is provided with one or more between the well region and the edge of the semiconductor substrate, and a guard ring of a second conductivity type exposed on the upper surface of the semiconductor substrate, a first guard ring closest to the well region among the one or more guard rings, and a first conductivity type region provided between the first guard ring and the well region, a first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring and has The first field plate is an upper part overlapping the first guard ring above the first guard ring, an extension part extending from the upper part in the direction of the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region and includes further includes two or more second field plates provided above the upper surface of the semiconductor substrate and connected to the guard rings other than the first guard ring, two second field plates provided on two adjacent guard rings have a portion overlapping with each other, each of the two second field plates overlapping with each other has an upper part overlapping the guard ring above the guard ring, among the two second field plates overlapping with each other, the second field plate arranged farther from the well region has an inner extension part extending from the upper part in the direction of the well region, among the two second field plates overlapping with each other, the other second field plate has an outer extension part extending from the upper part in the direction opposite to the well region, In the direction connecting the well region and the edge of the semiconductor substrate, the inner extension part is longer than the outer extension part semiconductor device.

16. Further comprising an insulating film provided between the first field plate and the semiconductor substrate, At least a part of the insulating film is disposed inside the semiconductor substrate The semiconductor device according to any one of claims 1 to 10.

17. Further comprising an insulating film provided between the first field plate and the semiconductor substrate, At least a part of the insulating film is disposed above the upper surface of the semiconductor substrate The semiconductor device according to any one of claims 1 to 10.

18. A semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, An active portion provided on the semiconductor substrate, An edge termination structure portion provided between the active portion and an edge of the semiconductor substrate in the semiconductor substrate, A well region of a second conductivity type provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate, and Comprising The edge termination structure portion is One or more guard rings of the second conductivity type provided between the well region and the edge of the semiconductor substrate and exposed on the upper surface of the semiconductor substrate, A first conductive type region provided between the first guard ring closest to the well region among the one or more guard rings and the well region, A first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring Having The first field plate is An upper portion overlapping the first guard ring above the first guard ring, A stretching portion extending from the upper portion in the direction of the well region and overlapping with 90% or more of the first conductive type region between the first guard ring and the well region, Including further comprising an insulating film provided between the first field plate and the semiconductor substrate, at least a part of the insulating film is disposed inside the semiconductor substrate, the thickness of the insulating film provided below the first field plate satisfies the following formula (φ ０ - φ １ ) / E Ｃ < t where φ ０ is the potential of the well region, φ １ is the potential of the first field plate, t is the thickness of the insulating film, and E Ｃ is the critical electric field strength of the insulating film semiconductor device.

19. The extension portion of the first field plate is connected to the upper portion and includes a first portion extending in the direction from the upper portion to the well region, and a second portion connected to the first portion, extending in the direction from the first portion to the well region, and at least a part of which is disposed above the first portion The semiconductor device according to any one of claims 1 to 10.

20. A base region of a second conductivity type is provided in the active portion, The well region is provided deeper than the base region from the upper surface of the semiconductor substrate The semiconductor device according to any one of claims 1 to 10.

21. A semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, an active portion provided on the semiconductor substrate, an edge termination structure portion provided between the active portion and an edge of the semiconductor substrate in the semiconductor substrate, a well region of a second conductivity type provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate and The edge termination structure part is One or more are provided between the well region and the end side of the semiconductor substrate, and a guard ring of the second conductivity type exposed on the upper surface of the semiconductor substrate; A first guard ring closest to the well region among the one or more guard rings, and a first conductivity type region provided between the first guard ring and the well region; A first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring and has The first field plate is An upper part overlapping the first guard ring above the first guard ring, and An extending part extending from the upper part toward the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region including A channel stopper provided in contact with the end side and the upper surface of the semiconductor substrate; One or more second field plates provided above the upper surface of the semiconductor substrate and connected to the guard rings other than the first guard ring; It further includes a first conductivity type region provided between the guard ring connected to the second field plate adjacent to the channel stopper and the channel stopper; The second field plate adjacent to the channel stopper covers all of the first conductivity type region between the guard ring and the channel stopper Semiconductor device.

22. A semiconductor substrate having an upper surface and a lower surface and provided with a drift region of the first conductivity type, An active part provided on the semiconductor substrate, An edge termination structure part provided between the active part and the end side of the semiconductor substrate in the semiconductor substrate, A well region of the second conductivity type provided between the active part and the edge termination structure part in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate comprises wherein the edge termination structure includes one or more second conductivity type guard rings provided between the well region and the edge of the semiconductor substrate and exposed on the upper surface of the semiconductor substrate, a first guard ring closest to the well region among the one or more guard rings, a first conductivity type region provided between the first guard ring and the well region, a first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring and has wherein the first field plate has an upper portion overlapping the first guard ring above the first guard ring, and an extending portion extending from the upper portion toward the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region and includes two or more second field plates provided above the upper surface of the semiconductor substrate and connected to the guard rings other than the first guard ring, further includes an insulating film provided between the second field plate and the semiconductor substrate, wherein the thickness of the insulating film provided below the second field plate satisfies the following formula (φ ｎ −φ ｎ＋１ ) / E Ｃ <t where φ ｎ＋１ is the potential of the second field plate, φ ｎ is the potential of the second field plate disposed on one well region side more than the second field plate, t is the thickness of the insulating film, and E Ｃ is the critical electric field strength of the insulating film a semiconductor device.

23. A semiconductor substrate having an upper surface and a lower surface and provided with a first conductivity type drift region, an active portion provided on the semiconductor substrate, An edge termination structure portion provided between the active portion and the edge of the semiconductor substrate in the semiconductor substrate, A second conductivity type well region provided between the active portion and the edge termination structure portion in the semiconductor substrate and exposed on the upper surface of the semiconductor substrate, and comprising, The edge termination structure portion is One or more second conductivity type guard rings provided between the well region and the edge of the semiconductor substrate and exposed on the upper surface of the semiconductor substrate, A first conductivity type region provided between the first guard ring closest to the well region among the one or more guard rings and the well region, A first field plate provided above the upper surface of the semiconductor substrate and connected to the first guard ring, and having, The first field plate is An upper portion overlapping the first guard ring above the first guard ring, An extension portion extending from the upper portion in the direction of the well region and overlapping with 90% or more of the first conductivity type region between the first guard ring and the well region, and including, Further comprising two or more second field plates provided above the upper surface of the semiconductor substrate and connected to the guard rings other than the first guard ring, Two second field plates provided on two adjacent guard rings have a portion overlapping each other, Further comprising an insulating film separating two second field plates provided on two adjacent guard rings, The thickness of the insulating film satisfies the following formula (φ ｎ - φ ｎ＋１ ) / E Ｃ < t However, φ ｎ＋１ is the potential of the second field plate, φ ｎis the potential of the second field plate disposed on the well region side by one than the second field plate, t is the thickness of the insulating film, E Ｃ is the critical electric field strength of the insulating film Semiconductor device.

Images