Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device 10 according to the present invention comprises a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, an n-type drift layer 38, and an n-type high-concentration layer 39. The n-type high-concentration layer is in contact with at least a part of the lower surface of a p-type deep layer corresponding thereto among the plurality of p-type deep layers, and has a higher n-type impurity concentration than the drift layer.

Description

Cross-reference to Related Applications

[0001] This application is a related application of Japanese Patent Application No. 2022-066834 filed on April 14, 2022, claims priority based on this Japanese patent application, and incorporates all the contents described in this Japanese patent application as constituting this specification.

Technical Field

[0002] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0003] Japanese Unexamined Patent Application Publication Nos. 2003-309261 and 2017-152488 disclose a semiconductor device in which p-type layers and n-type layers are alternately and repeatedly arranged in the plane direction of a semiconductor substrate. When this semiconductor device is turned off, a plurality of p-type layers and a plurality of n-type layers are depleted, and the voltage between the source and the drain is maintained.

Summary of the Invention

[0004] In such a semiconductor device having a plurality of p-type layers and a plurality of n-type layers, there is a trade-off relationship between the on-resistance and the breakdown voltage. This specification proposes a technique for improving the trade-off existing between the on-resistance and the breakdown voltage.

[0005] The semiconductor device disclosed in this specification can include a semiconductor substrate provided with trenches on its upper surface, a gate insulating film covering the inner surface of the trenches, and a gate electrode disposed in the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes an n-type source layer in contact with the gate insulating film on the side surface of the trench, a p-type body layer in contact with the gate insulating film on the side surface of the trench located below the source layer, a plurality of p-type deep layers, each extending from the body layer below the bottom surface of the trench, and extending along a first direction and spaced apart from each other in a second direction orthogonal to the first direction when viewed from above the semiconductor substrate, a plurality of n-type deep layers, each disposed in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers and in contact with the gate insulating film on the side surface of the trench located below the body layer, an n-type drift layer disposed below the plurality of p-type deep layers and the plurality of n-type deep layers and in contact with the plurality of n-type deep layers, and an n-type high-concentration layer in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and having a higher concentration of n-type impurities than the drift layer.

[0006] In the above semiconductor device, since the n-type high-concentration layer is provided so as to be in contact with at least a part of the lower surface of the p-type deep layer, the spread of the depletion layer from the p-type deep layer toward the drift layer when turned on can be suppressed. Therefore, in the above semiconductor device, a wide current path is ensured, so that it can have the characteristic of low on-resistance. Further, the n-type high-concentration layer is partially provided so as to be in contact with the lower surface of the p-type deep layer. Therefore, in the above semiconductor device, a decrease in breakdown voltage is also suppressed. The above semiconductor device can achieve both low on-resistance and high breakdown voltage.

[0007] The manufacturing method of the semiconductor device disclosed in this specification includes a deep layer forming step of forming a plurality of p-type deep layers and a plurality of n-type deep layers in an n-type epitaxial layer, wherein each of the plurality of p-type deep layers extends along a first direction and is spaced apart from each other in a second direction orthogonal to the first direction when viewing the epitaxial layer from above, and each of the plurality of n-type deep layers is disposed in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers; and an n-type high-concentration layer forming step of forming an n-type high-concentration layer that is in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the epitaxial layer. Note that the chronological order of the deep layer forming step and the n-type high-concentration layer forming step is not particularly limited.

[0008] According to this manufacturing method of the semiconductor device, a semiconductor device having both low on-resistance and high breakdown voltage can be manufactured.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, each embodiment will be described with reference to the drawings. For the purpose of clarity of illustration, only some of the repeatedly arranged components are labeled with reference numerals.

[0011] The semiconductor device 10 shown in FIGS. 1 to 5 is a type of power device called a MOSFET (metal-oxide-semiconductor field effect transistor), and has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 (one direction orthogonal to the z direction) is referred to as the x direction, and the direction orthogonal to the x direction and the z direction is referred to as the y direction. The semiconductor substrate 12 is made of silicon carbide (SiC). Note that the semiconductor substrate 12 may be made of other semiconductor materials such as silicon and gallium nitride. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 2, the plurality of trenches 14 extend long along the y direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x direction.

[0012] As shown in FIGS. 1, 2, and 5, the inner surfaces (that is, the side surfaces and the bottom surfaces) of the respective trenches 14 are covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in FIGS. 1 and 5, the upper surfaces of the respective gate electrodes 18 are covered with an interlayer insulating film 20. A source electrode 22 is provided above the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 does not exist. A drain electrode 24 is provided below the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0013] As shown in FIGS. 1, 2, and 5, the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench lower layers 35, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, a drift layer 38, a plurality of n-type high-concentration layers 39, and a drain layer 40.

[0014] Each source layer 30 is an n-type layer with a high concentration of n-type impurities. Each source layer 30 is disposed in a range that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 makes an ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the uppermost part of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 through the gate insulating film 16. Each source layer 30 extends long in the y direction along the side surface of the trench 14. That is, when looking at the semiconductor substrate 12 from above, each source layer 30 extends parallel to the longitudinal direction of the trench 14 and extends from one end to the other end of the longitudinal direction of the trench 14.

[0015] Each contact layer 32 is a p-type layer with a high concentration of p-type impurities. Each contact layer 32 is disposed in a range that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 makes an ohmic contact with the source electrode 22. Each contact layer 32 extends long in the y direction. That is, when looking at the semiconductor substrate 12 from above, each contact layer 32 extends parallel to the longitudinal direction of the trench 14 and extends from one end to the other end of the longitudinal direction of the trench 14.

[0016] The body layer 34 is a p-type layer with a lower concentration of p-type impurities than the contact layer 32. The body layer 34 is disposed below the plurality of source layers 30 and the plurality of contact layers 32. The body layer 34 is in contact with the plurality of source layers 30 and the plurality of contact layers 32 from below. The body layer 34 is in contact with the gate insulating film 16 at the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 through the gate insulating film 16.

[0017] Each p-type trench lower layer 35 is a p-type layer disposed below the corresponding trench 14. As will be described later, each p-type trench lower layer 35 may be formed in an ion implantation process common to the body layer 34. In this case, the depth-direction concentration profiles of the p-type impurities in each p-type trench lower layer 35 and the body layer 34 coincide, and the depth from the bottom surface of the corresponding trench 14 to the lower surface of each p-type trench lower layer 35 coincides with the depth from the upper surface 12a of the semiconductor substrate 12 to the lower surface of the body layer 34. In this example, each p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the corresponding trench 14. As shown in FIG. 3, when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends long along the longitudinal direction (y direction in this example) of the corresponding trench 14 and extends continuously from one end to the other end in the longitudinal direction of the trench 14.

[0018] Each p-type deep layer 36 is a p-type layer protruding downward from the lower surface of the body layer 34. The concentration of the p-type impurities in each p-type deep layer 36 is higher than the concentration of the p-type impurities in the body layer 34 and lower than the concentration of the p-type impurities in the contact layer 32. As shown in FIG. 4, when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 extends long in the x direction and is orthogonal to the longitudinal direction (y direction in this example) of the trench 14. The p-type deep layers 36 are arranged at intervals in the y direction. The p-type deep layer 36 has a shape that is long in the z direction in the yz cross section. That is, the dimension of the p-type deep layer 36 in the z direction (i.e., the height of the p-type deep layer 36) is larger than the dimension of the p-type deep layer 36 in the y direction (i.e., the lateral width of the p-type deep layer 36). Each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14. Each p-type deep layer 36 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Also, as shown in FIG. 3, each p-type deep layer 36 is in contact so as to cross the p-type trench lower layer 35 disposed below the trench 14.

[0019] Each n-type deep layer 37 is an n-type layer protruding downward from the lower surface of the body layer 34. The concentration of n-type impurities in each n-type deep layer 37 is higher than the concentration of n-type impurities in the drift layer 38. The concentration of n-type impurities in each n-type deep layer 37 is lower than the p-type impurity concentration in each p-type deep layer 36. Instead of this example, each n-type deep layer 37 may have the same concentration as the concentration of n-type impurities in the drift layer 38. As shown in FIGS. 1, 2, and 5, each n-type deep layer 37 is disposed in a corresponding interval among a plurality of intervals defined by adjacent p-type deep layers 36. When the semiconductor substrate 12 is viewed from above as shown in FIG. 4, each n-type deep layer 37 extends long in the x direction and is orthogonal to the longitudinal direction of the trench 14 (in this example, the y direction). Each n-type deep layer 37 is in contact with the side surfaces of the p-type deep layers 36 on both sides thereof. The n-type deep layer 37 has a shape that is long in the z direction in the yz cross section. That is, the dimension of the n-type deep layer 37 in the z direction (i.e., the height of the n-type deep layer 37) is larger than the dimension of the n-type deep layer 37 in the y direction (i.e., the lateral width of the n-type deep layer 37). In the present embodiment, the height of the n-type deep layer 37 is equal to the height of the p-type deep layer 36. In this specification, considering the variation in the ion implantation process, if the difference between the height of the p-type deep layer 36 and the height of the n-type deep layer 37 is within 3%, it is said that the height of the n-type deep layer 37 and the height of the p-type deep layer 36 are the same. The lateral width of the n-type deep layer 37 is substantially equal to the lateral width of the p-type deep layer 36. As shown in FIGS. 1, 2, and 5, each n-type deep layer 37 extends from the lower surface of the body layer 34 to below the bottom surface of each trench 14. Each n-type deep layer 37 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Further, as shown in FIG. 3, each n-type deep layer 37 is in contact with the p-type trench lower layer 35 disposed below the trench 14 so as to intersect.

[0020] The drift layer 38 is an n-type layer disposed below the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37. The concentration of n-type impurities in the drift layer 38 is lower than the concentration of n-type impurities in the n-type deep layer 37. The drift layer 38 is in contact with the n-type deep layer 37 from below.

[0021] Each n-type high-concentration layer 39 is an n-type layer that contacts the entire lower surface of the corresponding p-type deep layer 36. The concentration of n-type impurities in each n-type high-concentration layer 39 is higher than the concentration of n-type impurities in the drift layer 38. The concentration of n-type impurities in each n-type high-concentration layer 39 may be lower than the concentration of n-type impurities in the n-type deep layer 37. Each n-type high-concentration layer 39 is disposed between the drift layer 38 and the p-type deep layer 36 and separates the drift layer 38 and the p-type deep layer 36. Each n-type high-concentration layer 39 is partially provided so as to contact the lower surface of the p-type deep layer 36 and is not provided so as to cover at least a part of the lower surface of the n-type deep layer 37. In other words, each n-type high-concentration layer 39 does not continuously extend between adjacent p-type deep layers 36 and is divided below the n-type deep layer 37. For this reason, the n-type deep layer 37 and the drift layer 38 are in contact with each other in the region between adjacent n-type high-concentration layers 39. When the semiconductor substrate 12 is viewed from above, each n-type high-concentration layer 39 extends long along the longitudinal direction (the y direction in this example) of the corresponding p-type deep layer 36 and continuously extends from one end to the other end in the longitudinal direction of the p-type deep layer 36. Further, as shown in FIG. 5, each n-type high-concentration layer 39 also contacts the lower surface of the p-type trench lower layer 35 that intersects the corresponding p-type deep layer 36 and is disposed between the drift layer 38 and the p-type trench lower layer 35. Adjacent n-type high-concentration layers 39 may be connected below the p-type trench lower layer 35. In this example, the n-type high-concentration layer 39 may extend in the y direction along the lower surface of the p-type trench lower layer 35 and may be formed so as to separate the drift layer 38 and the p-type trench lower layer 35.

[0022] The drain layer 40 is an n-type layer having a higher concentration of n-type impurities than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in a range including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0023] Next, the operation of the semiconductor device 10 will be described. The semiconductor device 10 is used with a potential higher than that of the source electrode 22 applied to the drain electrode 24. When a potential equal to or higher than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 in the vicinity of the gate insulating film 16. The source layer 30 and the n-type deep layer 37 are connected by the channel. For this reason, electrons flow from the source layer 30 through the channel, the n-type deep layer 37, and the drift layer 38 to the drain layer 40. That is, the semiconductor device 10 is turned on. When the potential of each gate electrode 18 is lowered from a value equal to or higher than the gate threshold to a value lower than the gate threshold, the channel disappears and the flow of electrons stops. That is, the semiconductor device 10 is turned off.

[0024] When the n-type high-concentration layer 39 is not provided, when the semiconductor device 10 is turned on, a depletion layer spreads from the p-type deep layer 36 toward the drift layer 38. In particular, when the depletion layer spreads toward the drift layer 38 below the n-type deep layer 37, there is a concern that the current path becomes narrow and the on-resistance increases. Such an increase in on-resistance is called the JFET effect. On the other hand, in the semiconductor device 10, since the n-type high-concentration layer 39 is provided so as to be in contact with the lower surface of the p-type deep layer 36, the spread of the depletion layer from the p-type deep layer 36 toward the drift layer 38 can be suppressed. For this reason, since a wide current conduction path is ensured, the semiconductor device 10 can have the characteristic of low on-resistance. Note that the thickness of the n-type high-concentration layer 39 may be larger than the thickness of the depletion layer generated by the built-in potential in the pn junction between the p-type deep layer 36 and the n-type high-concentration layer 39. The JFET effect can be suppressed well. Further, the n-type high-concentration layer 39 is partially provided below the p-type deep layer 36, is not provided in at least a part below the n-type deep layer 37, and is not continuously formed in the plane direction of the semiconductor substrate 12. Thus, since the n-type high-concentration layer 39 is partially provided, a decrease in the breakdown voltage of the semiconductor device 10 is also suppressed. The semiconductor device 10 can achieve both low on-resistance and high breakdown voltage.

[0025] In the modification shown in FIG. 6, the n-type high-concentration layer 39 is selectively arranged at both ends in the width direction of the lower surface of the corresponding p-type deep layer 36 and does not contact the entire lower surface of the p-type deep layer 36. Even in this modification, when the semiconductor device 10 is turned on, the spread of the depletion layer from the p-type deep layer 36 toward the drift layer 38 below the n-type deep layer 37 can be suppressed. Further, since a part of the p-type deep layer 36 is in contact with the drift layer 38, when the semiconductor device 10 is turned off, the depletion layer spreads well from the p-type deep layer 36 to the drift layer 38. For this reason, in this modification, the breakdown voltage can be improved.

[0026] In the modified example shown in FIG. 7, the lateral width of the n-type high-concentration layer 39 is larger than the lateral width of the corresponding p-type deep layer 36. As a result, the n-type high-concentration layer 39 is in contact with the n-type deep layer 37 adjacent to the corresponding p-type deep layer 36 in addition to the entire lower surface of the corresponding p-type deep layer 36. According to this example, when the semiconductor device 10 is turned on, the spread of the depletion layer from the p-type deep layer 36 toward the drift layer 38 can be favorably suppressed.

[0027] In the modified example shown in FIG. 8, the p-type deep layer 36 extends below the n-type deep layer 37. The n-type high-concentration layer 39 is in contact with not only the entire lower surface of the p-type deep layer 36 but also the side surface of the p-type deep layer 36 below the n-type deep layer 37. When the p-type deep layer 36 extends below the n-type deep layer 37, the breakdown voltage of the semiconductor device 10 is improved. Further, since the n-type high-concentration layer 39 is also disposed on the side surface of the p-type deep layer 36, even when the p-type deep layer 36 extends below the n-type deep layer 37, the spread of the depletion layer from the p-type deep layer 36 toward the drift layer 38 below the n-type deep layer 37 can be suppressed when the semiconductor device 10 is turned on. In this modified example, the trade-off existing between the on-resistance and the breakdown voltage can be further improved. Note that also in this modified example, as shown in FIG. 6, the n-type high-concentration layer 39 may not be provided in a part of the lower surface of the p-type deep layer 36, and the p-type deep layer 36 and the drift layer 38 may be formed to be in contact with each other.

[0028] Next, a method for manufacturing the semiconductor device 10 will be described. The semiconductor device 10 is manufactured from a semiconductor substrate entirely constituted by a drain layer 40. First, as shown in FIG. 9, an n-type epitaxial layer 50 is formed on the drain layer 40 by using an epitaxial growth technique.

[0029] Next, as shown in FIG. 10, an n-type layer 60 is formed by introducing n-type impurities into a predetermined depth range away from the surface of the epitaxial layer 50 by using an ion implantation technique. A part of the epitaxial layer 50 below the n-type layer 60 becomes the drift layer 38.

[0030] Next, as shown in FIG. 11, a mask 52 having an opening is patterned on the epitaxial layer 50.

[0031] Next, as shown in FIG. 12, using ion implantation technology, an n-type impurity is introduced into the upper part of the drift layer 38 through the opening of the mask 52 to form an n-type high-concentration layer 39.

[0032] Next, as shown in FIG. 13, using ion implantation technology, a p-type impurity is introduced into a part of the n-type layer 60 through the opening of the mask 52 to form a plurality of p-type deep layers 36. A part of the n-type layer 60 where the plurality of p-type deep layers 36 are not formed becomes a plurality of n-type deep layers 37. In this specification, among the steps illustrated in FIGS. 10 to 13, the step of forming the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37 is an example of the deep layer forming step. After forming the plurality of p-type deep layers 36, the mask 52 is removed.

[0033] In this example, the mask 52 serves as both a mask for ion implantation to form the n-type high-concentration layer 39 and a mask for ion implantation to form the p-type deep layer 36. Therefore, the number of steps is reduced and the manufacturing cost can be suppressed. Note that after forming the p-type deep layer 36, the n-type high-concentration layer 39 may be formed. Also, when forming the n-type high-concentration layer 39, by performing oblique ion implantation at a predetermined angle with respect to the upper surface of the epitaxial layer 50, the n-type high-concentration layer 39 of the modified example shown in FIG. 6 can be formed. Note that without using the mask 52 in common, by making the opening width of the mask for ion implantation to form the n-type high-concentration layer 39 larger than the opening width of the mask for ion implantation to form the p-type deep layer 36, the n-type high-concentration layer 39 of the modified example shown in FIG. 7 can be formed.

[0034] Next, as shown in FIG. 14, using ion implantation technology, an n-type impurity and a p-type impurity are introduced into the surface layer portion of the epitaxial layer 50 to form a source layer 30 and a contact layer 32.

[0035] Next, as shown in FIG. 15, using an etching technique, a trench 14 is formed that reaches the n-type deep layer 37 and the p-type deep layer 36 from the surface of the epitaxial layer 50. The depth of the trench 14 is adjusted so as not to exceed the n-type deep layer 37 and the p-type deep layer 36. The trench 14 intersects a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37 when viewing the epitaxial layer 50 from above.

[0036] Next, as shown in FIG. 16, using an ion implantation technique, a body layer 34 and a p-type trench lower layer 35 are formed by introducing p-type impurities in multiple stages toward the surface of the epitaxial layer 50. The body layer 34 is formed above the n-type deep layer 37 and the p-type deep layer 36 and below the source layer 30 and the contact layer 32. The p-type trench lower layer 35 is formed below the bottom surface of the trench 14.

[0037] Thereafter, by forming the trench 14, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24, the semiconductor device 10 is completed.

[0038] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of these purposes itself has technical utility.

Claims

1. A semiconductor device (10), comprising: A semiconductor substrate (12) having a trench (14) provided on its upper surface; A gate insulating film (16) covering the inner surface of the trench; A gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; The semiconductor substrate includes: An n-type source layer (30) in contact with the gate insulating film on the side surface of the trench; A p-type body layer (34) in contact with the gate insulating film on the side surface of the trench located below the source layer; A plurality of p-type deep layers (36), each extending from the body layer below the bottom surface of the trench, and extending along a first direction and spaced apart from each other in a second direction orthogonal to the first direction when viewed from above the semiconductor substrate; A plurality of n-type deep layers (37), each disposed in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers, and in contact with the gate insulating film on the side surface of the trench located below the body layer; An n-type drift layer (38) disposed below the plurality of p-type deep layers and the plurality of n-type deep layers and in contact with the plurality of n-type deep layers; An n-type high-concentration layer (39) in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and having a higher concentration of n-type impurities than the drift layer; The n-type high-concentration layer is in contact with the entire lower surface of the corresponding p-type deep layer; The width of the n-type high-concentration layer in the second direction is larger than the width of the p-type deep layer in the second direction, whereby the n-type high-concentration layer is in contact with the n-type deep layer adjacent to the p-type deep layer. A semiconductor device.

2. The semiconductor device according to claim 1, wherein the plurality of p-type deep layers extend below the plurality of n-type deep layers.

3. The semiconductor device according to claim 2, wherein the n-type high-concentration layer is also in contact with a side surface of the p-type deep layer that is below the plurality of n-type deep layers.

4. The semiconductor device according to any one of claims 1 to 3, wherein the n-type high-concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers.

5. A semiconductor device (10), comprising: A semiconductor substrate (12) provided with a trench (14) on an upper surface; A gate insulating film (16) covering an inner surface of the trench; A gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes: An n-type source layer (30) in contact with the gate insulating film on a side surface of the trench; A p-type body layer (34) in contact with the gate insulating film on the side surface of the trench located below the source layer; A plurality of p-type deep layers (36), each extending from the body layer below a bottom surface of the trench and extending along a first direction and spaced apart from each other in a second direction orthogonal to the first direction when viewed from above the semiconductor substrate; A plurality of n-type deep layers (37), each disposed in a corresponding one of a plurality of intervals defined between adjacent ones of the p-type deep layers and in contact with the gate insulating film on the side surface of the trench located below the body layer; An n-type drift layer (38) disposed below the plurality of p-type deep layers and the plurality of n-type deep layers and in contact with the plurality of n-type deep layers; in contact with at least a part of the lower surface of the corresponding p-type deep layer among the plurality of p-type deep layers, and having an n-type high-concentration layer (39) with a higher concentration of n-type impurities than the drift layer. The n-type high-concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers. A semiconductor device.

6. A method for manufacturing a semiconductor device (10), A deep layer forming step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) in an n-type epitaxial layer (50), wherein each of the plurality of p-type deep layers extends along a first direction when the epitaxial layer is viewed from above, and is arranged at intervals from each other in a second direction orthogonal to the first direction, and each of the plurality of n-type deep layers is arranged in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers. A deep layer forming step. An n-type high-concentration layer forming step of forming an n-type high-concentration layer in contact with at least a part of the lower surface of the corresponding p-type deep layer among the plurality of p-type deep layers and having a higher concentration of n-type impurities than the epitaxial layer. comprising A method for manufacturing a semiconductor device, wherein a mask for ion implantation for forming the plurality of p-type deep layers in the deep layer forming step and a mask for ion implantation for forming the n-type high-concentration layer in the n-type high-concentration layer forming step are common.

7. A method for manufacturing a semiconductor device (10), A deep layer forming step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) in an n-type epitaxial layer (50), wherein each of the plurality of p-type deep layers extends along a first direction when the epitaxial layer is viewed from above, and is arranged at intervals from each other in a second direction orthogonal to the first direction, and each of the plurality of n-type deep layers is arranged in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers. A deep layer forming step. A step of forming an n-type high-concentration layer that is in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the epitaxial layer. It includes: A method for manufacturing a semiconductor device, wherein an opening width in the second direction of a mask for ion implantation for forming the n-type high-concentration layer in the n-type high-concentration layer forming step is larger than an opening width in the second direction of a mask for ion implantation for forming the plurality of p-type deep layers in the deep layer forming step.

8. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein in the n-type high-concentration layer forming step, the n-type high-concentration layer is formed using an oblique ion implantation technique.

9. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the n-type high-concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers.

10. A method for manufacturing a semiconductor device (10), comprising: A deep layer forming step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) in an n-type epitaxial layer (50), wherein each of the plurality of p-type deep layers extends along a first direction and is arranged at intervals from each other in a second direction orthogonal to the first direction when looking at the epitaxial layer from above, and each of the plurality of n-type deep layers is arranged in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers. A step of forming an n-type high-concentration layer that is in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the epitaxial layer. It includes: A method for manufacturing a semiconductor device, wherein in the n-type high-concentration layer forming step, the n-type high-concentration layer is formed using an oblique ion implantation technique.

11. A method for manufacturing a semiconductor device (10), comprising: A deep layer forming step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) in an n-type epitaxial layer (50), wherein each of the plurality of p-type deep layers extends along a first direction when viewing the epitaxial layer from above and is arranged at intervals from each other in a second direction orthogonal to the first direction, and each of the plurality of n-type deep layers is arranged in a corresponding one of a plurality of intervals defined between adjacent ones of the p-type deep layers. An n-type high concentration layer forming step of forming an n-type high concentration layer that is in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the epitaxial layer. comprising The manufacturing method of a semiconductor device, wherein the n-type high concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers.

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