Silicon carbide semiconductor device

Abstract

In the present invention, a super junction layer has first regions and second regions in an alternating configuration. A device layer is provided above the super junction layer. Each first region has a first section, and a second section that is positioned between the first section and a first main surface. Each second region has a third section that is in contact with a first section, and a fourth section that is in contact with a second section and is positioned between the third section and the first main surface. In a cross section perpendicular to a second main surface and parallel to a direction heading from a first region toward a second region, the width of the second sections is greater than the width of the first sections, the width of the fourth sections is smaller than the width of the third sections, the total value of the widths of the first sections and the widths of the third sections is 0.5 μm to 4 μm inclusive, and the respective heights of the first regions and the second regions are 2 μm or more.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device. This application claims priority based on Japanese Patent Application No. 2020-118899, filed on July 10, 2020. All the descriptions contained in the Japanese patent application are incorporated herein by reference.

Background Art

[0002] WO 2017 / 179377 (Patent Document 1) describes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a super junction structure. Further, Patent Document 2, Japanese Patent Application Laid-Open No. 2019-520703, and Patent Document 3, Japanese Patent Application Laid-Open No. 2015-216182, describe a super junction structure of a silicon carbide semiconductor formed by ion implantation using the channeling phenomenon.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0004] The silicon carbide semiconductor device according to the present disclosure includes a substrate, a superjunction layer, an element layer, a first electrode, and a second electrode. The substrate is made of a silicon carbide semiconductor of a first conductivity type. The superjunction layer is provided above the first main surface of the substrate and has a first region of a first conductivity type and a second region of a second conductivity type alternately. The element layer is provided above the superjunction layer. The first electrode is provided on the element layer. The second electrode is provided on the second main surface facing the first main surface of the substrate. The first region has a first portion and a second portion located between the first portion and the first main surface. The second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface. In a cross section perpendicular to the second main surface and parallel to the direction from the first region to the second region, the width of the second portion is larger than the width of the first portion, the width of the fourth portion is smaller than the width of the third portion, the total value of the width of the first portion and the width of the third portion is 0.5 μm or more and 4 μm or less, and the height of each of the first region and the second region is 2 μm or more.

Brief Description of the Drawings

[0005]

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Embodiments for Carrying Out the Invention

[0006] [Problems to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of improving breakdown voltage while reducing on-resistance. [Effects of the Present Disclosure] According to the present disclosure, it is possible to provide a silicon carbide semiconductor device capable of improving breakdown voltage while reducing on-resistance. [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the crystallographic description of this specification, individual orientations are indicated by [], collective orientations are indicated by <>, individual planes are indicated by (), and collective planes are indicated by {}. A negative crystallographic index is usually expressed by attaching a "-" (bar) above the number, but in this specification, a negative crystallographic index is expressed by attaching a negative sign before the number.

[0007] (1) A silicon carbide semiconductor device 100 according to the present disclosure includes a substrate 11, a superjunction layer 10, an element layer 40, a first electrode 6 2 and a second electrode 6 1 . The substrate 11 is made of a silicon carbide semiconductor of a first conductivity type. The superjunction layer 10 is provided above the first main surface 1 of the substrate 11 and has a first region 41 of a first conductivity type and a second region 42 of a second conductivity type alternately. The element layer 40 is provided above the superjunction layer 10. The first electrode 6 2 is provided on the element layer 40. The second electrode 6 1 is provided on the second main surface 2 facing the first main surface 1 of the substrate 11. The first region 41 has a first portion 71 and a second portion 72 located between the first portion 71 and the first main surface 1. The second region 42 has a third portion 73 in contact with the first portion 71 and a fourth portion 74 in contact with the second portion 72 and located between the third portion 73 and the first main surface 1. In a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 is larger than the width of the first portion 71, the width of the fourth portion 74 is smaller than the width of the third portion 73, the total value of the width of the first portion 71 and the width of the third portion 73 is 0.5 μm or more and 4 μm or less, and the height of each of the first region 41 and the second region 42 is 2 μm or more.

[0008] (2) According to the silicon carbide semiconductor device 100 according to (1) above, in a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the first portion 71 may be smaller than the height of the first portion 71, and the width of the third portion 73 may be smaller than the height of the third portion 73.

[0009] (3) According to the silicon carbide semiconductor device 100 according to (1) or (2) above, the impurity concentration in the third portion 73 may be higher than the impurity concentration in the fourth portion 74.

[0010] (4) According to the silicon carbide semiconductor device 100 according to any one of (1) to (3) above, the impurity concentration of each of the first portion 71 and the third portion 73 is 3×10 16 cm -3 or more and 5×10 17 cm -3 or less.

[0011] (5) According to the silicon carbide semiconductor device 100 according to any one of (1) to (4) above, a buffer layer 12 of the first conductivity type may be provided between the super junction layer 10 and the substrate 11.

[0012] (6) According to the silicon carbide semiconductor device 100 according to any one of (1) to (5) above, the element layer 40 may include a first impurity region 15 of the first conductivity type, a second impurity region 23 that is in contact with the first impurity region 15 and has the second conductivity type, and a third impurity region 30 that is separated from the first impurity region 15 by the second impurity region 23 and has the first conductivity type. The element layer 40 may be provided with a trench 5 having a side surface 8 formed by each of the first impurity region 15, the second impurity region 23, and the third impurity region 30, and a bottom surface 9 that is continuous with the side surface 8 and is formed by the first impurity region 15. The first electrode 6 2 is a source electrode, and the second electrode 6 1 may be a drain electrode. A gate electrode may be provided inside the trench 5.

[0013] (7) According to the silicon carbide semiconductor device 100 according to any one of (1) to (6) above, the first main surface 1 may be a surface inclined at an angle of 8° or less with respect to the {0001} plane or the {0001} plane. [Details of Embodiments of the Present Disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0014] (First Embodiment) First, the configuration of the silicon carbide semiconductor device 100 according to the first embodiment will be described. FIG. 1 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0015] As shown in FIG. 1, the silicon carbide semiconductor device 100 according to the first embodiment is, for example, a trench type MOSFET. The silicon carbide semiconductor device 100 according to the first embodiment mainly includes, for example, a substrate 11, a super junction layer 10, an element layer 40, a first electrode 6 2 and a second electrode 6 1 and a third electrode 63, a gate insulating film 6, a separation insulating film 64, and a buffer layer 12. The substrate 11 is made of a silicon carbide semiconductor of the first conductivity type. The first conductivity type is, for example, n-type. The substrate 11 contains an n-type impurity that can impart an n-type, such as N (nitrogen) for example. The substrate 11 has a first main surface 1 and a second main surface 2. The second main surface 2 faces the first main surface 1. The second main surface 2 is the surface on the opposite side of the first main surface 1.

[0016] The substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide. The first main surface 1 may be, for example, a surface inclined at an angle of 8° or less with respect to the {0001} plane or the {0001} plane. Specifically, the first main surface 1 may be a surface inclined at an angle of 8° or less with respect to the (0001) plane or the (0001) plane. The first main surface 1 may be a surface inclined at an angle of 8° or less with respect to the (000-1) plane or the (000-1) plane.

[0017] The buffer layer 12 is located between the superjunction layer 10 and the substrate 11. The buffer layer 12 has, for example, an n-type (first conductivity type). The buffer layer 12 contains an n-type impurity that can impart an n-type, such as N (nitrogen), for example.

[0018] The superjunction layer 10 is provided above the first main surface 1 of the substrate 11. The superjunction layer 10 is in contact with the buffer layer 12. The superjunction layer 10 has a first region 41 and a second region 42 alternately. The first region 41 and the second region 42 are alternately arranged, for example, along a direction (first direction 101) parallel to the first main surface 1. From another perspective, the first region 41 and the second region 42 are alternately arranged, for example, along a direction intersecting the thickness direction of the substrate 11.

[0019] The first region 41 has an n-type (first conductivity type). The first region 41 contains an n-type impurity that can impart an n-type, such as N (nitrogen), for example. The second region 42 has a p-type (second conductivity type). The second region 42 contains a p-type impurity that can impart a p-type, such as Al (aluminum), for example.

[0020] FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG. 1. As shown in FIG. 2, in a plan view, the longitudinal direction of each of the first region 41 and the second region 42 is the second direction 102. In a plan view, the short transverse direction of each of the first region 41 and the second region 42 is the first direction 101. In a plan view, the shape of each of the first region 41 and the second region 42 may be substantially rectangular.

[0021] Each of the first direction 101 and the second direction 102 is parallel to the first main surface 1. The first direction 101 is a direction perpendicular to the second direction 102. The first direction 101 is, for example, the <11-20> direction. The second direction 102 is, for example, the <1-100> direction. The first direction 101 may be, for example, a direction obtained by projecting the <11-20> direction onto the first main surface 1. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1.

[0022] As shown in FIG. 1, the third direction 103 is a direction perpendicular to each of the first direction 101 and the second direction 102. The third direction 103 is, for example, the <0001> direction. The third direction 103 may be a direction inclined with respect to, for example, the <0001> direction.

[0023] The first region 41 has a first portion 71 and a second portion 72. The second portion 72 is located between the first portion 71 and the first main surface 1. The first portion 71 and the second portion 72 are adjacent to each other in the third direction 103. The second portion 72 may be in contact with the buffer layer 12 or may be in contact with the first main surface 1.

[0024] The second region 42 has a third portion 73 and a fourth portion 74. The fourth portion 74 is located between the third portion 73 and the first main surface 1. The third portion 73 and the fourth portion 74 are adjacent to each other in the third direction 103. The fourth portion 74 may be in contact with the buffer layer 12 or may be in contact with the first main surface 1.

[0025] The third portion 73 is in contact with the first portion 71. The third portion 73 and the first portion 71 are adjacent to each other in the first direction 101. The third portion 73 and the first portion 71 are alternately arranged in the first direction 101. The fourth portion 74 is in contact with the second portion 72. The fourth portion 74 and the second portion 72 are adjacent to each other in the first direction 101. The fourth portion 74 and the second portion 72 are alternately arranged in the first direction 101.

[0026] As shown in FIG. 1, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 is larger than the width of the first portion 71 (the first width W1). As going from the first portion 71 toward the first main surface 1, the width of the second portion 72 may monotonically increase. The width of the second portion 72 (the second width W2) in contact with the buffer layer 12 is larger than the first width W1.

[0027] As shown in FIG. 1, in a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the fourth portion 74 is smaller than the width of the third portion 73 (the third width W3). As going from the third portion 73 toward the first main surface 1, the width of the fourth portion 74 may monotonically decrease. The width of the fourth portion 74 (the fourth width W4) in contact with the buffer layer 12 is smaller than the third width W3.

[0028] As shown in FIG. 1, the total value of the width of the first portion 71 (the first width W1) and the width of the third portion 73 (the third width W3) is 0.5 μm or more and 4 μm or less. The total value of the width of the first portion 71 (the first width W1) and the width of the third portion 73 (the third width W3) is the pitch P of the super junction layer. The lower limit of the total value of the width of the first portion 71 (the first width W1) and the width of the third portion 73 (the third width W3) is not particularly limited, and may be, for example, 1 μm or more, or may be 2 μm or more. The upper limit of the total value of the width of the first portion 71 (the first width W1) and the width of the third portion 73 (the third width W3) is not particularly limited, and may be, for example, 4 μm or less, or may be 3 μm or less.

[0029] As shown in FIG. 1, in a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the first portion 71 (the first width W1) may be smaller than the height of the first portion 71 (the first height T1). The height of the first portion 71 (the first height T1) may be larger than the height of the second portion 72 (the second height T2).

[0030] As shown in FIG. 1, in a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the third portion 73 (the third width W3) may be smaller than the height of the third portion 73 (the first height T1). The height of the third portion 73 (the first height T1) may be larger than the height of the fourth portion 74 (the second height T2).

[0031] The sum of the height of the first part 71 (the first height T1) and the height of the second part 72 (the second height T2) is the height of the first region 41 (the third height T3). Similarly, the sum of the height of the third part 73 (the first height T1) and the height of the fourth part 74 (the second height T2) is the height of the second region 42 (the third height T3).

[0032] The height of each of the first region 41 and the second region 42 (the third height T3) is 2 μm or more. The lower limit of the height of each of the first region 41 and the second region 42 is not particularly limited, and may be, for example, 2.5 μm or more, or 3 μm or more. The upper limit of the height of each of the first region 41 and the second region 42 is not particularly limited, and may be, for example, 5 μm or less, or 4 μm or less.

[0033] The impurity concentration in the third part 73 may be higher than the impurity concentration in the fourth part 74. The impurity concentration in the first part 71 is substantially the same as the impurity concentration in the second part 72. The impurity concentration in the first part 71 is substantially the same as the impurity concentration in the third part 73. The impurity concentration in the fourth part 74 may be lower than the impurity concentration in the second part 72.

[0034] The impurity concentration of each of the first part 71 and the third part 73 is, for example, 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The lower limit of the impurity concentration of each of the first part 71 and the third part 73 is not particularly limited, and may be, for example, 4×10 16 cm -3 or more, or 5×10 16 cm -3 or more. The upper limit of the impurity concentration of each of the first part 71 and the third part 73 is not particularly limited, and may be, for example, 3×10 17 cm -3 or less, or 2×10 17 cm -3 or less.

[0035] The element layer 40 is provided above the super junction layer 10. The element layer 40 is, for example, a switching element. The element layer 40 has, for example, a first impurity region 15, a second impurity region 23, a third impurity region 30, a fourth impurity region 24, and a fifth impurity region 20. The first impurity region 15 is, for example, a drift region.

[0036] The first impurity region 15 has an n-type (first conductivity type). The first impurity region 15 contains an n-type impurity capable of imparting an n-type, such as N (nitrogen) for example. The first impurity region 15 is in contact with the first region 41. The first impurity region 15 has a first drift layer 14 and a second drift layer 13. The first drift layer 14 is in contact with the gate insulating film 6. The second drift layer 13 is continuous with the first drift layer 14. The second drift layer 13 is located between the first drift layer 14 and the first region 41. In the second drift layer 13, the width at the center is smaller than the widths at the top and bottom.

[0037] The second impurity region 23 is, for example, a body region. The second impurity region 23 is in contact with the first impurity region 15. The second impurity region 23 has a p-type (second conductivity type). The second impurity region 23 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum) for example. The second impurity region 23 is electrically connected to the second region 42. The concentration of the p-type impurity contained in the second impurity region 23 may be higher than the concentration of the n-type impurity contained in the first impurity region 15.

[0038] The third impurity region 30 is, for example, a source region. The third impurity region 30 is separated from the first impurity region 15 by the second impurity region 23. The third impurity region 30 has an n-type (first conductivity type). The third impurity region 30 contains an n-type impurity capable of imparting an n-type, such as P (phosphorus) for example. The concentration of the n-type impurity contained in the third impurity region 30 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0039] The fourth impurity region 24 is, for example, a contact region. The fourth impurity region 24 is in contact with the second impurity region 23 and the third impurity region 30. The fourth impurity region 24 has a p-type (second conductivity type). The fourth impurity region 24 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum). The concentration of the p-type impurity contained in the fourth impurity region 24 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0040] The fifth impurity region 20 connects the second impurity region 23 and the second region 42. The fifth impurity region 20 is in contact with each of the first impurity region 15, the second impurity region 23, and the second region 42. The fifth impurity region 20 has a p-type (second conductivity type). The fifth impurity region 20 contains a p-type impurity capable of imparting a p-type, such as Al (aluminum).

[0041] The fifth impurity region 20 has a first connection region 21 and a second connection region 22. The first connection region 21 is in contact with each of the second impurity region 23 and the first drift layer 14. The second connection region 22 is in contact with each of the first connection region 21 and the second region 42. The second connection region 22 is located between the first connection region 21 and the second region 42 in the third direction 103.

[0042] The gate insulating film 6 is provided on the element layer 40. The gate insulating film 6 is composed of, for example, silicon dioxide. The gate insulating film 6 is in contact with each of the first impurity region 15, the second impurity region 23, and the third impurity region 30, for example. A channel can be formed in the second impurity region 23 in contact with the gate insulating film 6.

[0043] Gate electrode 63 is provided on the gate insulating film 6. Gate electrode 63 is in contact with the gate insulating film 6. Gate electrode 63 is composed of a conductor such as, for example, polysilicon doped with an impurity.

[0044] The element layer 40 is provided with a trench 5. The trench 5 is defined by a side surface 8 and a bottom 9. The side surface 8 is composed of each of a first impurity region 15, a second impurity region 23, and a third impurity region 30. The bottom 9 is continuous with the side surface 8. The bottom 9 is composed of the first impurity region 15.

[0045] At least a part of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 is in contact with each of the first impurity region 15, the second impurity region 23, and the third impurity region 30 on the side surface 8. The gate insulating film 6 is in contact with the first impurity portion region on the bottom 9. At least a part of the gate electrode is provided, for example, inside the trench 5.

[0046] The 1 electrode 62 is, for example, a source electrode. The 1 electrode 62 is provided on the element layer 40. The 1 electrode 62 is in contact with the third impurity region 30 and the fourth impurity region 24. The 1 electrode 62 may cover the isolation insulating film 64. The 2 electrode 61 is, for example, a drain electrode. The 2 electrode 61 is provided on the second main surface 2 of the substrate 11.

[0047] The isolation insulating film 64 is provided so as to cover the gate electrode 63 The isolation insulating film 64 is in contact with each of the gate electrode 63 and the gate insulating film 6. The isolation insulating film 64 is composed of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The isolation insulating film 64 electrically insulates the gate electrode 63 from the 1 electrode 62.

[0048] Next, a method for forming the super junction layer 10 will be described. First, a buffer layer 12 is formed on a substrate 11. The buffer layer 12 is formed, for example, by epitaxial growth. Next, a first region 41 is formed on the buffer layer 12. The first region 41 is formed, for example, by epitaxial growth. Each of the buffer layer 12 and the first region 41 has an n-type (first conductivity type). Next, a mask layer (not shown) is formed on the first region 41.

[0049] Next, a channeling ion implantation process is performed. Specifically, with a mask layer disposed on the first region 41, impurity ions capable of imparting a p-type (second conductivity type), such as aluminum, are implanted into the first region 41. The implantation energy is, for example, 960 keV. The implantation temperature is, for example, room temperature. As a result, a second region 42 is formed in a part of the first region 41. The second region 42 is provided spaced apart in a first direction 101. As described above, a super junction layer 10 in which the first region 41 and the second region 42 are alternately arranged is formed (see FIG. 2).

[0050] In the channeling ion implantation process, impurity ions are implanted in a direction substantially parallel to the <0001> direction, which is a crystal axis of silicon carbide. The implantation direction of the impurity ions may be inclined by, for example, an angle of 0.5° or less with respect to the <0001> direction. Specifically, the implantation direction of the impurity ions may be a direction in which a third direction 103 is inclined off-direction. The off-direction may be, for example, the first direction 101 or the second direction 102. Thereby, by reducing the scattering between the impurity ions and silicon carbide, the impurity ions can be implanted deeply. As a result, a second region 42 having a thickness of 2 μm or more is formed (see FIG. 1). The second region 42 has a third portion 73 and a fourth portion 74. The width of the fourth portion 74 is formed smaller than the width of the third portion 73.

[0051] FIG. 3 is a schematic diagram showing an impurity concentration profile. Condition A is a box profile when random implantation is performed. In Condition A, the implantation energy is changed in the range from 960 keV to 9 MeV. Condition B is a single profile when random implantation is performed. In Condition B, the implantation energy is set to 960 keV. Condition C is a single profile when channeling implantation is performed. In Condition C, the implantation energy is set to 960 keV.

[0052] As shown in Condition B and Condition C of FIG. 3, in the case of channeling implantation, it is possible to implant deeper than in random implantation. In the case of Condition C, the implantation depth becomes 2 μm or more. On the other hand, when multi-step implantation is performed using random implantation, an impurity region having an implantation depth comparable to that of Condition C can be formed. However, when an impurity region having an implantation depth comparable to that of Condition C is formed using random implantation, it is necessary to increase the implantation energy to about 9 MeV.

[0053] (Second Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the second embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the second embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment in that each of the first region 41 and the second region 42 is laminated in the superjunction layer 10, and the other points are the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0054] FIG. 4 is a schematic partial longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the second embodiment. As shown in FIG. 4, in the superjunction layer 10, each of the first region 41 and the second region 42 is laminated. A plurality of the first regions 41 are provided along the third direction 103. The first portion 71 and the second portion 72 are alternately arranged along the third direction 103. Similarly, a plurality of the second regions 42 are provided along the third direction 103. The third portion 73 and the fourth portion 74 are alternately arranged along the third direction 103.

[0055] The lower limit of the number of each of the stacked first region 41 and second region 42 is not particularly limited, and for example, it may be 2 or more, or may be 3 or more. The upper limit of the number of each of the stacked first region 41 and second region 42 is not particularly limited, and for example, it may be 10 or less, or may be 6 or less.

[0056] The stacked first region 41 and second region 42 can be formed by alternately repeating an epitaxial growth process and a channeling ion implantation process. For example, the first region 41 in the lower layer is formed in the first epitaxial growth process. The first region 41 in the upper layer is formed in the second epitaxial growth process. Strictly speaking, the growth conditions of the first epitaxial growth process and the growth conditions of the second epitaxial growth process are different. Therefore, the impurity concentration of the first region 41 in the lower layer may be different from the impurity concentration of the first region 41 in the upper layer. From another perspective, when the impurity concentration profiles of the first region 41 in the upper layer and the first region 41 in the lower layer are measured by SIMS (Secondary Ion Mass Spectrometry) along the third direction 103, the impurity concentration profile of the first region 41 in the upper layer may be discontinuous with the impurity concentration profile of the first region 41 in the lower layer.

[0057] The height of each of the single-layer first region 41 and second region 42 is, for example, 2 μm or more and 4 μm or less. By stacking each of the first region 41 and the second region 42, the total thickness of each of the first region 41 and the second region 42 can be increased. The lower limit of the total thickness of each of the first region 41 and the second region 42 is not particularly limited, but may be, for example, 4 μm or more, or may be 6 μm or more. The upper limit of the total thickness of each of the first region 41 and the second region 42 is not particularly limited, but may be, for example, 30 μm or less, or may be 20 μm or less.

[0058] (Third Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the third embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the third embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to each of the first embodiment and the second embodiment in that the silicon carbide semiconductor device 100 is a planar MOSFET, and in other respects, it is the same as the configuration of the silicon carbide semiconductor device 100 according to each of the first embodiment and the second embodiment. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to each of the first embodiment and the second embodiment.

[0059] FIG. 5 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the third embodiment. As shown in FIG. 5, no trench 5 is provided in the element layer 40. The upper end surface of the element layer 40 is, for example, a flat surface. The gate insulating film 6 extends, for example, along a direction parallel to the first main surface 1. The gate insulating film 6 is in contact with each of the first impurity region 15, the second impurity region 23, and the third impurity region 30 on the upper end surface of the element layer 40.

[0060] As shown in FIG. 5, the first region 41 of the superjunction layer 10 faces each of the gate insulating film 6 and the third electrode 63. The second region 42 of the superjunction layer 10 faces each of the third impurity region 30 and the fourth impurity region 24. The second region 42 may be in contact with the third impurity region 30 and separated from the first impurity region 15.

[0061] (Fourth Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment is mainly different from the configuration of the silicon carbide semiconductor device 100 according to each of the first and second embodiments in that the silicon carbide semiconductor device 100 is a PN diode, and in other respects, it is the same as the configuration of the silicon carbide semiconductor device 100 according to each of the first and second embodiments. Hereinafter, the description will focus on the configuration different from the configuration of the silicon carbide semiconductor device 100 according to each of the first and second embodiments.

[0062] FIG. 6 is a schematic longitudinal sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment. As shown in FIG. 6, the element layer 40 has, for example, a p-type (second conductivity type). The 1 Electrode 62 is in contact with the element layer 40. The 1 Electrode 62 is provided on the element layer 40. The element layer 40 is provided on the superjunction layer 10. The element layer 40 is in contact with, for example, each of the first region 41 and the second region 42. The 2 Electrode 61 is, for example, a cathode electrode. The 1 Electrode 62 is, for example, an anode electrode.

[0063] Note that although the fourth embodiment shows an example of a PN diode, it can also be modified to a Schottky diode. That is, in FIG. 6, the element layer 40 may be replaced with a silicon carbide semiconductor layer to be a Schottky electrode.

[0064] Next, a method for measuring the concentration of p-type impurities and the concentration of n-type impurities in each impurity region will be described.

[0065] The concentrations of p-type impurities and n-type impurities in each impurity region can be measured using SIMS. The measuring device is, for example, a secondary ion mass spectrometer manufactured by Cameca. The measurement pitch is, for example, 0.01 μm. When the n-type impurity to be detected is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the p-type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0066] Next, a method for discriminating between the p-type region and the n-type region will be described. For the method of discriminating between the p-type region and the n-type region, SCM (Scanning Capacitance Microscope) is used. The measuring device is, for example, NanoScope IV manufactured by Bruker AXS. SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a silicon probe coated with metal is used to scan the surface of the sample. At this time, a high-frequency voltage is applied to the sample. The majority carriers are excited and the capacitance of the system is modulated. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V.

[0067] In the above description, it has been described that the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. The impurity concentration in the impurity region having n-type is the concentration of n-type impurities. The impurity concentration in the impurity region having p-type is the concentration of p-type impurities.

[0068] Next, the operation and effect of the silicon carbide semiconductor device 100 according to the above embodiment will be described. In a super junction structure, the on-resistance can be reduced as the impurity concentration in each of the first region 41 and the second region 42 is high and the pitch (the sum of the width of the first region 41 and the width of the second region 42) is small. Also, the breakdown voltage increases as the thickness of each of the first region 41 and the second region 42 is large. Therefore, in order to reduce the on-resistance and increase the breakdown voltage, it is desirable that the thickness of each of the first region 41 and the second region 42 is large and the pitch (the sum of the width of the first region 41 and the width of the second region 42) is small.

[0069] Normally, when impurity ions are implanted into a silicon carbide layer at a high acceleration energy, the scattering within the silicon carbide layer increases. Therefore, the width of the implantation region becomes larger than the opening width of the mask pattern. As a result, it is difficult to form a super junction structure with a large thickness and a small pitch. Also, in order to implant the impurity ions deeply, it is necessary to increase the thickness of the mask pattern. However, when the thickness of the mask pattern increases, problems such as an increase in stress and a large warp of the wafer also occur.

[0070] On the other hand, the implantation depth that can be formed at a low acceleration energy of about 1 MeV or less is about 1 μm. For example, in order to obtain a super junction layer 10 having a breakdown voltage of about 1.2 kV, it is necessary to repeat epitaxial growth and ion implantation about 5 to 6 times.

[0071] The super junction layer 10 of the silicon carbide semiconductor device 100 according to the present embodiment is formed by using a channeling implantation technique. Therefore, a super junction layer 10 with a large thickness and a small pitch can be formed at a low acceleration energy of about 1 MeV or less. Specifically, the sum of the width of the first portion 71 and the width of the third portion 73 is 0.5 μm or more and 4 μm or less, and the height of each of the first region 41 and the second region 42 is 2 μm or more. Thereby, the on-resistance can be reduced while improving the breakdown voltage.

[0072] According to the silicon carbide semiconductor device 100 according to the present embodiment, the number of times of each of epitaxial growth and ion implantation can be reduced. Therefore, it is possible to suppress polycrystalline silicon carbide particles from being sandwiched between epitaxial layers. As a result, the yield of the silicon carbide semiconductor device 100 can be improved.

[0073] Furthermore, when forming a p-type region by repeating epitaxial growth and ion implantation, it is necessary to connect the upper and lower p-type regions by overlapping a part of the p-type region formed in the lower epitaxial layer with a part of the p-type region formed in the upper epitaxial layer. The impurity concentration of the overlapping portion of the p-type region is higher than the impurity concentration of the non-overlapping portion of the p-type region. By reducing the number of times of each of epitaxial growth and ion implantation, the number of portions of the overlapping p-type region can be reduced. Therefore, it is possible to suppress the breakdown of the charge balance in the superjunction layer 10.

[0074] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of Reference Numerals

[0075] 1 First main surface, 2 Second main surface, 5 Trench, 6 Gate insulating film, 8 Side surface, 9 Bottom surface, 10 Superjunction layer, 11 Substrate, 12 Buffer layer, 13 Second drift layer, 14 First drift layer, 15 First impurity region, 20 Fifth impurity region, 21 First connection region, 22 Second connection region, 23 Second impurity region, 24 Fourth impurity region, 30 Third impurity region, 40 Element layer, 41 First region, 42 Second region, 6 2 First electrode, 6 1 Second electrode, 63 Third electrode (Gate electrode), 64 isolation insulating film, 71 first part, 72 second part, 73 third part, 74 fourth part, 100 silicon carbide semiconductor device, 101 first direction, 102 second direction, 103 third direction, P pitch, T1 first height, T2 second height, T3 third height, W1 first width, W2 second width, W3 third width, W4 fourth width.

Claims

1. A substrate made of a silicon carbide semiconductor of a first conductivity type, A superjunction layer provided above the first main surface of the substrate, having alternating first regions of the first conductivity type and second regions of a second conductivity type, An element layer provided above the superjunction layer, A first electrode provided on the element layer, A second electrode provided on the second main surface of the substrate facing the first main surface, comprising: The first region has a first portion and a second portion located between the first portion and the first main surface, The second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface, In a cross-section perpendicular to the second main surface and parallel to the direction from the first region to the second region, The width of the second portion is larger than the width of the first portion, The width of the fourth portion is smaller than the width of the third portion, The total value of the width of the first portion and the width of the third portion is 0.5 μm or more and 4 μm or less, The height of each of the first region and the second region is 2 μm or more, The second region is an ion implantation region, a silicon carbide semiconductor device.

2. In a cross-section perpendicular to the second main surface and parallel to the direction from the first region to the second region, The width of the first portion is smaller than the height of the first portion, The width of the third portion is smaller than the height of the third portion, the silicon carbide semiconductor device according to claim 1.

3. The impurity concentration in the third portion is higher than the impurity concentration in the fourth portion, the silicon carbide semiconductor device according to claim 1 or claim 2.

4. The impurity concentration of each of the first part and the third part is 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The silicon carbide semiconductor device according to any one of claims 1 to 3.

5. A buffer layer of the first conductivity type is provided between the superjunction layer and the substrate, and each of the second part and the fourth part is in contact with the buffer layer. The silicon carbide semiconductor device according to any one of claims 1 to 4.

6. The element layer includes a first impurity region of the first conductivity type, a second impurity region that is in contact with the first impurity region and has the second conductivity type, and a third impurity region that is separated from the first impurity region by the second impurity region and has the first conductivity type, and a trench is provided in the element layer, the trench having a side surface formed by each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface that is continuous with the side surface and is formed by the first impurity region, the first electrode is a source electrode, and the second electrode is a drain electrode, and a gate electrode is provided inside the trench. The silicon carbide semiconductor device according to any one of claims 1 to 5.

7. The first main surface is a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. The silicon carbide semiconductor device according to any one of claims 1 to 6.

8. The ion implantation region is a channeling ion implantation region. The silicon carbide semiconductor device according to any one of claims 1 to 7.

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