Imaging device and electronic apparatus

Abstract

[Problem] To provide an imaging device that is capable of being adapted to an increase in the number of analog-digital converters arranged in parallel while maintaining a chip size in which the contribution of a pixel chip on which pixels are disposed is dominant. [Solution] The imaging device according to the present disclosure has a layered chip structure in which at least three semiconductor chips including a first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are layered. A pixel array unit including pixels two-dimensionally arranged in a matrix is formed on the first layer semiconductor chip. An analog circuit unit of the analog-digital conversion unit that converts an analog pixel signal read from each pixel of the pixel array unit through a signal line into a digital pixel signal, is disposed on one of the second layer semiconductor chip and the third layer semiconductor chip. A digital circuit unit of the analog-digital conversion unit is disposed on the other of the second layer semiconductor chip and the third layer semiconductor chip.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and an electronic device.

Background Art

[0002] An imaging device is equipped with an analog-digital conversion unit that digitizes an analog pixel signal read from a pixel. The analog-digital conversion unit is a so-called column-parallel type analog-digital conversion unit composed of a plurality of analog-digital converters arranged corresponding to pixel columns.

[0003] In addition, in an imaging device, a pixel array unit in which pixels are arranged is formed on a first-layer semiconductor chip, while an analog-digital conversion unit is formed on a second-layer semiconductor chip, and a stacked chip structure in which the first-layer semiconductor chip and the second-layer semiconductor chip are stacked is adopted (see, for example, Patent Document 1). According to this stacked chip structure, as the first-layer semiconductor chip, one having a size (area) sufficient to form the pixel array unit 11 can be used, so that the size of the first-layer semiconductor chip, and thus the size of the entire chip, can be reduced.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the prior art described in Patent Document 1, two or four analog-digital converters are provided in parallel, and an analog pixel signal read in parallel from each pixel of two or four pixel rows is digitally processed in parallel by the two or four analog-digital converters, thereby shortening the read time of the pixel signal.

[0006] However, although the stacked chip structure aims to reduce the chip size, if the number of parallel analog-to-digital converters is increased, the size of the second-layer semiconductor chip, and ultimately the size of the entire chip, will increase.

[0007] The present disclosure aims to provide an imaging device that can accommodate an increase in the number of parallel analog-to-digital converters while maintaining a chip size in which the contribution of the pixel chip on which pixels are arranged is dominant, and an electronic device that has the imaging device. [Means for solving the problem]

[0008] In order to achieve the above object, the imaging device of the present disclosure comprises: A stacked chip structure is provided in which at least three semiconductor chips, a first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip, are stacked, The first-layer semiconductor chip has a pixel array section in which pixels are arranged two-dimensionally in a matrix. An analog circuit unit of an analog-to-digital conversion unit that converts analog pixel signals read out from each pixel of the pixel array unit through a signal line into digital pixel signals is disposed on one of the second layer semiconductor chip and the third layer semiconductor chip; A digital circuit section of an analog-to-digital conversion section is disposed on the other of the second-layer semiconductor chip and the third-layer semiconductor chip.

[0009] In order to achieve the above object, an electronic device according to the present disclosure includes an imaging device having the above configuration. [Brief description of the drawings]

[0010]

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MODE FOR CARRYING OUT THE INVENTION

[0011] Hereinafter, embodiments for carrying out the technology according to the present disclosure (hereinafter referred to as "embodiments") will be described in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiments, and various numerical values and the like in the embodiments are examples. In the following description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted. The description will be made in the following order. 1. Description regarding the imaging device and electronic device of the present disclosure in general 2. Imaging device according to the first embodiment 2-1. Configuration example of CMOS image sensor 2-2. Circuit Configuration Example of Pixel 2-3. Configuration Example of Analog-Digital Conversion Unit 2-4. Circuit Configuration Example of Comparator 2-4-1. Circuit Configuration Example 1 2-4-2. Circuit Configuration Example 2 2-4-3. Circuit Configuration Example 3 2-4-4. Circuit Configuration Example 4 2-5. Stacked Chip Structure 3. Imaging Device According to the Second Embodiment 3-1. Configuration Example of CMOS Image Sensor 3-2. Stacked Chip Structure 3-3. Electrical Connection Structure between Semiconductor Chips 3-3-1. Electrical Connection Structure Example 1 3-3-2. Electrical Connection Structure Example 2 4. Imaging Device According to the Third Embodiment 4-1. Configuration Example of CMOS Image Sensor 4-2. Stacked Chip Structure 5. Imaging Device According to the Fourth Embodiment 6. Imaging Device According to the Fifth Embodiment 7. Imaging Device According to the Sixth Embodiment 8. Imaging Device According to the Seventh Embodiment 9. Imaging Device According to the Eighth Embodiment 10. Modification Example 11. Application Example 12. Application Example of the Technology According to the Present Disclosure 12-1. Electronic Device of the Present Disclosure (Example of Imaging System) 12-2. Application Example to Mobile Body 13. Configurations That the Present Disclosure Can Adopt

[0012] <Description of the Imaging Device and Electronic Device According to the Present Disclosure in General> In the imaging device and the electronic device of the present disclosure, the analog-digital conversion unit includes a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit. For the analog-digital converter, it can be configured to have a comparator that compares an analog pixel signal with a reference signal of a ramp wave, and a counter that measures the time from the generation timing of the reference signal until the analog pixel signal and the reference signal of the ramp wave cross. Then, the comparator of the analog-digital conversion unit is arranged on one of the second-layer semiconductor chip and the third-layer semiconductor chip, and the counter of the analog-digital conversion unit is arranged on the other of the second-layer semiconductor chip and the third-layer semiconductor chip.

[0013] In the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, the second-layer semiconductor chip is arranged with the comparator of the analog-digital conversion unit and a load current source connected to the signal line, and the third-layer semiconductor chip can be configured to have the counter of the analog-digital conversion unit, a logic circuit unit, and an interface. Also, in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface, the third-layer semiconductor chip can be configured to have a memory unit or an AI (Artificial Intelligence) circuit.

[0014] Also, in the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, it can be configured to have a fourth-layer semiconductor chip. And the fourth-layer semiconductor chip can be configured to have a memory unit or an AI circuit. Also, for the fourth-layer semiconductor chip, it can be configured to have a size smaller than that of the semiconductor chips of other layers.

[0015] In the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, in the second-layer semiconductor chip, a counter, a logic circuit section, and an interface of the analog-digital conversion section are arranged, and in the third-layer semiconductor chip, a comparator of the analog-digital conversion section and a load current source connected to a signal line can be arranged.

[0016] In the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, for the analog-digital conversion section, it can be configured to include a plurality of systems of analog-digital conversion sections including a first analog-digital conversion section and a second analog-digital conversion section that convert each of the analog pixel signals read out in parallel from the pixels of each pixel row of the pixel array section into digital pixel signals. And for the signal line, in the length direction thereof, for each pixel column, it can be configured to be divided into a plurality of signal lines including a first signal line and a second signal line corresponding to the plurality of systems of analog-digital conversion sections.

[0017] In the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, for the first connection section that connects the first signal line and the first analog-digital conversion section and the second connection section that connects the second signal line and the second analog-digital conversion section, they can be configured to be provided in the vicinity within the region of the pixel array section. Also, for the first connection section and the second connection section, the first-layer semiconductor chip and the second-layer semiconductor chip can be connected by direct bonding using Cu electrodes.

[0018] <Imaging Device According to the First Embodiment> As an imaging device according to the first embodiment to which the technology according to the present disclosure is applied, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of X-Y address type imaging device, will be described as an example. This also applies to the embodiments described later. The CMOS image sensor is an image sensor manufactured by applying or partially using the CMOS process.

[0019] [Configuration Example of CMOS Image Sensor] FIG. 1 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor which is an example of an imaging device to which the technology according to the present disclosure is applied in a first embodiment.

[0020] The CMOS image sensor 1A according to the first embodiment has a configuration including a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11. The pixel array unit 11 has a configuration in which pixels (pixel circuits) 20 including light-receiving elements are two-dimensionally arranged in a row direction and a column direction, that is, in a matrix. Here, the row direction refers to the arrangement direction of the pixels 20 in a pixel row, and the column direction refers to the arrangement direction of the pixels 20 in a pixel column. The pixel 20 generates and accumulates photoelectric charges corresponding to the amount of received light by performing photoelectric conversion.

[0021] The peripheral circuit unit of the pixel array unit 11 is configured by, for example, a row selection unit 12, a load current source unit 13, an analog-digital conversion unit 14, a logic circuit unit 15 as a signal processing unit, and a timing control unit 16.

[0022] In the pixel array unit 11, pixel control lines 31 (311 to 31 m ) are wired along the row direction for each pixel row of the matrix-like pixel arrangement. Also, signal lines 32 (321 to 32 n ) are wired along the column direction for each pixel column. The pixel control line 31 transmits a drive signal for driving when reading a signal from the pixel 20. In FIG. 1, the pixel control line 31 is shown as a single wiring, but it is not limited to one. One end of the pixel control line 31 is connected to an output end corresponding to each row of the row selection unit 12.

[0023] Hereinafter, each component of the peripheral circuit unit of the pixel array unit 11, that is, the row selection unit 12, the load current source unit 13, the analog-digital conversion unit 14, the logic circuit unit 15, and the timing control unit 16 will be described.

[0024] The row selection unit 12 is composed of a shift register, an address decoder, etc., and controls the scanning of pixel rows and the addresses of pixel rows when selecting each pixel 20 of the pixel array unit 11. Although the specific configuration of this row selection unit 12 is not shown in the figure, generally, it has a configuration with two scanning systems: a readout scanning system and a blanking scanning system.

[0025] The readout scanning system sequentially selects and scans the pixels 20 of the pixel array unit 11 row by row in order to read out pixel signals from the pixels 20. The pixel signals read out from the pixels 20 are analog signals. The blanking scanning system performs blanking scanning on the readout row where readout scanning is performed by the readout scanning system, with a time corresponding to the shutter speed ahead of the readout scanning.

[0026] By the blanking scanning by this blanking scanning system, unnecessary charges are swept out from the photoelectric conversion units of the pixels 20 in the readout row, thereby resetting the photoelectric conversion units. And by sweeping out (resetting) the unnecessary charges by this blanking scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding the photoelectric charges of the photoelectric conversion unit and starting new exposure (starting the accumulation of photoelectric charges).

[0027] The load current source unit 13 consists of a set of a plurality of load current sources I (see FIG. 2) connected to each of the signal lines 321 to 32 n for each pixel column. The load current source I is composed of, for example, a MOS field effect transistor (FET), and supplies a bias current to each pixel 20 of the pixel row selected and scanned by the row selection unit 12 through each of the signal lines 321 to 32 n respectively.

[0028] The analog-digital conversion unit 14 consists of a set of a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit 11 (for example, for each pixel column). The analog-digital conversion unit 14 is provided with signal lines 321 to 32 for each pixel column nIt is a column-parallel analog-to-digital conversion unit that converts the analog pixel signals output through each of them into digital signals.

[0029] As the analog-to-digital converter in the analog-to-digital conversion unit 14, for example, a single-slope type analog-to-digital converter, which is an example of a reference signal comparison type analog-to-digital converter, can be used. However, the analog-to-digital converter is not limited to the single-slope type analog-to-digital converter, and a successive approximation type analog-to-digital converter, a delta-sigma modulation type (ΔΣ modulation type) analog-to-digital converter, etc. can be used.

[0030] The logic circuit unit 15, which is a signal processing unit, reads the pixel signals digitized by the analog-to-digital conversion unit 14 and performs predetermined signal processing. Specifically, in the logic circuit unit 15, as the predetermined signal processing, for example, correction of vertical line defects and dot defects, or clamping of signals, and further, digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operation is performed. The logic circuit unit 15 outputs the generated image data to the subsequent device as the output signal OUT of this CMOS image sensor 1A.

[0031] The timing control unit 16 generates various timing signals, clock signals, control signals, etc. based on the synchronization signal given from the outside. Then, the timing control unit 16 performs drive control of the row selection unit 12, the analog-to-digital conversion unit 14, the logic circuit unit 15, etc. based on these generated signals.

[0032] [Example of Pixel Circuit Configuration] FIG. 2 is a circuit diagram showing an example of the circuit configuration of the pixel 20. The pixel 20 has, for example, a photodiode 21 as a photoelectric conversion element that is a light receiving element. In addition to the photodiode 21, the pixel 20 has a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0033] As the four transistors, namely the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, for example, N-channel MOS field-effect transistors are used. However, the combination of conductivity types of the four transistors 22 to 25 illustrated here is only an example and is not limited to these combinations.

[0034] For this pixel 20, as the aforementioned pixel control lines 31 (311 to 31 m ), a plurality of pixel control lines are commonly wired to each pixel 20 in the same pixel row. These plurality of pixel control lines are connected in pixel row units to the output terminals corresponding to each pixel row of the row selection unit 12. The row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines.

[0035] The photodiode 21 has its anode electrode connected to a low-potential side power supply (for example, ground), and photoelectrically converts the received light into photocharges (here, photoelectrons) with a charge amount corresponding to the light amount and accumulates the photocharges. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region where the gate electrode of the amplification transistor 24 is electrically connected is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage conversion unit that converts charge into voltage.

[0036] A transfer signal TRG at a high level (for example, V DD level) that becomes active is given from the row selection unit 12 to the gate electrode of the transfer transistor 22. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, transfers the photocharges photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffusion FD.

[0037] The reset transistor 23 is a high-potential side power supply voltage V DDis connected between the node and the floating diffusion FD. A reset signal RST, at a high level of which is active, is supplied from the row selection unit 12 to the gate electrode of the reset transistor 23. The reset transistor 23 becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the node at voltage V DD thereby resetting the floating diffusion FD.

[0038] The gate electrode of the amplification transistor 24 is connected to the floating diffusion FD, and the drain electrode is connected to the node at the high potential side power supply voltage V DD respectively. The amplification transistor 24 serves as the input part of a source follower that reads out the signal obtained by the photoelectric conversion in the photodiode 21. That is, the source electrode of the amplification transistor 24 is connected to the signal line 32 via the selection transistor 25. Then, the amplification transistor 24 and the current source I connected to one end of the signal line 32 constitute a source follower that converts the voltage of the floating diffusion FD into the potential of the signal line 32.

[0039] The drain electrode of the selection transistor 25 is connected to the source electrode of the amplification transistor 24, and the source electrode is connected to the signal line 32. A selection signal SEL, at a high level of which is active, is supplied from the row selection unit 12 to the gate electrode of the selection transistor 25. The selection transistor 25 becomes conductive in response to the selection signal SEL, and transmits the signal output from the amplification transistor 24 to the signal line 32 with the pixel 20 in a selected state.

[0040] Further, in the above circuit example, as the pixel 20, an example of a 4Tr configuration including a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25, that is, a configuration including four transistors (Tr) was given, but it is not limited to this. For example, the selection transistor 25 may be omitted, and a 3Tr configuration may be adopted in which the amplification transistor 24 has the function of the selection transistor 25. Alternatively, if necessary, a configuration with five or more transistors may be adopted by increasing the number of transistors.

[0041] [Configuration Example of Analog-Digital Conversion Unit] Next, an example of the configuration of the analog-digital conversion unit 14 will be described. Here, a case where a single-slope type analog-digital converter is used as each analog-digital converter of the analog-digital conversion unit 14 will be described as an example.

[0042] An example of the configuration of the analog-digital conversion unit 14 is shown in FIG. 3. In the CMOS image sensor 1A according to the first embodiment, the analog-digital conversion unit 14 is composed of a set of a plurality of single-slope type analog-digital converters provided corresponding to each pixel column of the pixel array unit 11. Here, the single-slope type analog-digital converter 140 in the n-th column will be described as an example.

[0043] The analog-digital converter 140 has a circuit configuration including a comparator 141 and a counter 142. In the single-slope type analog-digital converter 140, the reference signal generated by the reference signal generation unit 17 is used. The reference signal generation unit 17 generates a reference signal V RAMP of a ramp wave whose level (voltage) monotonically decreases over time, and supplies it as a reference signal to the comparator 141 provided for each pixel column.

[0044] The comparator 141 uses the analog pixel signal V VSL read from the pixel 20 as a comparison input, and the ramp wave reference signal V RAMPTaking this as the reference input, the two signals are compared. And the comparator 141, for example, outputs a signal in the first state (e.g., high level) when the reference signal V RAMP is greater than the pixel signal V VSL , and outputs a signal in the second state (e.g., low level) when the reference signal V RAMP is less than or equal to the pixel signal V VSL . Thus, the comparator 141 outputs, as the comparison result, a pulse signal having a pulse width corresponding to the signal level of the pixel signal VVSL, specifically, corresponding to the magnitude of the signal level.

[0045] The counter 142 is supplied with the clock signal CLK from the timing control unit 16 at the same timing as the start timing of the supply of the reference signal V RAMP to the comparator 141. And the counter 142 measures the period of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation, by performing a counting operation in synchronization with the clock signal CLK. The count result (count value) of the counter 142 is supplied to the logic circuit unit 15 as a digital value obtained by digitizing the analog pixel signal V VSL .

[0046] As described above, in the analog-digital conversion unit 14 composed of a set of single-slope type analog-digital converters 140, a digital value is obtained from the time information until the magnitude relationship between the ramp wave reference signal V RAMP generated by the reference signal generation unit 17 and the analog pixel signal V VSL output from the pixel 20 changes.

[0047] Note that in the above example, as the analog-digital conversion unit 14, a configuration in which the analog-digital converters 140 are arranged in a one-to-one correspondence with the pixel columns of the pixel array unit 11 is illustrated, but a configuration in which the analog-digital converters 140 are arranged in units of a plurality of pixel columns is also possible.

[0048] [Example of Circuit Configuration of Comparator] As the comparator 141 of the analog-digital converter 140, comparators with various configurations can be used. Hereinafter, specific circuit configuration examples of the comparator that can be used as the comparator 141 of the analog-digital converter 140 will be described.

[0049] (Circuit Configuration Example 1) FIG. 4 is a circuit diagram showing the circuit configuration of the comparator according to Circuit Configuration Example 1. The comparator 50A according to Circuit Configuration Example 1 includes a differential amplifier 51, a first capacitive element C 11 , a second capacitive element C 12 , a first switch transistor NT 13 , and a second switch transistor NT 14 .

[0050] The first switch transistor PT 13 and the second switch transistor PT 14 are an example of a switch element. Here, as the first switch transistor PT 13 and the second switch transistor PT 14 , for example, an N-channel MOS transistor is used, but a P-channel MOS transistor may also be used.

[0051] The differential amplifier 51 includes a first differential transistor NT 11 , a second differential transistor NT 12 , a current source I 11 , a first load transistor PT 11 , and a second load transistor PT 12 . Here, an N-channel MOS transistor is used as the first differential transistor NT 11 and the second differential transistor NT 12 , and a P-channel MOS transistor is used as the first load transistor PT 11 and the second load transistor PT 12 .

[0052] In the differential amplifier 51, the first differential transistor NT 11and the second differential transistor NT 12 forms a differential pair in which the source electrodes are commonly connected to perform differential operation. The current source I 11 is connected between the source common connection node of the first differential transistor NT 11 and the second differential transistor NT 12 and the ground GND. The first load transistor PT 11 has a diode-connected configuration in which the gate electrode and the drain electrode are commonly connected, and is connected in series to the first differential transistor NT 11 . That is, the drain electrodes of the first load transistor PT 11 and the first differential transistor NT 11 are commonly connected.

[0053] The second load transistor PT 12 is connected in series to the second differential transistor NT 12 . That is, the drain electrodes of the second load transistor PT 12 and the second differential transistor NT 12 are commonly connected. And the first load transistor PT 11 and the second load transistor PT 12 form a current mirror circuit by commonly connecting the gate electrodes.

[0054] Also, the common connection node N 12 between the second differential transistor NT12 and the second load transistor PT 11 serves as the output node of the differential amplifier 51, and the output signal OUT is derived from the output terminal T 10 through the said output node. The source electrodes of the first load transistor PT 11 and the second load transistor PT 12 are connected to the node of the power supply voltage V DD .

[0055] The first capacitive element C 11 is connected to the input terminal T of the reference signal V RAMP of the ramp wave11 and the first differential transistor NT 11 is connected between the gate electrode of, and a reference signal V RAMP to form an input capacitance with respect to. The second capacitive element C 12 is the input terminal T of the pixel signal V VSL and the second differential transistor NT 12 is connected between the gate electrode of, and the pixel signal V 12 to form an input capacitance with respect to. VSL

[0056] The first switch transistor NT 13 is connected between the gate electrode and the drain electrode of the first differential transistor NT 11 . The second switch transistor NT 14 is connected between the gate electrode and the drain electrode of the second differential transistor NT 12 . The first switch transistor NT 13 and the second switch transistor NT 14 are selectively auto-zeroed (initialized) by being turned on (conducted) / off (non-conducted) by a drive signal AZ input via the input terminal T 13 from the timing control unit 16 shown in FIG. 1.

[0057] The comparator 50A according to Circuit Configuration Example 1 described above is a well-known comparator having a differential amplifier configuration. In the case of the comparator 50A according to Circuit Configuration Example 1, since it is necessary to secure an input range corresponding to the signal amount of the pixel 20, the power supply voltage V DD needs to be set relatively high (for example, about 1.8 V).

[0058] (Circuit Configuration Example 2) FIG. 5 is a circuit diagram showing the circuit configuration of the comparator according to Circuit Configuration Example 2. The comparator 50B according to Circuit Configuration Example 2 includes a differential amplifier 51, a first capacitive element C 21 , a second capacitive element C 22 , a third capacitive element C 23 , a first switch transistor PT 23 , and a second switch transistor PT 24 ​It has a configuration including

[0059] The first switch transistor PT 23 and the second switch transistor PT 24 are an example of an auto-zero switch. Here, the first switch transistor PT 23 and the second switch transistor PT 24 are, for example, P-channel MOS transistors, but N-channel MOS transistors may also be used.

[0060] The differential amplifier 51 is composed of the first differential transistor PT 21 , the second differential transistor PT 22 , the current source I 21 , the first load transistor NT 21 , and the second load transistor NT 22 . Here, the first differential transistor PT 21 and the second differential transistor PT 22 are P-channel MOS transistors, and the first load transistor NT 21 and the second load transistor NT 22 are N-channel MOS transistors, but these differential transistors and load transistors may be configured with the opposite channel (opposite conductivity type).

[0061] In the differential amplifier 51, the first differential transistor PT 21 and the second differential transistor PT 22 form a differential pair with their source electrodes commonly connected to perform a differential operation. The current source I 21 is connected between the source common connection node of the first differential transistor PT 21 and the second differential transistor PT 22 and the node of the power supply voltage V DD . The first load transistor NT 21 has a diode-connected configuration with its gate electrode and drain electrode commonly connected, and the first differential transistor PT 21is connected in series therewith. That is, the first load transistor NT 21 and the first differential transistor PT 21 have their drain electrodes commonly connected.

[0062] The second load transistor NT 22 is connected in series with respect to the second differential transistor PT 22 That is, the second load transistor NT 22 and the second differential transistor PT 22 have their drain electrodes commonly connected. And the first load transistor NT 21 and the second load transistor NT 22 constitute a current mirror circuit by having their gate electrodes commonly connected.

[0063] Also, the common connection node between the second differential transistor PT 22 and the second load transistor NT 22 serves as the output node of the differential amplifier 51, and an output signal OUT is derived from the output node through an output terminal T 20 The source electrodes of the first load transistor NT 21 and the second load transistor NT 22 are each connected to a low potential side power source, for example, ground GND.

[0064] The first capacitive element C 21 is connected between the input terminal T VSL of the pixel signal V 21 and the gate electrode of the first differential transistor PT 21 and serves as an input capacitance with respect to the pixel signal V VSL The second capacitive element C 22 is connected between the input terminal T RAMP of the reference signal V of the ramp wave 22 and the gate electrode of the first differential transistor PT21 and serves as an input capacitance with respect to the reference signal V RAMP Accordingly, the first differential transistor PT 21 is responsive to the pixel signal V VSL and the reference signal VRAMP is the signal synthesized (added) through the first capacitive element C 21 and the second capacitive element C 22 as the gate input.

[0065] The first switch transistor PT 23 is connected between the gate electrode and the drain electrode of the first differential transistor PT 21 . The second switch transistor PT 24 is connected between the gate electrode and the drain electrode of the second differential transistor PT 22 . The first switch transistor PT 23 and the second switch transistor PT 24 are selectively auto-zeroed (initialized) by being turned on / off controlled by the drive signal AZ input from the timing control unit 16 shown in FIG. 1 via the input terminal T 23 .

[0066] The third capacitive element C 23 is connected between the gate electrode of the second differential transistor PT22 and the input terminal T of a predetermined voltage REF 24 . Thereby, the second differential transistor PT 22 uses the predetermined voltage REF applied through the terminal T 24 as the gate input through the third capacitive element C 23 . The predetermined voltage REF is an arbitrary constant voltage such as the power supply voltage V DD , the GND (ground) level, etc. Here, the predetermined voltage REF is set to the GND level.

[0067] According to the comparator 50B according to the above-described circuit configuration example 2, regardless of the signal amount of the pixel 20, the input voltage of the differential amplifier 51 at the time of inversion of the output signal OUT of the differential amplifier 51 does not vary and is constant. Therefore, it is possible to reduce the power supply voltage V DD to a low voltage (for example, about 1.3V). As a result, the power consumption of the analog-digital conversion unit 14 can be reduced, and thus the CMOS image sensor 1A can be made to consume less power.

[0068] (Circuit Configuration Example 3) FIG. 6 is a circuit diagram showing the circuit configuration of a comparator according to Circuit Configuration Example 3. The comparator 50C according to Circuit Configuration Example 3 includes a first capacitor element C 31 , a second capacitor element C 32 , an input transistor PT 31 , a switch transistor PT 32 , a first current source transistor NT 31 , and a second current source transistor NT 32 .

[0069] The switch transistor PT 32 is an example of an auto-zero switch. Here, as the switch transistor PT 32 , for example, a P-channel MOS transistor is used, but an N-channel MOS transistor may also be used. A predetermined bias voltage V 31 is applied to the gate electrode of the first current source transistor NT bias1 . A predetermined bias voltage V 32 is applied to the gate electrode of the second current source transistor NT bias2 .

[0070] The first current source transistor NT 31 , the input transistor PT 31 , and the second current source transistor NT 32 are connected in series in that order between the node of the power supply voltage V DD and the low potential side power supply, for example, ground GND. And the common connection node between the input transistor PT 31 and the second current source transistor NT 32 becomes the output node, and the output signal OUT is derived from the output node through the output terminal T 30 .

[0071] The first capacitor element C 31 is connected between the input terminal T VSL of the pixel signal V 31 and the gate electrode of the input transistor PT 31 , and the pixel signal V VSLserves as the input capacitance for. The second capacitive element C 32 is connected between the input terminal T RAMP of the reference signal V of the ramp wave 32 and the gate electrode of the input transistor PT 31 and serves as the input capacitance for the reference signal V RAMP . As a result, the input transistor PT 31 uses, as the gate input, the signal obtained by synthesizing (adding) the pixel signal V VSL and the reference signal V RAMP through the first capacitive element C 31 and the second capacitive element C 32 .

[0072] The switch transistor PT 32 is connected between the gate electrode and the drain electrode of the input transistor PT 31 . The switch transistor PT 32 selectively performs auto-zero (initialization operation) by being turned on / off by the drive signal AZ input through the input terminal T 33 from the timing control unit 16 shown in FIG. 1.

[0073] The comparator 50C according to Circuit Configuration Example 3 described above is a comparator obtained by simplifying the comparator 50B according to Circuit Configuration Example 2 having a differential amplifier configuration, and the current flowing through the second current source transistor NT 32 can be reduced to about half of that of the comparator 50B according to Circuit Configuration Example 2. As a result, further power consumption reduction of the analog-digital conversion unit 14 and, consequently, power consumption reduction of the CMOS image sensor 1A can be achieved as compared with the case of the comparator 50B according to Circuit Configuration Example 2.

[0074] (Circuit Configuration Example 4) FIG. 7 is a circuit diagram showing the circuit configuration of the comparator according to Circuit Configuration Example 4. The comparator 50D according to Circuit Configuration Example 4 includes a first capacitive element C 41 , an input transistor PT 41 , an input-side load current source I 41 , a second capacitive element C 42 , an output transistor PT 42 , and an output-side load current source I42 and a switch transistor PT 43 are configured to include them.

[0075] Input transistor PT 41 is composed of a P-channel MOS transistor and is connected between the signal line 32 and the input-side load current source I 41 . Specifically, the source electrode of the input transistor PT 41 is connected to the signal line 32, and the drain electrode is connected to one end of the input-side load current source I 41 . As a result, the pixel signal V 41 is input to the source electrode of the input transistor PT through the signal line 32 VSL .

[0076] Input-side load current source I 41 The other end is connected to a low-potential side power source, for example, the ground GND. The input-side load current source I 41 supplies a constant current I 41 to the series connection circuit of the input transistor PT and the signal line 32 d1 . For the input-side load current source I 41 , for example, it can be configured using an N-channel MOS transistor or the like.

[0077] The first capacitive element C 41 is connected between the input terminal T RAMP of the reference signal V of the ramp wave and the gate electrode of the input transistor PT 41 and serves as the input capacitance with respect to the reference signal V 41 . As a result, the pixel signal V RAMP is input to the source electrode of the input transistor PT through the signal line 32, and the reference signal V 41 of the ramp wave is input to the gate electrode through the first capacitive element C VSL . RAMP 41 41 RAMP

[0078] Input transistor PT 41 has a reference signal V input to its gate electrode RAMPand the pixel signal V input to the source electrode VSL and the difference therebetween, i.e., the gate-source voltage V 41 of the input transistor PT gs is amplified and output as a drain voltage from the drain electrode. Note that, in the input transistor PT 41 it is desirable that the back gate electrode and the source electrode be short-circuited to suppress the back gate effect.

[0079] The switch transistor PT 43 is an example of an auto-zero switch connected between the gate electrode and the drain electrode of the input transistor PT 41 . Here, as the switch transistor PT 43 for example, a P-channel MOS transistor is used, but an N-channel MOS transistor may also be used. The switch transistor PT 43 is selectively auto-zeroed (initialized operation) by being turned on / off controlled by a drive signal AZ input from the timing control unit 16 shown in FIG. 1 via an input terminal T 42 .

[0080] The second capacitor element C 42 is connected in parallel to the input transistor PT 41 . Specifically, one end of the second capacitor element C 42 is connected to the source electrode of the input transistor PT 41 , and the other end of the second capacitor element C 42 is connected to the drain electrode of the input transistor PT 41 .

[0081] The output transistor PT 42 is composed of, for example, a P-channel MOS transistor and is connected between the signal line 32 and the output-side load current source I 42 . Specifically, the source electrode of the output transistor PT 42 is connected to the signal line 32, and the drain electrode is connected to one end of the output-side load current source I 42 . Thereby, the output transistor PT 42The source electrode of VSL receives the pixel signal V through the signal line 32.

[0082] The other end of the output-side load current source I 42 is connected to the low-potential side power supply, for example, the ground GND. The output-side load current source I 42 supplies a constant current I 42 to the series connection circuit of the output transistor PT d2 and the signal line 32. The output-side load current source I 42 can be configured using, for example, an N-channel MOS transistor or the like.

[0083] The gate electrode of the output transistor PT 42 is connected to the drain electrode of the input transistor PT 41 . As a result, the drain voltage of the input transistor PT 42 is input to the gate electrode of the output transistor PT 41 . It is desirable to short-circuit the back gate electrode and the source electrode of the output transistor PT 42 in order to suppress the back gate effect.

[0084] The output transistor PT 42 outputs a signal OUT indicating whether the voltage difference between the pixel signal V VSL input to the source electrode through the signal line 32 and the drain voltage of the input transistor PT 41 input to the gate electrode exceeds a predetermined threshold voltage from the drain electrode through the output terminal T 40 .

[0085] Note that the circuit configuration of the comparator 50D according to Circuit Configuration Example 4 illustrated here is an example and is not limited to this circuit configuration. Specifically, in the circuit configuration subsequent to the input transistor PT 41 , for example, a clamp transistor that suppresses the decrease in the drain voltage when the input transistor PT 41 is in the non-conducting state is added to the input transistor PT 41It can be configured to be provided in parallel with respect to 41 . Alternatively, regardless of the potential of the signal line 32, a clamp transistor that limits the lower limit of the drain voltage of the input transistor PT 41 can be configured to be provided in parallel with respect to the input transistor PT

[0086] The comparator 50D according to the above-described circuit configuration example 4 has a circuit configuration in which a load current source connected to the signal line 32 (corresponding to the load current source I in FIG. 2) is shared as the load current source used in the comparator 50D in the same single comparator as the circuit configuration example 3. Also in the case of the comparator 50D according to the circuit configuration example 4, the low power consumption of the analog-digital conversion unit 14 due to the reduction of the power supply voltage V DD of the comparator 50D can be achieved, and thus the low power consumption of the CMOS image sensor 1A can be achieved.

[0087] [Stacked chip structure] The CMOS image sensor 1A according to the first embodiment has a stacked chip structure in which at least three semiconductor chips, namely, the semiconductor chip of the first layer, the semiconductor chip of the second layer, and the semiconductor chip of the third layer, are stacked. A schematic exploded perspective view of the stacked chip structure of the CMOS image sensor 1A according to the first embodiment is shown in FIG. 8.

[0088] As shown in FIG. 8, the CMOS image sensor 1A according to the first embodiment has a stacked chip structure in which the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, and the semiconductor chip 43 of the third layer are stacked.

[0089] And, in the semiconductor chip 41 of the first layer, a pixel array unit 11 in which pixels 20 are two-dimensionally arranged in a matrix is formed. Also, pads 51 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor chip 41 of the first layer.

[0090] In the second-layer semiconductor chip 42, an analog circuit section of the analog-digital conversion section 14, specifically, a comparator 141 of the analog-digital converter 140 is arranged. In the second-layer semiconductor chip 42, further, a load current source section 13 and a reference signal generation section 17 are arranged. Note that the arrangement of the load current source section 13, the reference signal generation section 17, and the comparator 141 on the second-layer semiconductor chip 42 shown in FIG. 4 is an example and is not limited to this arrangement example.

[0091] In the third-layer semiconductor chip 43, a digital circuit section of the analog-digital conversion section 14, specifically, a counter 142 of the analog-digital converter 140 is arranged. In the third-layer semiconductor chip 43, further, a logic circuit section 15 which is a signal processing section, a row selection section 12, and an interface (I / F) 18 are arranged. Note that the arrangement of the counter 142, the logic circuit section 15, the row selection section 12, and the interface 18 on the third-layer semiconductor chip 43 shown in FIG. 4 is an example and is not limited to this arrangement example.

[0092] At, for example, both left and right ends of the second-layer semiconductor chip 42, connection parts (VIAs) 52 and 53 for electrically connecting the semiconductor chip 42 and the semiconductor chip 43 are provided. Examples of the connection parts 52 and 53 include a through-silicon via (TSV) and a metal-metal junction including a Cu-Cu junction.

[0093] In the above-described stacked chip structure, the signal lines 32 (see FIG. 1) wired for each pixel column in the pixel array section 11 of the first-layer semiconductor chip 41 and each load current source I (see FIG. 2) of the load current source section 13 arranged in the second-layer semiconductor chip 42 are electrically connected for each pixel column through the first-layer connection section 54 and the second-layer connection section 55. Further, the comparator 141 arranged in the second-layer semiconductor chip 42 and the counter 142 arranged in the third-layer semiconductor chip 43 are electrically connected for each pixel column through the second-layer connection section 56 and the third-layer connection section 57. Examples of the connection section 54, the connection section 55, the connection section 56, and the connection section 57 include a silicon through electrode (TSV) and a metal-metal junction including a Cu-Cu junction.

[0094] In the above example, the analog circuit section of the analog-digital conversion section 14 is formed in the second-layer semiconductor chip 42, and the digital circuit section of the analog-digital conversion section 14 is formed in the third-layer semiconductor chip 43. However, the reverse configuration may also be used. That is, a configuration may be adopted in which the digital circuit section of the analog-digital conversion section 14 is formed in the second-layer semiconductor chip 42, and the analog circuit section of the analog-digital conversion section 14 is formed in the third-layer semiconductor chip 43.

[0095] In the above example, the case where the stacked chip structure is a three-layer stacked structure is illustrated. However, the present invention is not limited to the three-layer stacked structure, and a stacked structure of four or more layers may be used. In the case of a stacked structure of four or more layers, the analog circuit section and the digital circuit section of the analog-digital conversion section 14 can be arranged in a dispersed manner in the semiconductor chips of each layer after the second layer.

[0096] As described above, according to the CMOS image sensor 1A according to the first embodiment, by adopting a stacked chip structure of three or more layers and arranging (forming) the analog circuit section and the digital circuit section of the analog-digital conversion section 14 in semiconductor chips of different layers, the following operations and effects can be obtained.

[0097] For example, as shown in FIG. 9, when a plurality of systems (e.g., four systems) of analog-digital converters 140 are provided in parallel for each pixel column to increase the number of lines read out simultaneously, in the case of a two-layer stacked structure, the size of the second semiconductor chip, and thus the size of the entire chip, increases by the increased number of analog-digital converters 140 in parallel. On the other hand, by adopting a stacked structure of three or more layers and arranging the analog circuit portion and the digital circuit portion of the analog-digital conversion unit 14 on semiconductor chips of different layers, the parallel number of analog-digital converters 140 can be increased while maintaining the chip size dominated by the contribution of the first semiconductor chip 41 on which the pixel array portion 11 is formed, thereby improving the frame rate.

[0098] Further, according to the CMOS image sensor 1A according to the first embodiment having a stacked chip structure of three or more layers, a process suitable for fabricating the pixels 20 can be applied to the first semiconductor chip 41. Also, in the case of the above example, a low-cost process (e.g., 55 nm process) suitable for fabricating the analog circuit portion of the analog-digital conversion unit 14 can be applied to the second semiconductor chip 42, and a process (e.g., 22 nm process) suitable for fabricating the digital circuit portion of the analog-digital conversion unit 14 can be applied to the third semiconductor chip 43, so that optimization of characteristics and cost becomes possible. In particular, when fabricating the digital circuit portion, the application of a leading-edge process becomes possible.

[0099] <Imaging Device According to the Second Embodiment> The imaging device according to the second embodiment to which the technology according to the present disclosure is applied is composed of a CMOS image sensor, similar to the case of the first embodiment. The pixel array portion 11 is divided into a plurality of regions, e.g., two regions, in the column direction, and correspondingly, the signal lines 32 are divided into a plurality of signal lines (e.g., two divisions) in the length direction (column direction).

[0100] [Configuration Example of CMOS Image Sensor] FIG. 10 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor which is an example of an imaging device to which the technology according to the present disclosure is applied in a second embodiment.

[0101] In the CMOS image sensor 1B according to the second embodiment, a pixel array unit 11 in which pixels 20 are arranged in a matrix is divided into, for example, two regions 11A and 11B in the column direction. Correspondingly, signal lines 32 are divided into a first signal line 32A (32A1 to 32A n ) and a second signal line 32B (32B1 to 32B n ) for each pixel column in the length direction (column direction).

[0102] Also, corresponding to the two regions 11A and 11B of the pixel array unit 11, two load current source units 13 and two analog-digital conversion units 14 are provided. Specifically, a load current source unit 13A and an analog-digital conversion unit 14A are provided corresponding to the region 11A of the pixel array unit 11, and a load current source unit 13B and an analog-digital conversion unit 14B are provided corresponding to the region 11B of the pixel array unit 11. A logic circuit unit 15 as a signal processing unit is provided, for example, in common for the two regions 11A and 11B of the pixel array unit 11.

[0103] The circuit configurations of the pixels 20 in the two regions 11A and 11B of the pixel array unit 11 and the configurations of the analog-digital converters of the analog-digital conversion unit 14 are basically the same as those in the case of the CMOS image sensor 1A according to the first embodiment.

[0104] [Stacked chip structure] FIG. 11 shows a schematic exploded perspective view of the stacked chip structure of the CMOS image sensor 1B according to the second embodiment.

[0105] As shown in FIG. 11, similar to the case of the CMOS image sensor 1A according to the first embodiment, the CMOS image sensor 1B according to the second embodiment also has a stacked chip structure in which at least three semiconductor chips, i.e., the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, and the semiconductor chip 43 of the third layer, are stacked.

[0106] In the semiconductor chip 41 of the first layer, two divided regions 11A and 11B of the pixel array portion 11 in which pixels 20 are two-dimensionally arranged in a matrix are formed with connection portions (VIAs) 54A and 54B for electrical connection to the semiconductor chip 42 of the second layer interposed therebetween. Further, pads 51 for external connection and power supply are provided, for example, at both left and right ends of the semiconductor chip 41 of the first layer.

[0107] In the semiconductor chip 42 of the second layer, an analog circuit portion of the analog-digital conversion unit 14, specifically, comparators 141A and 141B of the analog-digital converter 140 are arranged. In the semiconductor chip 42 of the second layer, load current source portions 13A and 13B are further arranged with connection portions (VIAs) 55A and 55B for electrical connection to the semiconductor chip 41 of the first layer interposed therebetween.

[0108] Further, in the semiconductor chip 42 of the second layer, a reference signal generation unit 17 is preferably arranged at a position equidistant from the comparators 141A and 141B. Here, the "equidistant" means not only the case of being strictly equidistant but also the case of being substantially equidistant, and the existence of various variations caused in design or manufacturing is allowed.

[0109] Note that the arrangement of the comparators 141A and 141B, the load current source portions 13A and 13B, and the reference signal generation unit 17 of the analog-digital converter 140 on the semiconductor chip 42 of the second layer shown in FIG. 11 is an example and is not limited to this arrangement example.

[0110] In the third-layer semiconductor chip 43, the digital circuit part of the analog-digital conversion part 14, specifically, the counters 142A and 142B of the analog-digital converter 140 are arranged. In the third-layer semiconductor chip 43, further, a logic circuit part 15 which is a signal processing part, a row selection part 12, and an interface (I / F) 18 are arranged.

[0111] Note that the arrangement of the counters 142A and 142B, the logic circuit part 15, the row selection part 12, and the interface 18 on the third-layer semiconductor chip 43 shown in FIG. 11 is an example and is not limited to this arrangement example.

[0112] In the above-described stacked chip structure, the signal lines 32A and 32B which are divided and wired for each pixel column in the two regions 11A and 11B of the first-layer semiconductor chip 41 and the circuit parts arranged corresponding to the two regions 11A and 11B in the second-layer semiconductor chip 42 are electrically connected for each pixel column through the first-layer connection parts 54A and 54B and the second-layer connection parts 55A and 55B.

[0113] More specifically, the first signal line 32A and each load current source I of the load current source part 13A and the comparator 141A are electrically connected through the first-layer connection part 54A and the second-layer connection part 55A which are the first connection parts. Also, the second signal line 32B and each load current source I of the load current source part 13B and the comparator 141B are electrically connected through the first-layer connection part 54B and the second-layer connection part 55B which are the second connection parts.

[0114] Also, the comparators 141A and 141B arranged corresponding to the two regions 11A and 11B in the second-layer semiconductor chip 42 and the counters 142A and 142B arranged in the third-layer semiconductor chip 43 are electrically connected for each pixel column through the second-layer connection parts 56A and 56B and the third-layer connection parts 57A and 57B. Examples of the connection parts 54A and 54B, the connection parts 55A and 55B, the connection parts 56A and 56B, and the connection parts 57A and 57B include through-silicon vias (TSVs) and metal-metal junctions including Cu-Cu junctions.

[0115] In the above example, the case where the stacked chip structure is a three-layer stacked structure has been exemplified, but it is not limited to the three-layer stacked structure, and a stacked structure of four or more layers may be used. In the case of a stacked structure of four or more layers, the analog circuit section and the digital circuit section of the analog-digital conversion section 14 can be dispersed and arranged on the semiconductor chips of each layer after the second layer.

[0116] [Electrical connection structure between semiconductor chips] Next, the electrical connection structure between the semiconductor chip of the first layer 41 - the semiconductor chip of the second layer 42 and between the semiconductor chip of the second layer 42 - the semiconductor chip of the third layer 43 will be described.

[0117] (Example 1 of electrical connection structure) A cross-sectional view of the end face of the cut portion in the case of Example 1 of the electrical connection structure between semiconductor chips is shown in FIG. 12A. Example 1 of the electrical connection structure is an example using a silicon through electrode (TSV) as the electrical connection portion between semiconductor chips. As shown in FIG. 12A, openings 61 for pads 51 for external connection and power supply are formed at both the left and right ends of the semiconductor chip 41 of the first layer on which the pixel array section (pixel region) 11 is formed.

[0118] And, in Example 1 of the electrical connection structure, a silicon through electrode 62 is used as the electrical connection portion between the semiconductor chip of the first layer 41 - the semiconductor chip of the second layer 42 - the semiconductor chip of the third layer 43. Further, the connection portions 54A(54B)-55A(55B) for making the electrical connection between the semiconductor chip of the first layer 41 - the semiconductor chip of the second layer 42 are provided close to the inside of the pixel array section 11. As the connection portions 54A(54B)-55A(55B) in the pixel array section 11, Cu-Cu bonding (direct bonding using Cu electrodes) is used.

[0119] (Example 2 of electrical connection structure) A cross-sectional view of the cut end surface in the case of Example 2 of the electrical connection structure between semiconductor chips is shown in FIG. 12B. In the electrical connection structure example 2, a Cu-Cu junction is used as the connection portions 54A(54B)-55A(55B) in the pixel array portion 11 between the first-layer semiconductor chip 41 and the second-layer semiconductor chip 42. For the connection portions outside the pixel array portion 11 between the second-layer semiconductor chip 42 and the third-layer semiconductor chip 43, a silicon through electrode 62 may be used, or a Cu-Cu junction may be used.

[0120] As described above, according to the CMOS image sensor 1B according to the second embodiment, by adopting a stacked chip structure with three or more stacked layers and arranging the analog circuit portion and the digital circuit portion of the analog-digital conversion unit 14 on semiconductor chips of different layers, the same operations and effects as those of the CMOS image sensor 1A according to the first embodiment can be obtained.

[0121] That is, while maintaining the chip size in which the contribution of the first-layer semiconductor chip 41 on which the pixel array portion 11 is formed is dominant, the parallel number of the analog-digital converter 140 can be increased to improve the frame rate. In addition, a process suitable for fabricating the pixels 20 can be applied to the first-layer semiconductor chip 41.

[0122] In addition, in the case of the above example, a low-cost process (for example, a 55 nm process) suitable for fabricating the analog circuit portion of the analog-digital conversion unit 14 can be applied to the second-layer semiconductor chip 42, and a process (for example, a 22 nm process) suitable for fabricating the digital circuit portion of the analog-digital conversion unit 14 can be applied to the third-layer semiconductor chip 43, so that the characteristics and cost can be optimized. In particular, when fabricating the digital circuit portion, the application of a leading-edge process becomes possible.

[0123] In addition, in the CMOS image sensor 1B according to the second embodiment, the pixel array portion 11 is divided into a plurality of regions in the column direction, and correspondingly, the signal lines 32 are divided into a plurality of signal lines in the length direction for each pixel column. As a result, the following operations and effects can be obtained.

[0124] As shown in FIG. 13, let the parasitic resistance of the signal line 32 be R VSL , the parasitic capacitance be C VSL , the current flowing through the load current source I be I LM , and the mutual conductance of the MOS transistor be g m . When this is the case, the pixel P-phase / D-phase setting time is 1 / g m (∝1 / √I LM ), and is determined by the parasitic resistance R VSL and the parasitic capacitance C VSL . By dividing the signal line 32 into a plurality of signal lines, the parasitic resistance R VSL and the parasitic capacitance C VSL of one signal line can be reduced. For example, when the signal line 32 is divided into two, the parasitic resistance R VSL and the parasitic capacitance C VSL can be halved.

[0125] FIG. 14 shows a timing diagram of one horizontal period (1H). When the parasitic resistance R VSL and the parasitic capacitance C VSL can be halved, the pixel P-phase / D-phase setting time (the setting time of the signal line potential) can be shortened, so the time required to read out the pixel signals of one row can be shortened, and the frame rate can be improved. Also, since the setting time can be shortened, as shown in FIG. 14, free time occurs within one horizontal period, and by stopping the circuit operation during the free time, the power consumption can be reduced. Alternatively, without shortening the setting time and while maintaining the same one horizontal period, the current I VSL flowing through the load current source I may be reduced by the amount by which the parasitic resistance R VSL and the parasitic capacitance C LM are decreased.

[0126] <Imaging device according to the third embodiment> The imaging device according to the second embodiment has a configuration in which the analog circuit portion of the analog-digital conversion unit 14 is formed on the second-layer semiconductor chip 42, and the digital circuit portion of the analog-digital conversion unit 14 is formed on the third-layer semiconductor chip 43. On the other hand, the imaging device according to the third embodiment has a configuration in which the digital circuit portion of the analog-digital conversion unit 14 is formed on the second-layer semiconductor chip 42, and the analog circuit portion of the analog-digital conversion unit 14 is formed on the third-layer semiconductor chip 43.

[0127] [Configuration Example of CMOS Image Sensor] FIG. 15 is a block diagram schematically showing an outline of the system configuration of a CMOS image sensor which is an example of an imaging device to which the technology according to the present disclosure is applied in the third embodiment.

[0128] In the CMOS image sensor 1C according to the third embodiment, the pixel array portion 11 is divided into two regions 11A and 11B in the column direction. Correspondingly, the signal line 32 is divided into a first signal line 32A (32A1 to 32A n ) and a second signal line 32B (32B1 to 32B n ) for each pixel column. This is the same as in the case of the second embodiment.

[0129] Also, corresponding to the two regions 11A and 11B of the pixel array portion 11, two sets of a load current source portion 13, an analog-digital conversion portion 14, and a logic circuit portion 15 as a signal processing portion are provided. Specifically, corresponding to the region 11A of the pixel array portion 11, a load current source portion 13A, an analog-digital conversion portion 14A, and a logic circuit portion 15A are provided, and corresponding to the region 11B of the pixel array portion 11, a load current source portion 13B, an analog-digital conversion portion 14B, and a logic circuit portion 15B are provided.

[0130] The circuit configuration of each pixel 20 in the two regions 11A and 11B of the pixel array portion 11 and the configuration of each analog-digital converter in the analog-digital conversion portion 14 are basically the same as in the case of the CMOS image sensor 1A according to the first embodiment.

[0131] [Stacked Chip Structure] Fig. 16 shows a schematic exploded perspective view of the stacked chip structure of the CMOS image sensor 1C according to the third embodiment.

[0132] As shown in Fig. 16, the CMOS image sensor 1C according to the third embodiment also has a stacked chip structure in which at least three semiconductor chips, i.e., a first-layer semiconductor chip 41, a second-layer semiconductor chip 42, and a third-layer semiconductor chip 43, are stacked, similar to the case of the CMOS image sensor 1A according to the first embodiment.

[0133] In the first-layer semiconductor chip 41, two divided regions 11A and 11B of the pixel array portion 11 in which pixels 20 are two-dimensionally arranged in a matrix are formed with connection portions (VIAs) 54A and 54B for electrical connection to the second-layer semiconductor chip 42 interposed therebetween. Further, pads 51 for external connection and power supply are provided, for example, at both left and right ends of the first-layer semiconductor chip 41.

[0134] In the second-layer semiconductor chip 42, digital circuit portions of the analog-digital conversion portion 14, specifically, counters 142A and 142B of the analog-digital converter 140 are arranged. Connection portions 56A and 56B for electrical connection to the third-layer semiconductor chip 43 are provided outside the counters 142A and 142B.

[0135] In the second-layer semiconductor chip 42, in addition to the digital circuit portions of the analog-digital conversion portion 14, logic circuit portions 15A and 15B which are signal processing portions are arranged. Connection portions 55A and 55B for relaying the electrical connection between the first-layer semiconductor chip 41 and the second-layer semiconductor chip 42 are provided between the logic circuit portions 15A and 15B. Further, an interface (I / F) 18 is arranged in the second-layer semiconductor chip 42.

[0136] The arrangement of the counters 142A and 142B, the logic circuit sections 15A and 15B, and the interface 18 of the analog-digital converter 140 on the second-layer semiconductor chip 42 shown in FIG. 16 is an example and is not limited to this arrangement example.

[0137] In the third-layer semiconductor chip 43, an analog circuit section of the analog-digital conversion section 14, specifically, the comparators 141A and 141B of the analog-digital converter 140 are arranged. Connection portions 57A and 57B for making electrical connection with the second-layer semiconductor chip 42 are provided outside the comparators 141A and 141B.

[0138] In the third-layer semiconductor chip 43, in addition to the comparators 141A and 141B, load current source sections 13A and 13B are arranged with connection portions (VIAs) 58A and 58B for making electrical connection with the first-layer semiconductor chip 41 via the connection portions 55A and 55B of the second-layer semiconductor chip 42 interposed therebetween. In the third-layer semiconductor chip 43, a row selection section 12 is further arranged. Also, in the third-layer semiconductor chip 43, a reference signal generation section 17 is preferably arranged at a position equidistant from the comparators 141A and 141B.

[0139] The arrangement of the comparators 141A and 141B, the load current source sections 13A and 13B, the row selection section 12, and the reference signal generation section 17 of the analog-digital converter 140 on the third-layer semiconductor chip 43 shown in FIG. 16 is an example and is not limited to this arrangement example.

[0140] In the above-described stacked chip structure, the signal lines 32A and 32B that are segmented and wired for each pixel column in the first-layer semiconductor chip 41 and the respective load currents I of the load current source sections 13A and 13B arranged in the third-layer semiconductor chip 43 are electrically connected for each pixel column through the first-layer connection portions 54A and 54B, the second-layer connection portions 55A and 55B, and the third-layer 58A and 58B.

[0141] Further, the counters 142A and 142B arranged corresponding to the two regions 11A and 11B on the second-layer semiconductor chip 42 and the comparators 141A and 141B arranged on the third-layer semiconductor chip 43 are electrically connected for each pixel column through the second-layer connection portions 56A and 56B and the third-layer connection portions 57A and 57B. Examples of the connection portions 54A and 54B, the connection portions 55A and 55B, the connection portions 56A and 56B, the connection portions 57A and 57B, and the connection portions 58A and 58B include through-silicon vias (TSVs) and metal-metal junctions including Cu-Cu junctions.

[0142] In addition, in the above example, the case of a three-layer stacked structure of the stacked chip structure is illustrated, but it is not limited to the three-layer stacked structure, and a stacked structure of four or more layers may be used. In the case of a stacked structure of four or more layers, the analog circuit portion and the digital circuit portion of the analog-digital conversion unit 14 can be distributed and arranged on the semiconductor chips of each layer after the second layer.

[0143] As described above, according to the CMOS image sensor 1C according to the third embodiment, by using a stacked chip structure of three or more layers and forming the analog circuit portion and the digital circuit portion of the analog-digital conversion unit 14 on semiconductor chips of different layers, the same operations and effects as those of the CMOS image sensor 1A according to the first embodiment can be obtained.

[0144] That is, while maintaining the chip size in which the contribution of the first-layer semiconductor chip 41 on which the pixel array portion 11 is formed is dominant, the parallel number of the analog-digital converter 140 can be increased to improve the frame rate. Further, a process suitable for manufacturing the pixels 20 can be applied to the first-layer semiconductor chip 41.

[0145] Also, in the case of the above example, for the second-layer semiconductor chip 42, a process suitable for fabricating the digital circuit part of the analog-digital conversion unit 14 (e.g., 22 nm process) can be applied, and for the third-layer semiconductor chip 43, a low-cost process suitable for fabricating the analog circuit part of the analog-digital conversion unit 14 (e.g., 55 nm process) can be applied, so that the characteristics and cost can be optimized. In particular, when fabricating the digital circuit part, the application of a leading-edge process becomes possible.

[0146] Also, in the CMOS image sensor 1C according to the third embodiment, since the signal line 32 is divided into a plurality of signal lines in its length direction, the same operations and effects as those of the CMOS image sensor 1B according to the second embodiment can be obtained. That is, the parasitic resistance R VSL and the parasitic capacitance C VSL of one signal line can be reduced, so that the setting time of the signal line potential can be shortened. As a result, the time required to read out the pixel signals of one row can be shortened, and the frame rate can be improved.

[0147] Also, since the setting time can be shortened, an idle time is generated within one horizontal period, and the power consumption can be reduced by stopping the circuit operation during the idle time. Alternatively, without shortening the setting time and while maintaining the same one horizontal period, the current I VSL flowing through the load current source I can be reduced by the amount by which the parasitic resistance R VSL and the parasitic capacitance C LM are reduced.

[0148] Also, in the case of the CMOS image sensor 1C according to the third embodiment, since the interface 18 is provided on the second-layer semiconductor chip 42, the parasitic resistance and parasitic capacitance associated with the output of the interface 18 can be reduced as compared with the case where it is provided on the third-layer semiconductor chip 43. The output of the interface 18 is a high-speed signal, and reducing the parasitic resistance and parasitic capacitance for one layer is important in terms of design.

[0149] <Imaging Device According to the Fourth Embodiment> The fourth embodiment is a modification of the second embodiment, and is an example in which a memory area is secured in the third semiconductor chip.

[0150] FIG. 17 shows a schematic exploded perspective view of a stacked chip structure of a CMOS image sensor which is an example of an imaging device according to the fourth embodiment to which the technology according to the present disclosure is applied.

[0151] In a stacked chip structure in which at least three semiconductor chips, i.e., a first-layer semiconductor chip 41, a second-layer semiconductor chip 42, and a third-layer semiconductor chip 43, are stacked, the configurations of the first-layer semiconductor chip 41 and the second-layer semiconductor chip 42 are the same as those in the case of the CMOS image sensor 1B according to the second embodiment.

[0152] In the CMOS image sensor 1D according to the fourth embodiment, in addition to the counters 142A and 142B which are digital circuit parts of the analog-digital conversion part 14, the logic circuit part 15 which is a signal processing part, the row selection part 12, and the interface 18, a memory part 71 is arranged in the third-layer semiconductor chip 43. The memory part 71 can be used, for example, to temporarily hold data in the process of performing desired signal processing by the logic circuit part 15.

[0153] <Imaging Device According to the Fifth Embodiment> The fifth embodiment is a modification of the fourth embodiment, and is an example in which an AI (Artificial Intelligence) area is secured in the third semiconductor chip instead of a memory area.

[0154] FIG. 18 shows a schematic exploded perspective view of a stacked chip structure of a CMOS image sensor which is an example of an imaging device according to the fifth embodiment to which the technology according to the present disclosure is applied.

[0155] In a stacked chip structure in which at least three semiconductor chips, i.e., a first-layer semiconductor chip 41, a second-layer semiconductor chip 42, and a third-layer semiconductor chip 43, are stacked, the configurations of the first-layer semiconductor chip 41 and the second-layer semiconductor chip 42 are the same as those in the case of the CMOS image sensor 1B according to the second embodiment.

[0156] In the CMOS image sensor 1E according to the fifth embodiment, in addition to the counters 142A and 142B which are digital circuit parts of the analog-digital conversion unit 14, the logic circuit part 15 which is a signal processing part, the row selection part 12, and the interface 18, an AI circuit 72 is arranged in the third-layer semiconductor chip 43. The AI circuit 72 can be used, for example, for image processing and various settings for analog signals.

[0157] <Imaging device according to the sixth embodiment> The sixth embodiment is a modification of the second embodiment and is an example of a stacked structure of four layers.

[0158] FIG. 19 shows a schematic exploded perspective view of a stacked chip structure of a CMOS image sensor which is an example of an imaging device according to the sixth embodiment to which the technology according to the present disclosure is applied.

[0159] As shown in FIG. 19, the CMOS image sensor 1F according to the sixth embodiment has a stacked chip structure in which four semiconductor chips, i.e., a first-layer semiconductor chip 41, a second-layer semiconductor chip 42, a third-layer semiconductor chip 43, and a fourth-layer semiconductor chip 44, are stacked.

[0160] The configurations of the first-layer semiconductor chip 41, the second-layer semiconductor chip 42, and the third-layer semiconductor chip 43 are the same as those of the CMOS image sensor 1B according to the second embodiment. That is, in the first-layer semiconductor chip 41, two divided regions 11A and 11B of the pixel array portion 11 are formed, and in the second-layer semiconductor chip 42, comparators 141A and 141B, load current source portions 13A and 13B, and a reference signal generation portion 17 of the analog-to-digital converter 140 are arranged. The first-layer semiconductor chip 41 and the second-layer semiconductor chip 42 are electrically connected through the first-layer connection portions 54A and 54B and the second-layer connection portions 55A and 55B.

[0161] In the third-layer semiconductor chip 43, counters 142A and 142B, a logic circuit portion 15, and a row selection portion 12 of the analog-to-digital converter 140 are arranged. The comparators 141A and 141B on the second-layer semiconductor chip 42 and the counters 142A and 142B on the third-layer semiconductor chip 43 are electrically connected through the second-layer connection portions 56A and 56B and the third-layer connection portions 57A and 57B.

[0162] In the fourth-layer semiconductor chip 44, a memory portion 71 and an interface 18 are arranged. The third-layer semiconductor chip 43 and the fourth-layer semiconductor chip 44 are connected, for example, by CoW (Chip on Wafer). The logic circuit portion 15 on the third-layer semiconductor chip 43 and the memory portion 71 on the fourth-layer semiconductor chip 44 are electrically connected through the third-layer connection portion 63 and the fourth-layer connection portion 64. The memory portion 71 can be used, for example, to temporarily hold data in the process of performing desired signal processing by the logic circuit portion 15.

[0163] <Imaging Device According to the Seventh Embodiment> The seventh embodiment is a modification of the sixth embodiment, and is an example in which an AI region is secured in the fourth-layer semiconductor chip instead of the memory region.

[0164] FIG. 20 shows a schematic exploded perspective view of a stacked chip structure of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied, according to a seventh embodiment.

[0165] As shown in FIG. 20, the CMOS image sensor 1G according to the seventh embodiment also has a stacked chip structure in which four semiconductor chips, i.e., a first-layer semiconductor chip 41, a second-layer semiconductor chip 42, a third-layer semiconductor chip 43, and a fourth-layer semiconductor chip 44, are stacked, similar to the CMOS image sensor 1E according to the sixth embodiment.

[0166] In the above stacked chip structure, the configurations of the first-layer semiconductor chip 41, the second-layer semiconductor chip 42, and the third-layer semiconductor chip 43 are the same as those in the case of the CMOS image sensor 1F according to the sixth embodiment. And, instead of the memory unit 71, an AI circuit 72 is arranged in the fourth-layer semiconductor chip 44. The third-layer semiconductor chip 43 and the fourth-layer semiconductor chip 44 are, for example, connected by CoW, and the logic circuit unit 15 on the third-layer semiconductor chip 43 and the AI circuit 72 on the fourth-layer semiconductor chip 44 are electrically connected through a third-layer connection part 63 and a fourth-layer connection part 64. The AI circuit 72 can be used, for example, for image processing and various settings for analog signals.

[0167] <Imaging Device According to the Eighth Embodiment> The eighth embodiment is a modification of the seventh embodiment, and is an example in which the size of the fourth-layer semiconductor chip is made smaller than the sizes of the other semiconductor chips.

[0168] FIG. 21 shows a schematic exploded perspective view of a stacked chip structure of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied, according to the eighth embodiment.

[0169] As shown in FIG. 21, the CMOS image sensor 1H according to the eighth embodiment also has a stacked chip structure in which four semiconductor chips, i.e., a first-layer semiconductor chip 41, a second-layer semiconductor chip 42, a third-layer semiconductor chip 43, and a fourth-layer semiconductor chip 44, are stacked. However, the fourth-layer semiconductor chip 44 is configured to be smaller in size than the other semiconductor chips 41, 42, and 43.

[0170] The third-layer semiconductor chip 43 and the fourth-layer semiconductor chip 44 are, for example, connected by CoW. The logic circuit portion 15 on the third-layer semiconductor chip 43 and the AI circuit 72 on the fourth-layer semiconductor chip 44 are electrically connected through the third-layer connection portion 63 and the fourth-layer connection portion 64. The AI circuit 72 can be used, for example, for image processing and various settings for analog signals.

[0171] In the CMOS image sensor 1H according to the eighth embodiment having the above-described stacked chip structure, an advanced process (for example, a 12 nm process) can be applied to the fourth-layer semiconductor chip 44. Since the size of the fourth-layer semiconductor chip 44 is smaller than the sizes of the other semiconductor chips 41, 42, and 43, a large number of semiconductor chips 44 can be manufactured from one wafer, thereby reducing costs.

[0172] <Modification Example> As described above, the technology according to the present disclosure has been described based on preferred embodiments. However, the technology according to the present disclosure is not limited to these embodiments. The configurations and structures of the imaging devices described in the above embodiments are examples and can be changed as appropriate.

[0173] <Application Example> The imaging device according to the present embodiment described above can be used in various devices that sense light such as visible light, infrared light, ultraviolet light, and X-rays, as shown in FIG. 22, for example. Specific examples of various devices are listed below.

[0174] · Devices for taking pictures of images for viewing, such as digital cameras and mobile devices with camera functions · In-vehicle sensors for taking pictures of the front, rear, surroundings, and inside of a vehicle for safe driving such as automatic stop and recognition of the driver's state, surveillance cameras for monitoring moving vehicles and roads, distance measurement sensors for measuring distances between vehicles, etc., devices for traffic use · Devices for home appliances such as TVs, refrigerators, and air conditioners for taking pictures of the user's gestures and performing device operations according to the gestures · Devices for medical and healthcare use, such as endoscopes and devices for taking pictures of blood vessels by receiving infrared light · Devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication · Devices for beauty use, such as skin measuring devices for taking pictures of the skin and microscopes for taking pictures of the scalp · Devices for sports use, such as action cameras and wearable cameras for sports applications · Devices for agricultural use, such as cameras for monitoring fields and crop conditions

[0175] <Examples of applications of the technology according to the present disclosure> The technology according to the present disclosure can be applied to various products. Hereinafter, more specific application examples will be described.

[0176] [Electronic devices of the present disclosure] Here, the case of applying to imaging systems such as digital still cameras and video cameras, portable terminal devices having an imaging function such as mobile phones, and electronic devices such as copiers using an imaging device in an image reading unit will be described.

[0177] (Example of an imaging system) FIG. 23 is a block diagram showing a configuration example of an imaging system which is an example of the electronic device of the present disclosure.

[0178] As shown in FIG. 23, the imaging system 100 according to this example includes an imaging optical system 101 including a lens group and the like, an imaging unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, a power supply system 108, and the like. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are configured to be mutually connected via a bus line 109.

[0179] The imaging optical system 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal in pixel units and outputs it as a pixel signal. The DSP circuit 103 performs general camera signal processing, for example, white balance processing, demosaic processing, gamma correction processing, and the like.

[0180] The frame memory 104 is appropriately used for storing data in the process of signal processing in the DSP circuit 103. The display device 105 is composed of a panel-type display device such as a liquid crystal display device or an organic EL (electro luminescence) display device, and displays a moving image or a still image captured by the imaging unit 102. The recording device 106 records the moving image or the still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or an HDD (Hard Disk Drive).

[0181] The operation system 107 issues operation commands for various functions of the imaging device 100 under the operation of the user. The power supply system 108 appropriately supplies various power supplies that serve as the operating power of the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

[0182] In the imaging system 100 configured as described above, as the imaging unit 102, the imaging devices according to the above-described embodiments can be used. According to the imaging device, the parallel number of analog-to-digital converters can be increased while maintaining the chip size in which the contribution of the pixel chip on which pixels are arranged is dominant, so that the frame rate can be improved.

[0183] [Application Example to a Moving Body] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as an imaging device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, and an agricultural machine (tractor).

[0184] FIG. 24 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a movement control system to which the technology according to the present disclosure can be applied.

[0185] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 24, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an out-vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0186] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a driving force generation device for generating a driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0187] The body control unit 12020 controls the operations of various devices installed in the vehicle according to various programs. For example, the body control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a backlamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches can be input to the body control unit 12020. The body control unit 12020 receives these inputs of radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0188] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing on objects such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

[0189] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as ranging information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.

[0190] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the degree of driver fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0191] Based on the information inside and outside the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing functions of an ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle.

[0192] In addition, based on the information around the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving that travels autonomously without relying on the driver's operation by controlling the driving force generation device, the steering mechanism, or the braking device, etc.

[0193] In addition, based on the out-vehicle information acquired by the out-vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control for the purpose of anti-glare such as controlling the headlamp according to the position of the preceding vehicle or oncoming vehicle detected by the out-vehicle information detection unit 12030 and switching the high beam to the low beam.

[0194] The audio-visual output unit 12052 transmits at least one of an audio output signal and a visual output signal to an output device capable of notifying information visually or aurally to the vehicle occupants or outside the vehicle. In the example of FIG. 24, as the output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0195] FIG. 25 is a diagram showing an example of the installation position of the imaging unit 12031.

[0196] In FIG. 25, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0197] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose of the vehicle 12100, side mirrors, rear bumper, back door, and the upper part of the front glass in the vehicle interior. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the front glass in the vehicle interior mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires images behind the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle or pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0198] Note that FIG. 25 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 provided at the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 provided at the side mirrors respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 provided at the rear bumper or back door. For example, by overlapping the image data captured by imaging units 12101 to 12104, an overhead image of vehicle 12100 viewed from above can be obtained.

[0199] At least one of imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0200] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 obtains the distance to each solid object within imaging ranges 12111 to 12114 and the temporal change of this distance (relative speed with respect to vehicle 12100), and thus can extract, as the preceding vehicle, the closest solid object on the traveling path of vehicle 12100 that travels in substantially the same direction as vehicle 12100 at a predetermined speed (for example, 0 km / h or more). Further, microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control), etc. In this way, cooperative control for the purpose of autonomous driving, etc., which runs autonomously without relying on the driver's operation, can be performed.

[0201] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 classifies and extracts solid object data related to solid objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other solid objects, and can use it for automatic avoidance of obstacles. For example, the microcomputer 12051 discriminates obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, it outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or avoidance steering via the drive system control unit 12010, thereby providing driving assistance for collision avoidance.

[0202] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian exists in the captured image of the imaging units 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as an infrared camera, and a procedure of performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured image of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio and image output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline for emphasis on the recognized pedestrian. Further, the audio and image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0203] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. By applying the technology according to the present disclosure to the imaging unit 12031 or the like, it is possible to increase the number of parallel analog-to-digital converters while maintaining the chip size in which the contribution of the pixel chip formed by arranging pixels is dominant, so that the frame rate can be improved.

[0204] <Configurations that the present disclosure can adopt> Note that the present disclosure can also adopt the following configurations.

[0205] ≪A. Imaging device≫ [A-01] It has a stacked chip structure in which at least three semiconductor chips, namely, the semiconductor chip of the first layer, the semiconductor chip of the second layer, and the semiconductor chip of the third layer, are stacked. On the semiconductor chip of the first layer, a pixel array unit in which pixels are two-dimensionally arranged in a matrix is formed. On one of the semiconductor chip of the second layer and the semiconductor chip of the third layer, an analog circuit unit of an analog-to-digital conversion unit that converts an analog pixel signal read out from each pixel of the pixel array unit through a signal line into a digital pixel signal is arranged. On the other of the semiconductor chip of the second layer and the semiconductor chip of the third layer, a digital circuit unit of the analog-to-digital conversion unit is arranged. Imaging device. [A-02] The analog-to-digital conversion unit is composed of a plurality of analog-to-digital converters provided corresponding to the pixel columns of the pixel array unit. The analog-to-digital converter has a comparator that compares an analog pixel signal with a reference signal of a ramp wave, and a counter that measures the time from the generation timing of the reference signal until the analog pixel signal and the reference signal of the ramp wave cross. On one of the second-layer semiconductor chip and the third-layer semiconductor chip, a comparator of the analog-digital conversion unit is arranged. On the other of the second-layer semiconductor chip and the third-layer semiconductor chip, a counter of the analog-digital conversion unit is arranged. The imaging device according to [A-01] above. [A-03] On the second-layer semiconductor chip, a comparator of the analog-digital conversion unit and a load current source connected to a signal line are arranged. On the third-layer semiconductor chip, a counter, a logic circuit unit, and an interface of the analog-digital conversion unit are arranged. The imaging device according to [A-02] above. [A-04] On the third-layer semiconductor chip, in addition to a counter, a logic circuit unit, and an interface of the analog-digital conversion unit, a memory unit is arranged. The imaging device according to [A-03] above. [A-05] On the third-layer semiconductor chip, in addition to a counter, a logic circuit unit, and an interface of the analog-digital conversion unit, an AI circuit is arranged. The imaging device according to [A-03] above. [A-06] It has a fourth-layer semiconductor chip. On the fourth-layer semiconductor chip, a memory unit is arranged. The imaging device according to [A-03] above. [A-07] It has a fourth-layer semiconductor chip. On the fourth-layer semiconductor chip, an AI circuit is arranged. The imaging device according to [A-03] above. [A-08] The fourth-layer semiconductor chip is smaller in size than the semiconductor chips of other layers. The imaging device according to [A-07] above. [A-09] In the semiconductor chip of the second layer, a counter, a logic circuit section, and an interface of the analog-digital conversion section are arranged. In the semiconductor chip of the third layer, a comparator of the analog-digital conversion section and a load current source connected to a signal line are arranged. The imaging device according to [A-02] above. [A-10] The analog-digital conversion section includes a plurality of systems of analog-digital conversion sections including a first analog-digital conversion section and a second analog-digital conversion section that convert each of the analog pixel signals read out in parallel from the respective pixels of a plurality of pixel rows of the pixel array section into digital pixel signals. The imaging device according to any one of [A-01] to [A-09] above. [A-11] The signal line is divided into a plurality of signal lines including a first signal line and a second signal line corresponding to a plurality of systems of analog-digital conversion sections for each pixel column in the length direction thereof. The imaging device according to [A-10] above. [A-12] A first connection section connecting the first signal line and the first analog-digital conversion section and a second connection section connecting the second signal line and the second analog-digital conversion section are provided in proximity within the region of the pixel array section. The imaging device according to [A-11] above. [A-13] The first connection section and the second connection section connect the semiconductor chip of the first layer and the semiconductor chip of the second layer by direct bonding using Cu electrodes. The imaging device according to [A-12] above.

[0206] ≪B. Electronic device≫ [B-01] It has a stacked chip structure in which at least three semiconductor chips including a semiconductor chip of the first layer, a semiconductor chip of the second layer, and a semiconductor chip of the third layer are stacked. In the semiconductor chip of the first layer, a pixel array section in which pixels are two-dimensionally arranged in a matrix is formed. On one of the second-layer semiconductor chip and the third-layer semiconductor chip, an analog circuit portion of an analog-digital conversion unit that converts an analog pixel signal read out from each pixel of the pixel array portion through a signal line into a digital pixel signal is arranged. On the other of the second-layer semiconductor chip and the third-layer semiconductor chip, a digital circuit portion of the analog-digital conversion unit is arranged. An electronic device having an imaging device. [B-02] The analog-digital conversion unit is composed of a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array portion. The analog-digital converter has a comparator that compares an analog pixel signal with a reference signal of a ramp wave, and a counter that measures the time from the generation timing of the reference signal until the analog pixel signal and the reference signal of the ramp wave cross. On one of the second-layer semiconductor chip and the third-layer semiconductor chip, the comparator of the analog-digital conversion unit is arranged. On the other of the second-layer semiconductor chip and the third-layer semiconductor chip, the counter of the analog-digital conversion unit is arranged. The electronic device according to [B-01] above. [B-03] In the second-layer semiconductor chip, the comparator of the analog-digital conversion unit and a load current source connected to the signal line are arranged. In the third-layer semiconductor chip, the counter, logic circuit portion, and interface of the analog-digital conversion unit are arranged. The electronic device according to [B-02] above. [B-04] In the third-layer semiconductor chip, in addition to the counter, logic circuit portion, and interface of the analog-digital conversion unit, a memory portion is arranged. The electronic device according to [B-03] above. [B-05] In the semiconductor chip of the third layer, in addition to the counter, logic circuit section, and interface of the analog-digital conversion section, an AI circuit is arranged. The electronic device according to [B-03] above. [B-06] Having a semiconductor chip of the fourth layer, In the semiconductor chip of the fourth layer, a memory section is arranged. The electronic device according to [B-03] above. [B-07] Having a semiconductor chip of the fourth layer, In the semiconductor chip of the fourth layer, an AI circuit is arranged. The electronic device according to [B-03] above. [B-08] The semiconductor chip of the fourth layer is smaller in size than the semiconductor chips of the other layers. The electronic device according to [B-07] above. [B-09] In the semiconductor chip of the second layer, the counter, logic circuit section, and interface of the analog-digital conversion section are arranged. In the semiconductor chip of the third layer, a comparator of the analog-digital conversion section and a load current source connected to the signal line are arranged. The electronic device according to [B-02] above. [B-10] The analog-digital conversion section is composed of a plurality of systems of analog-digital conversion sections including a first analog-digital conversion section and a second analog-digital conversion section that convert each of the analog pixel signals read out in parallel from the pixels of the plurality of pixel rows of the pixel array section into digital pixel signals. The electronic device according to any one of [B-01] to [B-09] above. [B-11] In the length direction of the signal line, for each pixel column, it is divided into a plurality of signal lines including a first signal line and a second signal line corresponding to the plurality of systems of analog-digital conversion sections. The electronic device according to [B-10] above. [B-12] A first connection portion that connects a first signal line and a first analog-digital conversion unit, and a second connection portion that connects a second signal line and a second analog-digital conversion unit are provided close to each other within the region of the pixel array portion. The electronic device according to [B-11] above. [B-13] The first connection portion and the second connection portion connect the first-layer semiconductor chip and the second-layer semiconductor chip by direct bonding using Cu electrodes. The electronic device according to [B-12] above.

Explanation of Signs

[0207] 1A... CMOS image sensor of the first embodiment, 1B... CMOS image sensor according to the second embodiment, 1C... CMOS image sensor of the third embodiment, 1D... CMOS image sensor according to the fourth embodiment, 1E... CMOS image sensor of the fifth embodiment, 1F... CMOS image sensor according to the sixth embodiment, 1G... CMOS image sensor of the seventh embodiment, 1H... CMOS image sensor according to the eighth embodiment, 11... Pixel array portion, 12... Row selection portion, 13... Load current source portion, 14... Analog-digital conversion unit, 15... Logic circuit portion (signal processing portion), 16... Timing control portion, 17... Reference signal generation portion, 20... Pixel (pixel circuit), 21... Photodiode, 22... Transfer transistor, 23... Reset transistor, 24... Amplification transistor, 25... Selection transistor, 31(311~31 m )... Pixel control line, 32(321~32 n )... Signal line, 41... First-layer semiconductor chip, 42... Second-layer semiconductor chip, 43... Third-layer semiconductor chip, 44... Fourth-layer semiconductor chip, 71... Memory portion, 72... AI circuit, 140... Analog-digital converter, 141... Comparator, 142... Counter

Claims

1. having a stacked chip structure in which at least four semiconductor chips, namely, a first-layer semiconductor chip, a second-layer semiconductor chip, a third-layer semiconductor chip, and a fourth-layer semiconductor chip, are stacked, a pixel array portion in which pixels are two-dimensionally arranged in a matrix is formed on the first-layer semiconductor chip, an analog circuit portion of an analog-digital conversion unit that converts an analog pixel signal read out from each pixel of the pixel array portion through a signal line into a digital pixel signal is disposed on one of the second-layer semiconductor chip and the third-layer semiconductor chip, a digital circuit portion of the analog-digital conversion unit is disposed on the other of the second-layer semiconductor chip and the third-layer semiconductor chip, the first-layer semiconductor chip, the second-layer semiconductor chip, and the third-layer semiconductor chip have the same size, the fourth-layer semiconductor chip has a size smaller than that of the first-layer semiconductor chip, the second-layer semiconductor chip, and the third-layer semiconductor chip, an imaging device.

2. the analog-digital conversion unit is composed of a plurality of analog-digital converters provided corresponding to pixel columns of the pixel array portion, the analog-digital converter includes a comparator that compares an analog pixel signal with a reference signal of a ramp wave, and a counter that measures the time from the generation timing of the reference signal until the analog pixel signal and the reference signal of the ramp wave cross, the comparator of the analog-digital conversion unit is disposed on one of the second-layer semiconductor chip and the third-layer semiconductor chip, the counter of the analog-digital conversion unit is disposed on the other of the second-layer semiconductor chip and the third-layer semiconductor chip, the imaging device according to Claim 1.

3. the comparator of the analog-digital conversion unit and a load current source connected to the signal line are disposed on the second-layer semiconductor chip, In the semiconductor chip of the third layer, a counter, a logic circuit section, and an interface of the analog-digital conversion section are arranged. The imaging device according to claim 2.

4. In the semiconductor chip of the third layer, in addition to a counter, a logic circuit section, and an interface of the analog-digital conversion section, a memory section is arranged. The imaging device according to claim 3.

5. In the semiconductor chip of the third layer, in addition to a counter, a logic circuit section, and an interface of the analog-digital conversion section, an AI circuit is arranged. The imaging device according to claim 3.

6. In the semiconductor chip of the fourth layer, a memory section is arranged. The imaging device according to claim 3.

7. In the semiconductor chip of the fourth layer, an AI circuit is arranged. The imaging device according to claim 3.

8. The semiconductor chip of the third layer and the semiconductor chip of the fourth layer are connected by CoW (Chip on Wafer). The imaging device according to claim 7.

9. In the semiconductor chip of the second layer, a counter, a logic circuit section, and an interface of the analog-digital conversion section are arranged, In the semiconductor chip of the third layer, a comparator of the analog-digital conversion section and a load current source connected to a signal line are arranged. The imaging device according to claim 2.

10. The analog-digital conversion section is composed of a plurality of systems of analog-digital conversion sections including a first analog-digital conversion section and a second analog-digital conversion section that convert each of the analog pixel signals read out in parallel from the pixels of a plurality of pixel rows of the pixel array section into digital pixel signals. The imaging device according to claim 1.

11. In the length direction, the signal line is divided into a plurality of signal lines including a first signal line and a second signal line corresponding to a plurality of analog-to-digital conversion units for each pixel column. The imaging device according to claim 10.

12. A first connection portion connecting the first signal line and the first analog-to-digital conversion unit, and a second connection portion connecting the second signal line and the second analog-to-digital conversion unit are provided close to each other within the region of the pixel array portion. The imaging device according to claim 11.

13. The first connection portion and the second connection portion connect the first semiconductor chip and the second semiconductor chip by direct bonding using Cu electrodes. The imaging device according to claim 12.

14. It has a stacked chip structure in which at least four semiconductor chips, namely, a first-layer semiconductor chip, a second-layer semiconductor chip, a third-layer semiconductor chip, and a fourth-layer semiconductor chip are stacked. A pixel array portion in which pixels are two-dimensionally arranged in a matrix is formed on the first-layer semiconductor chip. An analog circuit portion of an analog-to-digital conversion unit that converts an analog pixel signal read out from each pixel of the pixel array portion through a signal line into a digital pixel signal is arranged on one of the second-layer semiconductor chip and the third-layer semiconductor chip. A digital circuit portion of the analog-to-digital conversion unit is arranged on the other of the second-layer semiconductor chip and the third-layer semiconductor chip. The first-layer semiconductor chip, the second-layer semiconductor chip, and the third-layer semiconductor chip have the same size. The fourth-layer semiconductor chip has a size smaller than that of the first-layer semiconductor chip, the second-layer semiconductor chip, and the third-layer semiconductor chip. An electronic device having the imaging device.

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